STV7618 [STMICROELECTRONICS]
PLASMA DISPLAY PANEL DATA DRIVER; 等离子显示面板的数据驱动器
| 型号： | STV7618 |
| 厂家： | 
ST |
| 描述： | PLASMA DISPLAY PANEL DATA DRIVER |
| 文件： | 总16页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV7618
PLASMA DISPLAY PANEL DATA DRIVER
FEATURES
■ 96 Outputs Plasma Display Driver
■ 90V Absolute Maximum Rating
■ 3.3V / 5V Compatible Logic
■ -40 / 30 mA Source / Sink Output MOS
■ 3 or 6 Bit Data Bus (40 MHz)
■ BCD Process
■ Packaging Adapted to Customer’s Request
(DICE, COB, COF, TAB).
Die
ORDER CODE: STV7618/WAF (1)
(1)Unsawn tested wafer
DESCRIPTION
STV7618 is a data driver for Plasma Display
Panel (PDP) designed in the ST proprietary BCD
high voltage technology. Using a 3 or 6 bit wide
data bus, it can control 96 high current & high
voltage outputs. The STV7618 is supplied with a
separated 70V power output supply and a 5V logic
supply. All command inputs are CMOS and 3.3V
logic levels compatible.
Version 4.2
April 2002
1/16
1
STV7618
Revision follow-up
Target specification
05/2000
05/2000
07/2000
version 1.1
document creation
version 1.2
few changes in figures
version 1.3
addition of pads dimensions/coordinates,
few changes in figures and electrical characteristics
02/2001
version 1.4
TBD mentions replaced with values for Vouthl and Voutlh
Datasheet
06/2001
version 4.0
general update
version 4.1
10/2001
04/2002
addition of die photo in cover page
new pads dimensions
version 4.2
Cover page
features related to output diode current deleted
New values for Source/sink output MOS: -40/30mA
Absolute maximum ratings
I
values -150/150mA
POUT
added definition and values for I
-200/300mA
DOUT
Addition of note 4: Transient current. Spike current duration inferior to 300ns.
Tested wafer disclaimer
chapter added
2/15
2
STV7618
1 - BLOCK DIAGRAM
CLK
F/R
BS
P1 16bit Shift register
P2 16bit Shift register
P91
P92
A1
A2
P3 16bit Shift register
P4 16bit Shift register
P93
P94
A3
A4
P5 16bit Shift register
P6 16bit Shift register
P95
P96
A5
A6
Latch
VSSLOG
STB
POC
Q1 Q2 Q3 Q4 Q5 Q6
Q94 Q95 Q96
VSSSUB
VCC
&
&
&
&
&
&
&
&
BLK
STV7618
VSSP
OUT1
OUT96
VPP
3/15
STV7618
2 - DIE PIN OUT / DIE DESCRIPTION
OUT57
OUT40
y
0/0
x
OUT95
OUT2
OUT1
VPP
VPP
VSSP
VSSP
OUT96
VPP
VPP
VSSP
VSSP
4/15
STV7618
3 - PADS DIMENSIONS (in µm)/ PADS POSITIONS
The reference is the centre of the die (x=0, y=0)
TOP SIDE from left to right
BOTTOM SIDE from right to left
Centre: Centre:
Name
Centre:
X
Size:x
SIze: y
Name
Centre:Y
Size:x
SIze: y
X
Y
OUT56 -774.478 2700.96
OUT55 -671.288 2700.96
OUT54 -568.098 2700.96
OUT53 -464.907 2700.96
OUT52 -361.718 2700.96
OUT51 -258.528 2700.96
OUT50 -155.338 2700.96
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
VSSLOG 773.542 -2701.045
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
CLK
F/R
POC
VCC
STB
BLK
A1
670.352 -2701.045
567.162 -2701.045
463.972 -2701.045
360.782 -2701.045
258.442 -2701.045
155.252 -2701.045
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
-52.147 2700.96
51.042 2700.96
52.062
-2701.045
A2
-51.128 -2701.045
-154.318 -2701.045
-257.508 -2701.045
-360.698 -2701.045
-463.888 -2701.045
154.232 2700.96
257.422 2700.96
360.612 2700.96
463.802 2700.96
566.992 2700.96
670.267 2700.96
773.458 2700.96
A3
A4
A5
A6
VSSSUB -567.078 -2701.045
BS -670.352 -2701.045
VSSLOG -773.542 -2701.045
5/15
STV7618
RIGHT SIDE from top to bottom
LEFT SIDE from bottom to top
Centre:
Centre:
Name
Centre:Y
Size:x
SIze: y
Name
Centre:Y
Size:x
SIze: y
X
X
OUT40
OUT39
OUT38
OUT37
OUT36
OUT35
OUT34
OUT33
OUT32
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
892.670 1950.792
892.670 1847.602
892.670 1744.327
892.670 1641.138
892.670 1537.947
892.670 1434.757
892.670 1331.568
892.670 1228.378
892.670 1125.188
892.670 1021.998
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
VSSP
VSSP
VPP
-892.670 -2486.208
-892.670 -2383.018
-892.670 -2279.912
-892.670 -2176.722
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
VPP
OUT96 -892.670 -2073.702
OUT95 -892.670 -1970.512
OUT94 -892.670 -1867.322
OUT93 -892.670 -1764.132
OUT92 -892.670 -1660.942
OUT91 -892.670 -1557.752
OUT90 -892.670 -1454.562
OUT89 -892.670 -1351.372
OUT88 -892.670 -1248.182
OUT87 -892.670 -1144.992
OUT86 -892.670 -1041.802
OUT85 -892.670 -938.612
OUT84 -892.670 -835.422
OUT83 -892.670 -732.232
OUT82 -892.670 -629.042
OUT81 -892.670 -525.852
OUT80 -892.670 -422.662
OUT79 -892.670 -319.472
OUT78 -892.670 -216.282
OUT77 -892.670 -113.092
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
892.670
918.807
815.618
712.428
609.238
506.048
402.857
299.668
196.478
93.288
-9.902
-113.092
-216.282
-319.472
-422.662
-525.852
-629.042
-732.232
-835.422
-938.612
OUT76 -892.670
OUT75 -892.670
OUT74 -892.670
OUT73 -892.670
OUT72 -892.670
OUT71 -892.670
OUT70 -892.670
OUT69 -892.670
OUT68 -892.670
OUT67 -892.670
-9.902
93.288
196.478
299.668
402.857
506.048
609.238
712.428
815.618
918.807
892.670 -1041.802
892.670 -1144.992
892.670 -1248.182
892.670 -1351.372
892.670 -1454.562
892.670 -1557.752
892.670 -1660.942
892.670 -1764.132
892.670 -1867.322
892.670 -1970.512
892.670 -2073.702
OUT8
OUT7
OUT6
OUT66 -892.670 1021.998
OUT65 -892.670 1125.188
OUT64 -892.670 1228.378
OUT63 -892.670 1331.568
OUT62 -892.670 1434.757
OUT61 -892.670 1537.947
OUT5
OUT4
OUT3
OUT2
OUT1
6/15
STV7618
Centre:
X
Centre:
X
Name
Centre:Y
Size:x
SIze: y
Name
Centre:Y
Size:x
SIze: y
VPP
VPP
892.670 -2176.722
892.670 -2279.912
892.670 -2383.018
892.670 -2486.208
90
90
90
90
75
75
75
75
OUT60 -892.670 1641.138
OUT59 -892.670 1744.327
OUT58 -892.670 1847.602
OUT57 -892.670 1950.792
90
90
90
90
75
75
75
75
VSSP
VSSP
7/15
STV7618
4 - DATA BUS CONFIGURATION
BS F/R Input
Data Shift
CLK
01
02
03
04
05
06
...
11
12
13
14
15
16
A1
A2
A3
A4
A5
A6
Out
Out
Out
Out
Out
Out
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
For-
ward
L
L
L
Shift
A1
A2
A3
A4
A5
A6
Out
Out
Out
Out
Out
Out
91
92
93
94
95
96
85
86
87
88
89
90
79
80
81
82
83
84
73
74
75
76
77
78
67
68
69
70
71
72
61
62
63
64
65
66
31
32
33
34
35
36
25
26
27
28
29
30
19
20
21
22
23
24
13
14
15
16
17
18
07
08
09
10
11
12
01
02
03
04
05
06
Re-
verse
H
Shift
CLK
01
02
03
04
05
06
...
27
28
29
30
31
32
A1
A2
A3
Out
Out
Out
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
For-
ward
H
H
L
A1
A2
A3
Out
Out
Out
94
95
96
91
92
93
88
89
90
85
86
87
82
83
84
79
80
81
16
17
18
13
14
15
10
11
12
07
08
09
04
05
06
01
02
03
Re-
verse
H
This table describes the position of the first data sampled by the first rising edge of the CLK signal. For the
first configuration described in the above table, (BS = “L” and F/R= “L”), data on A1 bus sampled by the
1st clock pulse is applied on Output1. After 16 clock pulses this data will be shifted to Output 91.
8/15
STV7618
5 - PIN DESCRIPTION
Symbol
OUT(01-96)
VSSP
Function
Description
Output
Ground
Supply
Input
Power output
Ground of power outputs
VPP
High voltage supply of power outputs
Blanking input
BLK
POC
Input
Power output control input
Selection of shift direction
Selection of 3/6 bits shift register
5V logic supply
F/R
Input
BS
Input
VCC
Supply
Ground
Ground
Input
VSSLOG
VSSSUB
CLK
Logic ground
Substrate ground
Clock of data shift register
Latch of data to outputs
Shift register input for BS = “L”
Shift register input for BS = “H”
STB
Input
IN (A1-A6)
IN (A1-A3)
Input
Input
9/15
STV7618
6 - CIRCUIT DESCRIPTION
STV7618 includes all the logic and power circuits
necessary to drive column electrodes of a Plasma
Display Panel (P. D. P.). Binary values of each pix-
el of the displayed line are loaded into the shift reg-
ister by a 6 bits wide (A1 - A6) or 3 bits wide (A1 -
A3) data bus depending on the configuration of the
BS input pin. Data is shifted at each low to high
transition of the CLK clock.
The maximum frequency of the shift clock is
40MHz. This leads to an equivalent 240 MHz seri-
al shift register for a 6 x 16 bits arrangement.
When the STB signal is Low, data are transferred
from the shift register to the latch and power output
stages.
All the output data are kept memorised and held in
the latch stage when the latch input STB is pulled
high.
The forward /reverse (F/R) input is used to select
the direction of the shift register.
Vsssub and Vsslog must be connected as close as
possible to the logical reference ground of the ap-
plication.
The BS input is used to configure the shift register
either in 3 x 32 bits or in 6 x 16 bits.
In case of a 3bits arrangement, A1, A2 and A3
data bus input pins are used. The 3 shift registers
are loaded with 32 clock pulses. A4, A5 and A6
data bus input pins are at high impedance status.
STV7618 is supplied with a 5 volt power supply. All
the logic inputs can be driven either by 5V CMOS
logic, or by 3.3V CMOS logic.
Table 1: Shift register truth table
Input
Shift register function
BS
X
F/R
L
CLK
rise
Output Q
Forward shift
Steady
X
L
H or L
rise
X
H
H
X
Reverse shift
Steady
X
H or L
X
H
L
3 bits shift register
6 bits shift register
X
X
Table 2: Power output truth table
Qn
X
STB
BLK
L
POC
X
Driver Output
Comments
X
X
H
L
all L
all H
Qn
L
Output at low level
Output at high level
Data latched
X
H
L
X
H
H
L
H
H
Data copied
H
L
H
H
H
Data copied
Qn+1 = A1, Qn+2 = A2, Qn+3 = A3, Qn+4 = A4, Qn+5 = A5, Qn+6 = A6, n = [0,6,12,18,...,90]
and BS = “L”
10/15
STV7618
7 - ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Parameter
Value
-0.3, +7
Unit
V
Logic supply range
Driver supply range
Vpp
-0.3, +90
-0.3, Vcc+0.3
-150 / +150
-200 / +300
125
V
Vin
Logic input voltage range
V
Ipout
Idout
Tjmax
Tstg
Driver Output Current ( Note 1) ( Note 3) ( Note 4)
Diode Output Current ( Note 2) ( Note 3) ( Note 4)
Maximum junction temperature
mA
mA
°C
°C
°C
V
Storage temperature range
-50, +150
-20, +85
Toper
Vout
Operating ambient temperature
Output power voltage range
-0.3, +90
Note 1 Through one power output (all power outputs).
Note 2 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal than
Tjmax.
Note 3 These parameters are measured during ST’s internal qualification which includes temperature characterisation
on standard batches and on corners batches of the process. These parameters are not tested on the parts.
Note 4 Transient current. Spike current duration inferior to 300ns.
11/15
STV7618
ELECTRICAL CHARACTERISTICS
(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vss = 0V, Tamb = 25°C, FCLK = 40 MHz, unless otherwise specified)
Symbol
SUPPLY
Vcc
Parameter
Min
Typ
Max
Unit
Logic supply voltage
4.50
5
5.5
100
-
V
µA
mA
µA
V
Icc
Logic supply current (Note 5)
-
-
Iccl
Logic Dynamic Supply Current (FCLK=20Mhz) (Note 6)
Logic Supply Current (Vih=2.0V)
20
Icc
500
750
70
Vpp
Power output supply voltage - DC mode
Power output supply voltage - AC mode
15
15
Vpp
75
V
Power output supply current
(steady outputs)
Ipph
-
-
100
µA
OUTPUT
OUT1-OUT96
Power output high level (voltage drop versus Vpp)
@Ipouth = - 25mA and Vpp = 70V
Vpouth
Vpoutl
Vdouth
-
-
11
8
16
13
2
V
V
V
V
Power output low level
@ Ipoutl = + 25mA
Output diode voltage drop
@ Idouth = + 30mA (Note 7)
-
1
Output diode voltage drop
@ Idoutl = - 30mA (Note 7)
Vdoutl
-2
-1
-
INPUT
CLK, F/R, STB, POC, BLK, BS, A1-A6
Vih
Vil
Iih
Input high level
2.0
-
-
-
-
-
0.9
5
V
Input low level
-
-
-
V
High level input current (Vih >=2.0V)
Low level input current (Vil = 0v)
Input capacitance (Note 8)
µA
µA
pF
Iil
5
Cin
15
Note 5: Logic input levels compatible with 5V CMOS logic
Note 6: All data inputs are commuted at 10MHz
Note 7: see Figure 2.Test configuration page15
Note 8: This parameter is measured during ST’s internal qualification which includes temperature characterization on
standard and corner batches of the process. This parameter is not tested on the part.
12/15
STV7618
AC TIMING REQUIREMENTS
(Vcc = 4.5v to 5.5v, T amb = -20 to +85°C, input signals max leading edge & trailing edge (tr,tf) = 5ns)
Symbol
Parameter
Min
25
10
10
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t
Data clock period
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK
t
Duration of CLK pulse at high level
WHCLK
t
Duration of CLK pulse at low level
WLCLK
t
Set-up time of data input before low to high clock transition
Hold-time of data input after low to high clock transition
Hold-time of STB after low to high clock transition
STB low level pulse duration
SDAT
t
5
HDAT
t
5
HSTB
t
10
5
STB
t
STB set-up time before CLK rise
SSTB
AC TIMING CHARACTERISTICS
(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb = 25°C, FCLK = 40MHz,)
( Vilmax = 0.2Vcc, Vihmin = 0.8Vcc)
Symbol
Parameter
Min
Typ
Max
Unit
Delay of power output change after CLK transition
t
t
PHL1
PLH1
- high to low
- low to high
-
-
35
30
100
100
ns
ns
Delay of power output change after STB transition
t
t
PHL2
PLH2
- high to low
- low to high
30
25
95
95
ns
ns
-
Delay of power output change after BLK, POC transition
t
t
PHL3
PLH3
- high to low
- low to high
25
20
90
90
ns
ns
-
t
Power output rise time (Note 9)
Power output fall time (Note 9)
50
50
90
200
200
ns
ns
R OUT
t
120
F OUT
Note 9: one output among 96, loading capacitor CL = 50pF, other outputs at low level
13/15
STV7618
Figure 1. AC Characteristics Waveform
t
CLK
t
t
WLCLK
WHCLK
“1”
CLK
“0”
“1”
t
t
HDAT
SDAT
50%
50%
A INPUT
“0”
t
t
STB
HSTB
“1”
“0”
STB
50%
50%
t
SSTB
t
t
PHL2
PHL1
“1”
90%
10%
90%
10%
OUTn
“0”
t
t
PLH1
PLH2
“1”
(POC=”L”)
50%
50%
BLK
“0”
“1”
t
t
PLH3
PHL3
OUTn
90%
90%
10%
10%
“0”
t
t
F OUT
R OUT
14/15
STV7618
Figure 2. Test configuration
VPP
V
VPP VSSP
=
=
SSP
VDOUTH
IDOUTH
VDOUTL
IDOUTL
VSSP
VSSP
Output sinking current as positive value, sourcing current as negative value
8 - TESTED WAFER DISCLAIMER
All wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for
a period of ninety (90) days from the delivery date.
We remind you that it is the customer’s responsibility to test and qualify their application in which the die
is used. ST Microelectronics is ready to support the customer when qualifying the product.
15/15
STV7618
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under
any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel -Italy - Japan
- Malaysia - Malta-Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
16/15
3
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DC PLASMA DISPLAY DRIVER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
STMICROELECTR
STV7619DU
64 OUTPUT PLASMA DISPLAY PANEL SCAN DRIVER WITH 100MA/1A SOURCE/SINK OUTPUT MOS AND 120V ABSOLUTE MAXIMUM SUPPLY
ETC
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