STV8130AD [STMICROELECTRONICS]
ADJUSTABLE AND +3.3 V DUAL VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS; 可调， + 3.3V双电压带关闭和复位功能稳压器
| 型号： | STV8130AD |
| 厂家： | 
ST |
| 描述： | ADJUSTABLE AND +3.3 V DUAL VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS |
| 文件： | 总12页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
STV8130AD
ADJUSTABLE AND +3.3 V DUAL VOLTAGE REGULATOR
WITH DISABLE AND RESET FUNCTIONS
PRELIMINARY DATA
FEATURES
■ Input Voltage Range: 5 V to 18 V
■ Output Currents up to 750 mA
■ Fixed Precision Output 1 Voltage: 3.3 V ±2%
■ Adjustable Output 2 Voltage: 2.8 to 16 V
■ Output 1 with Reset Function
■ Output 2 with Disable Function by TTL Input
■ Short-circuit Protection at both Outputs
■ Thermal Protection
SIP9 (Plastic Package)
ORDER CODE: STV8130A#
■ Low Dropout Voltage
DESCRIPTION
The STV8130A# and STV8130D# are monolithic
dual positive voltage regulators designed to provide
a fixed precision output voltage of 3.3 V and an
adjustable voltage between 2.8 and 16 V for
currents up to 750 mA.
An internal reset circuit generates a reset pulse
when the voltage of Output 1 drops below the
regulated voltage value.
DIP16 (8 + 8)
ORDER CODE: STV8130D#
Output 2 can be disabled via the TTL input.
Short-circuit and thermal protections are included.
INPUT1
GROUND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
9
8
7
6
5
4
3
2
1
OUTPUT1
OUTPUT2
PROGRAM
RESET
GROUND
DISABLE
INPUT2
DELAY CAPACITOR
DISABLE
GROUND
GROUND
GROUND
GROUND
GROUND
RESET
DELAY CAPACITOR
INPUT2
INPUT1
PROGRAM
OUTPUT2
OUTPUT1
GROUND
GROUND
10
9
Tab is connected to GROUND
September 2003
1/12
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STV8130AD
TABLE OF CONTENTS
Chapter 1
GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Chapter 2
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Absolute Maximum Ratings ................................................................................................4
Thermal Data ......................................................................................................................4
Electrical Characteristics ......................................................................................................4
2.1
2.2
2.3
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
APPLICATION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
POWER DISSIPATION AND LAYOUT INDICATIONS . . . . . . . . . . . . . . . . . . . . . .8
PACKAGE MECHANICAL DATA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2/12
STV8130AD
GENERAL INFORMATION
1
GENERAL INFORMATION
Figure 1: STV8130A# Block Diagram
DELAY CAPACITOR
3
RESET
6
9
Reference
INPUT1
1
Regulator 1
Regulator 2
OUTPUT1
Protection
OUTPUT2
INPUT2
2
4
8
7
DISABLE
PROGRAM
5
GROUND
Figure 2: STV8130D# Block Diagram
DELAY CAPACITOR
3
5
8
7
RESET
Reference
INPUT1
1
Regulator 1
OUTPUT1
Protection
OUTPUT2
PROGRAM
INPUT2
2
4
Regulator 2
DISABLE
6
Pins 9 to 16
GROUND
3/12
ELECTRICAL CHARACTERISTICS
STV8130AD
2
ELECTRICAL CHARACTERISTICS
2.1
Absolute Maximum Ratings
Symbol
Parameter
DC Input Voltage at pins INPUT1 and INPUT2
Disable Input Voltage at pin DISABLE
Output Voltage at pin RESET
Output Currents
Value
Unit
V
20
20
V
V
V
IN
V
V
DIS
20
RST
I
Internally Limited
Internally Limited
-65 to +150
0 to +150
OUT1,2
P
Power Dissipation
t
T
Storage Temperature
°C
°C
STG
T
Junction Temperature
J
2.2
Thermal Data
Symbol
Parameter
Value
Unit
STV8130A#
STV8130D#
Thermal Resistance
(Junction-to-Case)
9
15
R
°C/W
thJC
1
STV8130A#
STV8130D#
50
56
Thermal Resistance
R
°C/W
thJA
(Junction-to-Ambient)
T
Maximum Recommended Junction Temperature
Operating Free Air Temperature Range
140
°C
°C
J
T
0 to +70
OPER
1. Mounted on board. For more information, refer to Section 5.
2.3
Electrical Characteristics
TAMB = 25° C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified.
Symbol
Parameter
Output Voltage
Test Conditions
Min.
Typ.
Max.
Unit
V
I
I
I
= 10 mA
= 10 mA
= 750 mA
3.23
2.8
3.30
3.37
16.0
1.4
V
V
V
OUT1
OUT1
OUT2
V
Output Voltage
Dropout Voltage
OUT2
V
IO1,2
OUT1,2
6 V < V
< 12 V
12 V < V < 18 V
IN2
IN1
50
100
V
Line Regulation
Load Regulation
mV
mV
O1,2LI
I
= 200 mA
OUT1,2
5 mA < I
5 mA < I
< 600 mA
< 600 mA
100
200
OUT1
OUT2
V
O1,2LO
4/12
STV8130AD
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Quiescent Current
Test Conditions
Min.
Typ.
Max.
Unit
I
= 10 mA, OUTPUT2
OUT1
I
2
mA
Q
Disabled
1
V
K = V
, I
≥ 50 mA
K - 0.4
20
K - 0.25
50
K - 0.1
75
V
Reset Threshold Voltage
O1RST
OUT1 OUT1
V
t
Reset Threshold Hysteresis
See circuit description.
mV
RTH
C = 100 nF
e
Reset Pulse Delay
25
ms
RD
See circuit description.
V
I
= 5 mA
= 10 V
Saturation Voltage in Reset Condition
Leakage Current in Normal Condition
0.4
10
V
RL
RESET
I
V
RESET
µA
RH
∆V0 106
K0 = ------------------------
∆T V0
K
Output Voltage Thermal Drift
100
ppm/°C
OUT1, 2
T = 0 to + 125°C
J
V
V
= 7 V, V
= 10 V
IN1
IN2
2
1.6
1.0
I
Short Circuit Output Current
A
OUT1,2SC
= 16 V
IN1,2
V
Disable Voltage when pin DISABLE is High (OUTPUT2 active)
Disable Voltage when pin DISABLE is Low (OUTPUT2 disabled)
2
V
V
DISH
V
0.8
2
DISL
I
0 V < V
< 7 V
DIS
Disable Bias Current
-100
µA
V
DIS
V
Reference Voltage at PROGRAM Pin
2.44
145
REF
T
Junction Temperature for Thermal Shutdown
°C
JSD
1. This reset signal is activated by a decrease of V
voltage which can be due to an overload of pin OUT1
OUT1
or by a lack of Input Voltage (V ).
IN1
2. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption
of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent
short-circuit protection is only guaranteed for input voltages up to 16 V.
5/12
CIRCUIT DESCRIPTION
STV8130AD
3
CIRCUIT DESCRIPTION
The STV8130A# and STV8130D# are dual-voltage regulators with Reset and Disable functions.
The two regulation parts are supplied from a single voltage reference circuit trimmed by zener
zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin
INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not supplied.
The adjustable voltage of pin OUTPUT2 (VOUT2) is defined by output bridge resistors (R1, R2): the
values of these resistors are calculated to obtain, with the targetted value for VOUT2, the reference
voltage (VREF = 2.44 V) on the median point connected to pin PROGRAM.
The output stages are designed using a Darlington configuration with a typical dropout voltage of
1.2 V.
The Disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin
DISABLE.
The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1 - 0.25 V
(3.05 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the
reset output immediately switches to low. This drop can be caused by a parasitic loading condition
on pin OUTPUT1 or by a too low value of VIN (short powering off). When the voltage at pin
OUTPUT1 exceeds VOUT1 - 0.2 V (3.1 V Typ.), the VCe voltage increases linearly to the reference
voltage (VREF = 2.44 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4.
Ce × 2.44V
tRD = ----------------------------
10µA
Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second
comparator "b" has a large hysteresis (1.84 V).
Figure 3: Reset Diagram
10 µA
RESET
b
V
a
50
-
+
REF
+
-
OUTPUT1
3
REG
Ce
V
0.6V
REF
V
= 2.44 V
REF
Figure 4: Internal Reset Voltages
V
OUT1
K
V
O1RST
V
RTH
RESET
K = Actual Value of V
OUT1
t
t
RD
Power Off
RD
Power On
6/12
STV8130AD
APPLICATION DIAGRAMS
4
APPLICATION DIAGRAMS
Figure 5: STV8130A# Typical Application
RESET
R1 + R2
VO2 = VREF--------------------
Ce
0.1 µF
R1
6
3
R1 Value (typ.) = 10 kΩ
DELAY
CAPACITOR
RESET
V
= 2.44 V
REF
INPUT1
OUTPUT1
VIN1
1
2
9
8
VOUT1
STV8130A#
OUTPUT2
VIN2
VOUT2
INPUT2
GROUND DISABLE PROGRAM
5
4
7
C4
R2
C1
C2
C3
DISABLE
R1
C1 to C4 = 10 µF
Figure 6: STV8130D# Typical Application
RESET
R1 + R2
VO2 = VREF--------------------
Ce
0.1 µF
R1
5
3
R1 Value (typ.) = 10 kΩ
DELAY
CAPACITOR
RESET
V
= 2.44 V
REF
INPUT1
OUTPUT1
VIN1
1
2
8
7
VOUT1
STV8130D#
VIN2
OUTPUT2
VOUT2
INPUT2
DISABLE PROGRAM
GROUND
4
6
C4
R2
C1
C2
C3
DISABLE
R1
C1 to C4 = 10 µF
7/12
POWER DISSIPATION AND LAYOUT INDICATIONS
STV8130AD
5
POWER DISSIPATION AND LAYOUT INDICATIONS
The power is mainly dissipated by the two device buffers. It can be calculated by the equation:
P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2
The following table lists the different RthJA values of these packages with or without a heat sink and
the corresponding maximum power dissipation assuming:
● Maximum Ambient Temperature = 70° C
● Maximum Junction Temperature = 140° C
R
in °C/W
P
in W
Device
Heat Sink
thJA
MAX
1.4
3.5
No
Yes
No
50
20
STV8130A#
56 to 40
32
1.25 to 1.75
2.2
STV8130D#
Yes
Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP16 Package without Heat Sink
To optimize the thermal conductivity of the copper
layer and the exchanges with the air, the solder
must cover the maximum amount of this area.
60
55
50
Test Board with
“On Board” square heat sink area.
45
40
6
0
2
4
8
10
12
Copper area (cm²) (35 µm plus solder) Board is face-down
Figure 8: Metal plate mounted near the STV8130D# for heat sinking
Top View
Bottom View
8/12
STV8130AD
PACKAGE MECHANICAL DATA
6
PACKAGE MECHANICAL DATA
Figure 9: 9-Pin Plastic Single In Line Package
mm
Inches
Typ.
Dim.
Min.
Typ.
Max.
Min.
Max.
A
a1
B
7.1
3
0.280
0.118
0.976
2.7
0.106
24.8
b1
b3
C
0.5
0.020
0.85
1.6
0.033
0.063
3.3
0.130
0.017
0.052
c1
c2
D
0.43
1.32
21.2
0.835
d1
e
14.5
2.54
0.571
0.100
0.800
e3
L
20.32
3.1
1.122
L1
L2
L3
M
3
0.116
0.693
17.6
0.25
0.010
3.2
1
0.126
0.039
N
9/12
PACKAGE MECHANICAL DATA
STV8130AD
Figure 10: 16-Pin Plastic Dual In-Line Package, 300-mil Width
mm
Inches
Typ.
Dim.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
0.015
0.115
0.014
3.30
4.95
0.56
1.78
0.36
19.69
0.130
0.195
0.022
0.070
0.014
0.775
b2
c
1.52
0.25
19.18
2.54
6.35
3.30
0.060
0.010
0.755
0.100
0.250
0.130
0.20
0.008
0.735
D
18.67
e
E1
L
6.10
2.92
7.11
3.81
0.240
0.115
0.280
0.150
10/12
STV8130AD
REVISION HISTORY
7
REVISION HISTORY
Revision
Main Changes
Date
1.8
1.9
2.0
2.1
General Update; DISABLE pin renamed DISABLE (function remains unchanged).
Thermal Data updated.
August 2001
September 2001
September 2001
October 2001
Addition of DIP16 package.
Thermal Data updated. Figure 1 and Figure 2 updated.
Order code changed from STV8130A and STV8130D to STV8130A# and
STV8130D#. Update of V
values in Chapter 2.3: Electrical Characteristics
2.2
31 January 2002
O1RST
on page 4.
11/12
STV8130AD
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without
express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - All Rights Reserved
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12/12
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