VND5E004A-E [STMICROELECTRONICS]

Double 4 m high-side driver with analog current sense for automotive applications;
VND5E004A-E
型号: VND5E004A-E
厂家: ST    ST
描述:

Double 4 m high-side driver with analog current sense for automotive applications

文件: 总43页 (文件大小:974K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
VND5E004A-E  
VND5E004ASP30-E  
Double 4 mhigh-side driver with analog current sense  
for automotive applications  
Datasheet - production data  
– Protection against loss of ground and loss  
of V  
CC  
– Overtemperature shutdown with auto  
restart (thermal shutdown)  
PQFN - 12x12 Power lead-less  
MultiPowerSO-30  
– Inrush current active management by  
power limitation  
– Reverse battery protection with self switch-  
on of the Power MOSFET  
Features  
Max transient supply voltage  
Operating voltage range  
VCC  
41 V  
– Electrostatic discharge protection  
VCC 4.5 to 28 V  
Applications  
Max on-state resistance (per ch.) RON  
4 m  
90 A  
2 µA(1)  
Current limitation (typ)  
Off-state supply current  
ILIMH  
IS  
All types of resistive, inductive and capacitive  
loads  
Suitable for power management applications  
1. Typical value with all loads connected  
Description  
AEC-Q100 qualified  
General  
The VND5E004A-E and VND5E004ASP30-E are  
double channel high-side drivers manufactured  
using ST proprietary VIPower M0-5 technology  
– Very low standby current  
– 3.0 V CMOS compatible inputs  
®
and housed in PQFN-12x12 power lead-less and  
MultiPowerSO-30 packages. The devices are  
designed to drive 12 V automotive grounded  
loads, and to provide protection and diagnostics.  
They also implement a 3 V and 5 V   
– Optimized electromagnetic emissions  
– Very low electromagnetic susceptibility  
– Compliant with European directive  
2002/95/EC  
– Very low current sense leakage  
CMOS-compatible interface for use with any  
microcontroller.  
Diagnostic functions  
– Proportional load current sense  
The devices integrate advanced protective  
functions such as load current limitation, inrush  
and overload active management by power  
limitation, overtemperature shut-off with auto-  
restart and overvoltage active clamp. A dedicated  
analog current sense pin is associated with every  
output channel providing enhanced diagnostic  
functions including fast detection of overload and  
short-circuit to ground through power limitation  
indication, overtemperature indication, short-  
– High current sense precision for wide  
currents range  
– Diagnostic enable pin  
– Off-state open-load detection  
– Output short to V detection  
CC  
– Overload and short to ground (power  
limitation) indication  
– Thermal shutdown indication  
Protection  
– Undervoltage shutdown  
– Overvoltage clamp  
circuit to V diagnosis and on-state and off-state  
CC  
open-load detection. The current sensing and  
diagnostic feedback of the whole device can be  
disabled by pulling the DE pin low to share the  
external sense resistor with similar devices.  
– Load current limitation  
– Self limiting of fast thermal transients  
January 2017  
DocID17359 Rev 5  
1/43  
This is information on a product in full production.  
www.st.com  
Contents  
VND5E004A-E, VND5E004ASP30-E  
Contents  
1
2
Block diagram and pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1  
2.2  
2.3  
2.4  
2.5  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
3.1  
3.2  
3.3  
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
3.3.1  
Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 26  
3.4  
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 27  
4
5
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
4.1  
4.2  
MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
PQFN - 12x12 power lead-less thermal data . . . . . . . . . . . . . . . . . . . . . . 31  
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
5.1  
5.2  
5.3  
5.4  
MultiPowerSO-30 package information . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
PQFN - 12x12 power lead-less package information . . . . . . . . . . . . . . . . 36  
MultiPowerSO-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
PQFN - 12x12 power lead-less packing information . . . . . . . . . . . . . . . . 39  
6
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
2/43  
DocID17359 Rev 5  
VND5E004A-E, VND5E004ASP30-E  
List of tables  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Suggested connections for unused and non connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Current sense (8 V < V < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
CC  
Open-load detection (8 V < V < 18 V; V = 5 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
CC  
DE  
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Thermal parameters for MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Thermal parameters for PQFN - 12x12 power lead-less . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
PQFN - 12x12 power lead-less mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
DocID17359 Rev 5  
3/43  
3
List of figures  
VND5E004A-E, VND5E004ASP30-E  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Configuration diagram (not to scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Open-load off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Delay response time between rising edge of output current and rising edge of   
current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Figure 8.  
Figure 9.  
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
/I vs I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
I
OUT SENSE  
OUT  
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 12. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 13. Intermittent overload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 14. Off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 15. Short to V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
CC  
Figure 16. T evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
J
Figure 17. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 20. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 21. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 23. On-state resistance vs T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
case  
Figure 24. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
CC  
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 26. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 27.  
I
vs T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
LIMH  
case  
Figure 28. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 29. DE high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 30. DE clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 31. DE low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 33. Current sense and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 34. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 35. MultiPowerSO-30 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 28  
Figure 37. MultiPowerSO-30 thermal impedance junction ambient single pulse (one channel ON) . . 29  
Figure 38. Thermal fitting model of a double channel HSD in MultiPowerSO-30 . . . . . . . . . . . . . . . . 29  
Figure 39. 12x12 Power lead-less package PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 40. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 31  
Figure 41. PQFN - 12x12 power lead-less package thermal impedance junction ambient   
single pulse (one channel ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 42. Thermal fitting model of a double channel HSD in PQFN - 12x12 power lead-less . . . . . 32  
Figure 43. MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Figure 44. PQFN - 12x12 power lead-less package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Figure 45. MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Figure 46. PQFN - 12x12 power lead-less tray shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
4/43  
DocID17359 Rev 5  
VND5E004A-E, VND5E004ASP30-E  
List of figures  
Figure 47. PQFN - 12x12 power lead-less tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . 40  
DocID17359 Rev 5  
5/43  
5
Block diagram and pin configurations  
VND5E004A-E, VND5E004ASP30-E  
1
Block diagram and pin configurations  
Figure 1. Block diagram  
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Table 1. Pin functions  
Function  
Name  
VCC  
OUT1,2  
GND  
Battery connection  
Power output  
Ground connection  
Voltage controlled input pin with hysteresis, CMOS compatible, controls  
output switch state  
IN1,2  
CS1,2  
DE  
Analog current sense pin; delivers a current proportional to the load current  
Active high diagnostic enable pin  
6/43  
DocID17359 Rev 5  
 
 
 
VND5E004A-E, VND5E004ASP30-E  
Block diagram and pin configurations  
Figure 2. Configuration diagram (not to scale)  
1 NC  
2 NC  
12  
11  
10  
9
8
7
6
3 NC  
4 GND  
5 DE  
15  
16  
6 CS 1  
7 CS 2  
8 IN 1  
9 IN 2  
10 NC  
11 NC  
PQFN -12x12 Power  
lead-less  
13  
14  
(bottom view)  
5
4
3
2
12 NC  
13 FOR TEST ONLY  
14 VCC  
1
15 OUT 2  
16 OUT 1  
1
30  
V
V
CC  
CC  
NC  
OUT 1  
OUT 1  
OUT 1  
OUT 1  
OUT 1  
OUT 1  
NC  
FOR TEST ONLY  
NC  
NC  
GND  
DE  
CS 1  
CS 2  
IN 1  
V
CC  
Heat Slug1  
MultiPowerSO-30  
(top view)  
OUT 2  
OUT 2  
OUT 2  
OUT 2  
OUT 2  
OUT 2  
IN 2  
NC  
FOR TEST ONLY  
NC  
15  
16  
V
V
CC  
CC  
Table 2. Suggested connections for unused and non connected pins  
Connection /  
Current  
sense  
NC(1)  
Output  
Input  
DE  
For test only  
X
pin  
Floating  
Not allowed  
X
X
X
X
X
Through  
1 kresistor  
Not  
allowed  
Through10k  
Through  
10 kresistor  
To ground  
Not allowed  
resistor  
1. Not connected  
DocID17359 Rev 5  
7/43  
42  
 
 
Electrical specifications  
VND5E004A-E, VND5E004ASP30-E  
2
Electrical specifications  
Figure 3. Current and voltage conventions  
IS  
VCC  
VCC  
IDE  
IOUT1,2  
DE  
OUTPUT1,2  
IIN1,2  
VDE  
VOUT1,2  
INPUT1,2  
ISENSE1,2  
CURRENT  
SENSE1,2  
VIN1,2  
GND  
VSENSE1,2  
IGND  
2.1  
Absolute maximum ratings  
Applying stress which exceeds the ratings listed in Table 3: Absolute maximum ratings may  
cause permanent damage to the device. These are stress ratings only and operation of the  
device at these or any other conditions above those indicated in the Operating sections of  
this specification is not implied. Exposure to the conditions in this section for extended  
periods may affect device reliability.  
Table 3. Absolute maximum ratings  
Symbol  
Parameter  
Value  
Unit  
V
DC supply voltage  
28  
V
V
CC  
V
Transient supply voltage (T < 400 msR  
Reverse DC supply voltage  
DC output current  
> 0.5   
41  
16  
CCPK  
load  
-V  
V
CC  
I
Internally limited  
70  
A
OUT  
-I  
Reverse DC output current  
DC input current  
A
OUT  
I
-1 to 10  
-1 to 10  
mA  
mA  
IN  
I
DC diagnostic enable input current  
DE  
V
- 41  
V
V
CC  
V
Current sense maximum voltage (V > 0 V)  
CSENSE  
CC  
+V  
CC  
Maximum switching energy (single pulse)  
E
600  
mJ  
(L = 0.3 mH; R = 0 ; V = 13.5 V; T = 150 °C;  
jstart  
MAX  
L
bat  
I
= I (Typ.))  
OUT  
limL  
Electrostatic discharge  
V
V
2000  
750  
V
V
ESD  
(Human Body Model: R = 1.5 k C = 100 pF)  
Charge device model (CDM-AEC-Q100-011)  
ESD  
8/43  
DocID17359 Rev 5  
 
 
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
Table 3. Absolute maximum ratings (continued)  
Parameter  
Junction operating temperature  
Storage temperature  
Symbol  
Value  
Unit  
T
-40 to 150  
-55 to 150  
°C  
°C  
j
T
STG  
2.2  
Thermal data  
Table 4. Thermal data  
Parameter  
Maximum value  
MultiPowerSO-30 12x12 PLLP  
Symbol  
Unit  
Thermal resistance junction-case (with one  
channel ON)  
R
0.35  
0.35  
°C/W  
°C/W  
thj-case  
(1)  
(2)  
R
Thermal resistance junction-ambient  
58  
39  
thj-amb  
1. PCB FR4 area 58 mm x 58 mm, PCB thickness 2 mm, Cu thickness 35 µm, minimum pad layout  
2. PCB FR4 area 78 mm x 78 mm, PCB thickness 2 mm, Cu thickness 35 µm, minimum pad layout  
2.3  
Electrical characteristics  
Values specified in this section are for 8 V < V < 24 V, -40 °C < T < 150 °C, unless  
CC  
j
otherwise stated.  
Table 5. Power section  
Test conditions  
Symbol  
Parameter  
Min. Typ. Max. Unit  
V
Operating supply voltage  
Undervoltage shutdown  
4.5  
13  
28  
V
V
CC  
V
3.5  
4.5  
USD  
Undervoltage shutdown  
hysteresis  
V
0.5  
3
V
USDhyst  
I
I
I
= 15 A; T = 25 °C  
m  
m  
m  
OUT  
OUT  
OUT  
j
(1)  
R
On-state resistance  
= 15 A; T = 150 °C  
6
6
ON  
j
= 15 A; V = 5 V; T = 25 °C  
CC  
j
R
in reverse battery  
V
= -13 V; I  
= -15 A;  
DSon  
CC  
OUT  
R
3
m  
ON REV  
condition  
T = 25 °C  
j
V
V
clamp voltage  
I
= 20 mA; I  
= 0 A  
41  
46  
52  
5
V
clamp  
CC  
CC  
OUT1,2  
Standby V = 0 V; V = 13 V;  
T = 25 °C; V = 0;  
DE  
CC  
2
µA  
j
IN  
V
= V  
= 0 V  
OUT  
SENSE  
Off-state; V = 13 V; V = 5 V;  
CC  
DE  
I
Supply current  
S
T = 25 °C;  
10  
15  
6
µA  
j
V
= V  
= V = 0 V  
SENSE  
IN  
OUT  
On-state; V = 13 V; V = 5 V;  
CC  
DE  
3.5  
mA  
V
= 5 V; I  
= 0 A  
IN  
OUT  
DocID17359 Rev 5  
9/43  
42  
 
 
 
 
Electrical specifications  
Symbol  
VND5E004A-E, VND5E004ASP30-E  
Table 5. Power section (continued)  
Test conditions  
Parameter  
Min. Typ. Max. Unit  
V
V
= 0 V or V = 0 V; V  
= 0 V;  
IN  
DE  
OUT  
0
0
0.01  
3
5
µA  
µA  
= 13 V; T = 25 °C  
CC  
j
(1)  
I
Off-state output current  
L(off)  
V
V
= 0 V or V = 0 V; V  
DE  
= 0 V;  
IN  
OUT  
= 13 V; T = 125 °C  
CC  
j
1. For each channel  
Table 6. Switching (V = 13 V; T = 25 °C)  
CC  
j
Symbol  
Parameter  
Test conditions  
Min.  
Typ.  
Max. Unit  
t
Turn-on delay time  
Turn-off delay time  
R = 0.87 (see Table 6)  
25  
35  
µs  
µs  
d(on)  
L
t
R = 0.87 (see Table 6)  
d(off)  
L
See  
Figure 26  
(dV  
(dV  
/dt)  
Turn-on voltage slope R = 0.87   
Vµs  
Vµs  
mJ  
OUT  
on  
off  
L
See  
Figure 28  
/dt)  
Turn-off voltage slope R = 0.87   
OUT  
L
Switching energy  
W
R = 0.87 (see Table 6)  
5.4  
2.3  
ON  
L
losses during t  
won  
Switching energy  
losses during t  
W
R = 0.87 (see Table 6)  
mJ  
OFF  
L
woff  
Table 7. Logic inputs  
Test conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
V
Input low level voltage  
Low level input current  
Input high level voltage  
High level input current  
Input hysteresis voltage  
0.9  
V
µA  
V
IL1,2  
I
V
V
= 0.9 V  
= 2.1 V  
1
IL1,2  
IN  
IN  
V
2.1  
IH1,2  
IH1,2  
I
10  
7
µA  
V
V
0.25  
5.5  
I(hyst)1,2  
I
I
= 1 mA  
V
IN  
V
Input clamp voltage  
ICL1,2  
= -1 mA  
-0.7  
V
IN  
V
DE low level voltage  
DE low level current  
DE high level voltage  
DE high level current  
DE hysteresis voltage  
0.9  
V
DEL  
I
V
V
= 0.9 V  
= 2.1 V  
1
µA  
V
DEL  
IN  
IN  
V
2.1  
DEH  
DEH  
I
10  
7
µA  
V
V
0.25  
5.5  
DE(hyst)  
I
I
= 1 mA  
V
DE  
V
DE clamp voltage  
DECL  
= -1 mA  
-0.7  
V
DE  
10/43  
DocID17359 Rev 5  
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
(1)  
Table 8. Protections and diagnostics  
Symbol  
Parameter  
Test conditions  
= 13 V  
Min.  
Typ.  
Max.  
Unit  
V
65  
90  
130  
130  
A
A
CC  
I
Short circuit current  
limH  
5 V < V < 24 V  
CC  
Shortcircuitcurrent  
during thermal  
cycling  
I
V
= 13 V; T < T < T  
TSD  
40  
A
limL  
CC  
R
j
Shutdown  
temperature  
T
150  
175  
200  
°C  
°C  
°C  
TSD  
T
Reset temperature  
T
+1  
T
+5  
R
RS  
RS  
Thermal reset of  
STATUS  
T
135  
RS  
Thermal hysteresis  
T
7
°C  
V
HYST  
(T  
-T )  
TSD  
R
Turn-off output  
voltage clamp  
V
I
I
= 2 A; V = 0; L = 6 mH  
V
-28 V -32 V -35  
DEMAG  
OUT  
IN  
CC CC CC  
= 1 A;  
OUT  
Output voltage drop  
limitation  
V
T = -40 °C to 150 °C  
(see Figure 8)  
25  
mV  
ON  
j
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related  
diagnostic signals must be used together with a proper software strategy. If the device is subjected to  
abnormal conditions, this software must limit the duration and number of activation cycles.  
Table 9. Current sense (8 V < V < 18 V)  
CC  
Symbol  
Parameter  
Test conditions  
= 5 A; V = 4 V; V = 5 V;  
Min.  
Typ. Max. Unit  
I
OUT  
SENSE  
DE  
T = -40 °C...150 °C  
K
I
I
/I  
11420 17580 23740  
j
0
OUT SENSE  
T = 25 °C...150 °C  
12130 17580 23030  
j
I
= 10 A; V  
= 4 V; V = 5 V;  
OUT  
SENSE  
DE  
T = -40 °C...150 °C  
K
/I  
11830 16910 21990  
12680 16910 21140  
%
%
%
j
1
OUT SENSE  
T = 25 °C...150 °C  
j
Current sense ratio I  
drift  
=10 A; V  
T = -40 °C to 150 °C  
= 4 V; V = 5 V;  
(1)  
OUT  
SENSE  
DE  
dK /K  
-14  
14  
1
1
2
3
j
I
= 15 A; V  
= 4 V; V = 5 V;  
OUT  
SENSE  
DE  
T = -40 °C...150 °C  
K
I
/I  
OUT SENSE  
11760 16110 20460  
13040 16110 19180  
j
2
T = 25 °C...150 °C  
j
Current sense ratio I  
= 15 A; V  
= 4 V;  
(1)  
(1)  
OUT  
DE  
SENSE  
dK /K  
-10  
10  
2
drift  
V
= 5 V; T = -40 °C to 150 °C  
j
I
= 30 A; V  
= 4 V; V = 5 V;  
OUT  
SENSE  
DE  
T = -40 °C...150 °C  
K
I
/I  
13040 15520 18000  
13810 15520 17230  
j
3
OUT SENSE  
T = 25 °C...150 °C  
j
Current sense ratio I  
= 30 A; V  
= 4 V;  
OUT  
DE  
SENSE  
dK /K  
-5  
5
3
drift  
V
= 5 V; T = -40 °C to 150 °C  
j
DocID17359 Rev 5  
11/43  
42  
 
 
Electrical specifications  
Symbol  
VND5E004A-E, VND5E004ASP30-E  
Table 9. Current sense (8 V < V < 18 V) (continued)  
CC  
Parameter  
Test conditions  
Min.  
Typ. Max. Unit  
I
V
= 0 A; V  
= 0 V; V = 0 V;  
OUT  
SENSE DE  
0
1
2
1
µA  
µA  
µA  
= 0 V; T = -40 °C...150 °C  
IN  
j
Analog sense  
leakage current  
I
V
= 0 A; V  
= 0 V; V = 5 V;  
OUT  
SENSE DE  
I
0
0
SENSE0  
= 5 V; T = -40 °C...150 °C  
IN  
j
I
V
= 15 A; V  
= 0 V;  
OUT  
SENSE  
= 0 V; V = 5 V;  
DE  
IN  
Open-load on-  
state current  
detection threshold  
V
= 5 V; 8 V < V < 18 V  
IN  
CC  
I
10  
5
150 mA  
OL  
I
I
= 5 µA  
SENSE  
Max analog sense  
output voltage  
= 45 A; V  
= 0 V;  
CSD  
OUT  
V
V
V
SENSE  
R
= 3.9 k  
SENSE  
Analog sense  
V
output voltage in  
V
=13 V; R  
=13 V; V  
= 3.9 k  
8
9
SENSEH  
SENSEH  
CC  
SENSE  
SENSE  
(2)  
fault condition  
Analog sense  
I
output current in  
V
= 5 V  
mA  
CC  
(2)  
fault condition  
V
I
< 4 V, 5 A < I < 30 A;  
Delay response  
time from rising  
edge of DE pin  
SENSE  
out  
= 90 % of I  
t
50  
100  
20  
µs  
µs  
µs  
µs  
SENSE  
SENSE max  
DSENSE1H  
(see Figure 4)  
V
I
< 4 V, 5 A < I < 30 A;  
out  
Delay response  
time from falling  
edge of DE pin  
SENSE  
= 10 % of I  
t
t
5
SENSE  
SENSE max  
DSENSE1L  
(see Figure 4)  
V
I
< 4 V, 5 A < I < 30 A;  
Delay response  
time from rising  
edge of INPUT pin  
SENSE  
out  
SENSE max  
= 90 % of I  
200  
100  
600  
250  
SENSE  
DSENSE2H  
V
= 5 V (see Figure 4)  
DE  
V
I
< 4 V, 5 A < I < 30 A;  
Delay response  
time from falling  
edge of INPUT pin  
SENSE  
out  
= 10 % of I  
t
SENSE  
SENSE max  
DSENSE2L  
V
= 5 V (see Figure 4)  
DE  
1. Parameter guaranteed by design; it is not tested.  
2. Fault condition includes: power limitation, overtemperature and open-load off-state detection.  
Table 10. Open-load detection (8 V < V < 18 V; V = 5 V)  
CC  
DE  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
Open-load off-state voltage  
detection threshold  
V
= 0 V, V = 5 V;  
IN  
DE  
V
2
4
V
OL  
See Figure 5  
Output short circuit to V  
CC  
t
V
= 5 V; See Figure 5  
180  
1200 µs  
DSTKON  
DE  
detection delay at turn off  
V
V
= 0 V; V  
= 0 V;   
IN  
SENSE  
Off-state output current at  
= 5 V;  
I
-120  
90  
µA  
DE  
L(off2)r  
V
= 4 V  
OUT  
V
rising from 0 V to 4 V  
OUT  
12/43  
DocID17359 Rev 5  
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
Min. Typ. Max. Unit  
Table 10. Open-load detection (8 V < V < 18 V; V = 5 V) (continued)  
CC  
DE  
Symbol  
Parameter  
Test conditions  
V
V
= 0 V; V  
= 5 V;  
= V  
;
IN  
SENSE  
SENSEH  
Off-state output current at  
= 2 V  
I
-50  
90  
20  
20  
µA  
µs  
µs  
DE  
L(off2)f  
V
OUT  
V
falling from V to 2 V  
OUT  
CC  
V
V
= 4 V; V = 0 V;  
= 5 V;  
Delay response from output  
td_vol rising edge to V rising  
OUT  
IN  
DE  
SENSE  
edge in open-load  
V
= 90 % of V  
SENSEH  
SENSE  
V
V
= 2 V; V = 0V;  
IN  
= 5 V;  
Delay response from output  
OUT  
td_voh falling edge to V falling  
DE  
SENSE  
edge in open-load  
V
= 10 % of V  
SENSEH  
SENSE  
Figure 4. Current sense delay characteristics  
INPUT  
DE  
LOAD CURRENT  
SENSE CURRENT  
tDSENSE2H tDSENSE1L  
tDSENSE1H  
tDSENSE2L  
Figure 5. Open-load off-state delay timing  
OUTPUT STUCK AT V  
CC  
V
IN  
V
> V  
OUT  
OL  
V
SENSEH  
V
CS  
t
DSTKON  
DocID17359 Rev 5  
13/43  
42  
 
 
Electrical specifications  
VND5E004A-E, VND5E004ASP30-E  
Figure 6. Switching characteristics  
V
OUT  
t
t
Woff  
Won  
90%  
80%  
dV  
/dt  
dV  
/dt  
OUT (off)  
OUT (on)  
10%  
t
t
f
r
t
INPUT  
t
t
d(on)  
d(off)  
t
Figure 7. Delay response time between rising edge of output current and rising edge  
of current sense (CS enabled)  
VIN  
tDSENSE2H  
t
t
t
IOUT  
IOUTMAX  
90% IOUTMAX  
ISENSE  
ISENSEMAX  
90% ISENSEMAX  
14/43  
DocID17359 Rev 5  
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
Figure 8. Output voltage drop limitation  
- V  
V
CC  
OUT  
Tj = 150 °C  
Tj = 25 °C  
Tj = -40 °C  
Von  
I
OUT  
Von/Ron(T)  
Figure 9. I  
/I  
vs I  
OUT SENSE  
OUT  
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Legend:  
A: Max, T = -40 °C to 150 °C  
D: Min, T = 25 °C to 150 °C  
j
j
B: Max, T = 25 °C to 150 °C  
E: Min, T = -40 °C to 150 °C  
j
j
C: Typical, T = -40 °C to 150 °C  
j
DocID17359 Rev 5  
15/43  
42  
 
 
Electrical specifications  
VND5E004A-E, VND5E004ASP30-E  
Figure 10. Maximum current sense ratio drift vs load current  
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1. Parameter guaranteed by design; it is not tested.  
Table 11. Truth table  
Sense  
Conditions  
Enable  
Input  
Output  
(VDE=5V)(1)  
H
H
L
H
L
H
0
Normal operation  
Nominal  
H
H
L
H
L
L
0
Overtemperature  
Undervoltage  
Overload  
V
SENSEH  
H
H
L
H
L
L
0
0
H
H
H
H
X (no power limitation)  
Cycling (power limitation)  
Nominal  
V
SENSEH  
Short circuit to GND (power  
limitation)  
H
H
L
H
L
L
0
V
V
V
SENSEH  
Open-load off-state  
(with external pull up)  
H
L
H
SENSEH  
Short circuit to V (external  
H
H
L
H
H
H
CC  
SENSEH  
< Nominal  
pull up disconnected)  
Negative output voltage  
clamp  
H
L
L
0
1. If the VDE is low, the SENSE output is at a high impedance; its potential depends on leakage currents and  
external circuit.  
16/43  
DocID17359 Rev 5  
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
Table 12. Electrical transient requirements (part 1/3)  
ISO 7637-2:  
2004(E)  
Test levels(1)  
Number of  
pulses or  
test times  
Burst cycle/pulse  
repetition time  
Delays and  
impedance  
III  
IV  
Test pulse  
5000  
pulses  
1
-75 V  
-100 V  
0.5 s  
5 s  
5 s  
2 ms, 10   
50 µs, 2   
5000  
pulses  
2a  
+37 V  
+50 V  
0.2 s  
3a  
3b  
-100 V  
+75 V  
-150 V  
+100 V  
1h  
1h  
90 ms  
90 ms  
100 ms  
100 ms  
0.1 µs, 50   
0.1 µs, 50   
100 ms, 0.01  
4
-6 V  
-7 V  
1 pulse  
1 pulse  
(2)  
5b  
+65 V  
+87 V  
400 ms, 2   
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.  
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy  
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy  
along the time and to transfer a part of it to the load.  
Table 13. Electrical transient requirements (part 2/3)  
ISO 7637-2:  
2004(E)  
Test level results(1)  
III  
IV  
Test pulse  
1
C
C
C
C
C
C
C
C
C
C
C
C
2a  
3a  
3b  
4
(2) (3)  
5b  
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b  
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy  
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy  
along the time and to transfer a part of it to the load.  
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in Table 3.  
Table 14. Electrical transient requirements (part 3/3)  
Class  
Contents  
C
All functions of the device are performed as designed after exposure to disturbance.  
One or more functions of the device are not performed as designed after exposure  
to disturbance and cannot be returned to proper operation without replacing the  
device.  
E
DocID17359 Rev 5  
17/43  
42  
 
 
 
Electrical specifications  
VND5E004A-E, VND5E004ASP30-E  
2.4  
Waveforms  
Figure 11. Normal operation  
INPUT  
IOUT  
Nominal load  
Nominal load  
VSENSE  
VDE  
Figure 12. Overload or short to GND  
INPUT  
Power Limitation  
ILimH  
>
Thermal cycling  
ILimL  
>
IOUT  
VSENSE  
VDE  
18/43  
DocID17359 Rev 5  
 
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
Figure 13. Intermittent overload  
INPUT  
Overload  
ILimH  
>
Nominal load  
ILimL  
>
IOUT  
VSENSEH  
>
VSENSE  
VDE  
Figure 14. Off-state open-load with external circuitry  
INPUT  
VOUT  
VOUT > VOL  
VOL  
IOUT  
VSENSEH  
tDSTK (on)  
>
VSENSE  
VDE  
DocID17359 Rev 5  
19/43  
42  
 
 
Electrical specifications  
VND5E004A-E, VND5E004ASP30-E  
Figure 15. Short to V  
CC  
Resistive  
Short to V  
Hard  
Short to V  
CC  
CC  
INPUT  
VOUT  
VOUT > VOL  
VOL  
IOUT  
tDSTK (on)  
tDSTK (on)  
VDE  
Figure 16. T evolution in overload or short to GND  
J
INPUT  
Self-limitation of fast thermal transients  
TTSD  
TR  
THYST  
TJ_START  
TJ  
Power Limitation  
ILimH  
>
< ILimL  
IOUT  
20/43  
DocID17359 Rev 5  
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
2.5  
Electrical characteristics curves  
Figure 17. Off-state output current  
Figure 18. High level input current  
,ORII >Q $ @  
,LKꢀ>X$@  
ꢉꢄꢈ  
ꢑꢇꢇꢇ  
ꢊꢇꢇꢇ  
ꢈꢇꢇꢇ  
ꢉꢇꢇꢇ  
ꢌꢇꢇꢇ  
ꢂꢇꢇꢇ  
ꢃꢇꢇꢇ  
7JOꢄꢅꢆꢇꢁ7  
ꢌꢄꢈ  
ꢂꢄꢈ  
ꢃꢄꢈ  
ꢇꢄꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
ꢎꢈꢇ ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ ꢃꢇꢇ ꢃꢂꢈ ꢃꢈꢇ ꢃꢑꢈ  
7Fꢀ>ƒ&@  
7 >ƒ&@  
F
*$3*&)7ꢇꢃꢇꢊꢃ  
*$3*&)7ꢇꢃꢇꢊꢇ  
Figure 19. Input clamp voltage  
Figure 20. Input low level voltage  
9LOꢀ>9@  
9LFOꢀ>9@  
ꢊꢄꢋ  
ꢊꢄꢊ  
ꢊꢄꢉ  
ꢊꢄꢂ  
ꢃꢄꢋ  
ꢃꢄꢊ  
ꢃꢄꢉ  
ꢃꢄꢂ  
*JOꢄꢅꢁN"  
ꢈꢄꢋ  
ꢈꢄꢊ  
ꢈꢄꢉ  
ꢈꢄꢂ  
ꢇꢄꢋ  
ꢇꢄꢊ  
ꢇꢄꢉ  
ꢇꢄꢂ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
7Fꢀ>ƒ&@  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢊꢂ  
*$3*&)7ꢇꢃꢇꢊꢌ  
Figure 21. Input high level voltage  
Figure 22. Input hysteresis voltage  
9LK\VWꢀ>9@  
9LKꢀ>9@  
ꢇꢄꢐ  
ꢇꢄꢋ  
ꢇꢄꢑ  
ꢇꢄꢊ  
ꢇꢄꢈ  
ꢇꢄꢉ  
ꢇꢄꢌ  
ꢇꢄꢂ  
ꢇꢄꢃ  
ꢌꢄꢈ  
ꢂꢄꢈ  
ꢃꢄꢈ  
ꢇꢄꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
7Fꢀ>ƒ&@  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢊꢈ  
*$3*&)7ꢇꢃꢇꢊꢉ  
DocID17359 Rev 5  
21/43  
42  
 
 
 
 
 
 
 
Electrical specifications  
VND5E004A-E, VND5E004ASP30-E  
Figure 23. On-state resistance vs T  
Figure 24. On-state resistance vs V  
case  
CC  
5RQꢀ>P2KP@  
5RQꢀ>P2KP@  
ꢈꢇ  
ꢉꢈ  
ꢉꢇ  
ꢌꢈ  
ꢌꢇ  
ꢂꢈ  
ꢂꢇ  
ꢃꢈ  
ꢃꢇ  
5Dꢄꢅꢁꢈꢀ¡$  
5Dꢄꢅꢁꢆꢈ¡$  
,RXW ꢀꢃꢈ$  
9FF ꢀꢃꢌ9  
5Dꢄꢅꢆꢈ¡$  
5Dꢄꢅꢉꢊꢀ¡$  
ꢃꢇ  
ꢃꢈ  
ꢂꢇ  
ꢂꢈ  
ꢌꢇ  
ꢌꢈ  
ꢉꢇ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
9FFꢀ>9@  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢊꢊ  
*$3*&)7ꢇꢃꢇꢊꢑ  
Figure 25. Undervoltage shutdown  
Figure 26. Turn-on voltage slope  
9XVGꢀ>9@  
ꢅG9RXWꢍGWꢆ2Qꢀ>9ꢍPV@  
ꢃꢊ  
ꢃꢉ  
ꢃꢂ  
ꢃꢇ  
ꢃꢇꢇꢇ  
ꢐꢇꢇ  
ꢋꢇꢇ  
ꢑꢇꢇ  
ꢊꢇꢇ  
ꢈꢇꢇ  
ꢉꢇꢇ  
ꢌꢇꢇ  
ꢂꢇꢇ  
ꢃꢇꢇ  
9FF ꢀꢃꢌ9  
5O ꢀꢇꢄꢋꢑȍ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
7Fꢀ>ƒ&@  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢊꢐ  
*$3*&)7ꢇꢃꢇꢊꢋ  
Figure 27. I  
vs T  
Figure 28. Turn-off voltage slope  
LIMH  
case  
,OLPKꢀ>$@  
ꢅG9RXWꢍGWꢆ2IIꢀ>9ꢍPV@  
ꢃꢇꢇ  
ꢃꢇꢇꢇ  
ꢐꢇꢇ  
ꢋꢇꢇ  
ꢑꢇꢇ  
ꢊꢇꢇ  
ꢈꢇꢇ  
ꢉꢇꢇ  
ꢌꢇꢇ  
ꢂꢇꢇ  
ꢃꢇꢇ  
ꢐꢇ  
ꢋꢇ  
ꢑꢇ  
ꢊꢇ  
ꢈꢇ  
7DDꢄꢅꢁꢋ7  
9FF ꢀꢃꢌ9  
5O ꢀꢇꢄꢋꢑȍ  
ꢉꢇ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
7Fꢀ>ƒ&@  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢑꢃ  
*$3*&)7ꢇꢃꢇꢑꢇ  
22/43  
DocID17359 Rev 5  
 
 
 
 
 
 
VND5E004A-E, VND5E004ASP30-E  
Electrical specifications  
Figure 29. DE high level voltage  
Figure 30. DE clamp voltage  
9GHKꢀ>9@  
9GHFOꢀ>9@  
ꢃꢇ  
ꢌꢄꢈ  
*JOꢄꢅꢁN"  
ꢂꢄꢈ  
ꢃꢄꢈ  
ꢇꢄꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
7Fꢀ>ƒ&@  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢑꢌ  
*$3*&)7ꢇꢃꢇꢑꢂ  
Figure 31. DE low level voltage  
9GHOꢀ>9@  
ꢌꢄꢈ  
ꢂꢄꢈ  
ꢃꢄꢈ  
ꢇꢄꢈ  
ꢎꢈꢇ  
ꢎꢂꢈ  
ꢂꢈ  
ꢈꢇ  
ꢑꢈ  
ꢃꢇꢇ  
ꢃꢂꢈ  
ꢃꢈꢇ  
ꢃꢑꢈ  
7Fꢀ>ƒ&@  
*$3*&)7ꢇꢃꢇꢑꢉ  
DocID17359 Rev 5  
23/43  
42  
 
 
 
Application information  
VND5E004A-E, VND5E004ASP30-E  
3
Application information  
Figure 32. Application schematic  
ꢒꢈ9  
9&&  
5SURW  
'(  
'
OG  
5SURW  
-&8  
,1387  
287387  
5SURW  
&855(17ꢀ6(16(  
*1'  
56(16(  
&
H[W  
("1($'5ꢀꢀꢆꢂꢊ  
3.1  
MCU I/Os protection  
When negative transients are present on the V line, the control pins are pulled negative to  
CC  
approximately -1.5 V.  
ST suggests the insertion of resistors (R ) in the lines to prevent the microcontroller I/O  
prot  
pins from latching up.  
The values of these resistors provide a compromise between the leakage current of the  
microcontroller, the current required by the HSD I/Os (input levels compatibility) and the  
latch-up limit of the microcontroller I/Os.  
-V  
/I  
R  
(V  
-V ) / I  
OHµC IH IHmax  
CCpeak latchup  
prot  
Calculation example:  
For V = - 1.5V and I  
20mA; V 4.5V  
OHµC  
CCpeak  
latchup  
75  R  
240k.  
prot  
Recommended values: R  
=10kC  
=10nF  
EXT  
prot  
3.2  
Load dump protection  
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the  
ld  
V
maximum rating. The same applies if the device is subject to transients on the V  
CCPK  
CC  
line that are greater than the ones shown in the Table 12.  
24/43  
DocID17359 Rev 5  
 
 
 
 
VND5E004A-E, VND5E004ASP30-E  
Application information  
3.3  
Current sense and diagnostic  
The current sense pin performs a double function (see Figure 33: Current sense and  
diagnostics):  
Current mirror of the load current in normal operation, delivering a current  
proportional to the load current according to a known ratio K .  
X
The current I  
can be easily converted to a voltage V  
by means of an  
SENSE  
SENSE  
external resistor R  
. Linearity between I  
and V  
is ensured up to 5V  
SENSE  
OUT  
SENSE  
minimum (see parameter V  
in Table 9: Current sense (8 V < V < 18 V)). The  
SENSE  
CC  
current sense accuracy depends on the output current (refer to current sense electrical  
characteristics in Table 9).  
Diagnostic flag in fault conditions, delivering a fixed voltage V  
up to a  
SENSEH  
maximum current I  
in case of the following fault conditions (refer to   
SENSEH  
Table 11: Truth table):  
Power limitation activation  
Overtemperature  
Short to V in off-state  
CC  
Open-load in off-state with additional external components.  
A logic level low on the DE pin simultaneously sets all the current sense pins of the device in  
a high impedance state, thus disabling the current monitoring and diagnostic detection. This  
feature allows multiplexing of the microcontroller analog inputs by sharing the sense  
resistance and ADC line among different devices.  
Figure 33. Current sense and diagnostics  
938  
9%$7  
9&&  
0DLQꢀ026Q  
ꢁꢂ9  
38B&0'  
2YHUWHPSHUDWXUH  
,
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2/ꢀ2))  
,
6(16(+  
92/  
,
,
/RIIꢃU  
3ZUB/LP  
287Q  
/RIIꢃI  
,1387Q  
96(16(+  
'(  
&855(17ꢀ  
6(16(Q  
*1'  
/RDG  
53527  
7RꢀX&ꢀ$'&  
53'  
56(16(  
96(16(  
("1($'5ꢀꢀꢆꢂꢈ  
DocID17359 Rev 5  
25/43  
42  
 
 
Application information  
VND5E004A-E, VND5E004ASP30-E  
3.3.1  
Short to V and off-state open-load detection  
CC  
Short to VCC  
A short circuit between V and output is indicated by the relevant current sense pin set to  
CC  
V
during the device off-state. Little or no current is delivered by the current sense  
SENSEH  
during the on-state depending on the nature of the short circuit.  
Off-state open-load with external circuitry  
Detection of an open-load in off mode requires an external pull-up resistor (R ) connecting  
PU  
the output to a positive supply voltage (V ).  
PU  
It is preferable that V be switched off during the module standby mode to avoid an  
PU  
increase in the overall standby current consumption in normal conditions, that is, when the  
load is connected.  
An external pull down resistor (R ) connected between output and GND is mandatory to  
PD  
avoid misdetection in case of floating outputs in off-state (see Figure 33: Current sense and  
diagnostics).  
R
must be selected in order to ensure V  
< V  
unless pulled up by the external  
OLmin  
PD  
OUT  
circuitry:  
V
= R  
I  
V  
= 2V  
OLmin  
OUT  
PD L(off2)f  
Pull-up_OFF  
R
22Kis recommended.  
PD  
For proper open-load detection in off-state, the external pull-up resistor must be selected  
according to the following formula:  
R
V  
R  
R I  
PD L(off2)r  
PD  
PU  
PU  
V
= ------------------------------------------------------------------------------------- = V  
= 4V  
OLmax  
OUT  
R
+ R  
Pull-up_ON  
PU  
PD  
For the values of V  
,V  
, I  
and I  
see Table 10: Open-load detection  
OLmin OLmax L(off2)r  
L(off2)f  
(8 V < V < 18 V; V = 5 V).  
CC  
DE  
26/43  
DocID17359 Rev 5  
 
VND5E004A-E, VND5E004ASP30-E  
Application information  
3.4  
Maximum demagnetization energy (VCC = 13.5 V)  
Figure 34. Maximum turn-off current versus inductance  
ꢀꢁꢁ  
ꢀꢁ  
"
#
$
ꢀꢁ  
ꢀꢁꢁ  
("1($'5ꢀꢁꢀꢂꢈ  
/ꢂꢃP+ꢄ  
A: T  
= 150 °C single pulse  
jstart  
B: T  
C: T  
= 100 °C repetitive pulse  
= 125 °C repetitive pulse  
jstart  
jstart  
9,1ꢓꢀ,/  
'HPDJQHWL]DWLRQ  
'HPDJQHWL]DWLRQ  
'HPDJQHWL]DWLRQ  
W
*$3*&)7ꢇꢇꢇꢉꢋ  
1. Values are generated with RL = 0   
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed  
the temperature specified above for curves A and B.  
DocID17359 Rev 5  
27/43  
42  
 
 
Package and PC board thermal data  
VND5E004A-E, VND5E004ASP30-E  
4
Package and PC board thermal data  
4.1  
MultiPowerSO-30 thermal data  
Figure 35. MultiPowerSO-30 PC board  
1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias, FR4  
area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 70 µm (front and back side), copper  
areas: from minimum pad layout to 16 cm2).  
Figure 36.  
R
vs PCB copper area in open box free air condition (one channel ON)  
thj-amb  
RTHj_amb(°C/W)  
60  
55  
50  
45  
40  
35  
0
1
2
3
4
5
PCB Cu heatsink area (cm^2)  
28/43  
DocID17359 Rev 5  
 
 
 
 
VND5E004A-E, VND5E004ASP30-E  
Package and PC board thermal data  
Figure 37. MultiPowerSO-30 thermal impedance junction ambient single pulse (one  
channel ON)  
=7+ꢀꢅƒ&ꢍ:ꢆ  
 
)RRWSULQW  
ꢃꢇ  
ꢉꢀFP  
ꢃꢇ  
ꢇꢄꢃ  
ꢇꢄꢇꢃ  
ꢇꢄꢇꢇꢇ ꢇꢄꢇꢇ  
ꢇꢄꢇꢃ  
ꢇꢄꢃ  
ꢃꢇ  
ꢃꢇ  
 
7LPHꢀꢅVꢆ  
*$3*&)7ꢇꢃꢇꢑꢊ  
Figure 38. Thermal fitting model of a double channel HSD in MultiPowerSO-30  
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded  
protection functions (power limitation or thermal cycling during thermal shutdown) are not triggered.  
Equation 1: Pulse calculation formula  
Z
= R  
  + Z  
1   
TH  
TH  
= t T  
THtp  
where  
p
DocID17359 Rev 5  
29/43  
42  
 
 
Package and PC board thermal data  
VND5E004A-E, VND5E004ASP30-E  
Table 15. Thermal parameters for MultiPowerSO-30  
Area/island (cm2)  
Footprint  
4
R1 (°C/W)  
R2 (°C/W)  
R3 (°C/W)  
R4 (°C/W)  
R5 (°C/W)  
R6 (°C/W)  
R7 (°C/W)  
R8 (°C/W)  
C1 (W.s/°C)  
C2 (W.s/°C)  
C3 (W.s/°C)  
C4 (W.s/°C)  
C5 (W.s/°C)  
C6 (W.s/°C)  
C7 (W.s/°C)  
C8 (W.s/°C)  
0.05  
0.3  
0.5  
1.3  
14  
44.7  
0.05  
0.3  
23.7  
0.005  
0.008  
0.01  
0.3  
0.6  
5
11  
0.005  
0.008  
30/43  
DocID17359 Rev 5  
 
VND5E004A-E, VND5E004ASP30-E  
Package and PC board thermal data  
4.2  
PQFN - 12x12 power lead-less thermal data  
Figure 39. 12x12 Power lead-less package PC board  
1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias, FR4  
area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 µm (front and back side), copper  
areas: minimum pad layout).  
Figure 40. R  
vs PCB copper area in open box free air condition (one channel  
ON)  
thj-amb  
50  
45  
40  
35  
30  
25  
20  
0
5
10  
15  
20  
PCB Cu heatsink area (cm^ 2)  
DocID17359 Rev 5  
31/43  
42  
 
 
 
Package and PC board thermal data  
VND5E004A-E, VND5E004ASP30-E  
Figure 41. PQFN - 12x12 power lead-less package thermal impedance junction  
ambient single pulse (one channel ON)  
ꢃꢇꢇ  
)RRWWSULQW  
ꢉꢀFP  
ꢋꢀFP  
ꢃꢊꢀFP  
ꢃꢇ  
ꢇꢓꢃ  
ꢇꢓ  
ꢇꢓꢇꢃ  
ꢇꢓꢃ  
ꢃꢇ  
ꢃꢇꢇ  
ꢇꢇ  
WLPHꢀꢅVꢆ  
*$3*&)7ꢇꢃꢇꢑꢑ  
Figure 42. Thermal fitting model of a double channel HSD in PQFN - 12x12 power lead-less  
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded  
protection functions (power limitation or thermal cycling during thermal shutdown) are not triggered.  
Equation 2: pulse calculation formula  
Z
= R  
  + Z  
1   
TH  
TH  
= t T  
THtp  
where  
p
32/43  
DocID17359 Rev 5  
 
 
VND5E004A-E, VND5E004ASP30-E  
Package and PC board thermal data  
Table 16. Thermal parameters for PQFN - 12x12 power lead-less  
Area/island (cm2)  
Footprint  
4
8
16  
R1 (°C/W)  
R2 (°C/W)  
R3 (°C/W)  
R4 (°C/W)  
R5 (°C/W)  
R6 (°C/W)  
R7 (°C/W)  
R8 (°C/W)  
C1 (W.s/°C)  
C2 (W.s/°C)  
C3 (W.s/°C)  
C4 (W.s/°C)  
C5 (W.s/°C)  
C6 (W.s/°C)  
C7 (W.s/°C)  
C8 (W.s/°C)  
0.35  
0.15  
4.2  
9.6  
9.4  
10.5  
12  
9.2  
8.5  
9
9
5.5  
6
15.1  
16.7  
0.35  
0.15  
0.018  
0.015  
0.2  
1.9  
2.2  
7.3  
22  
2.32  
13.7  
25  
2.45  
20  
2.45  
11.85  
0.018  
0.015  
30  
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Package information  
VND5E004A-E, VND5E004ASP30-E  
5
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of  
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK  
specifications, grade definitions and product status are available at: www.st.com.  
®
ECOPACK is an ST trademark.  
5.1  
MultiPowerSO-30 package information  
Figure 43. MultiPowerSO-30 package outline  
Table 17. MultiPowerSO-30 mechanical data  
Millimeters  
Symbol  
Min.  
Typ.  
Max.  
A
A2  
A3  
B
2.35  
2.25  
0.1  
1.85  
0
0.42  
0.23  
17.1  
0.58  
0.32  
17.3  
C
D
17.2  
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VND5E004A-E, VND5E004ASP30-E  
Package information  
Table 17. MultiPowerSO-30 mechanical data (continued)  
Millimeters  
Typ.  
Symbol  
Min.  
Max.  
E
E1  
“e”  
F6  
F7  
F8  
L
18.85  
15.9  
1
19.15  
16.1  
16  
14.3  
5.45  
0.73  
0.8  
1.15  
10 Deg  
7 Deg  
N
S
0 Deg  
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Package information  
VND5E004A-E, VND5E004ASP30-E  
5.2  
PQFN - 12x12 power lead-less package information  
Figure 44. PQFN - 12x12 power lead-less package outline  
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VND5E004A-E, VND5E004ASP30-E  
Package information  
Table 18. PQFN - 12x12 power lead-less mechanical data  
Millimeters  
Typ.  
Symbol  
Min.  
2
Max.  
2.2  
A
A1  
b
0
0.05  
0.47  
0.35  
C
0.50  
D
11.90  
4.65  
10.45  
4.80  
4.80  
11.90  
2.15  
5.15  
1.70  
12.10  
4.95  
10.65  
5
Dh1  
Dh2  
Dh3  
Dh4  
E
5
12.10  
2.45  
5.45  
2
Eh1  
Eh2  
Eh3  
e1  
e2  
e3  
f
0.90  
3.45  
1.10  
0.50  
0.60  
f1  
L
0.75  
1.65  
0.95  
1.90  
L1  
L2  
M
0.76  
0.78  
11.10  
11.10  
11.30  
11.30  
N
v
0.1  
0.05  
0.05  
0.1  
w
y
y1  
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Package information  
VND5E004A-E, VND5E004ASP30-E  
5.3  
MultiPowerSO-30 packing information  
The devices are packed in tape and reel shipments (see Table 19: Device summary on  
page 41).  
Figure 45. MultiPowerSO-30 tape and reel shipment (suffix “TR”)  
Reel dimension  
Dimension  
mm  
1000  
Base Q.ty  
Bulk Q.ty  
A (max)  
B (min)  
1000  
330  
1.5  
C (± 0.2)  
D (min)  
13  
20.2  
32  
G (+ 2 / -0)  
N (min)  
100  
38.4  
T (max)  
Tape dimensions  
According to Electronic Industries Association (EIA)  
Standard 481 rev. A, Feb 1986  
Description  
Dimension  
mm  
Tape width  
W
32  
4
Tape Hole Spacing  
Component Spacing  
Hole Diameter  
Hole Diameter  
Hole Position  
P0 (± 0.1)  
P
24  
1.5  
2
D (± 0.1/-0)  
D1 (min)  
F (± 0.1)  
K (max)  
P1 (± 0.1)  
14.2  
2.2  
2
Compartment Depth  
Hole Spacing  
End  
Start  
Top  
cover  
tape  
No components  
500 mm min  
Components  
No components  
500 mm min  
Empty components pockets  
User direction of feed  
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VND5E004A-E, VND5E004ASP30-E  
Package information  
5.4  
PQFN - 12x12 power lead-less packing information  
The devices can be packed in tray or tape and reel shipments (see Table 19: Device  
summary).  
Figure 46. PQFN - 12x12 power lead-less tray shipment (no suffix)  
Tray information  
Parameter  
Base Q.ty  
Bulk Q.ty  
189  
945  
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Package information  
VND5E004A-E, VND5E004ASP30-E  
Figure 47. PQFN - 12x12 power lead-less tape and reel shipment (suffix “TR”)  
Tape dimensions  
Dimension  
mm  
A0 ± 0.1  
B0 ± 0.1  
K0 ± 0.1  
F ± 0.1  
E ± 0.1  
W ± 0.3  
P2 ± 0.1  
P0 ± 0.1  
P1 ± 0.1  
T ± 0.05  
D
12.30  
12.30  
2.15  
11.50  
1.75  
24  
2
4
16  
0.30  
1.50  
1.50  
D1 (min)  
Reel dimensions  
Dimension  
mm  
Base Q.ty  
Bulk Q.ty  
A (max)  
B (min)  
1500  
1500  
330  
1.5  
C (± 0.2)  
D (min)  
13  
20.2  
32  
G (+ 2 / -0)  
N (min)  
100  
38.4  
T (max)  
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VND5E004A-E, VND5E004ASP30-E  
Order codes  
6
Order codes  
Table 19. Device summary  
Order codes  
Package  
Tape and reel  
VND5E004ATR-E  
VND5E004A30TR-E  
Tray  
VND5E004A-E  
PQFN-12x12 power lead-less  
MultiPowerSO-30  
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Revision history  
VND5E004A-E, VND5E004ASP30-E  
7
Revision history  
Table 20. Document revision history  
Changes  
Date  
Revision  
20-Jul-2010  
1
Initial release.  
Updated Figure 1: Block diagram and Figure 10: Maximum current  
sense ratio drift vs load current  
07-Nov-2012  
19-Sep-2013  
2
3
Updated Disclaimer.  
Updated footnote 2 into the Table 12: Electrical transient  
requirements (part 1/3) and Table 13: Electrical transient  
requirements (part 2/3).  
25-Oct-2013  
4
– Removed all information relative to tube packing of the product  
– Modified Section 5: Package information.  
11-Jan-2017  
5
– Added AEC-Q100 qualified in the Features section  
– Minor text edits throughout the document  
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VND5E004A-E, VND5E004ASP30-E  
IMPORTANT NOTICE – PLEASE READ CAREFULLY  
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and  
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on  
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order  
acknowledgement.  
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or  
the design of Purchasers’ products.  
No license, express or implied, to any intellectual property right is granted by ST herein.  
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2017 STMicroelectronics – All rights reserved  
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