VND5T100AJ-E [STMICROELECTRONICS]
Double channel high-side driver with analog current sense for 24 V automotive applications; 模拟电流检测的双通道高侧驱动器，用于24 V汽车应用
| 型号： | VND5T100AJ-E |
| 厂家： | 
ST |
| 描述： | Double channel high-side driver with analog current sense for 24 V automotive applications |
| 文件： | 总32页 (文件大小：533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5T100AJ-E
Double channel high-side driver with analog current sense
for 24 V automotive applications
Features
Max transient supply voltage
Operating voltage range
VCC
58 V
VCC 8 to 36 V
Typ on-state resistance (per ch.)
Current limitation (typ)
RON 100 mΩ
PowerSSO-12
ILIM
IS
22 A
2 µA(1)
Off-state supply current
Application
1. Typical value with all loads connected.
All types of resistive, inductive and capacitive
loads
■ General
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliance with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
Description
The VND5T100AJ-E is a monolithic device made
using STMicroelectronics™ VIPower™
technology, intended for driving resistive or
inductive loads with one side connected to
ground. Active V pin voltage clamp protects the
CC
■ Diagnostic functions
device against low energy spikes.
– Proportional load current sense
This device integrates an analog current sense
which delivers a current proportional to the load
current.
– High current sense precision for wide range
currents
– Off-state open-load detection
Fault conditions such as overload,
– Output short to V detection
CC
overtemperature or short to V are reported via
CC
– Overload and short to ground latch-off
– Thermal shutdown latch-off
– Very low current sense leakage
the current sense pin.
Output current limitation protects the device in
overload condition. The device latches off in case
of overload or thermal shutdown.
■ Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
The device is reset by a low level pass on the fault
reset standby pin.
A permanent low level on the inputs and fault
reset standby pin disables all outputs and sets the
device in standby mode.
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Thermal shutdown
– Electrostatic discharge protection
March 2011
Doc ID 018513 Rev 1
1/32
www.st.com
1
Contents
VND5T100AJ-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . 23
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
5.3
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
7
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
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VND5T100AJ-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense (8 V < V < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 018513 Rev 1
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List of figures
VND5T100AJ-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
T
T
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
standby
reset
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Open-load off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output stuck to V detection delay time at FRSTBY activation . . . . . . . . . . . . . . . . . . . . 15
CC
Figure 10. Delay response time between rising edge of output current and rising edge of current
sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. On-state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
case
Figure 20. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
Figure 21.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LIMH
case
Figure 22. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24
Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 25
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 25
Figure 30. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 32. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
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Table 1.
Name
Pin function
Function
VCC
OUTn
GND
Battery connection
Power output
Ground connection
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
INn
CSn
Analog current sense pin, delivers a current proportional to the load current
In case of latch-off for OT/overcurrent condition, a low pulse on the FR_Stby pin is
needed to reset the channel.
FR_Stby
The device enters in standby mode if all inputs and the FR_Stby pin are low.
Doc ID 018513 Rev 1
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Block diagram and pin description
VND5T100AJ-E
Figure 2.
Configuration diagram (top view)
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Table 2.
Suggested connections for unused and not connected pins
Connection / pin Current sense
N.C.
Output
Input
FR_Stby
Floating
Not allowed
X
X
X
X
Through10 KΩ
Through
10 KΩ resistor 10 KΩ resistor
Through
To ground
X
Not allowed
resistor
6/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
2
Electrical specifications
Figure 3.
Current and voltage conventions
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2.1
Absolute maximum ratings
Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions reported in this section for extended periods may affect device
reliability. Refer also to the STMicroelectronics™ SURE program and other relevant quality
documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V
VCC
DC supply voltage
58
0.3
-VCC
Reverse DC supply voltage
V
-IGND DC reverse ground pin current
200
mA
A
IOUT
-IOUT
IIN
DC output current
Internally limited
20
Reverse DC output current
DC input current
A
-1 to 10
-1 to 1.5
200
mA
mA
mA
IFR_Stby Fault reset standby DC input current
-ICSENSE DC reverse CS pin current
VCC - 58 to
+VCC
VCSENSE Current sense maximum voltage
V
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Electrical specifications
VND5T100AJ-E
Table 3.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
Maximum switching energy
(L = 1.9 mH; Vbat = 32 V; Tjstart = 150 °C; IOUT = IlimL (Typ))
EMAX
70
mJ
Electrostatic discharge
(Human Body Model: R = 1.5 KΩ; C = 100 pF)
– INPUT
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
– CURRENT SENSE
– FR_STBY
– OUTPUT
– VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
Maximum stray inductance in short circuit
LSmax
40
µH
RL = 300 mΩ, Vbat = 32 V, Tjstart = 150 °C, IOUT = IlimHmax
2.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Maximum value
Unit
Rthj-case Thermal resistance junction-case (with one channel ON)
Rthj-amb Thermal resistance junction-ambient
3
°C/W
°C/W
See Figure 27
8/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
2.3
Electrical characteristics
8 V < V < 36 V; -40 °C < T < 150 °C, unless otherwise specified.
CC
j
.
Table 5.
Symbol
Power section
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
8
24
36
5
V
V
VUSD Undervoltage shutdown
3.5
Undervoltage shutdown
hysteresis
VUSDhyst
0.5
V
IOUT = 1.5 A; Tj = 25 °C
IOUT = 1.5 A; Tj = 150 °C
IS = 20 mA
100
RON
On-state resistance(1)
mΩ
200
70
Vclamp Clamp voltage
58
64
V
Off-state: VCC = 24 V; Tj = 25 °C;
VIN = VOUT = VSENSE = 0 V
2(2)
5(2)
µA
IS
Supply current
On-state: VCC = 24 V; VIN = 5 V;
IOUT = 0 A
4.2
6
mA
VIN = VOUT = 0 V; VCC = 24 V;
Tj = 25 °C
0
0
0.01
3
IL(off)
Off-state output current
µA
V
VIN = VOUT = 0 V; VCC = 24 V;
Tj = 125 °C
5
VF
Output - VCC diode voltage -IOUT = 1.5 A; Tj = 150 °C
0.7
1. For each channel.
2. PowerMos leakage included
(1)
Table 6.
Symbol
td(on)
td(off)
Switching
Parameter
Test conditions
RL = 16 Ω
Min. Typ. Max. Unit
Turn-on delay time
Turn-off delay time
27
38
µs
µs
RL = 16 Ω
RL = 16 Ω
RL = 16 Ω
dVOUT/dt(on) Turn-on voltage slope
dVOUT/dt(off) Turn-off voltage slope
1
V/µs
V/µs
0.65
Switching energy losses
during twon
WON
RL = 16 Ω
RL = 16 Ω
0.23
0.26
mJ
mJ
Switching energy losses
during twoff
WOFF
1. Operating conditions: VCC = 24 V; Tj = 25 °C
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Electrical specifications
VND5T100AJ-E
Table 7.
Symbol
Logic inputs
Parameter
Input low level voltage
Test conditions
Min. Typ. Max. Unit
VIL
IIL
0.9
V
µA
V
Low level input current VIN = 0.9 V
Input high level voltage
1
VIH
2.1
IIH
High level input current VIN = 2.1 V
Input hysteresis voltage
10
7
µA
V
VI(hyst)
0.25
5.5
I
IN = 1 mA
V
VICL
Input clamp voltage
IIN = -1 mA
-0.7
V
Fault_reset_standby
low level voltage
VFR_Stby_L
0.9
V
µA
V
Low level
fault_reset_standby
current
IFR_Stby_L
VFR_Stby = 0.9 V
1
Fault_reset_standby
high level voltage
VFR_Stby_H
2.1
High level
IFR_Stby_H fault_reset_standby
current
VFR_Stby = 2.1 V
10
µA
V
Fault_reset_standby
VFR_Stby (hyst)
0.25
11
hysteresis voltage
IFR_Stby = 15 mA (t < 10 ms)
IFR_Stby = -1 mA
15
24
V
V
Fault_reset_standby
VFR_Stby_CL
clamp voltage
-0.7
Overload latch-off reset
treset
time
See Figure 4
See Figure 5
2
µs
tstby
Standby delay
120
1200 µs
Figure 4.
T
definition
standby
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10/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
Figure 5.
T
definition
reset
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Table 8.
Protections and diagnostics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
CC = 24 V
16
22
30
30
A
A
IlimH
DC short circuit current
5 V < VCC < 36 V
Short circuit current
during thermal cycling
VCC = 24 V;
TR < Tj < TTSD
IlimL
6
A
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
°C
TRS + 1 TRS + 5
135
TRS
Thermal reset of status
Thermal hysteresis
(TTSD - TR)
THYST
VDEMAG
VON
7
°C
V
Turn-off output voltage
clamp
IOUT = 1.5 A; VIN = 0;
L = 6 mH
VCC - 58 VCC - 64 VCC - 70
IOUT = 50 mA;
Output voltage drop
limitation
25
mV
Tj = -40 °C...+ 150 °C
Doc ID 018513 Rev 1
11/32
Electrical specifications
VND5T100AJ-E
Table 9.
Symbol
Current sense (8 V < V < 36 V)
CC
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT = 350 mA; VSENSE = 1 V;
Tj = -40 °C...150 °C
K1
dK1/K1
K2
IOUT SENSE
/I
930 1547
1050 1547
2185
2020
Tj = 25 °C...150 °C
IOUT = 350 mA; VSENSE = 1 V;
Tj = -40 °C to 150 °C
Current sense ratio
drift
(1)
(1)
(1)
(1)
-15
15
%
%
%
%
IOUT = 0.8 A; VSENSE = 2 V;
Tj = -40 °C...150 °C
IOUT SENSE
/I
1225 1528 1835
1310 1528 1745
Tj = 25 °C...150 °C
IOUT = 0.8 A; VSENSE = 2 V;
Tj = -40 °C to 150 °C
Current sense ratio
drift
dK2/K2
K3
-12
12
IOUT = 1.5 A; VSENSE = 2 V;
Tj = -40 °C...150 °C
IOUT SENSE
/I
1340 1525 1715
1405 1525 1655
Tj = 25 °C...150 °C
IOUT = 1.5 A; VSENSE = 2 V;
Tj = -40 °C to 150 °C
Current sense ratio
drift
dK3/K3
K4
-8
8
IOUT = 6 A; VSENSE = 4 V;
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
IOUT SENSE
/I
1450 1522 1600
1475 1522 1560
IOUT = 6 A; VSENSE = 4 V;
Tj = -40 °C to 150 °C
Current sense ratio
drift
dK4/K4
-5
5
IOUT = 0 A; VSENSE = 0 V;
Analog sense
leakage current
ISENSE0
VIN = 0 V; Tj = -40 °C...150 °C
VIN = 5 V; Tj = -40 °C...150 °C
0
0
1
2
µA
µA
Max analog sense
output voltage
VSENSE
IOUT = 6 A; RSENSE = 3.9 KΩ
VCC = 24 V; RSENSE = 3.9 KΩ
5
V
V
Analog sense
VSENSEH output voltage in
7.5
8.5
9
9.5
12
fault condition(2)
Analog sense
ISENSEH output current in
fault condition(2)
VCC = 24 V; VSENSE = 5 V
4.9
mA
µs
VSENSE < 4 V, 0.07 A < IOUT < 6 A
Delay response
tDSENSE2H time from rising
edge of INPUT pin
ISENSE = 90 % of ISENSE max
100
200
(see Figure 6)
12/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
Min. Typ. Max. Unit
Table 9.
Current sense (8 V < V < 36 V) (continued)
CC
Symbol
Parameter
Test conditions
Delay response
time between rising
edge of output
current and rising
edge of current
sense
VSENSE < 4 V,
ISENSE = 90 % of ISENSEMAX,
IOUT = 90 % of IOUTMAX
ΔtDSEN
150
20
µs
µs
SE2H
IOUTMAX = 1.5 A (see Figure 11)
VSENSE < 4 V, 0.07 A < IOUT < 6 A
Delay response
tDSENSE2L time from falling
edge of INPUT pin
ISENSE = 10 % of ISENSE max
5
(see Figure 6)
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition.
Table 10. Open-load detection
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Open-load off-state
voltage detection
threshold
VIN = 0 V; 8 V < VCC < 36 V;
FR_STBY = 5 V
VOL
2
4
1800
50
V
Output short circuit to
tDSTKON VCC detection delay at
turn off
See Figure 6;
FR_STBY = 5 V
180
µs
µs
µA
Output short circuit to
tDFRSTK_ON VCC detection delay at
FRSTBY activation
See Figure 9; Input1,2 = low
VIN = 0 V; VSENSE = 0 V;
VOUT rising from 0 V to 4 V;
FR_STBY = 5 V
Off-state output current
at VOUT = 4V
IL(off2)
-120
0
VOUT = 4 V; VIN = 0 V
Delay response from
output rising edge to
VSENSE rising edge in
open-load
VSENSE = 90 % of VSENSEH
td_vol
20
µs
RSENSE = 3.9 KΩ;
FR_STBY = 5 V
Figure 6.
Current sense delay characteristics
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Doc ID 018513 Rev 1
13/32
Electrical specifications
Figure 7.
VND5T100AJ-E
Open-load off-state delay timing
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Switching characteristics
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14/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
Figure 9.
Output stuck to V detection delay time at FRSTBY activation
CC
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9&6
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Figure 10. Delay response time between rising edge of output current and rising
edge of current sense
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Doc ID 018513 Rev 1
15/32
Electrical specifications
VND5T100AJ-E
Figure 11. Output voltage drop limitation
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Figure 12. Device behavior in overload condition
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16/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
Table 11.
Truth table
Conditions
Fault reset standby
Input
Output
Sense
Standby
L
L
L
0
X
X
L
L
0
Normal operation
Overload
H
H
Nominal
X
X
L
L
0
H
H
> Nominal
X
L
L
H
H
L
0
Overtemperature / short to ground
Undervoltage
Cycling
Latched
VSENSEH
VSENSEH
H
X
X
L
0
L
H
X
L
L
H
H
H
0
Short to VBAT
VSENSEH
< Nominal
H
L
H
X
L
L
H
H
H
0
VSENSEH
0
Open-load off-state (with pull-up)
Negative output voltage clamp
H
X
L
Negative
0
Doc ID 018513 Rev 1
17/32
Electrical specifications
VND5T100AJ-E
Table 12. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test levels (1)
Number of
pulses or test
times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
Test pulse
1
2a
- 450 V
+ 37 V
- 150 V
+ 150 V
- 12 V
- 600 V
+ 50 V
- 200 V
+ 200 V
- 16 V
5000 pulses
5000 pulses
1h
0.5 s
0.2 s
5 s
1 ms, 50 Ω
50 µs, 2 Ω
5 s
3a
90 ms
90 ms
100 ms
100 ms
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
350 ms, 1 Ω
3b
1h
4
1 pulse
1 pulse
5b (2)
+ 123 V
+ 174 V
Table 13. Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test level results
III
IV
Test pulse
1
2a
C
C
C
E
C
C
C
C
C
C
E
C
C
C
3a
3b(1)
3b(2)
4
5b (3)
1. Without capacitor between VCC and GND.
2. With 10 nF between VCC and GND.
3. External load dump clamp, 58 V maximum, referred to ground.
Table 14. Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
18/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Electrical specifications
2.4
Electrical characteristics curves
Figure 13. Off-state output current
Figure 14. High level input current
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ꢆꢁꢃꢀ
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6INꢊ ꢂꢁꢆ6
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/FF STATE
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ꢂ
6## ꢊ ꢂꢃ 6
6IN ꢊ 6OUT ꢊ ꢀ
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4C ; #=
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4C ; #=
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Figure 15. Input clamp voltage
Figure 16. Input high level voltage
6IH ;6=
ꢃ
6ICL ;6=
ꢉ
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ꢋꢁꢈ
ꢋ
)INꢊ ꢆM!
ꢄꢁꢄ
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4C ; #=
ꢉꢈ
ꢆꢀꢀ
ꢆꢂꢈ
ꢆꢈꢀ
ꢆꢉꢈ
4C ; #=
'!0'#&4ꢀꢀꢀꢈꢅ
'!0'#&4ꢀꢀꢀꢄꢀ
Figure 17. Input low level voltage
Figure 18. Input hysteresis voltage
6IHYST ;6=
ꢆ
6IL ;6=
ꢂ
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ꢀꢁꢅ
ꢀꢁꢉ
ꢀꢁꢄ
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4C ; #=
4C ; #=
'!0'#&4ꢀꢀꢀꢈꢌ
'!0'#&4ꢀꢀꢀꢄꢆ
Doc ID 018513 Rev 1
19/32
Electrical specifications
VND5T100AJ-E
Figure 19. On-state resistance vs T
Figure 20. On-state resistance vs V
CC
case
2ON ;M /HM =
5RQꢈ>P 2KP @
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4Cꢊ ꢇꢃꢀ #
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6CC ;6=
ꢈꢎꢆ
ꢈꢂꢎ
ꢆ
ꢂꢎ
ꢎꢆ
ꢊꢎ
ꢃꢆꢆ
ꢃꢂꢎ
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7Fꢈ>&@
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("1($'5ꢀꢀꢀꢁꢂ
Figure 21. I
vs T
Figure 22. Turn-on voltage slope
LIMH
case
ꢍD6OUTꢎDTꢏ/N ;6ꢎUS=
ꢂ
)LIMH ;!=
ꢂꢋ
ꢆꢁꢅ
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6CCꢊ ꢂꢃ6
6CCꢊ ꢂꢃ6
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ꢀ
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ꢂꢀ
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ꢀ
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ꢉꢈ
ꢆꢀꢀ
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ꢆꢈꢀ
ꢆꢉꢈ
4C ; #=
4C ; #=
'!0'#&4ꢀꢀꢀꢄꢈ
'!0'#&4ꢀꢀꢀꢄꢃ
Figure 23. Turn-off voltage slope
ꢍD6OUTꢎDTꢏ/FF ;6ꢎUS=
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6CCꢊ ꢂꢃ6
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4C ; #=
'!0'#&4ꢀꢀꢀꢄꢄ
20/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Application information
3
Application information
Figure 24. Application schematic
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3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (R
only)
GND
This solution can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤ 600 mV / (I
).
S(on)max
GND
GND
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power dissipation in R
(when V < 0: during reverse battery situations) is:
CC
GND
2
P = (-V ) / R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
produces a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).
Doc ID 018513 Rev 1
21/32
Application information
VND5T100AJ-E
3.1.2
Solution 2: diode (D
) in the ground line
GND
A resistor (R
inductive load.
= 4.7 kΩ) should be inserted in parallel to D
if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values, if the microprocessor ground is not common to the device
ground. This shift not varies if more than one HSD shares the same diode/resistor network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO T/R 7637/2 table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins are pulled negative. ST suggests that a resistor (R ) be inserted in line to
prot
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHμC IH GND IHmax
Calculation example:
For V = -600 V and I
≥ 20 mA; V ≥ 4.5 V
OHμC
CCpeak
latchup
30 kΩ ≤ R
≤ 180 kΩ.
prot
Recommended R
value is 60 kΩ.
prot
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Doc ID 018513 Rev 1
VND5T100AJ-E
Application information
3.4
Maximum demagnetization energy (VCC = 24 V)
Figure 25. Maximum turn-off current versus inductance
10
A
B
C
1
0.1
L (mH)
1
10
100
1000
A: T
= 150°C single pulse
jstart
B: T
C: T
= 100°C repetitive pulse
= 125°C repetitive pulse
jstart
jstart
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R =0 Ω.
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse must not exceed the temperature
jstart
specified above for curves A and B.
Doc ID 018513 Rev 1
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Package and PCB thermal data
VND5T100AJ-E
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 26. PowerSSO-12 PC board
*$3*&)7ꢆꢆꢆꢃꢂꢆ
.
Note:
Layout condition of R and Z measurements (Board finish thickness 1.6 mm +/- 10 %; Board double layer; Board
th
th
dimension 77 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation
1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint dimension 4.1 mm x 6.5 mm)
Figure 27.
R
vs PCB copper area in open box free air condition (one channel ON)
thj-amb
RTHjamb
65
60
55
50
45
40
35
30
RTHjamb
0
2
4
6
8
10
GAPGCFT000124
24/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Package and PCB thermal data
Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print
10
1
0.1
0.0001
0.001
0.01
0.1
Time (s)
1
10
100
1000
GAPGCFT000125
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-12
*$3*&)7ꢆꢆꢆꢃꢂꢃ
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power
limitation or thermal cycling during thermal shutdown) are not triggered.
Equation 1: pulse calculation formula
ZTHδ = RTH ⋅ δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Doc ID 018513 Rev 1
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Package and PCB thermal data
VND5T100AJ-E
8
Table 15. Thermal parameters
Area/island (cm2)
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
Footprint
0.8
2
1.5
3
R4 (°C/W)
8
8
7
R5 (°C/W)
22
15
20
10
15
R6 (°C/W)
26
C1 = C7 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.0008
0.005
0.05
0.2
C4 (W.s/°C)
0.1
0.8
6
0.1
1
C5 (W.s/°C)
0.27
3
C6 (W.s/°C)
9
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Doc ID 018513 Rev 1
VND5T100AJ-E
Package and packing information
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
5.2
PowerSSO-12 mechanical data
Figure 30. PowerSSO-12 package dimensions
*$3*&)7ꢆꢆꢆꢃꢂꢂ
Doc ID 018513 Rev 1
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Package and packing information
VND5T100AJ-E
Table 16. PowerSSO-12 mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
A
A1
A2
B
1.250
0.000
1.100
0.230
0.190
4.800
3.800
-
-
1.620
0.100
1.650
0.410
0.250
5.000
4.000
-
-
-
-
C
-
D
-
E
-
e
0.800
H
5.800
0.250
0.400
0°
-
-
-
-
-
-
-
6.200
0.500
1.270
8°
h
L
k
X
2.200
2.900
-
2.800
3.500
0.100
Y
ddd
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Doc ID 018513 Rev 1
VND5T100AJ-E
Package and packing information
5.3
Packing information
Figure 31. PowerSSO-12 tube shipment (no suffix)
All dimensions are in mm.
B
Base q.ty
100
2000
532
C
Bulk q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
GA P GCFT000123
Figure 32. PowerSSO-12 tape and reel shipment (suffix “TR”)
Reel dimensions
Base q.ty
Bulk q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape hole spacing
Component spacing
Hole diameter
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Hole diameter
Hole position
Compartment depth
Hole spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
Doc ID 018513 Rev 1
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Order code
VND5T100AJ-E
6
Order code
Table 17. Device summary
Package
Order codes
Tube
Tape and reel
VND5T100AJTR-E
PowerSSO-12
VND5T100AJ-E
30/32
Doc ID 018513 Rev 1
VND5T100AJ-E
Revision history
7
Revision history
Table 18. Document revision history
Date
Revision
Changes
08-Mar-2011
1
Initial release.
Doc ID 018513 Rev 1
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VND5T100AJ-E
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Doc ID 018513 Rev 1
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