VND7050AJTR [STMICROELECTRONICS]
Double channel high-side driver with MultiSense analog feedback;型号: | VND7050AJTR |
厂家: | ST |
描述: | Double channel high-side driver with MultiSense analog feedback |
文件: | 总46页 (文件大小:1921K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
VND7050AJ
Double channel high-side driver with MultiSense analog
feedback for automotive applications
Datasheet - production data
−
−
Loss of ground and loss of VCC
Reverse battery with external
components
−
Electrostatic discharge protection
Applications
•
All types of Automotive resistive, inductive
and capacitive loads
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per Ch)
Current limitation (typ)
VCC
40 V
•
Specially intended for Automotive Signal
Lamps (up to P27W or SAE1156 or LED
Rear Combinations)
VCC 4 to 28 V
RON
ILIMH
50 mΩ
30 A
Description
Standby current (max)
ISTBY 0.5 µA
The device is a double channel high-side driver
manufactured using ST proprietary VIPower® M0-
7 technology and housed in PowerSSO-16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, providing
protection and diagnostics.
•
•
Automotive qualified
General
−
Double channel smart high-side driver
with MultiSense analog feedback
Very low standby current
−
−
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
Compatible with 3 V and 5 V CMOS
outputs
•
MultiSense diagnostic functions
−
Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
−
Overload and short to ground (power
limitation) indication
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
−
−
−
−
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/disable
•
Protections
−
−
−
−
−
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Configurable latch-off on
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
overtemperature or power limitation
with dedicated fault reset pin
May 2015
DocID027396 Rev 1
1/46
www.st.com
This is information on a product in full production.
Contents
VND7050AJ
Contents
1
2
Block diagram and pin description................................................5
Electrical specification....................................................................7
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings................................................................7
Thermal data.....................................................................................8
Main electrical characteristics ...........................................................8
Waveforms......................................................................................19
Electrical characteristics curves ......................................................22
3
4
Protections.....................................................................................26
3.1
3.2
3.3
3.4
Power limitation...............................................................................26
Thermal shutdown...........................................................................26
Current limitation.............................................................................26
Negative voltage clamp...................................................................26
Application information ................................................................27
4.1
GND protection network against reverse battery.............................27
4.1.1
Diode (DGND) in the ground line ..................................................... 28
4.2
4.3
4.4
Immunity against transient electrical disturbances..........................28
MCU I/Os protection........................................................................28
Multisense - analog current sense ..................................................29
4.4.1
4.4.2
4.4.3
Principle of Multisense signal generation......................................... 30
TCASE and VCC monitor................................................................. 32
Short to VCC and OFF-state open-load detection ........................... 33
5
6
Maximum demagnetization energy (VCC = 16 V)........................35
Package and PCB thermal data....................................................36
6.1
PowerSSO-16 thermal data ............................................................36
7
Package information .....................................................................39
7.1
7.2
7.3
PowerSSO-16 package information................................................39
PowerSSO-16 packing information .................................................41
PowerSSO-16 marking information.................................................43
8
9
Order codes ...................................................................................44
Revision history ............................................................................45
2/46
DocID027396 Rev 1
VND7050AJ
List of tables
List of tables
Table 1: Pin functions .................................................................................................................................5
Table 2: Suggested connections for unused and not connected pins........................................................6
Table 3: Absolute maximum ratings ...........................................................................................................7
Table 4: Thermal data.................................................................................................................................8
Table 5: Power section ...............................................................................................................................8
Table 6: Switching.......................................................................................................................................9
Table 7: Logic inputs.................................................................................................................................10
Table 8: Protections..................................................................................................................................11
Table 9: MultiSense ..................................................................................................................................11
Table 10: Truth table.................................................................................................................................18
Table 11: MultiSense multiplexer addressing...........................................................................................19
Table 12: ISO 7637-2 - electrical transient conduction along supply line.................................................28
Table 13: MultiSense pin levels in off-state ..............................................................................................32
Table 14: PCB properties .........................................................................................................................36
Table 15: Thermal parameters .................................................................................................................38
Table 16: PowerSSO-16 mechanical data................................................................................................39
Table 17: Reel dimensions .......................................................................................................................41
Table 18: PowerSSO-16 carrier tape dimensions ....................................................................................42
Table 19: Device summary.......................................................................................................................44
Table 20: Document revision history ........................................................................................................45
DocID027396 Rev 1
3/46
List of figures
VND7050AJ
List of figures
Figure 1: Block diagram..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................15
Figure 5: Current sense accuracy versus IOUT .......................................................................................16
Figure 6: Switching time and Pulse skew .................................................................................................16
Figure 7: MultiSense timings (current sense mode).................................................................................17
Figure 8: Multisense timings (chip temperature and VCC sense mode)..................................................17
Figure 9: TDSTKON..................................................................................................................................18
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ......................19
Figure 11: Latch functionality - behavior in hard short circuit condition....................................................20
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off)....20
Figure 13: Standby mode activation .........................................................................................................21
Figure 14: Standby state diagram.............................................................................................................21
Figure 15: OFF-state output current .........................................................................................................22
Figure 16: Standby current .......................................................................................................................22
Figure 17: IGND(ON) vs. Iout ...................................................................................................................22
Figure 18: Logic Input high level voltage ..................................................................................................22
Figure 19: Logic Input low level voltage....................................................................................................22
Figure 20: High level logic input current ...................................................................................................22
Figure 21: Low level logic input current ....................................................................................................23
Figure 22: Logic Input hysteresis voltage .................................................................................................23
Figure 23: FaultRST Input clamp voltage .................................................................................................23
Figure 24: Undervoltage shutdown...........................................................................................................23
Figure 25: On-state resistance vs. Tcase.................................................................................................23
Figure 26: On-state resistance vs. VCC ...................................................................................................23
Figure 27: Turn-on voltage slope..............................................................................................................24
Figure 28: Turn-off voltage slope..............................................................................................................24
Figure 29: Won vs. Tcase.........................................................................................................................24
Figure 30: Woff vs. Tcase.........................................................................................................................24
Figure 31: ILIMH vs. Tcase.......................................................................................................................24
Figure 32: OFF-state open-load voltage detection threshold ...................................................................24
Figure 33: Vsense clamp vs. Tcase..........................................................................................................25
Figure 34: Vsenseh vs. Tcase ..................................................................................................................25
Figure 35: Application diagram.................................................................................................................27
Figure 36: Simplified internal structure .....................................................................................................27
Figure 37: MultiSense and diagnostic – block diagram............................................................................29
Figure 38: MultiSense block diagram .......................................................................................................30
Figure 39: Analogue HSD – open-load detection in off-state ...................................................................31
Figure 40: Open-load / short to VCC condition.........................................................................................32
Figure 41: GND voltage shift ....................................................................................................................33
Figure 42: Maximum turn off current versus inductance ..........................................................................35
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)............................................36
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................36
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on).....................37
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............37
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................38
Figure 48: PowerSSO-16 package outline ...............................................................................................39
Figure 49: PowerSSO-16 reel 13" ............................................................................................................41
Figure 50: PowerSSO-16 carrier tape ......................................................................................................42
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape ..................................................42
Figure 52: PowerSSO-16 marking information.........................................................................................43
4/46
DocID027396 Rev 1
VND7050AJ
Block diagram and pin description
1
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Function
Name
VCC
Battery connection.
OUTPUT0,1 Power output.
Ground connection. Must be reverse battery protected by an external diode / resistor
network.
GND
INPUT0,1
MultiSense
SEn
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs.
It controls output switch state.
Multiplexed analog sense output pin; it delivers a current proportional to the selected
diagnostic: load current, supply voltage or chip temperature.
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense
diagnostic pin.
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense
multiplexer.
SEL0,1
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in
case of fault; If kept low, sets the outputs in auto-restart. mode
FaultRST
DocID027396 Rev 1
5/46
Block diagram and pin description
VND7050AJ
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
SEn, SELx,
Connection /
pin
MultiSense
N.C. Output
Input
FaultRST
Floating
Not allowed
X (1)
X
X
X
X
Through 1 kΩ
Not
allowed
Through 15 kΩ
Through 15 kΩ
To ground
resistor
resistor
resistor
Notes:
(1)X: do not care.
6/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
2
Electrical specification
Figure 3: Current and voltage conventions
IS
VCC
VCC
VFn
IFR
IOUT
FaultRST
SEn
OUTPUT0,1
MultiSense
ISEn
VOUT
ISENSE
ISEL
SEL0,1
VSENSE
IIN
INPUT0,1
IGND
GAPGCFT00315
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
VCC DC supply voltage
-VCC Reverse DC supply voltage
Parameter
Value
38
Unit
V
0.3
Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped
to 40V; RL = 4 Ω)
VCCPK
40
V
VCCJS Maximum jump start voltage for single pulse short circuit protection
-IGND DC reverse ground pin current
28
V
200
mA
Internally
limited
IOUT OUTPUT0,1 DC output current
A
-IOUT Reverse DC output current
11
-1 to 10
7.5
IIN
INPUT0,1 DC input current
SEn DC input current
ISEn
ISEL
IFR
mA
SEL0,1 DC input current
FaultRST DC input current
FaultRST DC input voltage
VFR
V
DocID027396 Rev 1
7/46
Electrical specification
VND7050AJ
Symbol
Parameter
Value
Unit
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V)
MultiSense pin DC output current in reverse (VCC < 0 V)
Maximum switching energy (single pulse) (TDEMAG = 0.4 ms;
10
ISENSE
mA
-20
EMAX
30
mJ
T
jstart = 150 °C)
Electrostatic discharge (JEDEC 22A-114F)
4000
2000
4000
4000
4000
V
V
V
V
V
•
•
•
•
•
INPUT0,1
MultiSense
SEn, SEL0,1, FaultRST
OUTPUT0,1
VCC
VESD
VESD Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Junction operating temperature
Storage temperature
-40 to 150
-55 to 150
°C
Tstg
2.2
Thermal data
Table 4: Thermal data
Parameter
Symbol
Typ. value Unit
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1)(2)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2)
6.4
59
25
°C/W
Notes:
(1)One channel ON.
(2)Device mounted on four-layers 2s2p PCB
(3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
2.3
Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Power section
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Operating supply
voltage
VCC
4
13 28
V
V
V
VUSD Undervoltage shutdown
4
5
Undervoltage shutdown
VUSDReset
reset
Undervoltage shutdown
hysteresis
VUSDhyst
0.3
50
V
I
OUT = 2 A; Tj = 25°C
On-state resistance (1) IOUT = 2 A; Tj = 150°C
IOUT = 2 A; VCC = 4 V; Tj = 25°C
RON
100 mΩ
75
8/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
Symbol
Parameter
Test conditions
IS = 20 mA; 25°C < Tj < 150°C
IS = 20 mA; Tj = -40°C
Min. Typ. Max. Unit
41 46 52
38
V
V
Vclamp Clamp voltage
VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V;
0.5
VSEL0,1 = 0 V; Tj = 25°C
Supply current in
VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85°C
ISTBY standby at VCC = 13 V
0.5 µA
3
(3)
(2)
VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
VCC = 13 V;
Standby mode blanking
tD_STBY
time
VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V 60 300 550 µs
to 0 V
VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V;
V
IN0 = 5 V; VIN1 = 5 V;
IS(ON) Supply current
Control stage current
5
8
mA
I
OUT0 = 0 A; IOUT1 = 0 A
VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V;
IN0 = 5 V; VIN1 = 5 V; IOUT0 = 2 A;
consumption in ON
state. All channels
IGND(ON)
V
12 mA
IOUT1 = 2 A
active.
VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C
VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C
0
0
0.01 0.5
3
Off-state output current
IL(off)
µA
V
at VCC = 13 V (2)
Output - VCC diode
VF
I
OUT = -2 A; Tj = 150°C
0.7
voltage (2)
Notes:
(1)For each channel
(2)PowerMOS leakage included.
(3)Parameter specified by design; not subject to production test.
Table 6: Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
(1)
td(on)
Turn-on delay time at Tj = 25 °C
Turn-off delay time at Tj = 25 °C
10
10
60
40
120
100
0.7
RL = 6.5 Ω
RL = 6.5 Ω
µs
(1)
td(off)
(1)
(dVOUT/dt)on Turn-on voltage slope at Tj = 25 °C
0.1 0.3
V/µs
(1)
(dVOUT/dt)off Turn-off voltage slope at Tj = 25 °C
0.1 0.32 0.7
WON
Switching energy losses at turn-on (twon
Switching energy losses at turn-off (twoff
)
)
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
—
—
0.25 0.33(2) mJ
0.23 0.31 (2) mJ
WOFF
(1)
tSKEW
Differential Pulse skew (tPHL - tPLH
)
-80 -30
20
µs
Notes:
(1)See Figure 6: "Switching time and Pulse skew".
(2)Parameter guaranteed by design and characterization; not subject to production test.
DocID027396 Rev 1
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Electrical specification
VND7050AJ
Table 7: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter
INPUT0,1 characteristics
Test conditions
Min. Typ. Max. Unit
VIL
IIL
Input low level voltage
0.9
V
µA
V
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VIN = 0.9 V
VIN = 2.1 V
1
VIH
2.1
IIH
10
µA
V
VI(hyst)
0.2
5.3
I
IN = 1 mA
7.2
VICL
Input clamp voltage
V
IIN = -1 mA
-0.7
FaultRST characteristics
VFRL
IFRL
VFRH
IFRH
Input low level voltage
0.9
V
µA
V
Low level input current
Input high level voltage
High level input current
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VFR(hyst) Input hysteresis voltage
VFRCL Input clamp voltage
SEL0,1 characteristics (7 V < VCC < 18 V)
0.2
5.3
I
IN = 1 mA
7.5
V
IIN = -1 mA
-0.7
-0.7
-0.7
VSELL
ISELL
VSELH
ISELH
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VSEL(hyst) Input hysteresis voltage
VSELCL Input clamp voltage
SEn characteristics (7 V < VCC < 18 V)
0.2
5.3
I
IN = 1 mA
7.2
V
IIN = -1 mA
VSEnL
ISEnL
VSEnH
ISEnH
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VSEn(hyst) Input hysteresis voltage
0.2
5.3
I
IN = 1 mA
7.2
VSEnCL Input clamp voltage
V
IIN = -1 mA
10/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
Table 8: Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
V
CC = 13 V
21
30
ILIMH
DC short circuit current
42
4 V < VCC < 18 V (1)
A
VCC = 13 V;
Short circuit current
during thermal cycling
ILIML
10
TR < Tj < TTSD
TTSD
TR
Shutdown temperature
Reset temperature(1)
150
175
200
TRS + 1 TRS + 7
Thermal reset of fault
diagnostic indication
°C
TRS
VFR = 0 V; VSEn = 5 V
135
Thermal hysteresis
(TTSD - TR)(1)
THYST
7
ΔTJ_SD Dynamic temperature
Tj = -40°C; VCC = 13 V
60
K
VFR = 5 V to 0 V; VSEn = 5 V;
Fault reset time for
tLATCH_RST
VIN = 5 V; VSEL0 = 0 V;
3
10
20
µs
output unlatch (1)
VSEL1 = 0 V
IOUT = 2 A; L = 6 mH;
Tj = -40°C
VCC - 38
V
V
Turn-off output voltage
VDEMAG
clamp
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC - 41 VCC - 46 VCC - 52
20
Output voltage drop
limitation
VON
IOUT = 0.2 A
mV
Notes:
(1)Parameter guaranteed by design and characterization; not subject to production test.
Table 9: MultiSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSEn = 0 V; ISENSE = 1 mA
-17
-12
MultiSense clamp
voltage
VSENSE_CL
V
VSEn = 0 V; ISENSE = -1 mA
7
Current sense characteristics
IOUT = 0.01 A; VSENSE = 0.5 V;
KOL
dKcal/Kcal
KLED
IOUT/ISENSE
440
-30
VSEn = 5 V
IOUT = 0.01 A to 0.05 A;
Ical = 30 mA; VSENSE = 0.5 V;
Current sense ratio drift
at calibration point
(1)(2)
30
%
V
SEn = 5 V
IOUT = 0.05 A; VSENSE = 0.5 V;
SEn = 5 V
IOUT = 0.05 A; VSENSE = 0.5 V;
SEn = 5 V
IOUT/ISENSE
530 1450 2200
-25 25
V
(1)(2)
dKLED/KLED
Current sense ratio drift
%
V
DocID027396 Rev 1
11/46
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7050AJ
Symbol
Parameter
IOUT/ISENSE
Test conditions
Min. Typ. Max. Unit
IOUT = 0.2 A; VSENSE = 0.5 V;
VSEn = 5 V
K0
830 1400 1935
I
OUT = 0.2 A; VSENSE = 0.5 V;
(1)(2)
dK0/K0
K1
Current sense ratio drift
IOUT/ISENSE
-20
20
%
%
%
%
VSEn = 5 V
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
915 1300 1700
I
OUT = 0.4 A; VSENSE = 4 V;
(1)(2)
dK1/K1
K2
Current sense ratio drift
IOUT/ISENSE
-15
15
VSEn = 5 V
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
980 1230 1470
I
OUT = 1.5 A; VSENSE = 4 V;
(1)(2)
(1)(2)
dK2/K2
K3
Current sense ratio drift
IOUT/ISENSE
-10
10
VSEn = 5 V
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
1095 1215 1335
I
V
OUT = 4.5 A; VSENSE = 4 V;
SEn = 5 V
dK3/K3
Current sense ratio drift
-5
0
5
MultiSense disabled:
VSEn = 0 V
0.5
0.5
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
MultiSense enabled:
VSEn = 5 V; All channels ON;
IOUTX = 0 A; ChX diagnostic
selected;
0
0
2
2
•
E.g. Ch0:
IN0 = 5 V; VIN1 = 5 V;
MultiSense leakage
current
ISENSE0
µA
V
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 0 A; IOUT1 = 2 A
MultiSense enabled:
VSEn = 5 V; ChX channel OFF;
ChX diagnostic selected:
•
E.g. Ch0:
IN0 = 0 V; VIN1 = 5 V;
V
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT1 = 2 A
V
SEn = 5 V; RSENSE = 2.7 kΩ;
Output Voltage for
MultiSense shutdown
•
E.g. Ch0:
VIN0 = 5 V; VSEL0 = 0 V;
(1)
VOUT_MSD
5
V
V
V
SEL1 = 0 V; IOUT0 = 2 A
V
V
CC = 7 V; RSENSE = 2.7 kΩ;
SEn = 5 V; VIN0 = 5 V;
Multisense saturation
voltage
VSENSE_SAT
5
4
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 4.5 A; Tj = 150°C
V
V
CC = 7 V; VSENSE = 4 V;
IN0 = 5 V; VSEn = 5 V;
(1)
ISENSE_SAT
CS saturation current
mA
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
12/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V
V
CC = 7 V; VSENSE = 4 V;
IN0 = 5 V; VSEn = 5 V;
(1)
IOUT_SAT
Output saturation current
6
A
V
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
OFF-state diagnostic
VSEn = 5 V; ChX OFF;
OFF-state open-load
voltage detection
threshold
ChX diagnostic selected
VOL
2
3
4
•
E.g: Ch0
VIN0 = 0 V; VSEL0 = 0 V;
V
SEL1 = 0 V
OFF-state output sink
current
IL(off2)
VIN = 0 V; VOUT = VOL
-100
-15 µA
V
SEn = 5 V; ChX ON to OFF
transition;
OFF-state diagnostic
delay time from falling
edge of INPUT (see
Figure 9: "TDSTKON")
ChX diagnostic selected
tDSTKON
100 350 700 µs
•
E.g: Ch0
IN0 = 5 V to 0 V;
V
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
Settling time for valid
OFF-state open load
diagnostic indication from VSEL1 = 0 V; VOUT0 = 4 V;
VIN0 = 0 V; VIN1 = 0 V;
VFR = 0 V; VSEL0 = 0 V;
tD_OL_V
60
30
µs
µs
rising edge of SEn
VSEn = 0 V to 5 V
SEn = 5 V; ChX OFF;
ChX diagnostic selected
E.g: Ch0
IN0 = 0 V; VSEL0 = 0 V;
V
OFF-state diagnostic
delay time from rising
edge of VOUT
•
tD_VOL
5
V
VSEL1 = 0 V;
VOUT = 0 V to 4 V
Chip temperature analog feedback
VSEn = 5 V; VSEL0 = 0 V;
SEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = -40°C
V
2.325 2.41 2.495
1.985 2.07 2.155
V
V
V
MultiSense output
voltage proportional to
chip temperature
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = 25°C
VSENSE_TC
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
1.435 1.52 1.605
-5.5
RSENSE = 1 kΩ; Tj = 125°C
mV/
K
dVSENSE_TC/dT Temperature coefficient Tj = -40°C to 150°C
Transfer function
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
VCC = 13 V; VSEn = 5 V;
MultiSense output
VSEL0 = 5 V; VSEL1 = 5 V;
VSENSE_VCC
voltage proportional to
VCC supply voltage
3.16 3.23 3.3
V
VIN0,1 = 0 V; RSENSE = 1 kΩ
DocID027396 Rev 1
13/46
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7050AJ
Symbol
Parameter
Test conditions
VSENSE_VCC = VCC / 4
Min. Typ. Max. Unit
Transfer function (3)
Fault diagnostic feedback (see Table 10: "Truth table")
VCC = 13 V; RSENSE = 1 kΩ;
•
E.g: Ch0 in open load
VIN0 = 0 V; VSEn = 5 V;
MultiSense output
voltage in fault condition
VSENSEH
5
7
6.6
30
V
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
MultiSense output
current in fault condition
ISENSEH
V
CC = 13 V; VSENSE = 5 V
20
mA
MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense
mode)")(4)
Current sense settling
time from rising edge of
SEn
V
R
IN = 5 V; VSEn = 0 V to 5 V;
SENSE = 1 kΩ; RL = 6.5 Ω
tDSENSE1H
tDSENSE1L
tDSENSE2H
60
20
µs
µs
Current sense disable
delay time from falling
edge of SEn
V
IN = 5 V; VSEn = 5 V to 0 V;
5
RSENSE = 1 kΩ; RL = 6.5 Ω
Current sense settling
time from rising edge of
INPUT
V
R
IN = 0 V to 5 V; VSEn = 5 V;
SENSE = 1 kΩ; RL = 6.5 Ω
100 250 µs
Current sense settling
time from rising edge of
IOUT (dynamic response
to a step change of IOUT
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE = 90 % of
ΔtDSENSE2H
100 µs
I
SENSEMAX; RL = 6.5 Ω
)
Current sense turn-off
delay time from falling
edge of INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω
tDSENSE2L
50
250 µs
MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sense mode)")(4)
VSENSE_TC settling time
from rising edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 0 V;
tDSENSE3H
60
20
µs
µs
VSEL1 = 5 V; RSENSE = 1 kΩ
VSENSE_TC disable delay
V
SEn = 5 V to 0 V; VSEL0 = 0 V;
tDSENSE3L
time from falling edge of
SEn
VSEL1 = 5 V; RSENSE = 1 kΩ
MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sense mode)")(4)
VSENSE_VCC settling time
from rising edge of SEn VSEL1 = 5 V; RSENSE = 1 kΩ
VSEn = 0 V to 5 V; VSEL0 = 5 V;
tDSENSE4H
60
20
µs
µs
VSENSE_VCC disable delay
VSEn = 5 V to 0 V; VSEL0 = 5 V;
tDSENSE4L
time from falling edge of
SEn
VSEL1 = 5 V; RSENSE = 1 kΩ
MultiSense timings (Multiplexer transition times)(4)
VIN0 = 5 V; VIN1 = 5 V;
MultiSense transition
delay from ChX to ChY
V
SEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V; IOUT0 = 0 A;
OUT1 = 3 A; RSENSE = 1 kΩ
tD_XtoY
20
µs
I
14/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
MultiSense transition
VIN0 = 5 V; VSEn = 5 V;
tD_CStoTC
delay from current sense VSEL0 = 0 V; VSEL1 = 0 V to 5 V;
60
20
60
20
20
20
µs
µs
µs
µs
µs
µs
to TC sense
IOUT0 = 1.5 A; RSENSE = 1 kΩ
MultiSense transition
delay from TC sense to
current sense
VIN0 = 5 V; VSEn = 5 V;
tD_TCtoCS
tD_CStoVCC
tD_VCCtoCS
tD_TCtoVCC
tD_VCCtoTC
VSEL0 = 0 V; VSEL1 = 5 V to 0 V;
IOUT0 = 1.5 A; RSENSE = 1 kΩ
MultiSense transition
VIN1 = 5 V; VSEn = 5 V;
delay from current sense VSEL0 = 5 V; VSEL1 = 0 V to 5 V;
to VCC sense
IOUT1 = 1.5A; RSENSE = 1 kΩ
MultiSense transition
delay from VCC sense to
current sense
VIN1 = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V to 0 V;
IOUT1 = 1.5 A; RSENSE = 1 kΩ
MultiSense transition
delay from TC sense to
VCC sense
V
CC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 0 V to 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
MultiSense transition
delay from VCC sense to
TC sense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 5 V to 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
MultiSense transition
VIN0 = 5 V; VIN1 = 0 V;
delay from stable current VSEn = 5 V; VSEL1 = 0 V;
sense on ChX to VSENSEH VSEL0 = 0 V to 5 V; IOUT0 = 3 A;
tD_CStoVSENSEH
20
µs
on ChY
VOUT1 = 4 V; RSENSE = 1 kΩ
Notes:
(1)Parameter guaranteed by design and characterization; not subject to production test.
(2)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(3)
V
sensing and TC sensing are referred to GND potential.
CC
(4)Transition delay are measured up to +/- 10% of final conditions.
Figure 4: IOUT/ISENSE versus IOUT
DocID027396 Rev 1
15/46
Electrical specification
VND7050AJ
Figure 5: Current sense accuracy versus IOUT
Figure 6: Switching time and Pulse skew
twon
twoff
VOUT
Vcc
80% Vcc
20% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
GAPG2609141134CFT
16/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
Figure 7: MultiSense timings (current sense mode)
IN1
High
SEn
Low
High
SEL0
Low
High
SEL1
IOUT1
Low
CURRENT SENSE
tDSENSE2H
tDSENSE1L
tDSENSE1H tDSENSE2L
GAPGCFT00318
Figure 8: Multisense timings (chip temperature and VCC sense mode)
High
SEn
Low
High
SEL0
Low
High
SEL1
VCC
Low
VSENSE = VSENSE_VCC
VSENSE = VSENSE_TC
SENSE
tDSENSE4H
tDSENSE4L
tDSENSE3H
tDSENSE3L
VCC VOLTAGE SENSE MODE
CHIP TEMPERATURE SENSE MODE
GAPGCFT00319
DocID027396 Rev 1
17/46
Electrical specification
VND7050AJ
Figure 9: TDSTKON
VINPU T
VOU T
VOU T > VOL
MultiSense
TDSTKON
GAPG2609141140CFT
Table 10: Truth table
Mode
Conditions
INX FR SEn SELX OUTX MultiSense
Comments
Low quiescent current
consumption
Standby
All logic inputs low
L
L
L
X
L
L
L
L
L
Hi-Z
See (1)
See (1)
Nominal load
connected;
Outputs configured for
auto-restart
H
H
Normal
See (1)
Tj < 150 °C
Outputs configured for
Latch-off
H
L
H
X
H
L
See (1)
See (1)
Overload or short
to GND causing:
Output cycles with
temperature
Overload
H
H
X
L
H
X
See (1)
H
L
See (1)
See (1)
Tj > TTSD or
hysteresis
ΔTj > ΔTj_SD
Output latches-off
Re-start when
L
L
Hi-Z
Hi-Z
VCC > VUSD
+
Undervoltage
VCC < VUSD (falling)
X
X
VUSDhyst (rising)
Short to VCC
Open-load
L
L
X
X
H
H
See (1)
See (1)
OFF-state
diagnostics
See (1)
See (1)
External pull-up
Negative output Inductive loads
L
X
< 0 V
See (1)
voltage
turn-off
Notes:
(1)Refer to Table 11: "MultiSense multiplexer addressing"
18/46
DocID027396 Rev 1
VND7050AJ
Electrical specification
Table 11: MultiSense multiplexer addressing
MultiSense output
OFF-state
diag. (1)
SEn SEL1 SEL0 MUX channel
Negative
output
Normal mode
Overload
L
X
L
X
L
Hi-Z
Channel 0
diagnostic
ISENSE
1/K * IOUT0
=
VSENSE
VSENSEH
=
VSENSE
VSENSEH
=
H
Hi-Z
Hi-Z
Channel 1
diagnostic
ISENSE
1/K * IOUT1
=
VSENSE
VSENSEH
=
VSENSE
VSENSEH
=
H
L
H
H
H
H
H
L
TCHIP Sense
VCC Sense
VSENSE = VSENSE_TC
VSENSE = VSENSE_VCC
H
Notes:
(1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is
low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L
(latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN0 = 0; OUT0 = latched,
VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH
2.4
Waveforms
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
DocID027396 Rev 1
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Electrical specification
VND7050AJ
Figure 11: Latch functionality - behavior in hard short circuit condition
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
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VND7050AJ
Electrical specification
Figure 13: Standby mode activation
Figure 14: Standby state diagram
DocID027396 Rev 1
21/46
Electrical specification
VND7050AJ
2.5
Electrical characteristics curves
Figure 15: OFF-state output current
Figure 16: Standby current
Figure 17: IGND(ON) vs. Iout
Figure 18: Logic Input high level voltage
Figure 19: Logic Input low level voltage
Figure 20: High level logic input current
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VND7050AJ
Electrical specification
Figure 21: Low level logic input current
Figure 22: Logic Input hysteresis voltage
Figure 23: FaultRST Input clamp voltage
Figure 24: Undervoltage shutdown
VFRCL [V]
8
7
Iin = 1mA
6
5
4
3
2
1
Iin = -1mA
0
-1
-50
-25
0
25
50
75
100
125
150
175
T [°C]
GAPG2110131613CFT
Figure 25: On-state resistance vs. Tcase
Figure 26: On-state resistance vs. VCC
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Electrical specification
Figure 27: Turn-on voltage slope
VND7050AJ
Figure 28: Turn-off voltage slope
Figure 29: Won vs. Tcase
Figure 30: Woff vs. Tcase
Figure 32: OFF-state open-load voltage
detection threshold
Figure 31: ILIMH vs. Tcase
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VND7050AJ
Electrical specification
Figure 34: Vsenseh vs. Tcase
Figure 33: Vsense clamp vs. Tcase
VSENSEH [V]
10
9
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
T [°C]
GAPG1905151315CFT
DocID027396 Rev 1
25/46
Protections
VND7050AJ
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2
3.3
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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VND7050AJ
Application information
4
Application information
Figure 35: Application diagram
4.1
GND protection network against reverse battery
Figure 36: Simplified internal structure
DocID027396 Rev 1
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Application information
VND7050AJ
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test pulse severity
Test
Pulse
Minimum
number of
pulses or test
time
level with Status II
functional performance
status
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
2011(E)
(1)
Level
III
US
min
0,5 s
max
1
-112V
+55V
-220V
+150V
-7V
500 pulses
500 pulses
1h
2ms, 10Ω
50µs, 2Ω
2a
3a
3b
4 (2)
III
0,2 s
5 s
IV
90 ms
90 ms
100 ms
100 ms
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
IV
1h
IV
1 pulse
Load dump according to ISO 16750-2:2010
Test B (3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
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VND7050AJ
Application information
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
•
•
•
Current monitor: current mirror of channel output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
Figure 37: MultiSense and diagnostic – block diagram
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Application information
VND7050AJ
4.4.1
Principle of Multisense signal generation
Figure 38: MultiSense block diagram
Current monitor
When current mode is selected in the MultiSense, this output is capable to provide:
•
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
•
•
VSENSE is voltage measurable on RSENSE resistor
ISENSE is current provided from MultiSense pin in current output mode
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VND7050AJ
Application information
•
•
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH
.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH
.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 39: Analogue HSD – open-load detection in off-state
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Application information
VND7050AJ
Figure 40: Open-load / short to VCC condition
Table 13: MultiSense pin levels in off-state
Condition
Output
MultiSense
SEn
L
Hi-Z
VSENSEH
Hi-Z
0
VOUT > VOL
H
L
Open-load
VOUT < VOL
VOUT > VOL
VOUT < VOL
H
L
Hi-Z
VSENSEH
Hi-Z
0
Short to VCC
Nominal
H
L
H
4.4.2
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal.
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VND7050AJ
Application information
Figure 41: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable to provide information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C).
Short to VCC and OFF-state open-load detection
Short to VCC
4.4.3
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
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Application information
VND7050AJ
Equation
VPU - 4
IL(off2)min @ 4V
RPU <
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VND7050AJ
Maximum demagnetization energy (VCC = 16 V)
5
Maximum demagnetization energy (VCC = 16 V)
Figure 42: Maximum turn off current versus inductance
VND7050AJ
- Maximum turn off current versus inductance
100
10
1
VND7050AJ- Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1
10
100
1000
L (mH)
- Maximum turn off Energy versus Tdemag
VND7050AJ
1000
VND7050AJ- Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
100
10
1
0.01
0.1
1
10
100
Tdemag [ms]
GAPGCFT01245
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data
VND7050AJ
6
Package and PCB thermal data
6.1
PowerSSO-16 thermal data
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14: PCB properties
Dimension
Value
1.6 mm +/- 10%
77 mm x 86 mm
FR4
Board finish thickness
Board dimension
Board Material
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal vias separation
0.070 mm
0.035 mm
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
0.025 mm
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
2.2 mm x 3.9 mm
Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on)
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
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Package and PCB thermal data
VND7050AJ
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal parameters
Area/island (cm2)
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
Footprint
1.8
2
8
4L
3.2
8
8
6
8
6
6
4
3
7
R4 (°C/W)
14
R5 (°C/W)
30
20
20
10
18
R6 (°C/W)
26
C1 = C7 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.00035
0.005
0.05
0.2
C4 (W.s/°C)
0.3
1
0.3
1
0.4
4
C5 (W.s/°C)
0.4
C6 (W.s/°C)
3
5
7
18
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Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-16 package information
Figure 48: PowerSSO-16 package outline
Table 16: PowerSSO-16 mechanical data
Dimensions
Ref.
Millimeters
Typ.
Min.
0°
Max.
Θ
Θ1
Θ2
Θ3
A
8°
0°
5°
15°
15°
5°
1.70
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Package information
VND7050AJ
Dimensions
Millimeters
Typ.
Ref.
Min.
0.00
1.10
0.20
0.20
0.19
0.19
Max.
0.10
1.60
0.30
0.28
0.25
0.23
A1
A2
b
b1
c
0.25
c1
D
0.20
4.9 BSC
D1
e
2.90
3.50
0.50 BSC
6.00 BSC
3.90 BSC
E
E1
E2
h
2.20
0.25
0.40
2.80
0.50
0.85
L
0.60
1.00 REF
16
L1
N
R
0.07
0.07
0.20
R1
S
Tolerance of form and position
aaa
bbb
ccc
ddd
eee
fff
0.10
0.10
0.08
0.08
0.10
0.10
0.15
ggg
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Package information
7.2
PowerSSO-16 packing information
Figure 49: PowerSSO-16 reel 13"
Table 17: Reel dimensions
Value(1)
Description
Base quantity
Bulk quantity
A (max)
2500
2500
330
1.5
B (min)
C (+0.5, -0.2)
D (min)
13
20.2
100
12.4
18.4
N
W1 (+2 /-0)
W2 (max)
Notes:
(1)All dimensions are in mm.
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Package information
VND7050AJ
Figure 50: PowerSSO-16 carrier tape
P2
P0
2.0 0.1
4.0 0.1
X
1.55 0.05
1.6 0.1
1.75 0.1
0.30 0.05
Y
Y
R 0.5
Typical
K1
K0
X
P1
A0
SECTION X - X
REF 4.18
REF 0.5
SECTION Y - Y
GAPG2204151242CFT
Table 18: PowerSSO-16 carrier tape dimensions
Value(1)
Description
A0
B0
K0
K1
F
6.50 ± 0.1
5.25 ± 0.1
2.10 ± 0.1
1.80 ± 0.1
5.50 ± 0.1
8.00 ± 0.1
12.00 ± 0.3
P1
W
Notes:
(1)All dimensions are in mm.
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape
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Package information
7.3
PowerSSO-16 marking information
Figure 52: PowerSSO-16 marking information
Marking area
1
2
3
4
5
6
7
8
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not in scale)
GAPG0401151415CFT
Engineering Samples: these samples can be clearly identified by a dedicated
special symbol in the marking of each unit. These samples are intended to be
used for electrical compatibility evaluation only; usage for any other purpose may
be agreed only upon written authorization by ST. ST is not liable for any customer
usage in production and/or in reliability qualification trials.
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
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Order codes
VND7050AJ
8
Order codes
Table 19: Device summary
Order codes
Tape and reel
VND7050AJTR
Package
PowerSSO-16
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Revision history
9
Revision history
Table 20: Document revision history
Revision
Date
Changes
19-May-2015
1
Initial release.
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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