WS57C51C-70D [STMICROELECTRONICS]
HIGH SPEED 16K x 8 CMOS PROM/RPROM; 高速16K ×8 CMOS PROM / RPROM
| 型号： | WS57C51C-70D |
| 厂家： | 
ST |
| 描述： | HIGH SPEED 16K x 8 CMOS PROM/RPROM |
| 文件： | 总7页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WS57C51C
HIGH SPEED 16K x 8 CMOS PROM/RPROM
KEY FEATURES
• Very Fast Access Time
• Pin Compatible with Am27S51
and N82HS1281
35 ns
—
• Low Power Consumption
• Fast Programming
• Immune to Latch-Up
Up to 200 mA
—
• ESD Protection Exceeds 2000 V
GENERAL DESCRIPTION
The WS57C51C is a High Performance 128K UV Erasable Electrically Re-Programmable Read Only Memory
(RPROM). It is manufactured in an advanced CMOS technology which enables it to operate at Bipolar PROM
speeds while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C51C over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This enables the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS5751C in a windowed package is 100% tested with
worst case test patterns both before and after assembly.
The WS57C51C provides a low power alternative to those designs which are committed to a Bipolar PROM
footprint. It is a direct drop-in replacement for a Bipolar PROM of the same architecture (16K x 8). No software,
hardware or layout changes need be performed.
BLOCK DIAGRAM
PIN CONFIGURATION
TOP VIEW
Chip Carrier
CERDIP
EPROM ARRAY
131,072 BITS
8
ROW
DECODER
A6 - A13
ROW
ADDRESSES
1
28
A
A
A
A
A
A
A
A
A
A
O
O
O
V
A
A
A
A
9
8
7
6
5
4
3
2
1
0
0
1
2
CC
10
11
12
13
2
27
26
25
24
23
22
21
20
19
18
17
16
15
4
3
2
30
32 31
1
3
A
A
A
A
A
A
A
A
5
29
5
4
3
2
1
0
12
13
4
6
COLUMN
DECODER
6
28
27
26
25
24
23
22
21
A0 - A5
COLUMN
ADDRESSES
5
CS1/V
CS2
CS3
CS4
NC
7
PP
6
CS1/V
PP
8
7
CS2
9
8
CS3
10
11
12
13
SENSE
AMPLIFIERS
9
CS4
NC
10
11
12
13
14
O
7
O
0
O
O
7
O
O
6
O
CS1/VPP
1
6
5
14 15 16
18
20
17
O
19
CS2
CS3
CS4
O
4
O
GND
3
O
NC
NC O
O
4 5
2
3
8
OUTPUTS
PRODUCT SELECTION GUIDE
PARAMETER
57C51C-35
35 ns
57C51C-45
45 ns
57C51C-55
55 ns
57C51C-70
70 ns
Address Access Time (Max)
CS to Output Valid Time (Max)
20 ns
20 ns
25 ns
30 ns
2-47
Return to Main Menu
WS57C51C
ABSOLUTE MAXIMUM RATINGS*
MODE SELECTION
Storage Temperature............................–65° to + 150°C
PINS
CS1/
CS2 CS3 CS4 V
OUTPUTS
Voltage on any Pin with
Respect to Ground ....................................–0.6V to +7V
CC
CC
CC
V
MODE
PP
Read
V
V
V
V
V
V
V
D
OUT
IL
IL
IH
IL
V
with Respect to Ground...................–0.6V to + 14V
PP
Output
Disable
ESD Protection..................................................>2000V
X
X
X
High Z
High Z
High Z
High Z
IH
*
Output
Disable
NOTICE:
X
V
X
X
X
V
V
IH
CC
CC
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
Output
Disable
X
X
X
V
IL
Output
Disable
X
X
X
V
V
CC
V
CC
V
CC
IH
Program
V
V
X
D
IN
PP
IH
IL
Program
Verify
V
V
V
V
D
OUT
IL
IH
IL
OPERATING RANGE
RANGE
TEMPERATURE
0°C to +70°C
V
CC
Commercial
Industrial
Military
+5V ± 10%
+5V ± 10%
+5V ± 10%
–40°C to +85°C
–55°C to +125°C
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
VIL
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
TEST CONDITIONS
MIN
–0.1
2.0
MAX
UNITS
V
(Note 3)
0.8
VIH
(Note 3)
VCC + 0.3
0.4
V
VOL
IOL = 16 mA
V
VOH
Output High Voltage IOH = –4 mA
2.4
V
Comm'l
30
35
35
50
60
60
mA
mA
mA
mA
mA
mA
VCC = 5.5 V, f = 0 MHz (Note 1),
Output Not Loaded
VCC Active Current
(CMOS)
ICC1
Industrial
Military
Add 4 mA/MHz for AC Operation
Comm'l
Industrial
Military
VCC = 5.5 V, f = 0 MHz (Note 2),
Output Not Loaded
VCC Active Current
(TTL)
ICC2
Add 4 mA/MHz for AC Operation
ILI
Input Leakage
Current
VIN = 5.5V or Gnd
–10
–10
10
10
µA
µA
ILO
Output Leakage
Current
VOUT = 5.5 V or Gnd
NOTES: 1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V.
2. TTL inputs: VIL ≤ 0.8V, VIH ≥ 2.0V.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
2-48
WS57C51C
UNITS
AC READ CHARACTERISTICS Over Operating Range. (See Above)
57C51C-35
57C51C-45
57C51C-55
57C51C-70
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Address to Output Delay
CS to Output Delay
t
35
20
45
20
55
25
70
30
ACC
t
CS
ns
Output Disable to
Output Float*
t
20
20
25
25
DF
Address to Output Hold
t
0
0
0
0
OH
*Sampled, Not 100% Tested.
AC READ TIMING DIAGRAM
ADDRESSES
VALID
t
t
ACC
OH
CSX, CS3
OUTPUTS
t
CS
VALID
t
DF
2-49
WS57C51C
CAPACITANCE(4) T = 25°C, f = 1 MHz
A
(5)
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
CONDITIONS
= 0V
TYP
4
MAX
6
UNITS
pF
C
C
C
V
IN
IN
V
= 0V
OUT
8
12
pF
OUT
VPP
V
Capacitance
V
= 0 V
PP
18
25
pF
PP
NOTES: 4. This parameter is only sampled and is not 100% tested.
5.Typical values are for T = 25°C and nominal supply voltages.
A
TEST LOAD (High Impedance Test Systems)
A.C. TESTING INPUT/OUTPUT WAVEFORM
98 Ω
2.01 V
3.0
TEST
POINTS
1.5
1.5
D.U.T.
30 pF
0.0
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V
for a logic "0." Timing measurements are made at 1.5 V for
input and output transitions in both directions.
NOTE: 6. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters.
A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between V and ground is recommended.
CC
Inadequate decoupling may result in access time degradation or other transient performance failures.
2-50
WS57C51C
NORMALIZED SUPPLY CURRENT
TYPICAL ACCESS TIME CHANGE
vs.
vs.
SUPPLY VOLTAGE
OUTPUT LOADING
1.60
1.40
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
1.20
1.00
0.80
0.60
0.0
4.0
4.5
5.0
5.5
6.0
0.0
200
400
600
800
1000
(
)
SUPPLY VOLTAGE V
(
)
CAPACITANCE pF
NORMALIZED T
vs.
AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs.
aa
AMBIENT TEMPERATURE
1.6
1.4
1.2
1.0
0.8
0.6
1.2
1.1
1.0
0.9
0.8
-55 -35 -15
5
25 45 65 85 105 125
-55 -35 -15
5
25 45 65 85 105 125
(
)
AMBIENT TEMPERATURE °C
AMBIENT TEMPERATURE (°C)
2-51
WS57C51C
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V)
SYMBOLS
PARAMETER
MIN
MAX
UNITS
Input Leakage Current
(VIN = VCC or Gnd)
ILI
–10
10
µA
VPP Supply Current During
Programming Pulse
IPP
60
25
mA
mA
V
ICC
VOL
VCC Supply Current
Output Low Voltage During Verify
(IOL = 16 mA)
0.45
Output High Voltage During Verify
(IOH = –4 mA)
VOH
2.4
V
NOTE: 7. VPP must not be greater than 13 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V)
SYMBOLS
PARAMETER
Address Setup Time
Chip Disable Setup Time
Data Setup Time
MIN
TYP
MAX
30
UNITS
µs
tAS
tDF
tDS
tPW
tDH
2
ns
2
100
2
µs
Program Pulse Width
Data Hold Time
200
30
µs
µs
t
t
Chip Select Delay
ns
CS
RF
V
Rise and Fall Time
1
µs
PP
PROGRAMMING WAVEFORM
VIH
ADDRESSES
ADDRESS STABLE
V
IL
t
AS
VIH
DATA
DATA IN
DATA OUT
V
IL
t
t
t
CS
PW
DH
t
t
DS
DF
V
PP
VIH
CS1/V
PP
t
RF
V
IL
t
RF
2-52
WS57C51C
ORDERING INFORMATION
OPERATING
WSI
SPEED
PART NUMBER
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
TEMPERATURE MANUFACTURING
RANGE
PROCEDURE
WS57C51C-35D
WS57C51C-35T
WS57C51C-35TI
WS57C51C-45CMB
WS57C51C-45D
WS57C51C-45DMB
WS57C51C-45J
WS57C51C-45JI
WS57C51C-45L
WS57C51C-45T
WS57C51C-45TI
WS57C51C-45TMB
WS57C51C-55CMB
WS57C51C-55D
WS57C51C-55DMB
WS57C51C-55J
WS57C51C-55JI
WS57C51C-55L
WS57C51C-55T
WS57C51C-55TI
WS57C51C-55TMB
WS57C51C-70D
WS57C51C-70T
35
35
35
45
45
45
45
45
45
45
45
45
55
55
55
55
55
55
55
55
55
70
70
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.3"
32 Pad CLLCC
D2
T2
T2
C2
D2
D2
J4
Comm’l
Comm’l
Industrial
Military
Standard
Standard
Standard
MIL-STD-883C
Standard
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.6"
32 Pin PLDCC
Comm’l
Military
MIL-STD-883C
Standard
Comm’l
Industrial
Comm’l
Comm’l
Industrial
Military
32 Pin PLDCC
J4
Standard
32 Pin CLDCC
L3
T2
T2
T2
C2
D2
D2
J4
Standard
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.3"
32 Pad CLLCC
Standard
Standard
MIL-STD-883C
MIL-STD-883C
Standard
Military
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.6"
32 Pin PLDCC
Comm’l
Military
MIL-STD-883C
Standard
Comm’l
Industrial
Comm’l
Comm’l
Industrial
Military
32 Pin PLDCC
J4
Standard
32 Pin CLDCC
L3
T2
T2
T2
D2
T2
Standard
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.3"
Standard
Standard
MIL-STD-883C
Standard
Comm’l
Comm’l
Standard
NOTES: 8. The actual part marking will not include the initials "WS."
PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS
REFER TO
PAGE 5-1
The WS57C51C is programmed using Algorithm D shown on page 5-9.
2-53
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