SML2108 [SUMMIT]
Laser Diode Adaptive Power Controller; 激光二极管自适应功率控制器
| 型号： | SML2108 |
| 厂家： | 
SUMMIT MICROELECTRONICS, INC. |
| 描述： | Laser Diode Adaptive Power Controller |
| 文件： | 总21页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SUMMIT
SML2108
MICROELECTRONICS, Inc.
Laser Diode Adaptive Power Controller
PRELIMINARY
FEATURES
DESCRIPTION
! Integrated Bias Current Monitor
The SML2108 is an adaptive power controller for laser
diodes. It is the industry's first integrated device that can
directlymonitorandmeasurealaserdiode'stemperature,
and provide a variable modulation current. The
SML2108's integrated active feedback loop is used to
calibrate and control the mean and modulation power of
high speed, high power laser diodes.
" Monitors & Measures Laser Temperature
Directly
" Eliminates Need for External Thermistor &
Thermal Coupling Issues
" Alarm Output on Over-temperature Condition
! Adaptive Modulation Control (AMC)
Inherentmanufacturingtolerancesintroducevariationsof
performanceinlaserdiodes. Thesevariations, combined
with parametric changes over the laser’s extreme tem-
perature range and laser ageing, call for an efficient
temperature compensation scheme. Using an internal
digital control loop and a programmable nonvolatile com-
pensation lookup table, the SML2108 provides the most
optimum adaptive power control with a minimum number
of external components.
" Adjusts Modulation Current as a Function of
the Laser Temperature
" 8 × 8 Programmable Compensation Table
" 256 Independent Compensation Values
" Integrated 8-Bit Modulation Control DAC
! Flexible Biasing Architecture
" Bias Control and Modulation Control:
0 to 10mA / 0 to 100 mA Source,
0 to 100mA Sink
The SML2108 removes the need for any manual calibra-
tion of the laser control circuit, which is currently the
industry standard practice. All calibration values are
programmedthroughthe2-wirecommunicationinterface,
which can be controlled by most production ATE equip-
ment.
! Automatic Power Control (APC) with Integrated
10-Bit Programmable Offset
" Automatic Initial Bias Optimization
! Electronic Calibration Through 2-wire Interface
! 3V or 5V Operation
Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapterandWindowsGUIsoftwareobtainablefromSum-
mit Microelectronics.
The SML2108 is available in 48 lead TQFP.
SIMPLIFIED APPLICATION DIAGRAM
V
DD
LASER
DIODE
MONITOR
DIODE
IN+
LASER
MODULATION
DRIVER
IMOD
IN–
MODSET
V
DD
V
MODN
DD
BIASN
AUTOMON
SML2108
SDA
SCL
DETECT
Interface
V
SS
2053 SAD 1.0
©SUMMIT MICROELECTRONICS, Inc., 2000
Characteristics subject to change without notice
•
300 Orchard City Dr., Suite 131
•
Campbell, CA 95008
•
Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com
1
2053 2.2 11/07/00
SML2108
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CAP2
10
DETECT
12
CAP1
11
V
V
CC
DD
–
10-Bit
DAC
10-Bit
DAC Reg
+
10-Bit
NV Reg
1
2
3
BIAS P
A0
A1
EXT TEMP
BIAS N
5
A2
8-Bit
ADC
SDA
SCL
4
5
(All Rs 100kΩ)
13
14
V
V
A
D
SS
AUTOMON
6
CE# 48
NV Scaling
& Offset
SS
Config
7
8
RDY
ADC Read &
Alarm Reg
ALERT#
NV Look-up
Table
MOD P
MOD N
NV
POR
8-Bit
DAC
POR
Reg
V
SS
2053 BD 2.1
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
2
SML2108
PRELIMINARY
PIN CONFIGURATION
48-Pin TQFP
MODN
MODN
BIASN
BIASN
A0
A1
A2
SDA
SCL
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
V
SS
V
AUTOMON
RDY#
ALERT#
EXT TEMP
CAP2
SS
V
SS
V
SS
BIASN
BIASN
MODN
MODN
10
11
12
CAP1
DETECT
2053 PCon 2.0
PIN DESCRIPTIONS
DETECT (12)
SDA, SCL (4 & 5)
This is the analog input from the laser monitor photodiode Data and Clock lines, respectively, whose function and
for the integrator circuit. There is an on-board resistance use are based on the industry standard I2C interface.
of 2MΩ between the DETECT input and CAP1 pin.
Lookup table values, configuration data, and D/A and A/D
registers may all be accessed via these two pins of the
SML2108. These pins have internal 100kΩ pullups.
CAP1 and CAP2 (11 & 10)
Capacitor inputs for an external capacitor in the feedback
loopoftheMeanPowerControlIntegrator. Thereisanon-
board capacitance of 500pF.
A0, A1, A2 (1, 2, & 3)
Address Pins for the interface provided to allow multiple
devices on a single bus. These pins have internal 100kΩ
pullups.
AUTOMON (6)
Active high input used to enable the internal auto-monitor
function, which provides automatic adjustments to the
RDY# (7)
modulationoutputcurrents(MODPandMODN)basedon Active low, open-drain output. This pin is driven low
the internal A/D output and the values stored in the whenever the internal A/D is performing a conversion, or
nonvolatile lookup table. This pin has an internal 100kΩ while the on-board EEPROM is being programmed.
pullup.
EXT TEMP (9)
ALERT# (8)
Temperature input (or no connection). This pin can be
Active low, open-drain output. This pin is driven low programmed as an input to the ADC and can interface a
wheneverthebiascurrentincreasesbeyondapredefined temperature sensor. The EXT TEMP pin is multiplexed
nonvolatile threshold. This can be used to predict laser with the bias current to provide a means of configuring the
failure.
inputtotheADC. WhenEXTTEMPisprogrammedasthe
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
3
SML2108
PRELIMINARY
input to the ADC using bit 5 of Register 1, the converted BIASP (17, 18, 43, & 44)
valueofthecurrententeringthispinisusedastheaddress
High-side mean bias control current. Current source
outputrangeisprogrammable, withtheoptionalrangesof
0 to 100mA or 0 to 10mA.
of the EEPROM lookup table. In this configuration the
modulation current can be controlled by temperature
rather than the bias current. Refer to the application
example on using the EXT TEMP pin. If this option is not
used the pin should be left floating.
BIASN (27, 28, 33, & 34)
Low-side mean bias control current. Current sink input
range is 0 to 100mA.
VSSA, VSSD (13 & 14)
Analoganddigitallow-sidesuppliesforon-boardcircuitry.
Must be at same potential as all other VSS pins.
MODP (19, 20, 41, &42)
High-side modulation control current. Current source
outputrangeisprogrammable,withoptionalrangesof0to
100mA or 0 to 10mA.
V
DD (15, 16, 21, 22, 39, 40, 45, 46, & 47)
High-sidesupplyfortheBiasandModulationcurrentsand
power supply input for the chip.
MODN (25, 26, 35, &36)
Low-side modulation control current. Current sink input
range is 0 to 100mA.
CE# (48)
The chip enable input is active low and provides an
additional method of enabling the serial interface. The
stateofthispinhasnoeffectontheauto-monitorfunction.
This pin has an internal 100kΩ pullup.
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
4
SML2108
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...................... –55°C to 125°C *COMMENT
Storage Temperature ........................... –65°C to 150°C
Stresses listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Lead Solder Temperature (10 secs) ................... 300 °C
ELECTRICAL TABLES
(Over Recommended Operating Conditions; Voltages are relative to GND)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Typical ADC Performance
º
S/N
THD
Signal to Noise ratio
TA = 25ºC
70
dB
dB
Total harmonic distortion
–80
Peak harmonic intermodulation
distortion
2nd Order
3rd Order
–80
–80
dB
dB
DC Accuracy
Resolution
8
Bits
Bits
Reolution for which no missing
codes are guaranteed
8
Relative accuracy
±½
±1
±2
±2
LSB
LSB
LSB
LSB
DNL
Positive full scale error
Unipolar offset error
VSS = 5V
VSS = 2.7V to
3.6V
±2
LSB
2053 Elect Table A
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
5
SML2108
PRELIMINARY
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Maximum bias and modulation
current
VDD
Supply voltage
3
5.5
V
Bias and modulation current out-
puts open
ID
Supply current
2
mA
ILO
ILI
Input leakage current
VIN = 0V to VDD
1
µA
µA
V
Output leakage current VOUT = 0V to VDD
10
0.4
VOL
Output low voltage
IOL = 2mA
VDD = 5V, IOL = –400µA
2.4
V
VOH
Output high voltage
VDD < 4.5V, IOL = –100µA
VDD – 0.2
–0.1
V
VIL
VIH
Input low voltage
Input high voltage
0.3 × VDD
V
0.7 × VDD
0.5
V
Integrator loop
frequency
fINT
1
kHz
ms
Power up stabilization Integrator time constant is less
time
tPUS
10
than 10ms
Analog Inputs
DETECT DETECT input to ADC
IEXT TEMP Full scale current input
Analog Outputs
0
1.5
V
390.6
µA
N-channel modulation
current
IMODN
0
0
–100
mA
mA
P-channel modulation
current
IMODP
100
IBIASN
IBIASP
VDAC
N-channel bias current
P-channel bias current
10-Bit DAC output
0
0
0
–100
100
1.5
mA
mA
V
Digital Outputs
Open drain ALERT output is
active
ALERT
ALERT output
5
mA
2053 Elect Table B
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
6
SML2108
PRELIMINARY
DEVICE OPERATION
General Description
When the laser is operated at a second temperature (T2)
the required bias current is shown as IBIAS2. To maintain
a constant extinction ratio as in the T1 curve the laser
requires a modulation of IMOD2. The SML2108 is the
industry’s first integrated device capable of providing a
variable modulation current based on a function of either
the bias current or an external temperature. This ability to
be able to compensate the modulation output current
enables the system designer to optimize the extinction
ratio of the laser driver module.
The SML2108 is an adaptive power controller for laser
diodes with an active feedback loop used to calibrate and
control the mean and modulation power of high speed,
high power laser diodes. Inherent manufacturing toler-
ancesintroducevariationsofperformanceinlaserdiodes.
Thesevariations,combinedwithparametricchangesover
the laser’s extreme temperature range and laser ageing,
callforanefficientcompensationsolution. TheSML2108,
with a minimum number of external components, is de-
signed to compensate for these tolerances using a digital
control loop and a programmable nonvolatile calibration
lookup table.
The SML2108 has been specified to remove the need for
any manual calibration of the laser control circuit. All
calibration values are programmed through an industry
standard2-wirecommunicationinterface,whoseprotocol
and function can be controlled by most production ATE
equipment.
Figure 1 illustrates the usefulness of the SML2108. The
figureshowstheoutputlightpowerofalaserdiodeversus
its operating current. Depicted in the graph are typical
laser diode characteristics at two different temperatures.
Atthefirsttemperature(T1), thelaserrequiresanaverage
Bias Current — Mean Power Control
bias current of IBIAS1. The modulation current needed to The SML2108 bias current outputs (BIASP and BIASN)
switch the laser between its on and off state is labeled establishtheaveragepowerbeingdeliveredtoanexternal
IMOD1. The ratio of light power of its on state divided by laser diode. The output of the laser diode is separately
thelightpowerofitsoffstateisreferredtoastheextinction monitored using a local back-face diode, the output of
ratio. Ideally the laser will maintain a constant extinction which is tied to the DETECT pin of the SML2108. When
ratio over its entire operating temperature range, as the coupled with the on-board integrator this feedback loop
receiver module is calibrated to this level. Running the becomes the mean power control for the laser diode. The
laserdriveratahigherextinctionratioindicatesthatpower output block of the mean power control is shown in Figure
is being wasted, whereas operating at a lower extinction 2.
ratio indicates that data may possibly be lost.
Light
Power
(On) 1
T1
T2
BIAS
BIAS
2
1
(Off) 0
Total
MOD
2
2053 Fig01
MOD
1
Figure 1. Laser Current Increase Caused by Temperature Increase, Constant Light Power Out
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
7
SML2108
PRELIMINARY
V
The built-in integration time constant is nominally 1ms.
This is accomplished by using an internal 2MΩ resistor
and 500pF capacitor. The time constant can be modified
by adding external capacitance between the CAP1 and
CAP2 terminals, and/or by adding external resistance
between the DETECT and CAP1 terminals. For stability
reasons it is not recommended that the time constant be
decreased to less than 100us.
DD
I
Source
BIAS
0 to 10 mA or
0 to 100 mA
BIASP
ADC
Input
The output of an internal 10-Bit DAC biases the positive
terminaloftheintegratingamplifier. ThisDACprovidesan
analog reference to the integrator which is useful for initial
calibration of the laser module. The full-scale value of the
DAC output is 1.5V.
From MPC
Integrator
BIAS
CONTROL
BIASN
Sink
I
BIAS
10-Bit Bias Control D/A
0 to 100 mA
The 10-Bit D/A determines the reference voltage of the
non-inverting terminal of the integrating amplifier in the
mean power control loop. Associated with this DAC are a
10-Bit volatile register and a 10-Bit nonvolatile (NV) regis-
ter. The content of the volatile register determines the
DAC output voltage. The DAC output voltage is given by
the following relation:
2053 Fig02
Figure 2. Output Block 1: Mean Power Control
V
DD
I
Source
MOD
X
0 to 10 mA or
0 to 100 mA
OV =
×1.5V
1024
MODP
where X = the decimal equivalent of the 10-Bit data stored
in the volatile register. Note that the DAC output voltage
is not directly accessible external to the chip. However,
whentheSML2108isplacedinatypicalapplicationcircuit,
the mean power control feedback loop forces the voltage
at the DETECT pin to be the same as the DAC output. On
device power-up the volatile register may be loaded with
all zeroes, or it may be loaded from the contents of the 10-
Bit nonvolatile register.
From I
MOD
CONTROL
MOD
DAC
MODN
I
Sink
0 to 100 mA
MOD
Access to the 10-Bit volatile register is obtained via the 2-
wire interface at slave address 1001BIN, word address 0.
Refer to Figures 9, 10, 12, and 13 for details on program-
ming and reading data from the 10-Bit register. When
writing to the volatile register the new DAC output will
become valid immediately at the end of the write com-
mand. Reading the volatile register has no effect on the
DACoutput. Readingorwritingthevolatileregisterhasno
effect on the contents of the nonvolatile register.
2053 Fig03
Figure 3. Output Block 2: IMOD
thevolatileregister,exceptwordaddress2isusedinstead
of 0. When reading the NV register, the data is first
transferred into the volatile register where it may be
accessed by the serial interface. Note that upon this
transfer the DAC output will change immediately to reflect
the new data. Similarly, when writing to the NV register,
The 10-Bit NV register can only be accessed indirectly
through the volatile register. The command sequence to
communicate with the NV register is the same as that of
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
8
SML2108
PRELIMINARY
the data is first placed in the volatile register. At the to normalize overall module operation.
conclusion of the write command an internal nonvolatile
writesequenceinitiatesthestorageofthevolatilecontents
into the NV register.
Althoughthememorymaynormallybereadandwrittenas
a standard memory, a security feature exists in the con-
figuration settings that will prevent any external access to
Notethatwhenmodifyingthe10-BitDACoutput,themean the array. Additionally, if the auto-monitor feature is not
power control loop will become temporarily disrupted. It used, then the modulation output current may be pro-
may be several milliseconds before the bias current has grammed to a fixed value, and the array may be used as
settled to its steady state value. Until then its value will be a standard memory to store device settings, board identi-
undefined.
fication values, production dates, etc.
Modulation Current — Auto-Monitor Control
8-Bit Current Output D/A
The laser bias current, which relates directly to laser The 8-Bit D/A defines the modulation output current.
temperature, can be monitored using an on-board, cur- Associated with this DAC are an 8-Bit volatile register and
rent-sensingA/Dconverter. Intheauto-monitormodethe an 8-Bit nonvolatile (NV) register. The content of the
8-Bit output of the converter is used as an address to the volatile register determines the DAC output current. The
EEPROMlookuptable. Thesubsequent8-Bitdataoutput DAC output current is given by the following relation:
from the lookup table becomes the input for the compen-
sation DAC. The 8-Bit compensation DAC output is a
X
current in the range of 0 to 100mA and is used to control
the modulation current MODP and MODN. The output
block of the modulation current control is shown in Figure
3.
OC =
×100mA
256
where X = the 8-Bit data stored in the volatile register. On
device power-up the volatile register may be loaded with
all zeroes or it may be loaded from the contents of the 8-
Bit nonvolatile register.
The lookup table provides an arbitrary mapping from bias
currenttomodulationcurrent. TheinputrangetotheADC
may be scaled and/or offset to provide maximum resolu-
tionwithintheappropriateconversionspace. Thesample
interval is programmable from 10µs to 1s. Refer to the
ADC section for further details about configuring the A/D.
The interface is used to program the configuration regis-
ters as well as lookup table values.
Access to the 8-Bit volatile register is obtained via the 2-
wire interface at slave address 1001BIN, word address 4.
Refer to Figures 8 and 11 for details on programming and
reading data from the 8-Bit register. When writing to the
volatile register, the new DAC output will become valid
immediatelyattheendofthewritecommand. Readingthe
volatileregisterhasnoeffectontheDACoutput. Reading
orwritingthevolatileregisterhasnoeffectonthecontents
of the nonvolatile register.
Lookup Table
A 2k-Bit (256 x 8) memory array of on-board EEPROM
comprises the internal lookup table. This array is ac-
cessed via the 2-wire serial interface using a slave ad-
dress of 1010BIN. (Note: 1010BIN is the default, however
this may be set to 1110BIN, depending upon the contents
of Configuration Register 2.) Refer to the Bus Interface
section for details on programming and reading data from
the device.
The 8-Bit NV register can only be accessed indirectly
through the volatile register. The command sequence to
communicate with the NV register is the same as that of
thevolatileregister,exceptwordaddress6isusedinstead
of 4. When reading the NV register the data is first
transferred into the volatile register where it may be
accessed by the serial interface. Note that upon this
transfer the DAC output will change immediately to reflect
the new data. Similarly, when writing to the NV register,
the data is first placed in the volatile register. At the
conclusion of the write command, an internal nonvolatile
writesequenceinitiatesthestorageofthevolatilecontents
into the NV register.
In the auto-monitor mode the content of the array repre-
sentsthetransferfunctionbetweentheA/Doutputandthe
final value of modulation current. Using a lookup table to
implement this function allows arbitrary functions, and
even nonlinear relations, to be easily realized. Also, the
useofalookuptableallowseachdevicetobecustomized
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
9
SML2108
PRELIMINARY
ADC SCALING AND OFFSET
The ADC can be customized to monitor a particular range These combinations of scales and offsets allow the reso-
of bias current by programming Register 0. Bits 3 and 2 lution to be maximized over a given range of current. For
controlthescalingoftheADCwhilebits1and0controlthe example, if the bias current is known to be in the range of
ADCoffset. Thefourgraphs(Figures4,5,6,&7)illustrate 30mA to 70mA the choice would be the Half scale graph
the ADC scale values, according to the two bit code. In (code 10BIN) and the ¼ offset curve (code 01BIN) to
eachGraphthecurvesaredifferentiatedbytheADCoffset maximize the resolution of the ADC.
values. Note: if using IBIASP with the maximum current
Note that these graphs assume a full scale bias current of
option set to 10 mA, divide the x-axis value by 10 (i.e., 75
100mA. WhentheADCisconfiguredtoreceiveinputfrom
= 7.5, etc.).
the EXT TEMP pin full scale current becomes 390.6µA,
which limits the internal 1/256 scale factor between bias
current and the ADC input current.
255
224
192
160
128
96
255
224
192
160
128
96
Offset
00
01
10
11
Offset
00
01
10
11
64
64
32
32
0
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
I
(mA)
I
(mA)
BIAS
BIAS
2053 Fig04
2053 Fig05
Figure 4. Full Scale (code 11BIN) with Offset
Figure 5. Half Scale (code 10BIN) with Offset
255
224
192
255
224
192
160
128
96
64
32
0
160
Offset
00
01
10
11
Offset
00
01
10
11
128
96
64
32
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
I
(mA)
I
(mA)
BIAS
BIAS
2053 Fig06
2053 Fig07
Figure 6. Quarter Scale (code 01BIN) with Offset
Figure 7. Tenth Scale (code 00BIN) with Offset
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
10
SML2108
PRELIMINARY
REGISTERS
REGISTER BIT MAPS
reset by a low AUTOMON signal. Bit 5 is used to toggle
the source of the ADC input between the IBIAS current and
the EXT TEMP signal. Bit 2 initializes the input of the 10
bit DAC to either zero or a stored value from a nonvolatile
registerwhenthedeviceispoweredup. Bit1initializesthe
input of the 8 bit DAC to either zero or a stored value from
a nonvolatile register when the device is powered up. Bit
0 sets the maximum P-channel bias current (IBIASP) and
modulation current (IMODP) to either 10mA or 100mA.
The SML2108 has three user programmable, nonvolatile
configuration registers.
Register 0
This register is used to configure the 8-Bit ADC that
monitors the bias current. Bit 7 enables the ADC alert to
belatched,whichwillholdtheALERTpinlowuntilthealert
isreset. Bits6, 5, and4areusedtosetthesampleinterval
oftheADC. TheinputtotheADCcanbescaledandoffset
to provide maximum resolution over the bias current. Bits
3 and 2 are used to set the full scale range of the ADC,
while bits 1 and 0 are used to set the ADC offset. See the
Table.
Register 2
This register controls several functions related to the bus
interface. Bits 7 and 6 control the read and write access
to the configuration registers. It is imperative that register
2 be programmed properly to prevent an inadvertent
lockout. Bit 5 determines whether the memory array is
available or locked. Bit 4 selects the device type address
for accessing the memory array, while bit 3 determines
whether the device must receive a bus address that
corresponds to the biasing of the address pins. Bit 2 is
usedtoenableanalertconditionontheADCtoshutdown
the bias current. Bits 1 & 0 are unused.
Register 1
Thisregistercontrolsmultiplefunctions. Bit7disablesthe
alert during a manual analog-to-digital conversion of the
bias current. Bit 6 selects the action that will reset an alert
from the ADC. When this bit is set to a 0 any device read
or write will reset the alert. When set to a 1 the alert will be
7
6
5
4
3
2
1
0
Function
Alert not latched
ADC
Alert
ADC Sample Interval
ADC Range
ADC Offset
0
1
x
x
x
Alert latched
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5µs sample interval
20µs
"
"
160µs
1.28ms
6.25ms
25ms
200ms
1.6s
"
"
x
x
"
"
"
"
x
x
"
"
"
"
"
"
x
0
0
1
1
0
1
0
1
1/10 full scale bias current
1/4 full scale bias current
1/2 full scale bias current
Full scale bias current
x
x
x
0
0
1
1
0
1
0
1
No offset
1/4 of full scale bias current offset
1/2 of full scale bias current offset
3/4 of full scale bias current offset
x
x
2053 Reg0 1.0
Register 0
2053 2.2 11/07/00
SUMMIT MICROELECTRONICS, Inc.
11
SML2108
PRELIMINARY
7
6
5
4
3
2
1
0
Function
Alert ADC
Reset Input
10-Bit 8-Bit
Alert
Unused
IBIASP
DAC
DAC
0
1
Alert not allowed during manual conversion
Alert allowed during manual conversion
Alert reset by Read or Write
x
x
0
x
1
0
1
Alert reset by Low on AUTOMON pin
IBIASN or IBIASP current input to ADC
EXT TEMP pin input to ADC
x
x
0
1
Input to DAC is zero on power up
x
x
Input to DAC is from nonvolatile register on
power up
x
x
0
1
Input to DAC is zero on power up
x
Input to DAC is from nonvolatile register on
power up
x
0
1
Max current is 10mA: IBIASP , IMODP
Max current is 100mA: IBIASP , IMODP
x
2053 Reg1 1.0
Register 1
7
6
5
4
3
2
1
0
Function
Memory Device
Access Address Address Action
Pin
Alert
Register Access
Unused
0
0
1
1
0
1
0
1
All Registers locked; no Read or Write
Read all Registers; no Write
Write all Registers; no Read
Read and Write all Registers
EEPROM available
x
x
x
0
x
1
EEPROM locked
0
1
Device Type Adress is 1010BIN
Device Type Adress is 1110BIN
x
x
Responds to address pin biased
address only
x
x
0
1
x
Responds to any bus address
x
Bias current unaffected by alert
condition
0
1
x
Alert condition shuts down bias current
2053 Reg2 1.0
Register 2
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
12
SML2108
PRELIMINARY
BUS INTERFACE
GENERAL DESCRIPTION
The I2C bus is a two-way, two-line serial communication SDA line must be connected to a positive supply by a pull-
between different integrated circuits. The two lines are: a up resistor located on the bus. Summit parts have a
serial Data line (SDA) and a serial Clock line (SCL). All Schmitt input on both lines. See Figure X1 and Table X1
Summit Microelectronics parts support a 100kHz clock for waveforms and timing on the bus. One bit of Data is
rate, and some support the alternative 400kHz clock. transferred during each Clock pulse. The Data must
Check the AC Electrical Table for the value of fSCL. The remain stable when the Clock is high.
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:SDA
SU:DAT
HD:SDA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2053 Fig08
Figure 8. I2C Data Timing
Conditions
Symbol
Parameter
SCL clock frequency
Clock low period
Clock high period
Bus free time
Min.
0
Max.
Units
kHz
µs
fSCL
tLOW
tHIGH
tBUF
tSU:STA
tHD:STA
tSU:STO
tAA
100
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
µs
Before new transmission
µs
Start condition setup time
Start condition hold time
Stop condition setup time
µs
µs
µs
Clock edge to valid output
Data Out hold time
SCL low to valid SDA (cycle n)
3.5
µs
tDH
SCL low (cycle n+1) to SDA change
µs
tR
SCL and SDA rise time
SCL and SDA fall time
Data In setup time
1000
300
ns
tF
ns
tSU:DAT
tHD:DAT
TI
250
0
ns
Data In hold time
ns
Noise filter SCL and SDA
Write cycle time
Noise suppression
100
5
ns
tWR
ms
2053 Table01 1.0
Table 1. I2C Data Timing
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
13
SML2108
PRELIMINARY
Start and Stop Conditions
3
9
1
2
8
SCL
BothDataandClocklinesremainhighwhenthebusisnot
busy. Datatransferbetweendevicesmaybeinitiatedwith
aStartconditiononlywhenSCLandSDAarehigh. Ahigh-
to-lowtransitionoftheDatalinewhiletheClocklineishigh
is defined as a Start condition. A low-to-high transition of
theDatalinewhiletheClocklineishighisdefinedasaStop
condition. See Figure 9.
SDA
Trans
SDA
Rec
ACK
2053 Fig10
Figure 10. Acknowledge Timing
In the case of a Read from a Summit part, when the last
byte has been transferred to the Master, the Master will
leave the Data line high for a NACK. This will cause the
Summitparttostopsendingdata,andtheMasterwillissue
a Stop on the clock pulse following the NACK.
START
Condition
STOP
Condition
SCL
SDA In
InthecaseofaWritetoaSummitparttheMasterwillsend
aStopontheclockpulseafterthelastAcknowledge. This
will indicate to the Summit part that it should begin its
internal non-volatile write cycle.
2053 Fig09
Figure 9. I2C Start and Stop Timing
Read and Write
Protocol
The first byte from a Master is always made up of a seven
bitSlaveaddressandtheRead/Writebit. TheR/Wbittells
theSlavewhethertheMasterisreadingDatafromthebus
orwritingDatatothebus(1=read,0=write). Thefirstfour
of the seven address bits are called the Device Type
Identifier (DTI). The DTI for the SML2108 is 1010. The
next three bits are not used in the SML2108 (See Figure
11). The SML2108 will issue an Acknowledge after
recognizing a Start condition and its DTI.
The protocol defines any device that sends data onto the
busasaTransmitter,andanydevicethatreceivesdataas
a Receiver. The device controlling data transmission is
called the Master, and the controlled device is called the
Slave. In all cases the Summit Microelectronic devices
are slave devices, since they never initiate any data
transfers.
Acknowledge
Inthereadmodethe SML2108transmitseightbitsofdata,
then releases the SDA line, and monitors the line for an
Acknowledge signal. If an Acknowledge is detected, and
no Stop condition is generated by the Master, the
SML2108 will continue to transmit data. If an Acknowl-
edge is not detected (NACK) the SML2108 will terminate
further data transmission. See Figure 12.
Data is always transferred in 8-Bit bytes. Acknowledge
(ACK) is used to indicate a successful data transfer. The
Transmitting device will release the bus after transmitting
eight bits. During the ninth clock cycle the Receiver will
pull the SDA line low to Acknowledge that it received the
eight bits of data (See Figure 10). The termination of a
Master Read sequence is indicated by a non-Acknowl-
edge (NACK), where the Master will leave the Data line
high.
SCL
SDA
3
1
5
x
8
9
1
1
2
0
4
0
6
x
7
x
R/W
ACK
2053 Fig11
Figure 11. Typical Master Address Byte Transmission
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
14
SML2108
PRELIMINARY
S
T
A
R
T
N S
A T
C O
K P
R
/
W
A
C
K
Optional
Master
SDA
x x x
x x x x x x x
x x
x x
R
1 0 1 0
A
C
K
Slave
2053 Fig12
Figure 12. Read
S
T
A
R
T
S
T
O
P
R
/
W
Master
SDA
x x x
x x x x x x x x
x x
x x
1 0 1 0
W
A
C
K
A
C
K
A
C
K
Slave
2053 Fig13
Figure 13. Write
InthewritemodetheSML2108receiveseightbitsofdata, Sequential READ
then generates an Acknowledge signal. It will continue to
generate ACKs until a Stop condition is generated by the
Master. See Figure 13.
Sequential Reads can be initiated as either a current
address Read or a random access Read. The first word
is transmitted as with the other byte read modes (current
address byte Read or random address byte Read). How-
ever, the Master now responds with an Acknowledge,
Random Address Read
Random address Read operations allow the Master to indicating that it requires additional data. The SML2108
access any memory location in a random fashion. This continues to output data for each Acknowledge received.
operation involves a two-step process. First, the master The Master terminates the sequential Read operation by
issuesawritecommandwhichincludesthestartcondition not responding with an Acknowledge, and issues a Stop
and the Slave address field (with the R/W bit set to Write) condition. During a sequential read operation the internal
followed by the address of the word it is to read. This address counter is automatically incremented with each
procedure sets the internal address counter of the Acknowledgesignal. ForReadoperationsalladdressbits
SML2108 to the desired address. After the word address areincremented,allowingtheentirearraytobereadusing
acknowledge is received by the Master, it immediately a single Read command. After a count of the last memory
reissues a start condition followed by another Slave ad- address the address counter will ‘roll-over’ and the
dressfieldwiththeR/WbitsettoRead. TheSML2108will memory will continue to output data.
respondwithanAcknowledgeandthentransmitthe8data
The protocol for reading and writing to the registers and
bits stored at the addressed location. At this point, the
the lookup table are illustrated in Figures 14 through 24.
Master does not acknowledge the transmission, but does
generate a Stop condition. The SML2108 discontinues
data transmission.
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
15
SML2108
PRELIMINARY
TIMING DIAGRAMS
S
T
A
R
T
S
Data
Byte
n
Data
Byte
n+1
Data
T
Byte
O
Device
Address
R/
W
Master
SDA
n+15
P
x
0 1 0
x x
0
Word Address
1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Slave
2053 Fig14
Figure 14. Look-up Table Page/Byte Write
S
S
S
N
T
A
R
T
T
T
A
A
R
T
A
Device
Address
Device
Address
O
C
R/
W
R/
C
Master
SDA
P
K
W K
x
x
x
x x x
0
0
Word Address
1
Data Byte
1
0
1
0
1
0
1
A
C
K
A
C
K
2053 Fig15
Slave
Figure 15. Look-up Table Random Address Read with Dummy Write
S
T
A
R
S
S
T
O
P
T
A
R
T
First
Data
Byte
Last
Data
Byte
N
A
C
K
A
C
K
A
C
K
Device
Address
Device
Address
R/
W
R/
W
Master
T
x
x
x
x x x
0
0
Word Address
1
1
0
1
0
1
0
1
SDA
A
C
K
A
C
K
A
C
K
2053 Fig16
Slave
Figure 16. Look-up Table Sequential Read with Dummy Write
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
16
SML2108
PRELIMINARY
S
T
A
R
T
S
T
O
P
Device
Address
R/
W
Master
SDA
Location Address
0 0 1 0 0
D D D D D D D D
x
0 0 1
x x
0
0
0
0
1
7
6 5 4 3 2 1 0
A
C
K
A
C
K
A
C
K
Slave
2053 Fig17
Figure 17. 8-Bit DAC Volatile Register Write
S
T
A
R
T
S
S
T
O
P
T
N
A
C
K
A
R
T
Device
Address
Device
Address
R/
W
R/
W
Master
SDA
Location Address
0 0
D D D D D D D D
x
x
x
x x x
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
7
6 5 4 3 2 1 0
A
C
K
A
C
K
A
C
K
2053 Fig18
Slave
Figure 18. 8-Bit DAC Volatile Register Read with Dummy Write
S
S
T
T
A
R
T
Device
Address
O
P
R/
W
Master
SDA
Location Address
0 0 1 1 0
D D D D D D D D
x
0 0 1
x x
0
0
0
0
1
7
6 5 4 3 2 1 0
A
C
K
A
C
K
A
C
K
Slave
2053 Fig19
Figure 19. 8-Bit DAC Non-volatile Register Write
S
T
A
R
T
S
S
T
N
A
C
K
T
A
R
T
Device
Address
Device
Address
O
P
R/
W
R/
W
Master
SDA
Location Address
0 0
D D D D D D D D
x
x
x
x x x
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
7
6 5 4 3 2 1 0
A
C
K
A
C
K
A
C
K
2053 Fig20
Slave
Figure 20. 8-Bit DAC Non-volatile Register Read with Dummy Write
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
17
SML2108
PRELIMINARY
S
T
A
R
T
S
T
O
P
Device
Address
R/
W
Master
SDA
Location Address
0 0 0 0 0
D D
D D D D D D D D
7 6 5 4 3 2 1 0
x
x x x
x x
x
0 0 1
x
x
0
0
0
0
1
9
8
A
C
K
A
C
K
A
C
K
A
C
K
Slave
2053 Fig21
Figure 21. 10-Bit DAC Volatile Register Write
S
T
O
P
Device
Address
R/
W
Master
SDA
Location Address
0 0 0 1 0
D D
D D D D D D D D
7 6 5 4 3 2 1 0
x
x x x
x x
x
x
x
0
0
0
0
1
0 0 1
9
8
A
C
K
A
C
K
A
C
K
A
C
K
Slave
2053 Fig22
Figure 22. 10-Bit DAC Nonvolatile Register Write
S
T
A
R
S
S
T
O
P
N
A
C
K
T
A
C
K
A
R
T
Device
Address
Device
Address
R/
W
R/
W
Master
T
Location Address
D D
D D D D D D D D
7 6 5 4 3 2 1 0
x
x x x
x x
x
x
x
x
1 0 0 1
x
x
0
0
0
0
0
0
0
0
0
1
1
0
0
1
9
8
SDA
A
C
K
A
C
K
A
C
K
2053 Fig23
Slave
Figure 23. 10-Bit DAC Volatile Register Read with Dummy Write
S
T
A
R
T
S
T
S
T
O
P
N
A
C
K
A
A
C
Device
Address
Device
Address
R/
W
R/
W
R
T
Master
SDA
K
Location Address
D D
D D D D D D D D
7 6 5 4 3 2 1 0
x
x x x
x x
9
x
x
x
x
1 0 0 1
x
x
0
0
0
0
0
0
0
1
0
1
1
0
0
1
8
A
C
K
A
C
K
A
C
K
2053 Fig24
Slave
Figure 24. 10-Bit DAC Nonvolatile Register Read with Dummy Write
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
18
SML2108
PRELIMINARY
APPLICATIONS
APPLICATION EXAMPLE USING EXTERNAL TEM-
PERATURE INPUT
5V
TheEXTTEMPpinoftheSML2108allowstheinputofthe
internal ADC to be driven from an external device, rather
than a mirrored version of the bias current. Figure 25
shows an example using a National Semiconductor
LM334 to deliver a current into the SML2108 that is
proportional to absolute temperature. The scale and
offset features of the ADC input can be used to center this
current and maximize the full range of the look-up table.
LM334
+
–
R
210Ω ±1%
SET
SML2108
I
SET
EXT TEMP
For this application the current ISET coming out of the
LM334 and into the EXT TEMP pin of the SML2108 is
given by the following equation:
2053 Fig25
Figure 25. Example of an External Temperature
Sensing Device
I
SET = 227µV / oK / RSET
For example, using a value of 210Ω for RSET yields a
current of 295µA at 0oC and 387µA at 85oC.
Next select scale and offset values of the ADC input that
willoptimizethecurrentrangeoftheLM334. Nominalfull-
scale input current of the ADC is 390.6µA (= 100mA/256).
By setting the input offset to ¾ scale (293µA) and the full-
scalerangeto¼scale(97.6µA), thenthezeroscaleofthe
internal ADC becomes 293µA, and the full-scale is
390.6µA. Thisrepresentsatemperaturerangeofapproxi-
mately –2oC to 88oC using a 210Ω resistor in the configu-
rationshown. (Thesesettingscorrespondtoconfiguration
Register 0, Bits 3 - 0 set to 7HEX.)
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
19
SML2108
PRELIMINARY
PACKAGE
48 PIN TQFP PACKAGE
8.975 – 9.025
0.353 – 0.355
0.02
0.50 BSC
6.5 – 7.1
0.271 – 0.280
0.003
0.076
0.009
0.22
DETAIL "A"
1 ref
Pin 1
0.018 – 0.030
0.45 – 0.75
0.004 – 0.008
0.10 – 0.20
mm.
in.
DETAIL "B"
A
B
20xx Pckg 1.0
ORDERING INFORMATION
SML2108
F
Package
F = 48 Pin TQFP
Base Part Number
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
20
SML2108
PRELIMINARY
NOTICE
SUMMITMicroelectronics,Inc.reservestherighttomakechangestotheproductscontainedinthispublicationinorder
to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating
parameters, and may vary depending upon a user’s specific application. While the information in this publication has
been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any
error or omission.
SUMMITMicroelectronics,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportoraviationapplications
where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to
significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless
SUMMITMicroelectronics, Inc. receiveswrittenassurances, toitssatisfaction, that:(a)theriskofinjuryordamagehas
been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is
adequately protected under the circumstances.
© Copyright 2000 SUMMIT Microelectronics, Inc.
2
I C is a trademark of Philips Corporation.
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
21
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