PS11NG [SUPERTEX]
Power Supply Support Circuit, Adjustable, 1 Channel, PDSO14, SOIC-14;
| 型号： | PS11NG |
| 厂家： | 
Supertex, Inc |
| 描述： | Power Supply Support Circuit, Adjustable, 1 Channel, PDSO14, SOIC-14 光电二极管 |
| 文件： | 总13页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PS10 - Active High
PS11 - Active Low
Initial Release
Quad Power Sequencing Controller
Features
Description
ꢀ
Sequencing of Four or More* Supplies, ICs, or Sub-
Many of today’s high performance FPGA’s, Microproces-
sors, DSP and industrial/embedded subsystems require
sequencing of the input power. Historically this has been
accomplished: i) discretely using comparators, references
& RC circuits; ii) using expensive programmable control-
lers; or iii) with low voltage sequencers requiring resistor
drop downs and several high voltage optocoupler or level
shift components.
systems
ꢀ
Independently Programmable Delays Between Open
Drain PWRGD Flags (5ms to 200ms)
±10V to ±90V Operation
Tracking in Combination with Schottky Diodes
Input Supervisors Including:
ꢀ
ꢀ
ꢀ
o UV/OV Lock Out/Enable
o Power-On-Reset (POR)
Low Power Consumption, 0.4mA Supply Current
Small SO-14 Package
The PS10/11 saves board space, improves accuracy,
eliminates optocouplers or level shifts and reduces overall
component count by combining four timers, programmable
input UV/OV supervisors, a programmable POR and four
90V open drain outputs. A high reliability, high voltage,
junction isolated process allows the PS10/11 to be con-
nected directly across the high voltage input rails.
ꢀ
ꢀ
*By Daisy-Chaining PS10/11’s
Applications
The power-on-reset interval (POR) may be programmed
by a capacitor on Cramp. To sequence additional sys-
tems, PS10/11 may be daisy chained together. If at any
time the input supply falls outside the UV/OV detector
range the PWRGD outputs will immediately become IN-
ACTIVE. Down sequencing may be accomplished with
additional components (see page 11).
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power Supply Sequencing
-48V Telecom and Networking Distributed Systems
-24V Cellular and Fixed Wireless Systems
-24V PBX Systems
+48V Storage Systems
FPGA, Microprocessor Tracking
Industrial/Embedded System Timing/Sequencing
High Voltage MEMs Driver’s Supply Sequencing
High Voltage Display Driver’s Supply Sequencing
The PS10/PS11 is available in a space saving SO-14
package.
Typical Application Circuit/Waveform(49.9k pull-up on PS11 PWRGD pins)
GND or +48V
14
VIN
/EN
+12V
COM
487K
1
2
3
DC/DC
6
PWRGD-D / PWRGD-D
PWRGD-C / PWRGD-C
CONVERTER
UV
6.81K
9.76K
PWRGD-B / PWRGD-B
PWRGD-A / PWRGD-A
/EN
+5V
4
DC/DC
5
7
CONVERTER
PS10/PS11
OV
VEE
COM
TB
11
TC
12
TD
13
RAMP
10
TADJ
8
/EN
+3.3V
COM
DC/DC
CONVERTER
10nF
RTB
RTC
RTD
/EN
+2.5V
COM
DC/DC
CONVERTER
-48V or GND
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
Relative to Negative Rail
04/07/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate
“products liability indemnification insurance agreement.” Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices deter-
mined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the
latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the
Legal/Disclaimer page on the Supertex website.
PS10/PS11
Absolute Maximum Ratings*
Ordering Information
VEE referenced to VIN pin
+0.3V to -100V
Package Options
Active State of Power
Good Flags
VPWRGD referenced to VEE voltage
VUV and VOV referenced to VEE Voltage
Operating Ambient Temperature
Operating Junction Temperature
Storage Temperature Range
-0.3V to +100V
-0.3V to 12V
14 Pin SOIC
PS10NG
-40°C to +85°C
-40°C to +125°C
-65° to +150°C
High
Low
PS11NG
*Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation of
the device at the absolute rating level may affect device reliability. All voltages are refer-
enced to device ground.
Electrical Characteristics(-10V • VIN • -90V, TA = 25°C unless otherwise specified)
Symbol
Parameter
Min
Typ
Max Units
Conditions
Supply (Referenced to VIN pin)
VEE
IEE
Supply Voltage
Supply Current
-90
-10
V
400
450
VEE = -48V
µA
OV and UV Control (Referenced to VEE pin)
VUVH
VUVL
VUVHY
IUV
UV High Threshold
UV Low Threshold
UV Hysteresis
1.20 1.26 1.32
V
V
Low to High Transition
High to Low Transition
1.10 1.16 1.22
100
mV
nA
V
UV Input Current
OV High Threshold
OV Low Threshold
OV Hysteresis
1.0
1.20 1.26 1.32
1.10 1.16 1.22
100
VUV = VEE + 1.9V
VOVH
VOVL
VOVHY
IOV
Low to High Transition
High to Low Transition
V
mV
nA
OV Input Current
1.0
VUV = VEE + 1.9V
Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V)
VTADJ = 0V
IRAMP
Ramp Pin Output Current
10
µA
VEE = -48V, CRAMP = 10nF,
see Typical Application Cir-
cuit
tPWRGD-A
Time from UV High to PWRGD-A
8.8
ms
tPWRGD-B
tPWRGD-B
tPWRGD-C
tPWRGD-C
tPWRGD-D
tPWRGD-D
Maximum time from PWRGD-A to PWRGD-B
Minimum time from PWRGD-A to PWRGD-B
Maximum time from PWRGD-B to PWRGD-C
Minimum time from PWRGD-B to PWRGD-C
Maximum time from PWRGD-C to PWRGD-D
Minimum time from PWRGD-C to PWRGD-D
150
3.0
200*
5.0*
200*
5.0*
200*
5.0*
250
8.0
ms
ms
ms
ms
ms
ms
RTB = 120kΩ
RTB = 3kΩ
150
3.0
250
8.0
RTC = 120kΩ
RTC = 3kΩ
150
3.0
250
8.0
RTD = 120kΩ
RTD = 3kΩ
*Note: Variations will track. For example if tPWRGD-A is 250ms then so will betPWRGD-B/C/D. Contact factory for tighter tolerance version.
Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V)
PWRGD-x = HI Z
VPWRGD-x(hi)
VPWRGD-x(lo)
IPWRGD-x(lk)
Power Good Pin Breakdown Voltage
Power Good Pin Output Low Voltage
Maximum Leakage Current
90
V
V
IPWRGD = 1mA, PWRGD-x = LOW
VPWRGD = 90V, PWRGD-x = HI Z
0.5
0.8
10
<1.0
µA
2
PS10/PS11
PWRGD Logic
Model
Condition
PWRGD-A/B/C/D
INACTIVE (not ready)
0
1
1
0
VEE
HI Z
HI Z
VEE
PS10
ACTIVE (Ready)
INACTIVE (not ready)
ACTIVE (Ready)
PS11
Pinout
PWRGD-D (PS10)
PWRGD-D (PS11)
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN
TD
TC
TB
PWRGD-C (PS10)
PWRGD-C (PS11)
PWRGD-B (PS10)
PWRGD-B (PS11)
PWRGD-A (PS10)
PWRGD-A (PS11)
OV
UV
VEE
RAMP
NC
8
TADJ
Top View
Pin Description
VEE - This pin is the negative terminal of the power supply
PWRGD-D* – This open drain Power Good Output Pin is
held inactive on initial power application and goes active a
programmed time delay after PWRGD-C goes active.
input to the circuit.
VIN – This pin is the positive terminal of the power supply
input to the circuit and can withstand 90V with respect to
VEE.
PWRGD-C* – This open drain Power Good Output Pin is
held inactive on initial power application and goes active a
programmed time delay after PWRGD-B goes active.
TD – The resistor connected from this pin to VEE pin sets the
time delay from PWRGD-C going active to PWRGD-D going
active.
PWRGD-B* – This open drain Power Good Output Pin is
held inactive on initial power application and goes active a
programmed time delay after PWRGD-A goes active.
TC – The resistor connected from this pin to VEE pin sets the
time delay from PWRGD-B going active to PWRGD-C going
active.
PWRGD-A* – This open drain Power Good Output Pin is
held inactive on initial power application and goes active one
POR delay after the UV pin goes above its High threshold
(provided VIN stays within the UV/OV window during this
period).
TB – The resistor connected from this pin to VEE pin sets the
time delay from PWRGD-A going active to PWRGD-B going
active.
To function as an indicator a pullup resistor must be con-
nected from this pin to a voltage rail no more than 90V from
VEE.
RAMP – This pin provides a current output so that a timing
ramp is generated when a capacitor is connected. This tim-
ing Ramp is used to program POR and the time from satis-
faction of the UV/OV supervisors to PWRGD-A.
OV – This Over Voltage (OV) sense pin, when raised above
its high threshold will immediately cause the Power Good
Outputs to be pulled low. These outputs will remain low until
the voltage on this pin falls below the low threshold limit,
initiating a new start-up cycle.
TADJ– A voltage source (0-50mV) connected to this pin
with respect to VEE allows adjustment of the PWRGD-A time
delay. This allows simple interface connectivity with a µC
D/A converter for adjustable timing. Normally this pin is tied
to VEE.
UV – This Under Voltage (UV) sense pin, when lowered
below its low threshold will immediately cause the Power
Good Outputs to be pulled low. These outputs will remain
low until the voltage on this pin rises above the low thresh-
old limit, initiating a new start-up cycle.
3
PS10/PS11
Functional Block Diagram
Band Gap
Reference
Vint
Regulator
& POR
UV
VIN
-
+
Vbg
UVLO
PWRGD-A
Logic
-
OV
+
PWRGD-B
PWRGD-C
PWRGD-D
VEE
Vint
Programmable
Timer
10uA
+
-
Vint - 1.2V
5k
TADJ
TB
TC
RAMP
TD
The controller continuously monitors the UV and OV pins
as long as the internal UVLO and POR circuits are satis-
fied. At any time during the start up cycle or thereafter,
crossing the UV low and OV high limits will cause an im-
mediate discharge on Cramp and reset on the power good
pins. When the input voltage returns to a value within the
programmed UV and OV limits, a new start up sequence
will initiate immediately.
Functional Description
The PS10/PS11 are designed to sequence up to 4 power
supply modules, ICs or subsystems when the backplane
voltage is within the programmed Under-voltage and Over-
voltage limits. The power good open drain outputs are
sequentially enabled starting from PWRGD-A to PWRGD-
D. The time delay between power goods is programmable
up to 200ms simply by changing the value(s) of RTB,
RTC, and RTD. The initial time between satisfaction of the
UV/OV supervisors & PWRGD-A can be programmed with
Cramp.
Programming the Under and Over Voltage Limits
The UV and OV pins are connected to comparators with
nominal 1.21V thresholds and 100mV of hysteresis (1.21V
± 50mV). They are used to detect under voltage and over
voltage conditions at the input to the circuit. Whenever the
OV pin rises above its high threshold (1.26V) or the UV pin
falls below its low threshold (1.16V), the PWRGD outputs
immediately deactivate.
Description of Operation
During the initial power application, the Power Good pins
are held low (rising with VIN) for PS10 and high for the
PS11. Once the internal under voltage lock out has been
satisfied, the circuit checks the input supply under voltage
(UV) and over voltage (OV) sense circuits to ensure that
the input voltage is within programmed limits. These limits
are determined by the selected values for R1, R2, and R3,
which form a voltage divider.
Calculations can be based on either the desired input volt-
age operating limits or the input voltage shutdown limits. In
the following equations the shutdown limits are assumed.
The undervoltage and overvoltage shut down thresholds
can be programmed by means of the three resistor divider
formed by R1, R2 and R3. Since the input currents on the
UV and OV pins are negligible the resistor values may be
calculated as follows:
At the same time, a 10µA current source is enabled,
charging the external capacitor connected to the ramp pin.
The rise time of the ramp pin is determined by the value of
the capacitor (10µA/Cramp). When the ramp voltage
reaches 8.8V, the PWRGD-A pin will change into an active
state. PWRGD-B will change into an active state after a
programmed time delay from PWRGD-A inactive to active
transition. PWRGD-C will change into an active state after
a programmed time delay from PWRGD-B inactive to ac-
tive transition. PWRGD-D will change into an active state
after a programmed time delay from PWRGD-C inactive to
active transition.
UVOFF = VUVL = 1.16 = (VEEUV(off)) x (R2+R3)/(R1+R2+R3)
OVOFF = VOVL = 1.26 = (VEEOV(off)) x R3/(R1+R2+R3)
4
PS10/PS11
Where (VEEUV(off)) and (VEEOV(off)) relative to VEE are Under and
Over Voltage Shut Down Threshold points.
From the calculated resistor values the OV and UV start
up threshold voltages can be calculated as follows:
If we select a divider current of 100 µA at a nominal oper-
ating input voltage of 50 Volts, then
UVON = VUVH = 1.26 = (VEEUV(on)) x (R2+R3)/(R1+R2+R3)
OVON = VOVL = 1.16 = (VEEOV(on)) x R3/(R1+R2+R3)
R1+R2+R3 = 50V/100µA = 500kΩ
Where (VEEUV(on)) and (VEEOV(on)) are Under and Over Voltage
Start Up Threshold points relative to VEE.
From the second equation, for an OV shut down threshold
of 65V, the value of R3 may be calculated.
Then
(VEEUV(on)) = 1.26 x (R1+R2+R3)/(R2+R3)
OVOFF = 1.26 = (65xR3)/500k
R3 = (1.26x 500k)/65 = 9.69k
The closest 1% value is 9.76kΩ.
(VEEUV(on)) = 1.26 x (487k+6.81k+9.76k)/(6.81k+9.76k )
= 38.29V
And
(VEEOV(on)) = 1.16 x (R1+R2+R3)/R3
(VEEOV(on) ) = 1.16 x (487k +6.81k +9.76k)/9.76k = 59.85V
From the first equation, for a UV shut down threshold of
35V, the value of R2 can be calculated.
Therefore, the circuit will start when the input supply volt-
age is in the range of 38.29V to 59.85V.
UVOFF = 1.16 = 35 x (R2+R3)/ 500k
R2 = ((1.16 x 500k)/35) – 9.76k = 6.81k
6.81kΩ is a standard 1% value
Then
R1 = 500k – R2 – R3 = 483Ω.
487KΩ, is a standard 1% value.
5
PS10/PS11
Undervoltage/Overvoltage Operation
PWRGD Flags Delay Programming
GND
When the ramp voltage hits Vint – 1.2V, PWRGD-A be-
comes active indicating that the input supply voltage is
within the programmed limits. PWRGD-B goes active after
a programmed time delay after PWRGD-A went active.
PWRGD-C goes active after a programmed time delay
after PWRGD-B went active. PWRGD-D goes active after
a programmed time delay after PWRGD-C went active.
UVOFF
UVON
Vin
OVON
OVOFF
The resistors connected from TB, TC, and TD to VEE pin
determines the delay times between the PWRGD flags.
The value of the resistors determines the capacitor charg-
ing and discharging current of a triangular wave oscillator.
The oscillator output is fed into an 8-bit counter to gener-
ate the desired time delay.
PWRGD
SET RESET
The respective time delay is defined by the following equa-
tion:
Start-up Timing (PS11 PWRGD-A Active Low)
t
TX = (255 x 2 x COSC x VPP)/ICD
and
CD = Vbg / (4 x RTX)
Where
I
t
C
V
TX = Time delay between respective PWRGD flags
OSC = 120pF (internal oscillator capacitor)
PP = 8.2V (peak-to-peak voltage swing of oscillator)
ICD = Charge and discharge current of oscillator
Vbg = 1.2V (internal band gap reference)
RTX = Programming resistor at TB, TC, or TD
Combining the two equations and solving for RTX yields:
RTX
= (Vbg x tTX) / (2040 x COSC x VPP)
= 0.6 x 106 x tTX
tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going
active. It can be approximated by
For a time delay of 200ms
RTX
= 0.6 x 106 x 0.2 = 120k
tPWRGD-A = CRAMP x (VINT-1.2)/IRAMP
For a time delay of 5ms
RTX
= 0.6 x 106 x 0.005 = 3k
where
CRAMP = capacitor connected from RAMP pin to VEE pin
VINT = internal regulated power supply voltage (10V typ)
I
RAMP = 10µA charge current
6
PS10/PS11
The following waveforms demonstrate the sequencing of
the PWRGD flags:
PWRGD Timing (Maximum Delays)
Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 121k,
RTC = 121k, RTD = 121k, RPULL-UP = 47k.
PWRGD Timing (PS11)
Test conditions: VIN = 48V, CRAMP = 10nF,
RTB = 121k, RTC = 60.4k, and RTD = 47.0k.
Relative to Negative Rail
PS11 Power Down Sequence after UVOFF
Relative to Negative Rail
Test conditions: CRAMP = 10nF, RTB = 3.3k, RTC = 3.3k, RTD
=
PWRGD Timing (Minimum Delays)
Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 3.3k,
RTC = 3.3k, RTD = 3.3k, RPULL-UP = 47k.
3.3k, RPULL-UP = 47k, CPWRGD_B = 0.47µF, CPWRGD_C = 0.94µF,
CPWRGD_D = 1.41µF, VUVOFF = 33.4V, the assumed brick turn-
off threshold is 2.7V min TTL logic high. See power down
sequencing on Page 11.
Relative to Negative Rail
Relative to Negative Rail
7
PS10/PS11
PS11 Power Down Sequence after OVOFF
Test conditions: CRAMP = 10nF, RTB = 3.3k, RTC = 3.3k, RTD
=
3.3k, RPULL-UP= 47k, CPWRGD_B = 0.47µF, CPWRGD_C = 0.94µF,
CPWRGD_D = 1.41µF, VOVOFF = 61.6V, the assumed brick turn-
off threshold is 2.7V min TTL logic high. See power down
sequencing on Page 11.
Relative to Negative Rail
PWRGD Output Configuration
The PS10 and PS11 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter.
The internal pull-up and clamp of the DC/DC converter sets the logic High Enable/Disable voltage.
GND
487K
VIN
V+
DC/DC
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
Converter
UV
+3.3V
COM
6.81K
9.76K
PS10
EN
V-
OV
VEE
TADJ
TB
TC
TD
Ramp
10nF
RTB
RTC
RTD
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
3. Other power good outputs will have the same
configuration as PWGRGD-A for Active High Enabled
Converters.
8
PS10/PS11
PWRGD Output Configuration, cont’d.
GND
487K
VIN
V+
DC/DC
PWRGD-D
Converter
UV
PWRGD-C
+3.3V
COM
6.81K
9.76K
PWRGD-B
PWRGD-A
PS11
/EN
V-
OV
VEE
TADJ
TB
TC
TD
Ramp
10nF
RTB
RTC
RTD
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
3. Other power good outputs will have the same
configuration as PWGRGD-A for Active Low Enabled
Converters.
Opto-isolated Enable
Some applications require opto-isolator interface to the Enable pin of the DC/DC converter. Make sure that the current transfer
ratio of the opto-coupler selected is at least 100% to ensure proper pull-down current on the Enable pin.
GND
487K
VIN
V+
DC/DC
PWRGD-D
49.9k
Converter
UV
PWRGD-C
PWRGD-B
PWRGD-A
+3.3V
COM
6.81K
9.76K
Opto-coupler
PS10
EN
V-
OV
VEE
TADJ
TB
TC
TD
Ramp
10nF
RTB
RTC
RTD
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
3. Other power good outputs will have the same
configuration as PWGRGD-A for Active High Enabled
Converters.
9
PS10/PS11
Opto-isolated Enable, cont’d.
GND
487K
VIN
DC/DC
Converter
V+
PWRGD-D
49.9k
UV
PWRGD-C
PWRGD-B
PWRGD-A
+3.3V
COM
6.81K
9.76K
Opto-coupler
PS11
/EN
V-
OV
TADJ
VEE
TB
TC
TD
Ramp
10nF
RTB
RTC
RTD
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
3. Other power good outputs will have the same
configuration as PWGRGD-A for Active Low Enabled
Converters.
Increasing the Under and Over Voltage Hysteresis
If the internal UV hysteresis is insufficient for a particular system application, then it may be increased by using separate resis-
tor dividers for UV and OV and providing a resistor feedback from UV pin to the PWRGD pin.
GND
499k
487k
VIN
V+
DC/DC
PWRGD-D
Converter
UV
PWRGD-C
PWRGD-B
+3.3V
COM
PS10
Ruvhys
EN
V-
PWRGD-A
OV
VEE
TADJ
TB
TC
TD
Ramp
16.5k
9.76k
10nF
RTB
RTC
RTD
-48V
Note:
Ruvhys can be calculated based on higher UV On voltage (say
42V):
1. Other power good outputs will have the same configuration as
PWGRGD-A for Active High Enabled Converters.
Ruvhys = (Vuvon - Vdiode - Vpwrgdlow)/((Vin-Vuvon)/487k -
Vuvon/16.5k)
= (1.26-0.65-0.4)/((42-1.26)/487k - 1.26/16.5k)
= 28.8k
10
PS10/PS11
Increasing the Under and Over Voltage Hysteresis, cont’d.
GND
499k
487k
VIN
V+
DC/DC
Converter
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
+3.3V
UV
PS11
/EN
V-
OV
COM
TADJ
Ruvhys
9.76k
VEE
TB
TC
TD
Ramp
10k
16.5k
10nF
RTB
RTC
RTD
-48V
Note:
1. Other power good outputs will have the same configuration as
PWGRGD-A for Active Low Enabled Converters.
Ruvhys can be calculated based on higher UV On voltage (say
42V):
Ruvhys = (Vuvon - Vdiode - Vce/((Vin-Vuvon)/487k -
Vuvon/16.5k)
= (1.26-0.65-0.1)/((42-1.26)/487k - 1.26/16.5k)
= 69.9k
Power Down Sequencing
In some applications, a power down sequence may be required. To accomplish this, a capacitor is connected to the power
good pins that need to be sequenced down. The power good turn off delays can be approximated by
T
PWRGD-B(off) = C1 x VENOFF / IPULLUP
,
,
,
TPWRGD-C(off) = C2 x VENOFF / IPULLUP
TPWRGD-D(off) = C3 x VENOFF / IPULLUP
where:
TPWRGD-B(off)-Time delay from PWRGD-A going High to PWRGD-B going high.
TPWRGD-c(off) -Time delay from PWRGD-A going High to PWRGD-C going high.
TPWRGD-D(off)-Time delay from PWRGD-A going High to PWRGD-D going high.
VENOFF
IPULLUP
- DC/DC minimum off voltage (2.7V typ)
- DC/DC /EN pin pull-up current (1mA typ)
Note: Adding C1, C2, C3 will have a negligible affect on the power good fall time.
GND
487K
V
IN
/EN4
V+
DC/DC
Converter
PWRGD-D
UV
/EN3
/EN2
PWRGD-C
PWRGD-B
+3.3V
COM
6.81K
9.76K
PS11
/EN
V-
PWRGD-A
OV
TADJ
VEE
TB
TC
TD
Ramp
10nF
C3
C2
C1
RTB
RTC
RTD
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
3. Only PWRGD-A to DC/DC converter connection is shown
for simplicity.
11
PS10/PS11
PS10 Power Good Clamp
If the active high enabled dc/dc converter used does not have an internal clamp, an external zener diode may be used to pro-
tect the module.
GND
487K
VIN
V+
49.9k
DC/DC
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
Converter
UV
+3.3V
COM
6.81K
9.76K
PS10
EN
OV
VEE
TADJ
V-
TB
TC
TD
Ramp
10nF
RTB
RTC
RTD
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
3. Other power good outputs will have the same
configuration as PWGRGD-A for Active High Enabled
Converters.
Extending the PWRGD-A time Delay
The time delay from UV high to PWRGD-A active can be extended by connecting a low impedance voltage source like a DAC
output during start-up. A voltage 0 to 50mV applied to the TADJ pin will reduce the 10µA Cramp charging current according to:
IRAMP = 10µA – VTADJ/5K
Reducing the charging current will extend the PWRGD-A delay by:
TPWRGD-A = (CRAMP x 8.8V)/(10µA – VTADJ/5K)
Rearranging the equation
VTADJ = 5k x (10µA – CRAMP x 8.8V/ TPWRGD-A
)
For a 20ms delay, for example,
VTADJ = 5k x (10µA – 10nF x 8.8V/ 20ms) = 0.028V
GND or +48V
14
/EN
+12V
COM
487K
DC/DC
VIN
1
Converter
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
/
/
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
6
UV
OV
2
3
4
10V
/
6.81K
9.76K
/EN
+5V
COM
PS10/PS11
/
DC/DC
5
8
Converter
10uA
TADJ
/EN
+3.3V
COM
+
-
DC/DC
Converter
5k
7
EE
V
/EN
+2.5V
COM
Ramp
10
TB
11
TC
TD
13
DC/DC
Converter
+
12
0
-
50mV
DAC
RTB
RTC
RTD
10nF
-
-48V or GND
Notes:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) to 65V.
12
PS10/PS11
Typical Application Circuit for a 12V Non-Isolated System
Most FPGAs, Processors, ASICs, and DSPs require sequencing and rail voltage limititation during start-up and power down
sequence of its rails. A typical requirement is: VDD_CORE must not exceed VDD_IO more than 0.6V and VDD_IO must not ex-
ceed VIN at any time. This can be accomplished by sequencing the dc/dc converters by the following manner:
Turn On: VDD_CORE first, VDD_IO second, and VIN last.
Tun-Off: VIN first, VDD_IO second, and VDD_CORE last.
The Schottky diodes will limit the voltage between the rails to around 0.3V @ 3A during the power-up and power-down se-
quence.
Assuming that the /EN pins of the dc/dc converters have no pull-up and have a 1.0V turn-off threshold, the power-down se-
quence time delays can be approximated by:
T
T
PWRGD-C to TPWRGD-B = 1µF x 1V / 1mA = 1ms
PWRGD-B to TPWRGD-A = (2µF-1µF) x 1V / 1mA = 1ms
+12V
R9 R8
12k 12k
14
R1
VIN
1
2
3
6
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
/EN
Buck
UV
+5V
/EN
VIN
Converter
R2
30BQ015
LOAD
4
5
PS11
OV
+3.3V
/EN
Buck
VDD_IO
Converter
7
R3
VEE
VDD_CORE
GND
30BQ015
+2.5V
TB
11
TC
12
TD
13
Ramp
10
TADJ
8
Buck
Converter
10nF
C2
C1
RTB
RTC
RTD
2uF 1uF
GND
04/07/03rev7b
1225 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 222-8888 · FAX: (408) 222-4895
www.supertex.com
Supertex inc.
©2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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