TN1504NW [SUPERTEX]

N-Channel Enhancement-Mode Vertical DMOS FETs; N沟道增强型垂直DMOS场效应管


型号：	TN1504NW
厂家：	Supertex, Inc
描述：	N-Channel Enhancement-Mode Vertical DMOS FETs N沟道增强型垂直DMOS场效应管晶体晶体管功率场效应晶体管开关
文件：	总2页 (文件大小：311K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TN1504/TN1506/TN1510

Low Threshold

N-Channel Enhancement-Mode

Vertical DMOS FETs

Features

General Description

These low threshold enhancement-mode (normally-off)

transistors utilize a vertical DMOS structure and Supertex’s

well-proven silicon-gate manufacturing process. This combi-

nationproducesdeviceswiththepowerhandlingcapabilities

of bipolar transistors, and with the high input impedance and

positive temperature coefﬁcient inherent in MOS devices.

Characteristic of all MOS structures, these devices are free

from thermal runaway and thermally-induced secondary

breakdown.

► Low threshold - 2.0V max.

► High input impedance

► Low input capacitance - 50pF typical

► Fast switching speeds

► Low on resistance

► Free from secondary breakdown

► Low input and output leakage

► Complementary N- and P-channel devices

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

lowthresholdvoltage,highbreakdownvoltage,highinputim-

pedance, low input capacitance, and fast switching speeds

are desired.

Applications

► Logic level interfaces – ideal for TTL and CMOS

► Solid state relays

► Battery operated systems

► Photo voltaic drives

► Analog switches

► General purpose line drivers

► Telecom switches

Absolute Maximum Ratings

Parameter

Value

BV_DSS

BV_DGS

20V

Drain-to-source voltage

Operating and storage temperature

-55^OC to +150^OC

Absolute Maximum Ratings are those values beyond which damage to the

device may occur. Functional operation under these conditions is not implied.

Continuous operation of the device at the absolute rating level may affect

device reliability. All voltages are referenced to device ground.

Ordering Information

Order Number

R_DS(ON)

(max)

V_GS(th)

(max)

I_D(ON)

(min)

Device

BV_DSS/ BV_DGS

Die*

TN1504

TN1506

TN1504NW

TN1506NW

TN1510NW

40V

60V

3.0Ω

2.0V

2.0A

TN1510

100V

* Die in wafer form.

TN1504/TN1506/TN1510

Electrical Characteristics (@25^OC unless otherwise speciﬁed)

Symbol

Parameter

Min

Typ

Max

Units Conditions

TN1504

TN1506

TN1510

100

0.6

Drain-to-source break-

down voltage

BV_DSS

V_GS= 0V, I_D= 1.0mA

V_GS(th)

∆V_GS(th)

I_GSS

Gate threshold voltage

2.0

-5.0

100

V_GS= V_DS, I_D= 0.5mA

Change in V_GS(th)with temperature

Gate body leakage

-3.8

0.1

mV/^OC V_GS= V_DS, I_D= 1.0mA

μA

V_GS= 20V, V_DS= 0V

V_GS=0V, V_DS= Max Rating

I_DSS

Zero gate voltage drain current

V_GS= 0V, V_DS= 0.8 Max Rating

T_A= 125^OC

500

1.4

3.4

2.0

1.6

0.6

400

V_GS= 5V, V_DS= 25V

V_GS= 10V, V_DS= 25V

V_GS= 4.5V, I_D= 250mA

V_GS= 10V, I_D= 500mA

V_GS= 10V, I_D= 0.5A

I_D(ON)

ON-state drain current

4.5

3.0

1.1

Static drain-to-source ON-state

resistance

R_DS(ON)

∆R_DS(ON)

G_FS

Change in R_DS(ON)with temperature

Forward transconductance

Input capacitance

%/^OC

225

mmho V_DS= 25V, I_D= 500mA

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

8.05

5.0

7.0

6.0

1.5

Common source output capacitance

Reverse transfer capacitance

Turn-ON delay time

V_GS= 0V, V_DS= 25V f = 1 MHz

4.0

2.0

3.0

6.0

3.0

1.0

400

Rise time

V_DD= 25V, I_D= 1.0A

_GEN= 25Ω

t_d(OFF)

t_f

Turn-OFF delay time

Fall time

V_SD

Diode forward voltage drop

Reverse recovery time

V_GS= 0V, I_SD= 0.5A

t_rr

Notes:

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

V_DD

R_L

10V

90%

INPUT

PULSE

GENERATOR

10%

OUTPUT

t_(ON)

t_d(ON)

t_(OFF)

t_d(OFF)

R_GEN

t_r

t_F

V_DD

D.U.T.

10%

INPUT

OUTPUT

90%

Doc.# DSFP-TN1504/TN1506/TN1510

062706

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