TP5322K1 [SUPERTEX]
P-Channel Enhancement-Mode Vertical DMOS FET; P沟道增强型垂直DMOS FET
| 型号： | TP5322K1 |
| 厂家： | 
Supertex, Inc |
| 描述： | P-Channel Enhancement-Mode Vertical DMOS FET |
| 文件： | 总2页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP5322
Initial Release
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
General Description
These low threshold enhancement-mode (normally-off)
transistors utilize an advanced vertical DMOS structure and
Supertex's well-proven silicon-gate manufacturing process. This
combination produces devices with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent in MOS
devices. Characteristic of all MOS structures, these devices are
free from thermal runaway and thermally-induced secondary
breakdown.
ꢀ Low threshold, -2.4V max.
ꢀ High input impedance
ꢀ Low input capacitance, 110pFmax.
ꢀ Fast switching speeds
ꢀ Low on resistance
ꢀ Free from secondary breakdown
ꢀ Low input and output leakage
ꢀ Complementary N- and P-channel devices
Supertex's vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very low
threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds are
desired.
Application
ꢀ Logic level interfaces-ideal for TTL and CMOS
ꢀ Battery operated systems
ꢀ Photo voltaic devices
Package Options
ꢀ Analog switches
ꢀ General purpose line drivers
ꢀ Telecom switches
D
D
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
G
G
BVDSS
BVDGS
±20V
D
S
S
Gate-to-Source Voltage
TO-243AA
(SOT-89)*
TO-236AB
(SOT-23)*
Operating and Storage Temperature
Soldering Temperature****
****Distance of 1.6mm from case for 10 seconds.
-55°C to +150°C
300°C
* "Green" Certified Package
Product Marking for SOT-89
TP3C✶
Ordering Information
VGS(th)
(max)
ID(ON)
(min)
Order Number / Package
Where ✶=2-week alpha date code
BVDSS
BVDGS
/
RDS(ON)
(max)
TO-243AA**
TP5322N8
TO-236AB***
TP5322K1
-220V
-220V
-2.4V
-2.4V
-0.7A
-0.7A
12Ω
12Ω
Product Marking for SOT-23
P3C✶
TP5322N8-G*
TP5322K1-G*
**Same as SOT-89. Product supplied on 2000 piece carrier tape reels.
***Same as SOT-23. Products supplied on 3000 piece carrier tape reels.
Where ✶=2-week alpha date code
A042005
TP5322
Thermal Characteristics
Package
ID (continuous)
ID (pulsed)
Power Dissipation @
TA = 25°C
IDR*
IDRM
θJC
°C/W
15
θJA
°C/W
78**
350
TO-243AA
TO-236AB
-0.26A
-0.12A
-0.90A
-0.70A
1.6W
0.36W
-0.26A
-0.12A
-0.9A
-0.7A
200
*ID(continous) is limited by max rated Tj.
**Mounted on FR4 board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substate.
Electrical Characteristics (@25°C unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
Conditions
BVDSS
Drain-to-Source
-220
V
VGS = 0V, ID = -2mA
Breakdown Voltage
VGS(th)
∆VGS(th)
IGSS
Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
-1.0
-2.4
4.5
-100
-10
V
VGS = VDS, ID = -1mA
mV/°C VGS = VDS, ID = -1mA
nA
µA
mA
VGS = ±20V, VDS = 0V
VGS = 0V, VDS = Max Rating
VGS = 0V, VDS = 0.8 Max
IDSS
Zero Gate Voltage Drain Current
-1.0
Rating, TA = 125°C
ID(ON)
On-State Drain Current
-0.7
100
-0.95
10
8.0
A
Ω
VGS = -10V, VDS = -25V
VGS = -4.5V, ID = -100mA
RDS(ON) Static Drain-to-Source
ON-State Resistance
15
12
1.7
VGS = -10V, ID = -200mA
Change in RDS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
%/°C
VGS = -10V, ID = -200mA
∆RDS(ON)
GFS
CISS
COSS
CRSS
td(ON)
tr
250
mmho VDS = -25V, ID = -200mA
VGS = 0V, VDS = -25V
pF
110
45
20
10
15
f = 1MHz
VDD = -25V,
ID = -0.7A
ns
R
GEN = 25 Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
20
15
VSD
trr
Diode Forward Voltage Drop
Reverse Recovery Time
-1.8
V
ns
VGS = 0V, ISD = -0.5A
VGS = 0V, ISD = -0.5A
300
Notes:
1) All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
2) All AC parameters sample tested.
Switching Waveforms and Test Circuit
0V
Pulse
Generator
Input
RGEN
-10V
t(ON)
td(ON)
t(OFF)
D.U.T
Input
tr
td(OFF) tf
OUTPUT
0V
RL
Output
VDD
VDD
Doc.# DSFP-TP5322
A042005
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