IAM-20381 [TDK]
加速度传感器;
| 型号： | IAM-20381 |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | 加速度传感器 传感器 |
| 文件： | 总44页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IAM-20381
High Performance 3-Axis MotionTracking Accelerometer
GENERAL DESCRIPTION
APPLICATIONS
The IAM-20381 is a 3-axis MotionTracking accelerometer
for Automotive applications in a small 3x3x0.75 mm (16-
pin LGA) package. It also features a 512-byte FIFO that
can lower the traffic on the serial bus interface and
reduce power consumption by allowing the system
processor to burst read sensor data and then go into a
low-power mode. IAM-20381, with its 3-axis integration,
enables manufacturers to eliminate the costly and
complex selection, qualification, and system level
integration of discrete devices, guaranteeing optimal
motion performance.
•
•
•
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and
Infrastructure
360º View Camera Stabilization
Car Alarm
Telematics
Insurance Vehicle Tracking
•
•
•
•
ORDERING INFORMATION
PART
AXES
TEMP RANGE
PACKAGE
MSL*
IAM-20381†
X,Y,Z
-40°C to +85°C
16-Pin LGA
3
The accelerometer has a user-programmable
accelerometer full-scale range of ±2g, ±4g, ±8g, and
±16g. Factory-calibrated initial sensitivity of both sensors
reduces production-line calibration requirements.
†Denotes RoHS and Green-compliant package
* Moisture sensitivity level of the package
FEATURES
Other industry-leading features include on-chip 16-bit
ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The
device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate digital
IO supply, VDDIO from 1.71V to 3.6V.
•
Digital-output X-, Y-, and Z-axis accelerometer
with a programmable full scale range of ±2g,
±4g, ±8g, and ±16g and integrated 16-bit ADCs
User-programmable digital filters for
accelerometer, and temperature sensor
Self-test
Wake-on-motion interrupt for low power
operation of applications processor
Reliability testing performed per
AEC–Q100
•
•
•
BLOCK DIAGRAM
IAM-20381
•
INT
Interrupt
Status
Register
o
PPAP and qualification data available
upon request
CS
Slave I2C and
SA0 / SDO
Self
test
SPI Serial
Interface
X Accel
ADC
ADC
FIFO
SCL / SPC
SDA / SDI
TYPICAL OPERATING CIRCUIT
User & Config
Registers
Self
test
Y Accel
Z Accel
FSYNC
Sensor
Registers
Self
test
1.8 – 3.3VDC
ADC
ADC
VDD
C2, 0.1 µF
C4, 2.2 µF
REGOUT
16 15 14
Temp Sensor
C1, 0.47 µF
GND
VDDIO
1.8 – 3.3 VDC
C3, 10 nF
13
12
11
10
9
1
2
3
4
5
RESV
SCL/SPC
SDA/SDI
SCL
SDA
AD0
RESV
RESV
IAM-20381
SA0/SDO
CS
Bias & LDOs
VDDIO
RESV
VDD
GND
REGOUT
6
7
8
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
Document Number: DS-000216
Revision: 1.0
Rev. Date: 03/29/2017
InvenSense reserves the right to change the detail
specifications as may be required to permit
improvements in the design of its products.
www.invensense.com
IAM-20381
TABLE OF CONTENTS
General Description .............................................................................................................................................1
Block Diagram ......................................................................................................................................................1
Applications .........................................................................................................................................................1
Ordering Information...........................................................................................................................................1
Features ...............................................................................................................................................................1
Typical Operating Circuit......................................................................................................................................1
TABLE OF CONTENTS....................................................................................................................................................... 2
LIST OF FIGURES.............................................................................................................................................................. 4
LIST OF TABLES................................................................................................................................................................ 5
1
Introduction......................................................................................................................................................... 6
Purpose and Scope....................................................................................................................................6
Product Overview......................................................................................................................................6
Applications...............................................................................................................................................6
Features ............................................................................................................................................................... 7
Accelerometer Features............................................................................................................................7
Additional Features...................................................................................................................................7
Electrical Characteristics...................................................................................................................................... 8
Accelerometer Specifications....................................................................................................................8
Electrical Specifications.............................................................................................................................9
I2C Timing Characterization.....................................................................................................................12
SPI Timing Characterization ....................................................................................................................13
Absolute Maximum Ratings ....................................................................................................................14
Applications Information ................................................................................................................................... 15
Pin Out Diagram and Signal Description .................................................................................................15
Typical Operating Circuit.........................................................................................................................16
Bill of Materials for External Components..............................................................................................16
Block Diagram .........................................................................................................................................17
Overview .................................................................................................................................................17
Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning.........................................18
I2C and SPI Serial Communications Interfaces ........................................................................................18
Self-Test...................................................................................................................................................19
Clocking...................................................................................................................................................19
Sensor Data Registers .........................................................................................................................19
FIFO.....................................................................................................................................................20
Interrupts............................................................................................................................................20
Digital-Output Temperature Sensor ...................................................................................................20
Bias and LDOs .....................................................................................................................................20
Charge Pump ......................................................................................................................................20
Standard Power Modes ......................................................................................................................20
2
3
4
Document Number: DS-000216
Revision: 1.0
Page 2 of 44
IAM-20381
5
6
Programmable Interrupts .................................................................................................................................. 21
Wake-on-Motion Interrupt .....................................................................................................................21
Digital Interface ................................................................................................................................................. 22
I2C and SPI Serial Interfaces ....................................................................................................................22
I2C Interface.............................................................................................................................................22
IC Communications Protocol...................................................................................................................22
I2C Terms .................................................................................................................................................24
SPI Interface ............................................................................................................................................25
Serial Interface Considerations.......................................................................................................................... 26
IAM-20381 Supported Interfaces............................................................................................................26
Register Map...................................................................................................................................................... 27
Register Descriptions ......................................................................................................................................... 29
Registers 13 to 15 – Accelerometer Self-Test Registers..........................................................................29
Register 25 – Sample Rate Divider ..........................................................................................................29
Register 26 – Configuration.....................................................................................................................29
Register 28 – Accelerometer Configuration............................................................................................30
Register 29 – Accelerometer Configuration 2.........................................................................................31
Register 31 – Wake-on Motion Threshold (Accelerometer) ...................................................................32
Register 35 – FIFO Enable........................................................................................................................32
Register 54 – FSYNC Interrupt Status......................................................................................................32
Register 55 – INT/DRDY Pin / Bypass Enable Configuration....................................................................32
Register 56 – Interrupt Enable............................................................................................................33
Register 58 – Interrupt Status.............................................................................................................33
Registers 59 to 64 – Accelerometer Measurements ..........................................................................33
Registers 65 and 66 – Temperature Measurement............................................................................34
Register 104 – Signal Path Reset.........................................................................................................34
Register 105 – Accelerometer Intelligence Control............................................................................34
Register 106 – User Control................................................................................................................35
Register 107 – Power Management 1 ................................................................................................35
Register 108 – Power Management 2 ................................................................................................35
Registers 114 and 115 – FIFO Count Registers ...................................................................................36
Register 116 – FIFO Read Write..........................................................................................................36
Register 117 – Who Am I ....................................................................................................................36
Registers 119, 120, 122, 123, 125, 126 Accelerometer Offset Registers............................................37
Assembly............................................................................................................................................................ 38
Orientation of Axes.............................................................................................................................38
Package Dimensions ...........................................................................................................................39
Part Number Package Marking.......................................................................................................................... 41
Reference........................................................................................................................................................... 42
Revision History ................................................................................................................................................. 43
7
8
9
10
11
12
13
Document Number: DS-000216
Revision: 1.0
Page 3 of 44
IAM-20381
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram.............................................................................................................................................................12
Figure 2. SPI Bus Timing Diagram.............................................................................................................................................................13
Figure 3. Pin out Diagram for IAM-20381 3.0x3.0x0.75 mm LGA ............................................................................................................15
Figure 4. IAM-20381 LGA Application Schematic ....................................................................................................................................16
Figure 5. IAM-20381 Block Diagram ........................................................................................................................................................17
Figure 6. IAM-20381 Solution Using I2C Interface....................................................................................................................................18
Figure 7. IAM-20381 Solution Using SPI Interface ...................................................................................................................................19
Figure 8. START and STOP Conditions......................................................................................................................................................22
Figure 9. Acknowledge on the I2C Bus .....................................................................................................................................................23
Figure 10. Complete I2C Data Transfer.....................................................................................................................................................23
Figure 11. Typical SPI Master/Slave Configuration ..................................................................................................................................25
Figure 12. I/O Levels and Connections.....................................................................................................................................................26
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation ....................................................................................................38
Figure 14. Package Dimensions................................................................................................................................................................39
Figure 15. Part Number Package Marking ...............................................................................................................................................41
Document Number: DS-000216
Revision: 1.0
Page 4 of 44
IAM-20381
LIST OF TABLES
Table 1. Accelerometer Specifications.......................................................................................................................................................8
Table 2. D.C. Electrical Characteristics.......................................................................................................................................................9
Table 3. A.C. Electrical Characteristics .....................................................................................................................................................11
Table 4. Other Electrical Specifications....................................................................................................................................................11
Table 5. I2C Timing Characteristics...........................................................................................................................................................12
Table 6. SPI Timing Characteristics (8 MHz Operation) ...........................................................................................................................13
Table 7. Absolute Maximum Ratings .......................................................................................................................................................14
Table 8. Signal Descriptions .....................................................................................................................................................................15
Table 9. Bill of Materials ..........................................................................................................................................................................16
Table 10. Standard Power Modes for IAM-20381 ...................................................................................................................................20
Table 11. Table of Interrupt Sources........................................................................................................................................................21
Table 12. Serial Interface .........................................................................................................................................................................22
Table 13. I2C Terms ..................................................................................................................................................................................24
Table 14. Configuration............................................................................................................................................................................30
Table 15. Accelerometer Data Rates and Bandwidths (Low Noise Mode) ..............................................................................................31
Table 16. Accelerometer Filter Bandwidths, Noise, and Current Consumption (Low-Power Mode) ......................................................31
Table 17. Package Dimensions.................................................................................................................................................................40
Table 18. Part Number Package Marking ................................................................................................................................................41
Document Number: DS-000216
Revision: 1.0
Page 5 of 44
IAM-20381
1 INTRODUCTION
PURPOSE AND SCOPE
This document is a product specification, providing description, specifications, and design related information on the IAM-20381
Automotive MotionTracking device. The device is housed in a small 3x3x0.75 mm 16-pin LGA package.
PRODUCT OVERVIEW
The IAM-20381 is a 3-axis MotionTracking accelerometer for Automotive applications, in a small 3x3x0.75 mm (16-pin LGA) package.
It also features a 512-byte FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the
system processor to burst read sensor data and then go into a low-power mode. IAM-20381, with its 3-axis integration, enables
manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices,
guaranteeing optimal motion performance.
The accelerometer has a user-programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated initial
sensitivity of both sensors reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate
digital IO supply, VDDIO from 1.71V to 3.6V.
Communication with all registers of the device is performed using either I2C at 400 kHz or SPI at 8 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
3x3x0.75 mm (16-pin LGA), to provide a very small yet high-performance, low-cost package. The device provides high robustness by
supporting 10,000g shock reliability.
APPLICATIONS
•
•
•
•
•
•
•
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and Infrastructure
360º View Camera Stabilization
Car Alarm
Telematics
Insurance Vehicle Tracking
Document Number: DS-000216
Revision: 1.0
Page 6 of 44
IAM-20381
2 FEATURES
ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in IAM-20381 includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g and ±16g and
integrated 16-bit ADCs
•
•
•
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
ADDITIONAL FEATURES
The IAM-20381 includes the following additional features:
•
•
•
•
•
•
•
•
•
Smallest and thinnest LGA package for portable devices: 3x3x0.75 mm (16-pin LGA)
512-byte FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for accelerometer, and temperature sensor
10,000g shock tolerant
400 kHz Fast Mode I2C for communicating with all registers
8 MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Document Number: DS-000216
Revision: 1.0
Page 7 of 44
IAM-20381
3 ELECTRICAL CHARACTERISTICS
ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
All Zero-g output, sensitivity, and noise specifications include board soldering effects.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
Output in two’s complement format
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
Best Fit Straight Line for 2g, 25°C
25°C
±2
±4
±8
±16
16
16,384
8,192
4,096
2,048
g
g
g
3
3
3
3
3
3
3
3
3
1
1
Full-Scale Range
g
ADC Word Length
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
Sensitivity Scale Factor
Nonlinearity
Cross-Axis Sensitivity
-0.25
+0.25
±5
%
ZERO-G OUTPUT
All axes, 25°C
Zero-G Level Change vs. Temperature -40°C to +85°C
Initial Tolerance
±50
±50
mg
mg
1
1
NOISE PERFORMANCE
Low noise mode, -40°C to +85°C
Low noise mode, -40°C to +85°C, including
lifetime drift
135
190
µg/√Hz
µg/√Hz
1,4
1,4
Power Spectral Density
Low Pass Filter Response
Programmable Range
From Sleep mode
From Cold Start, 1ms VDD ramp
Low power (duty-cycled)
Low noise (active)
5
218
20
30
500
4000
Hz
ms
ms
Hz
Hz
3
1
1
Accelerometer Startup Time
0.24
4
Output Data Rate
1
Table 1. Accelerometer Specifications
Please contact TDK for a datasheet with maximum and minimum performance values over temperature and lifetime.
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
4. Calculated from Total RMS Noise.
Document Number: DS-000216
Revision: 1.0
Page 8 of 44
IAM-20381
ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
MIN
TYP
MAX
UNITS
NOTES
VDD
VDDIO
1.71
1.71
1.8
1.8
3.6
3.6
V
V
1
1
SUPPLY CURRENTS & BOOT TIME
3-axis Accelerometer, 4 kHz ODR
Normal Mode
Accelerometer Low -Power Mode
390
57
6
µA
µA
µA
1
2
1
100 Hz ODR, 1x averaging
Full-Chip Sleep Mode
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
°C
1
Table 2. D.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Based on simulation.
Document Number: DS-000216
Revision: 1.0
Page 9 of 44
IAM-20381
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Supply Ramp Time (TRAMP
)
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
0.01
100
ms
1
TEMPERATURE SENSOR
Operating Range
Room Temperature Offset
Sensitivity
Ambient
25°C
Untrimmed
-40
85
°C
°C
LSB/°C
1
1
1
0
326.8
POWER-ON RESET
Supply Ramp Time (TRAMP
)
Valid power-on RESET
From power-up
From sleep
0.01
100
100
5
ms
ms
ms
1
1
1
11
Start-up time for register read/write
SA0 = 0
SA0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
pF
0.3*VDDIO
1
1
< 10
DIGITAL OUTPUT (SDO, INT)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD=1 MΩ;
0.9*VDDIO
V
V
V
RLOAD=1 MΩ;
OPEN=1, 0.3 mA sink
Current
0.1*VDDIO
0.1
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
LATCH_INT_EN=0
100
50
nA
µs
I2C I/O (SCL, SDA)
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
-0.5V
0.7*VDDIO
0.3*VDDIO
VDDIO + 0.5
V
V
V
Vhys, Hysteresis
0.1*VDDIO
V
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3 mA sink current
VOL=0.4V
VOL=0.6V
0
0.4
V
1
3
6
100
mA
mA
nA
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
Cb bus capacitance in pf
20+0.1Cb
300
ns
Document Number: DS-000216
Revision: 1.0
Page 10 of 44
IAM-20381
INTERNAL CLOCK SOURCE
FCHOICE_B=1,2,3
SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=0 or 7
SMPLRT_DIV=0
FCHOICE_B=0;
32
8
kHz
kHz
2
2
Sample Rate
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
1
kHz
2
CLK_SEL=0, 6; 25°C
CLK_SEL=1,2,3,4,5; 25°C
CLK_SEL=0,6
-5
-1
-10
-1
+5
+1
+10
+1
%
%
%
%
1
1
1
1
Clock Frequency Initial Tolerance
Frequency Variation over
Temperature
CLK_SEL=1,2,3,4,5
Table 3. A.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SERIAL INTERFACE
MIN
TYP
MAX
UNITS NOTES
100
±10%
1
Low Speed Characterization
High Speed Characterization
kHz
1
SPI Operating Frequency, All
Registers Read/Write
8
MHz
1, 2
Modes 0
and 3
SPI Modes
All registers, Fast-mode
All registers, Standard-mode
400
100
kHz
kHz
1
1
I2C Operating Frequency
Table 4. Other Electrical Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. SPI clock duty cycle between 45% and 55% should be used for 8-MHz operation.
Document Number: DS-000216
Revision: 1.0
Page 11 of 44
IAM-20381
I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETERS
I2C TIMING
CONDITIONS
I2C FAST-MODE
MIN
TYP
MAX
UNITS
NOTES
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
400
kHz
µs
1
1
0.6
tLOW, SCL Low Period
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
1.3
0.6
0.6
0
100
20+0.1Cb
20+0.1Cb
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
300
300
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time
< 400
pF
µs
µs
1
1
1
0.9
0.9
Table 5. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
t
f
tSU.DAT
tr
SDA
SCL
70%
30%
70%
30%
continued below at
9th clock cycle
A
tf
t
r
tVD.DAT
70%
30%
70%
30%
tHD.DAT
tHD.STA
1/fSCL
t
LOW
1st clock cycle
S
tHIGH
tBUF
SDA
SCL
70%
30%
A
tSU.STO
t
SU.STA
tHD.STA
tVD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000216
Revision: 1.0
Page 12 of 44
IAM-20381
SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
NOTES
PARAMETERS
SPI TIMING
CONDITIONS
MIN
TYP
MAX
UNITS
fSPC, SPC Clock Frequency
tLOW, SPC Low Period
tHIGH, SPC High Period
tSU.CS, CS Setup Time
tHD.CS, CS Hold Time
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
2
56
56
2
63
3
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
tFall, SCLK Fall Time
7
Cload = 20 pF
Cload = 20 pF
40
6
20
6.5
6.5
tRise, SCLK Rise Time
Table 6. SPI Timing Characteristics (8 MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
tHD;CS
tSU;CS
t
HIGH
1/fCLK
SCLK
70%
30%
tSU;SDI
t
HD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
t
DIS;SDO
tVD;SDO
t
HD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. SPI Bus Timing Diagram
Document Number: DS-000216
Revision: 1.0
Page 13 of 44
IAM-20381
ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
PARAMETER
RATING
-0.5V to +4V
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
-0.5V to +4V
-0.5V to 2V
Input Voltage Level (SA0, FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
-0.5V to VDDIO + 0.5V
10,000g for 0.2 ms
-40°C to +85°C
-40°C to +125°C
2 kV (HBM);
250V (MM)
JEDEC Class II (2),125°C
±100 mA
Storage Temperature Range
Electrostatic Discharge (ESD) Protection
Latch-up
Table 7. Absolute Maximum Ratings
Document Number: DS-000216
Revision: 1.0
Page 14 of 44
IAM-20381
4 APPLICATIONS INFORMATION
PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
PIN NAME
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
PIN DESCRIPTION
Digital I/O supply voltage
1
2
3
4
5
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
I2C slave address LSB (SA0); SPI serial data output (SDO)
Chip select (0 = SPI mode; 1 = I2C mode)
Interrupt digital output (totem pole or open-drain)
Reserved. Do not connect.
6
7
INT
RESV
8
9
FSYNC
RESV
Synchronization digital input (optional). Connect to GND if unused.
Reserved. Connect to GND.
10
11
12
13
14
15
RESV
RESV
RESV
GND
REGOUT
RESV
Reserved. Connect to GND.
Reserved. Connect to GND.
Reserved. Connect to GND.
Connect to GND
Regulator filter capacitor connection
Reserved. Connect to GND.
16
VDD
Power Supply
Table 8. Signal Descriptions
Note: Power up with SCL/SPC and CS pins held low is not a supported use case. In case this power up approach is used, software reset is required using the
PWR_MGMT_1 register, prior to initialization.
16 15 14
13
12
11
10
9
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
1
2
3
4
5
GND
+Z
RESV
RESV
RESV
RESV
IAM-20381
IAM
-
20381
+Y
+X
6
7
8
LGA Package (Top View)
16-pin, 3mm x 3mm x 0.75mm
Typical Footprint and thickness
Orientation of Axes of Sensitivity and Polarity of Rotation
Figure 3. Pin out Diagram for IAM-20381 3.0x3.0x0.75 mm LGA
Document Number: DS-000216
Revision: 1.0
Page 15 of 44
IAM-20381
TYPICAL OPERATING CIRCUIT
1.8 – 3.3VDC
VDD
C4, 2.2 µF
C2, 0.1 µF
REGOUT
16 15 14
C1, 0.47 µF
GND
VDDIO
1.8 – 3.3 VDC
13
12
11
10
9
1
2
3
4
5
RESV
C3, 10 nF
SCL
SCL/SPC
SDA/SDI
RESV
RESV
IAM-20381
SDA
SA0/SDO
CS
AD0
VDDIO
RESV
6
7
8
Figure 4. IAM-20381 LGA Application Schematic
Note: I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required.
BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
REGOUT Capacitor
LABEL
C1
SPECIFICATION
X7R, 0.47 µF ±10%
QUANTITY
1
1
1
1
C2
X7R, 0.1 µF ±10%
X7R, 2.2 µF ±10%
X7R, 10 nF ±10%
VDD Bypass Capacitors
VDDIO Bypass Capacitor
C4
C3
Table 9. Bill of Materials
Document Number: DS-000216
Revision: 1.0
Page 16 of 44
IAM-20381
BLOCK DIAGRAM
IAM-20381
INT
Interrupt
Status
Register
CS
Slave I2C and
SPI Serial
Interface
SA0 / SDO
SCL / SPC
SDA / SDI
Self
test
X Accel
ADC
FIFO
User & Config
Registers
Self
test
Y Accel
Z Accel
ADC
ADC
ADC
FSYNC
Sensor
Registers
Self
test
Temp Sensor
Bias & LDOs
VDD
GND
REGOUT
Figure 5. IAM-20381 Block Diagram
OVERVIEW
The IAM-20381 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
Document Number: DS-000216
Revision: 1.0
Page 17 of 44
IAM-20381
THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20381’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The IAM-20381’s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full-scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The IAM-20381 communicates to a system processor using either a SPI or an I2C serial interface. The IAM-20381 always acts as a
slave when communicating to the system processor. The LSB of the I2C slave address is set by pin 4 (SA0).
IAM-20381 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the IAM-20381.
Interrupt
Status
Register
I2C Processor Bus: for reading all
sensor data from MPU
INT
IAM-20381
SA0
SCL
VDDIO or GND
Slave I2C
or SPI
SCL
SDA
System
Processor
Serial
Interface
SDA
FIFO
User & Config
Registers
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 6. IAM-20381 Solution Using I2C Interface
Document Number: DS-000216
Revision: 1.0
Page 18 of 44
IAM-20381
IAM-20381 Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the IAM-20381. Pins 2, 3, 4, and 5 are used to support the SPC, SDI, SDO, and CS
signals for SPI communications.
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU
Interrupt
Status
Register
INT
nCS
CS
IAM-20381
SDO
SDI
Slave I2C
or SPI
Serial
Interface
System
Processor
SPC
SDI
SPC
SDO
FIFO
Config
Register
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 7. IAM-20381 Solution Using SPI Interface
SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the accelerometer self-test register (register 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-
test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
CLOCKING
The IAM-20381 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. An on-chip
PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be used.
SENSOR DATA REGISTERS
The sensor data registers contain the latest accelerometer, and temperature measurement data. They are read-only registers, and
are accessed via the serial interface. Data from these registers may be read anytime.
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Revision: 1.0
Page 19 of 44
IAM-20381
FIFO
The IAM-20381 contains a 512-byte FIFO register that is accessible via the Serial Interface. The FIFO configuration register
determines which data are written into the FIFO. Possible choices include accelerometer data, temperature readings, and FSYNC
input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads.
The interrupt function may be used to determine when new data are available.
The IAM-20381 allows FIFO read in low-power accelerometer mode.
INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data are available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO overflow. The interrupt status can be read from the
Interrupt Status register.
DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the IAM-20381 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the IAM-20381. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
STANDARD POWER MODES
Table 10 lists the user-accessible power modes for IAM-20381.
MODE
NAME
ACCEL
Off
Duty-Cycled
On
1
3
4
Sleep Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Table 10. Standard Power Modes for IAM-20381
Notes:
1. Power consumption for individual modes can be found in section 3.2.1.
Document Number: DS-000216
Revision: 1.0
Page 20 of 44
IAM-20381
5 PROGRAMMABLE INTERRUPTS
The IAM-20381 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status flags indicate the
source of an interrupt. Interrupt sources may be enabled and disabled individually.
INTERRUPT NAME
Motion Detection
MODULE
Motion
FIFO Overflow
Data Ready
FIFO
Sensor Registers
Table 11. Table of Interrupt Sources
WAKE-ON-MOTION INTERRUPT
The IAM-20381 provides motion detection capability. A qualifying motion sample is one where the high passed sample from any axis
has an absolute value exceeding a user-programmable threshold. The following steps explain how to configure the Wake-on-Motion
Interrupt.
Step 1: Ensure that Accelerometer is running
•
•
In PWR_MGMT_1 register (0x6B) set CYCLE = 0, SLEEP = 0
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0
Step 2: Accelerometer Configuration
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 0 and A_DLPF_CFG[2:0] = 1 (b001)
Step 3: Enable Motion Interrupt
•
•
In INT_ENABLE register (0x38) set WOM_INT_EN = 111 to enable motion interrupt
Step 4: Set Motion Threshold
•
Set the motion threshold in ACCEL_WOM_THR register (0x1F)
Step 5: Enable Accelerometer Hardware Intelligence
•
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = ACCEL_INTEL_MODE = 1; Ensure that bit 0 is set to 0.
Step 6: Set Frequency of Wake-Up
•
In SMPLRT_DIV register (0x19) set SMPLRT_DIV[7:0] = 3.9Hz – 500Hz
Step 7: Enable Cycle Mode (Accelerometer Low-Power Mode)
•
In PWR_MGMT_1 register (0x6B) set CYCLE = 1
Document Number: DS-000216
Revision: 1.0
Page 21 of 44
IAM-20381
6 DIGITAL INTERFACE
I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the IAM-20381 can be accessed using either I2C at 400 kHz or SPI at 8 MHz. SPI operates in
four-wire mode.
PIN NUMBER
PIN NAME
VDDIO
PIN DESCRIPTION
Digital I/O supply voltage.
I2C Slave Address LSB (SA0); SPI serial data output (SDO)
1
4
SA0 / SDO
2
3
SCL / SPC
SDA / SDI
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
Table 12. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit. Setting this bit should be
performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in section 3.2.2.
For further information regarding the I2C_IF_DIS bit, please refer to sections 8 and 9 of this document.
I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The IAM-20381 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the IAM-20381 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level
on pin SA0. This allows two IAM-20381s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high).
IC COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see Figure 8).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
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Revision: 1.0
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IAM-20381
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to Figure 9).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 10. Complete I2C Data Transfer
To write the internal IAM-20381 registers, the master transmits the start condition (S), followed by the I2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the IAM-20381 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the IAM-20381 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the IAM-
20381 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
DATA
P
ACK
ACK
ACK
Document Number: DS-000216
Revision: 1.0
Page 23 of 44
IAM-20381
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
To read the internal IAM-20381 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the IAM-20381, the master transmits a start signal
followed by the slave address and read bit. As a result, the IAM-20381 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
AD+R
AD+R
NACK
P
ACK
ACK
ACK
ACK
ACK
DATA
Burst Read Sequence
Master
Slave
S
AD+W
S
ACK
NACK
P
ACK
DATA
DATA
I2C TERMS
SIGNAL
S
DESCRIPTION
Start Condition: SDA goes from high to low while SCL is high
AD
Slave I2C address
W
Write bit (0)
R
Read bit (1)
ACK
NACK
RA
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
IAM-20381 internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 13. I2C Terms
Document Number: DS-000216
Revision: 1.0
Page 24 of 44
IAM-20381
SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The IAM-20381 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data are delivered MSB first and LSB last
2. Data are latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 8 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data are two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
SPC
SDI
SPI Master
SPI Slave 1
SDO
CS
CS1
CS2
SPC
SDI
SDO
CS
SPI Slave 2
Figure 11. Typical SPI Master/Slave Configuration
Document Number: DS-000216
Revision: 1.0
Page 25 of 44
IAM-20381
7 SERIAL INTERFACE CONSIDERATIONS
IAM-20381 SUPPORTED INTERFACES
The IAM-20381 supports I2C communications on its serial interface.
The IAM-20381’s I/O logic levels are set to be VDDIO.
Figure 12 depicts a sample circuit of IAM-20381. It shows the relevant logic levels and voltage connections.
VDDIO
VDD_IO
(0V - VDDIO)
SYSTEM BUS
System
Processor IO
VDD
VDDIO
VDD
(0V - VDDIO)
INT
SDA
SCL
(0V - VDDIO)
(0V - VDDIO)
(0V - VDDIO)
SYNC
VDDIO
IAM-20381
VDDIO
(0V, VDDIO)
SA0
Figure 12. I/O Levels and Connections
Document Number: DS-000216
Revision: 1.0
Page 26 of 44
IAM-20381
8 REGISTER MAP
The following table lists the register map for the IAM-20381.
Accessible
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
(writable)
in Sleep
Mode
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0D
0E
0F
19
13
14
15
25
SELF_TEST_X_ACCEL
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
SMPLRT_DIV
R/W
R/W
R/W
R/W
N
N
N
N
N
XA_ST_DATA[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
SMPLRT_DIV[7:0]
FIFO_
MODE
1A
1C
1D
1F
23
36
26
28
29
31
35
54
CONFIG
ACCEL_CONFIG
ACCEL_CONFIG 2
ACCEL_WOM_THR
FIFO_EN
R/W
R/W
R/W
R/W
R/W
R/C
-
EXT_SYNC_SET[2:0]
ACCEL_FS_SEL[1:0]
ACCEL_FCHOI
DLPF_CFG[2:0]
N
N
N
N
N
XA_ST
YA_ST
ZA_ST
-
-
DEC2_CFG
A_DLPF_CFG
CE_B
WOM_THR[7:0]
TEMP
_FIFO_EN
ACCEL_FIFO_
EN
-
-
-
-
-
-
-
-
-
-
-
-
FSYNC_INT
FSYNC_INT
-
FSYNC
_INT_MODE_
EN
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_INT_L
EVEL
37
38
3A
55
56
58
INT_PIN_CFG
INT_ENABLE
INT_STATUS
R/W
R/W
R/C
Y
Y
INT_LEVEL
INT_OPEN
-
-
-
-
FIFO
_OFLOW
_EN
DATA_RDY_I
NT_EN
WOM_INT_EN[7:5]
WOM_INT[7:5]
-
-
-
-
FIFO
_OFLOW
_INT
DATA
_RDY_INT
N
3B
3C
3D
3E
3F
40
41
42
59
60
61
62
63
64
65
66
ACCEL_XOUT_H
ACCEL_XOUT_L
ACCEL_YOUT_H
ACCEL_YOUT_L
ACCEL_ZOUT_H
ACCEL_ZOUT_L
TEMP_OUT_H
TEMP_OUT_L
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
ACCEL_XOUT_H[15:8]
ACCEL_XOUT_L[7:0]
ACCEL_YOUT_H[15:8]
ACCEL_YOUT_L[7:0]
ACCEL_ZOUT_H[15:8]
ACCEL_ZOUT_L[7:0]
TEMP_OUT[15:8]
TEMP_OUT[7:0]
ACCEL
_RST
TEMP
_RST
68
69
6A
6B
104
105
106
107
SIGNAL_PATH_RESET
ACCEL_INTEL_CTRL
USER_CTRL
R/W
R/W
R/W
R/W
N
N
N
Y
-
-
-
-
-
-
-
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
-
I2C_IF
_DIS
FIFO
_RST
SIG_COND
_RST
-
FIFO_EN
SLEEP
-
-
DEVICE_RES
ET
PWR_MGMT_1
ACCEL_CYCLE
STBY_XA
-
TEMP_DIS
STBY_ZA
CLKSEL[2:0]
-
6C
72
73
74
75
77
78
7A
7B
7D
7E
108
114
115
116
117
119
120
122
123
125
126
PWR_MGMT_2
FIFO_COUNTH
FIFO_COUNTL
FIFO_R_W
R/W
R
Y
FIFO_LP_EN
-
-
STBY_YA
-
-
N
N
N
N
N
N
N
N
N
N
FIFO_COUNT[12:8]
R
FIFO_COUNT[7:0]
R/W
R
FIFO_DATA[7:0]
WHOAMI[7:0]
XA_OFFS [14:7]
WHO_AM_I
XA_OFFSET_H
XA_OFFSET_L
YA_OFFSET_H
YA_OFFSET_L
ZA_OFFSET_H
ZA_OFFSET_L
R/W
R/W
R/W
R/W
R/W
R/W
XA_OFFS [6:0]
YA_OFFS [14:7]
YA_OFFS [6:0]
ZA_OFFS [14:7]
ZA_OFFS [6:0]
-
-
-
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
Document Number: DS-000216
Revision: 1.0
Page 27 of 44
IAM-20381
In the detailed register tables that follow, register names are in capital letters, while register values are in capital letters and
italicized. For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most significant bits, ACCEL_XOUT[15:8], of the 16-
bit X-Axis accelerometer measurement, ACCEL_XOUT.
The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
•
•
Register 107 (0x40) Power Management 1
Register 117 (0xB6) WHO_AM_I
Document Number: DS-000216
Revision: 1.0
Page 28 of 44
IAM-20381
9 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the IAM-20381.
Note: The device will come up in sleep mode upon power-up.
REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)
REGISTER
BITS
NAME
FUNCTION
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
SELF_TEST_X_ACCEL
[7:0]
XA_ST_DATA[7:0]
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
[7:0]
[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _OTP = (2620/ 2FS )*1.01(ST _code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
log(ST _ FAC /(2620/ 2FS ))
ST _ code = round(
) +1
log(1.01)
REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
NAME
FUNCTION
[7:0] SMPLRT_DIV[7:0]
Divides the internal sample rate (see register CONFIG) to generate the sample rate that
controls sensor data output rate, FIFO sample rate.
Note: This register is only effective when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1 kHz
REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
[6]
NAME
FUNCTION
-
Always set to 0
FIFO_MODE
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO, replacing
the oldest data.
Document Number: DS-000216
Revision: 1.0
Page 29 of 44
IAM-20381
BIT
[5:3]
NAME
EXT_SYNC_SET[2:0]
FUNCTION
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
FSYNC bit location
function disabled
TEMP_OUT_L[0]
Reserved
Reserved
Reserved
ACCEL_XOUT_L[0]
ACCEL_YOUT_L[0]
ACCEL_ZOUT_L[0]
0
1
2
3
4
5
6
7
FSYNC will be latched to capture short strobes. This will be done such that if FSYNC toggles,
the latched value toggles, but won’t toggle again until the new latched value is captured by
the sample rate strobe.
[2:0]
DLPF_CFG[2:0]
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See Table 14.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The temperature sensor data is filtered according to the value
of DLPF_CFG and FCHOICE_B as shown in the table below.
Temperature
FCHOICE_B
Sensor
DLPF_CFG
<1>
<0>
3-dB BW (Hz)
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
7
4000
4000
4000
188
98
42
20
10
5
4000
Table 14. Configuration
REGISTER 28 – ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT
[7]
[6]
[5]
NAME
FUNCTION
XA_ST
YA_ST
ZA_ST
X Accel self-test
Y Accel self-test
Z Accel self-test
Accel Full Scale Select:
±2g (00), ±4g (01), ±8g (10), ±16g (11)
Reserved
[4:3]
[2:0]
ACCEL_FS_SEL[1:0]
-
Document Number: DS-000216
Revision: 1.0
Page 30 of 44
IAM-20381
REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
NAME
FUNCTION
[7:6]
-
Reserved
Averaging filter settings for Low Power Accelerometer mode:
0 = Average 4 samples
1 = Average 8 samples
[5:4]
DEC2_CFG[1:0]
2 = Average 16 samples
3 = Average 32 samples
[3]
[2:0]
ACCEL_FCHOICE_B
A_DLPF_CFG
Used to bypass DLPF as shown in the table below.
Accelerometer low pass filter setting as shown in the table below.
Accelerometer
ACCEL_FCHOICE_B
A_DLPF_CFG
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
1
0
0
0
0
0
0
0
0
X
0
1
2
3
4
5
6
7
1046.0
218.1
218.1
99.0
1100.0
235.0
235.0
121.3
61.5
4
1
1
1
1
1
1
1
1
44.8
21.2
10.2
31.0
15.5
5.1
420.0
7.8
441.6
Table 15. Accelerometer Data Rates and Bandwidths (Low Noise Mode)
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit
integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K.
The following table lists the accelerometer filter bandwidths, noise, and current consumption available in the low-power mode of
operation. In the low-power mode of operation, the accelerometer is duty-cycled.
ACCEL_FCHOICE_B
A_DLPF_CFG
1
x
0
7
0
7
0
7
0
7
DEC2_CFG
x
0
1
2
3
Averages
1x
4x
8x
16x
4.84
121.3
2.8
32x
8.84
61.5
2.0
Ton (ms)
Noise BW (Hz)
1.084
1100.0
8.3
1.84
441.6
5.3
2.84
235.4
3.8
Noise (mg) TYP based on 250 µg/√Hz
SMPLRT_DIV
ODR (Hz)
3.9
Current Consumption (µA) TYP
255
127
63
31
15
7
8.4
9.8
9.4
11.9
17.0
27.1
47.2
87.5
168.1
329.3
10.8
14.7
22.5
13.6
20.3
33.7
19.2
31.4
55.9
7.8
15.6
12.8
18.7
30.4
57.4
100.9
194.9
31.3
62.5
125.0
250.0
500.0
38.2
69.4
132.0
257.0
60.4
113.9
220.9
104.9
202.8
N/A
3
1
N/A
N/A
Table 16. Accelerometer Filter Bandwidths, Noise, and Current Consumption (Low-Power Mode)
Document Number: DS-000216
Revision: 1.0
Page 31 of 44
IAM-20381
REGISTER 31 – WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_THR
Register Type: READ/WRITE
Register Address: 31 (Decimal); 1F (Hex)
BIT
[7:0]
NAME
WOM_THR[7:0]
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for accelerometer.
REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
NAME
FUNCTION
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate
0 – Function is disabled.
Reserved
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H,
and ACCEL_ZOUT_L to the FIFO at the sample rate;
0 – Function is disabled.
[7]
TEMP_FIFO_EN
-
[6:4]
[3]
ACCEL_FIFO_EN
-
[2:0]
Reserved.
REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
NAME
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been generated. The bit
clears to 0 after the register has been read.
[7]
FSYNC_INT
REGISTER 55 – INT/DRDY PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
NAME
FUNCTION
1 – The logic level for INT/DRDY pin is active low.
0 – The logic level for INT/DRDY pin is active high.
1 – INT/DRDY pin is configured as open drain.
[7]
INT_LEVEL
INT_OPEN
[6]
[5]
[4]
[3]
0 – INT/DRDY pin is configured as push-pull.
1 – INT/DRDY pin level held until interrupt status is cleared.
0 – INT/DRDY pin indicates interrupt pulse’s width is 50 µs.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions to
the level specified by FSYNC_INT_LEVEL. When this bit is equal to 0, the FSYNC pin is
disabled from causing an interrupt.
LATCH_INT_EN
INT_RD_CLEAR
FSYNC_INT_LEVEL
[2]
FSYNC_INT_MODE_EN
[1]
[0]
-
-
Reserved.
Always set to 0.
Document Number: DS-000216
Revision: 1.0
Page 32 of 44
IAM-20381
REGISTER 56 – INTERRUPT ENABLE
Register Name: INT_ENABLE
Register Type: READ/WRITE
Register Address: 56 (Decimal); 38 (Hex)
BIT
NAME
FUNCTION
111 – Enable WoM interrupt on accelerometer.
000 – Disable WoM interrupt on accelerometer.
[7:5]
WOM_INT_EN[7:5]
1 – Enables a FIFO buffer overflow to generate an interrupt.
0 – Function is disabled.
[4]
FIFO_OFLOW_EN
[3:1]
[0]
-
Reserved.
Data ready interrupt enable.
DATA_RDY_INT_EN
REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT
NAME
FUNCTION
Accelerometer WoM interrupt status. Cleared on Read.
111 – WoM interrupt on accelerometer
[7:5]
WOM_INT
This bit automatically sets to 1 when a FIFO buffer overflow has been generated. The bit
clears to 0 after the register has been read.
[4]
FIFO_OFLOW_INT
[3:1]
[0]
-
Reserved.
This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears
to 0 after the register has been read.
DATA_RDY_INT
REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS
Register Name: ACCEL_XOUT_H
Register Type: READ only
Register Address: 59 (Decimal); 3B (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_H[15:8]
High byte of accelerometer x-axis data.
Register Name: ACCEL_XOUT_L
Register Type: READ only
Register Address: 60 (Decimal); 3C (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_L[7:0]
Low byte of accelerometer x-axis data.
Register Name: ACCEL_YOUT_H
Register Type: READ only
Register Address: 61 (Decimal); 3D (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_H[15:8]
High byte of accelerometer y-axis data.
Register Name: ACCEL_YOUT_L
Register Type: READ only
Register Address: 62 (Decimal); 3E (Hex)
BIT
[7:0]
NAME
ACCEL_YOUT_L[7:0]
FUNCTION
Low byte of accelerometer y-axis data.
Register Name: ACCEL_ZOUT_H
Register Type: READ only
Register Address: 63 (Decimal); 3F (Hex)
Document Number: DS-000216
Revision: 1.0
Page 33 of 44
IAM-20381
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT_H[15:8]
High byte of accelerometer z-axis data.
Register Name: ACCEL_ZOUT_L
Register Type: READ only
Register Address: 64 (Decimal); 40 (Hex)
BIT
[7:0]
NAME
ACCEL_ZOUT_L[7:0]
FUNCTION
Low byte of accelerometer z-axis data.
REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT
Register Name: TEMP_OUT_H
Register Type: READ only
Register Address: 65 (Decimal); 41 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT[15:8]
High byte of the temperature sensor output
Register Name: TEMP_OUT_L
Register Type: READ only
Register Address: 66 (Decimal); 42 (Hex)
BIT
NAME
FUNCTION
Low byte of the temperature sensor output
TEMP_degC
= ((TEMP_OUT –
RoomTemp_Offset)/Temp_Sensitivity) + 25degC
[7:0]
TEMP_OUT[7:0]
REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT
NAME
FUNCTION
[7:2]
Reserved
-
Reset accel digital signal path.
[1]
[0]
ACCEL_RST
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers.
Reset temp digital signal path.
TEMP_RST
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers.
REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
[7]
NAME
ACCEL_INTEL_EN
FUNCTION
This bit enables the Wake-on-Motion detection logic.
0 – Do not use.
[6]
ACCEL_INTEL_MODE
1 – Compare the current sample with the previous sample.
[5:0]
Reserved.
-
Document Number: DS-000216
Revision: 1.0
Page 34 of 44
IAM-20381
REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
[7]
NAME
FUNCTION
Reserved.
1 – Enable FIFO operation mode.
-
[6]
FIFO_EN
0 – Disable FIFO access from serial interface. To disable FIFO writes by DMA, use FIFO_EN
register.
[5]
[4]
[3]
-
Reserved.
I2C_IF_DIS
1 – Disable I2C Slave module and put the serial interface in SPI mode only.
Reserved.
-
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock cycle of the
internal 20 MHz clock.
Reserved.
1 – Reset all accel digital signal path, and temp digital signal path. This bit also clears all the
sensor registers.
[2]
[1]
[0]
FIFO_RST
-
SIG_COND_RST
REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit automatically clears
to 0 once the reset is done.
[7]
DEVICE_RESET
When set to 1, the chip is set to sleep mode.
[6]
[5]
SLEEP
Note: The default value is 1, the chip comes up in Sleep mode.
When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep
and taking a single accelerometer sample at a rate determined by SMPLRT_DIV
Note: When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled, the
chip will wake up at the rate determined by the respective registers above, but will not take any
samples.
ACCEL_CYCLE
[4]
[3]
-
Reserved.
TEMP_DIS
When set to 1, this bit disables the temperature sensor.
Code Clock Source
0
1
2
3
4
5
6
Internal 20 MHz oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Internal 20 MHz oscillator.
[2:0]
CLKSEL[2:0]
7
Stops the clock and keeps timing generator in reset.
Note: The default value of CLKSEL[2:0] is 000.
REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT
[7]
[6]
NAME
FIFO_LP_EN
FUNCTION
1 – Enable FIFO in low-power accelerometer mode. Default setting is 0.
Reserved.
1 – X accelerometer is disabled.
0 – X accelerometer is on.
-
[5]
STBY_XA
1 – Y accelerometer is disabled.
0 – Y accelerometer is on.
[4]
STBY_YA
Document Number: DS-000216
Revision: 1.0
Page 35 of 44
IAM-20381
BIT
[3]
[2:0]
NAME
FUNCTION
1 – Z accelerometer is disabled.
0 – Z accelerometer is on.
Reserved.
STBY_ZA
-
REGISTERS 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ Only
Register Address: 114 (Decimal); 72 (Hex)
BIT
NAME
FUNCTION
[7:5]
Reserved.
High Bits; count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
-
[4:0]
FIFO_COUNT[12:8]
Register Name: FIFO_COUNTL
Register Type: READ Only
Register Address: 115 (Decimal); 73 (Hex)
BIT
NAME
FUNCTION
Low Bits; count indicates the number of written bytes in the FIFO.
Note: Must read FIFO_COUNTH to latch new data for both FIFO_COUNTH and FIFO_COUNTL.
[7:0]
FIFO_COUNT[7:0]
REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT
NAME
FUNCTION
[7:0]
FIFO_DATA[7:0]
Read/Write command provides Read or Write operation for the FIFO.
Description:
This register is used to read and write data from the FIFO buffer.
Data are written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are enabled,
the contents of registers 59 through 72 will be written in order at the Sample Rate.
The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when their corresponding FIFO enable
flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in INT_STATUS
(Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO unless
register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data are available. Normal data
are precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty.
REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ only
Register Address: 117 (Decimal); 75 (Hex)
BIT
NAME
FUNCTION
[7:0]
WHOAMI
Register to indicate to user which device is being accessed.
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the
register is 0xB6. This is different from the I2C address of the device as seen on the slave I2C controller by the applications processor.
The I2C address of the IAM-20381 is 0x68 or 0x69 depending upon the value driven on AD0 pin.
Document Number: DS-000216
Revision: 1.0
Page 36 of 44
IAM-20381
REGISTERS 119, 120, 122, 123, 125, 126 ACCELEROMETER OFFSET REGISTERS
Register Name: XA_OFFSET_H
Register Type: READ/WRITE
Register Address: 119 (Decimal); 77 (Hex)
BIT
NAME
FUNCTION
Upper bits of the X accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[7:0]
XA_OFFS[14:7]
Register Name: XA_OFFSET_L
Register Type: READ/WRITE
Register Address: 120 (Decimal); 78 (Hex)
BIT
NAME
FUNCTION
Lower bits of the X accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[7:1]
XA_OFFS[6:0]
[0]
Reserved.
-
Register Name: YA_OFFSET_H
Register Type: READ/WRITE
Register Address: 122 (Decimal); 7A (Hex)
BIT
NAME
FUNCTION
Upper bits of the Y accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[7:0]
YA_OFFS[14:7]
Register Name: YA_OFFSET_L
Register Type: READ/WRITE
Register Address: 123 (Decimal); 7B (Hex)
BIT
NAME
FUNCTION
Lower bits of the Y accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[7:1]
YA_OFFS[6:0]
[0]
Reserved.
-
Register Name: ZA_OFFSET_H
Register Type: READ/WRITE
Register Address: 125 (Decimal); 7D (Hex)
BIT
NAME
FUNCTION
Upper bits of the Z accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[7:0]
ZA_OFFS[14:7]
Register Name: ZA_OFFSET_L
Register Type: READ/WRITE
Register Address: 126 (Decimal); 7E (Hex)
BIT
[7:1]
[0]
NAME
FUNCTION
Lower bits of the Z accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
ZA_OFFS[6:0]
Reserved.
-
Document Number: DS-000216
Revision: 1.0
Page 37 of 44
IAM-20381
10 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) devices packaged in
LGA package.
ORIENTATION OF AXES
Figure 13 below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure.
+Z
+Y
+Z
IAM
-
+Y
20381
+X
+X
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation
Document Number: DS-000216
Revision: 1.0
Page 38 of 44
IAM-20381
PACKAGE DIMENSIONS
16 Lead LGA (3x3x0.75) mm NiAu pad finish
Figure 14. Package Dimensions
Document Number: DS-000216
Revision: 1.0
Page 39 of 44
IAM-20381
DIMENSIONS IN MILLIMETERS
SYMBOLS
MIN
NOM
MAX
Total Thickness
Substrate Thickness
Mold Thickness
A
A1
A2
0.7
0.75
0.8
0.105
0.63
REF
REF
D
E
2.9
2.9
0.2
0.3
3
3
3.1
3.1
0.3
0.4
Body Size
Lead Width
Lead Length
W
0.25
0.35
L
e
n
Lead Pitch
Lead Count
0.5
BSC
16
D1
E1
SD
SE
b
2
1
BSC
BSC
BSC
BSC
Edge Ball Center to Center
Body Center to Contact Ball
---
---
Ball Width
Ball Diameter
Ball Opening
Ball Pitch
Ball Count
---
---
---
---
---
---
---
---
---
e1
n1
Pre-Solder
---
Package Edge Tolerance
Mold Flatness
aaa
bbb
ddd
eee
fff
0.1
0.2
0.08
---
---
0.06
Coplanarity
Ball Offset (Package)
Ball Offset (Ball)
Lead Edge to Package Edge
M
0.01
0.11
Table 17. Package Dimensions
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11 PART NUMBER PACKAGE MARKING
The part number package marking for IAM-20381 devices is summarized below:
PART NUMBER
IAM-20381
PART NUMBER PACKAGE MARKING
IA238
Table 18. Part Number Package Marking
TOP VIEW
IA238
XXXXXX
YYWW
Part Number
Lot Traceability Code
YY = Year Code
WW = Work Week
Figure 15. Part Number Package Marking
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12 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
• Manufacturing Recommendations
o
o
o
o
o
o
o
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
Reflow Specification
Storage Specifications
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
Packaging
Representative Shipping Carton Label
•
Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
Document Number: DS-000216
Revision: 1.0
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13 REVISION HISTORY
REVISION DATE
REVISION
DESCRIPTION
03/29/2017
1.0
Initial release
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IAM-20381
This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use,
or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves
the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes
no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any
claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to,
claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any
patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the
property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or
mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2017 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense
logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective
companies with which they are associated.
©2017 InvenSense. All rights reserved.
Document Number: DS-000216
Revision: 1.0
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