ITG-1010 [TDK]
陀螺仪;
| 型号： | ITG-1010 |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | 陀螺仪 |
| 文件： | 总46页 (文件大小：646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
InvenSense Inc.
Document Number: PS-ITG-1010A-00
Revision: 1.1
Release Date: 03/02/2015
1745 Technology Drive, San Jose, CA 95110 U.S.A.
Tel: +1 (408) 988-7339 Fax: +1 (408) 988-8104
Website: www.invensense.com
ITG-1010
Product Specification
Revision 1.1
Confidential & Proprietary
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Document Number: PS-ITG-1010A-00
Revision: 1.1
Release Date: 03/02/2015
ITG-1010 Product Specification
CONTENTS
1
DOCUMENT INFORMATION .....................................................................................................................4
1.1
REVISION HISTORY.................................................................................................................................4
PURPOSE AND SCOPE ............................................................................................................................5
PRODUCT OVERVIEW..............................................................................................................................5
APPLICATIONS........................................................................................................................................5
1.2
1.3
1.4
2
FEATURES .................................................................................................................................................6
2.1
SENSORS...............................................................................................................................................6
DIGITAL OUTPUT ....................................................................................................................................6
DATA PROCESSING ................................................................................................................................6
CLOCKING..............................................................................................................................................6
POWER..................................................................................................................................................6
PACKAGE...............................................................................................................................................6
2.2
2.3
2.4
2.5
2.6
3
ELECTRICAL CHARACTERISTICS ..........................................................................................................7
3.1
SENSOR SPECIFICATIONS .......................................................................................................................7
ELECTRICAL SPECIFICATIONS..................................................................................................................8
ELECTRICAL SPECIFICATIONS, CONTINUED ..............................................................................................9
I2C TIMING CHARACTERIZATION ............................................................................................................10
SPI TIMING CHARACTERIZATION ...........................................................................................................11
ABSOLUTE MAXIMUM RATINGS..............................................................................................................12
3.2
3.3
3.4
3.5
3.6
4
5
APPLICATIONS INFORMATION .............................................................................................................13
4.1
4.2
4.3
PIN OUT AND SIGNAL DESCRIPTION.......................................................................................................13
TYPICAL OPERATING CIRCUIT ...............................................................................................................14
BILL OF MATERIALS FOR EXTERNAL COMPONENTS.................................................................................14
FUNCTIONAL OVERVIEW.......................................................................................................................15
5.1
BLOCK DIAGRAM ..................................................................................................................................15
OVERVIEW ...........................................................................................................................................15
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING ..................................15
I2C AND SPI SERIAL COMMUNICATIONS INTERFACE ...............................................................................15
INTERNAL CLOCK GENERATION.............................................................................................................16
SENSOR DATA REGISTERS ...................................................................................................................16
FIFO...................................................................................................................................................16
INTERRUPTS.........................................................................................................................................16
DIGITAL-OUTPUT TEMPERATURE SENSOR .............................................................................................16
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10 BIAS AND LDO.....................................................................................................................................16
6
7
DIGITAL INTERFACE...............................................................................................................................17
6.1
SERIAL INTERFACE CONSIDERATIONS..............................................................................................22
I2C SERIAL INTERFACE .........................................................................................................................17
7.1
7.2
SUPPORTED INTERFACES .....................................................................................................................22
LOGIC LEVELS......................................................................................................................................22
8
ASSEMBLY...............................................................................................................................................23
8.1
8.2
8.3
ORIENTATION OF AXES .........................................................................................................................23
PACKAGE DIMENSIONS .........................................................................................................................24
PACKAGE MARKING SPECIFICATION ......................................................................................................25
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Document Number: PS-ITG-1010A-00
Revision: 1.1
Release Date: 03/02/2015
ITG-1010 Product Specification
8.4
8.5
TAPE & REEL SPECIFICATION................................................................................................................25
PCB DESIGN GUIDELINES.....................................................................................................................27
9
REGISTER MAP .......................................................................................................................................28
REGISTER DESCRIPTIONS ................................................................................................................30
10
10.1 REGISTERS 04-05, 07-08, 10-11- GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC)....................30
10.2 REGISTERS 19 TO 24 – GYROSCOPE OFFSET ADJUSTMENT ....................................................................30
10.3 REGISTER 25 – SAMPLE RATE DIVIDER .................................................................................................31
10.4 REGISTER 26 – CONFIGURATION...........................................................................................................31
10.5 REGISTER 27 – GYROSCOPE CONFIGURATION.......................................................................................32
10.6 REGISTER 35 – FIFO ENABLE...............................................................................................................34
10.7 REGISTER 55 – INT PIN / BYPASS ENABLE CONFIGURATION...................................................................35
10.8 REGISTER 56 – INTERRUPT ENABLE......................................................................................................36
10.9 REGISTER 58 – INTERRUPT STATUS......................................................................................................37
10.10 REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT........................................................................38
10.11 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS...........................................................................39
10.12 REGISTER 106 – USER CONTROL .........................................................................................................40
10.13 REGISTER 107 – POWER MANAGEMENT 1.............................................................................................41
10.14 REGISTER 108 – POWER MANAGEMENT 2.............................................................................................42
10.15 REGISTER 114 AND 115 – FIFO COUNT REGISTERS..............................................................................43
10.16 REGISTER 116 – FIFO READ WRITE .....................................................................................................44
10.17 REGISTER 117 – WHO AM I ..................................................................................................................45
11
ENVIRONMENTAL COMPLIANCE ......................................................................................................46
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Document Number: PS-ITG-1010A-00
Revision: 1.1
Release Date: 03/02/2015
ITG-1010 Product Specification
1
Document Information
1.1
Revision History
Revision
Date
Revision Description
12/24/2013
03/02/2015
1.0
1.1
Initial Release
Changed the top mark specification from IT10 to T36D C
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Document Number: PS-ITG-1010A-00
Revision: 1.1
Release Date: 03/02/2015
ITG-1010 Product Specification
1.2
Purpose and Scope
This document is a preliminary product specification, providing a description, specifications, and design
related information for the three axis ITG-1010™ gyroscope. The device is housed in a small 3x3x0.9mm
QFN package.
1.3
Product Overview
The ITG-1010 is a single-chip, digital output, 3 Axis MEMS gyroscope IC which features a 512-byte FIFO.
The FIFO can lower the traffic on the serial bus interface, and reduce power consumption by allowing the
system processor to burst read sensor data and then go into a low-power mode.
The gyroscope includes a programmable full-scale range of ±250, ±500, ±1000, and ±2000 degrees/sec,
very low Rate noise at 0.01 dps/√Hz and extremely low power consumption at 3.2mA. Factory-calibrated
initial sensitivity reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, a precision clock
with 1% drift from -40°C to 85°C, an embedded temperature sensor, and programmable interrupts. The
device features I2C and SPI serial interfaces, a VDD operating range of 1.71 to 3.6V, and a separate digital
IO supply, VDDIO from 1.71V to 3.6V.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS
wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the gyro
package size down to a footprint and thickness of 3x3x0.9mm (16-pin QFN), to provide a very small yet high
performance low cost package. The device provides high robustness by supporting 10,000g shock
reliability.
1.4
Applications
•
•
•
•
•
Motion UI
Handset gaming
Location based services, points of interest, and dead reckoning
Health and sports monitoring
Power management
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Document Number: PS-ITG-1010A-00
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ITG-1010 Product Specification
2
Features
The ITG-1010 MEMS gyroscope includes a wide range of features:
2.1 Sensors
•
•
•
Monolithic X-, Y-, Z-Axis angular rate sensor (gyros) integrated circuit
Digital-output temperature sensor
External sync signal connected to the FSYNC pin supports image, video and GPS
synchronization
•
•
•
Factory calibrated scale factor
High cross-axis isolation via proprietary MEMS design
10,000g shock tolerant
2.2
2.3
Digital Output
Fast Mode (400kHz) I2C serial interface
•
•
•
•
•
1 MHz SPI serial interface for full read/write capability
20 MHz SPI to read gyro sensor & temp sensor data.
16-bit ADCs for digitizing sensor outputs
User-programmable full-scale-range of ±250, ±500, ±1000, and ±2000 °/sec
Data Processing
•
The total data set obtained by the device includes gyroscope data, temperature data, and the one
bit external sync signal connected to the FSYNC pin.
•
•
•
•
FIFO allows burst read, reduces serial bus traffic and saves power on the system processor.
FIFO can be accessed through both I2C and SPI interfaces.
Programmable interrupt
Programmable low-pass filters
2.4
2.5
Clocking
•
On-chip timing generator clock frequency ±1% drift over full temperature range
Power
•
•
VDD supply voltage range of 1.71V to 3.6V
Flexible VDDIO reference voltage allows for multiple I2C and SPI interface voltage levels
•
•
•
Power consumption with three axes active: 3.2mA
Sleep mode: 8μA
Each axis can be individually powered down
2.6
Package
•
•
•
3x3x0.9mm footprint and maximum thickness 16-pin QFN plastic package
MEMS structure hermetically sealed at wafer level
RoHS and Green compliant
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Document Number: PS-ITG-1010A-00
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Release Date: 03/02/2015
ITG-1010 Product Specification
3
Electrical Characteristics
3.1
Sensor Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA=25°C.
Parameter
Conditions
Min
Typical
Max
Unit
Notes
GYRO SENSITIVITY
Full-Scale Range
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
±250
±500
±1000
±2000
º/s
º/s
º/s
º/s
Sensitivity Scale Factor
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
131
65.5
32.8
16.4
16
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
bits
Gyro ADC Word Length
Sensitivity Scale Factor Tolerance
25°C
±4.5
±4
%
Sensitivity Scale Factor Variation Over
Temperature
-10°C to +75°
%
Nonlinearity
Best fit straight line; 25°C
±0.2
±2
%
%
Cross-Axis Sensitivity
GYRO ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
±15
±15
º/s
º/s
ZRO Variation Over Temperature
GYRO NOISE PERFORMANCE
Total RMS Noise
-10°C to +75°C
FS_SEL=0
DLPFCFG=2 (92 Hz)
At 10Hz
0.1
º/s-rms
Rate Noise Spectral Density
0.01
º/s/√Hz
GYRO MECHANICAL
Mechanical Frequency
25
27
29
kHz
GYRO START-UP TIME
DLPFCFG=0, to ±1º/s of Final
From Sleep Mode to ready
From Power On to ready
ZRO Settling
35
50
ms
ms
TEMPERATURE SENSOR
Range
Sensitivity
Untrimmed
21°C
-10 to +75
321.4
0
ºC
LSB/ºC
LSB
Room-Temperature Offset
Linearity
±0.2
°C
TEMPERATURE RANGE
Specification Temperature Range
-10
+75
ºC
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Document Number: PS-ITG-1010A-00
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ITG-1010 Product Specification
3.2
Electrical Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA = 25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
VDD POWER SUPPLY
Operating Voltage Range
1.71
1
3.6
V
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
Power-Supply Ramp Rate
100
ms
Normal Operating Current
Sleep Mode Current
Three Axes Active
3.2
8
mA
µA
VDDIO REFERENCE VOLTAGE
(must be regulated)
Voltage Range
1.71
0.1
3.6
V
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
Power-Supply Ramp Rate
Normal Operating Current
100
ms
10pF load, 5MHz data rate.
Does not include pull up
resistor current draw as
that is system dependent
300
12
µA
ms
START-UP TIME FOR REGISTER
READ/WRITE
AD0 = 0
AD0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, AD0,
SCLK, SDI, /CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
0.9*VDDIO
V
V
pF
0.3*VDDIO
< 5
DIGITAL OUTPUT (INT, SDO)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT1, INT Low-Level Output Voltage
RLOAD=1MΩ
RLOAD=1MΩ
OPEN=1, 0.3mA sink
current
V
V
V
0.1*VDDIO
0.1
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
LATCH_INT_EN=0
100
50
nA
µs
Note: Power-Supply Ramp Rates are defined as the time it takes for the voltage to rise from 10% to 90% of the
final value. VDD and VDDIO must be monotonic ramps.
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Document Number: PS-ITG-1010A-00
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Release Date: 03/02/2015
ITG-1010 Product Specification
3.3
Electrical Specifications, continued
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA = 25°C.
Parameters
Conditions
Min
Typical
Max
Units Notes
I2C I/O (SCL, SDA)
-0.5V to 0.3*VDDIO
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
V
V
0.7*VDDIO to VDDIO +
0.5V
Vhys, Hysteresis
0.1*VDDIO
0 to 0.4
V
V
VOL1, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3mA sink current
VOL = 0.4V
VOL = 0.6V
3
6
mA
mA
Output Leakage Current
100
20+0.1Cb to 250
< 10
nA
ns
pF
tof, Output Fall Time from VIHmax to VILmax
CI, Capacitance for Each I/O pin
INTERNAL CLOCK SOURCE
Cb bus capacitance in pf
Fchoice=0,1,2
SMPLRT_DIV=0
32
8
kHz
kHz
Fchoice=3;
DLPFCFG=0 or 7
SMPLRT_DIV=0
Sample Rate
Fchoice=3;
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
1
kHz
Clock Frequency Initial Tolerance
Frequency Variation over Temperature
PLL Settling Time
CLK_SEL=0, 6; 25°C
CLK_SEL=1,2,3,4,5; 25°C
CLK_SEL=0,6
-2
-1
+2
+1
%
%
-10 to +10
%
CLK_SEL=1,2,3,4,5
CLK_SEL=1,2,3,4,5
±1
4
%
ms
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ITG-1010 Product Specification
3.4
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA=25°C.
I2C Timing Characterization
Parameters
I2C TIMING
Conditions
I2C FAST-MODE
Min
Typical
Max
Units
Notes
fSCL, SCL Clock Frequency
0
400
kHz
µs
tHD.STA, (Repeated) START Condition
Hold Time
0.6
tLOW, SCL Low Period
tHIGH, SCL High Period
1.3
0.6
0.6
µs
µs
µs
tSU.STA, Repeated START Condition
Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
0
µs
ns
ns
100
Cb bus cap. from 10 to
400pF
Cb bus cap. from 10 to
400pF
20+0.1
Cb
20+0.1
Cb
300
300
tf, SDA and SCL Fall Time
ns
tSU.STO, STOP Condition Setup Time
0.6
µs
µs
tBUF, Bus Free Time Between STOP and
START Condition
1.3
Cb, Capacitive Load for each Bus Line
< 400
pF
µs
µs
tVD.DAT, Data Valid Time
0.9
0.9
tVD.ACK, Data Valid Acknowledge Time
I2C Bus Timing Diagram
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ITG-1010 Product Specification
3.5
SPI Timing Characterization
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA = 25°C,
Parameters
Conditions
Min
Typical
Max
Units
SPI TIMING
fSCLK, SCLK Clock Frequency
11
MHz
MHz
ns
202
tLOW, SCLK Low Period
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
tHD.CS, CS Hold Time
400
400
8
ns
ns
500
11
7
ns
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
ns
ns
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
Cload = 20pF
Cload = 20pF
100
10
ns
4
ns
ns
Notes:
1. R/W of all Registers
2. Read of Sensor Registers only
SPI Bus Timing Diagram
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Document Number: PS-ITG-1010A-00
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ITG-1010 Product Specification
3.6
Absolute Maximum Ratings
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, VDD
-0.5V to +4.0V
-0.5V to 4.0V
VDDIO Input Voltage Level
REGOUT
-0.5V to 2V
Input Voltage Level (AD0, FSYNC)
SCL, SDA, INT (SPI enable)
SCL, SDA, INT (SPI disable)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Protection
Latch-up
-0.5V to VDD
-0.5V to VDD
-0.5V to VDD
10,000g for 0.2ms
-40°C to +85°
-40°C to +125°C
2kV (HBM); 200V (MM)
JEDEC Class II (2),125°C, ±100mA
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ITG-1010 Product Specification
4
Applications Information
4.1
Pin Out and Signal Description
Pin Number
Pin Name
Pin Description
Digital I/O supply voltage
I2C serial clock (SCL); SPI serial clock (SCLK)
I2C serial data (SDA); SPI serial data input (SDI)
I2C Slave Address LSB (AD0); SPI serial data output (SDO)
SPI chip select (0=SPI mode, 1= I2C mode)
Reserved. Connect to Ground.
3x3x0.9mm
1
2
3
4
5
6
VDDIO
SCL/SCLK
SDA/SDI
AD0 / SDO
/CS
RESV
7
8
INT
Interrupt digital output (totem pole or open-drain)
FSYNC
Frame synchronization digital input. Connect to GND if not used.
13
14
15
GND
Power supply ground
REGOUT
RESV-G
Regulator filter capacitor connection
Reserved. Connect to Ground.
16
VDD
NC
Power supply voltage
9, 10, 11, 12
Not internally connected. May be used for PCB trace routing.
16 15 14
GND
VDDIO
SCL/SCLK
SDA/SDI
AD0/SDO
/CS
1
2
3
4
5
13
+Z
12 NC
11 NC
10 NC
ITG-1010
(16-pin QFN)
ITG
-
1010
9
NC
+Y
+X
6
7
8
QFN Package (Top View)
16-pin, 3mm x 3mm x 0.90mm
Footprint and maximum thickness
Orientation of Axes of Sensitivity and Polarity of Rotation
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ITG-1010 Product Specification
4.2
Typical Operating Circuit
GND
VDD
C2, 0.1 µ F
REGOUT
VDD
GND
16 15 14
C1, 0.1 µ F
GND
VDDIO
1
2
3
4
5
13
C3
10nF
12 NC
SCL/SCLK
GND
ITG-1010
(16-pin QFN)
11
10
9
NC
NC
NC
SDA/SDI
AD0/SDO
GND
/CS
6
7
8
INT FSYNC
GND
Typical Operating Circuit
4.3
Bill of Materials for External Components
Component
Label
C1
Specification
Quantity
Regulator Filter Capacitor
VDD Bypass Capacitor
VDDIO Bypass Capacitor
Ceramic, X7R, 0.1µF ±10%, 2V
Ceramic, X7R, 0.1µF ±10%, 4V
Ceramic, X7R, 10nF ±10%, 4V
1
1
1
C2
C3
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ITG-1010 Product Specification
5
Functional Overview
5.1
Block Diagram
VDD
CLOCK
Gen
Factory
Test Modes
OTP Factory
Calibration
POR
VDDIO
REGOUT
GND
CSN
IIC SLAVE
AD0 / SDO
Drive block
Sensing Block
SCL / SCLK
SDA / SDI
SPI SLAVE
Digital Low Pass Filter OIS
ADC
ADC
ADC
ADC
CV
CV
CV
Single
XYZ
GYRO
Drive
FIFO
INTC
SENSOR
Digital Low Pass Filter OIS
OUTPUT
REGS
DRDY
Digital Low Pass Filter OIS
Digital Low Pass Filter
INT
FSYNC
Temp
Sensor
Status
Registers
Automatic Gain
Control
Charge
Pump
Reference
Gen
Voltage
Regulator
Control
Registers
Self test
Trims and config ckts
5.2
Overview
The ITG-1010 is comprised of the following key blocks / functions:
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
I2C and SPI serial communications interfaces
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDO
5.3
Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning
The ITG-1010 consists of a single structure vibratory MEMS rate gyroscope, which detects rotation about the
X, Y, and Z axes. When the gyro is rotated about any of the sense axes, the Coriolis Effect causes a
vibration that is detected by a capacitive pick off. The resulting signal is amplified, demodulated, and filtered
to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip
16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The chip features a programmable full-
scale range of the gyro sensors of ±250, ±500, ±1000, and ±2000 dps. User-selectable low-pass filters
enable a wide range of cut-off frequencies. The ADC sample rate can be programmed to 32 kHz, 8 kHz, 1
kHz, 500 Hz, 333.3 Hz, 250 Hz, 200 Hz, 166.7 Hz, 142.9 Hz, or 125 Hz.
5.4
I2C and SPI Serial Communications Interface
The ITG-1010 has both I2C and SPI serial interfaces. The device always acts as a slave when
communicating to the system processor. The logic level for communications to the master is set by the
voltage on the VDDIO pin. The LSB of the of the I2C slave address is set by the AD0 pin. The I2C and SPI
protocols are described in more detail in Section 6.
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ITG-1010 Product Specification
5.5
Internal Clock Generation
The ITG-1010 has a flexible clocking scheme, allowing for a variety of internal clock sources for the internal
synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, various control
circuits, and registers.
Allowable internal sources for generating the internal clock are:
•
•
An internal relaxation oscillator
PLL (gyroscope based clock)
In order for the gyroscope to perform to spec, the PLL must be selected as the clock source. When the
internal 20MHz oscillator is chosen as the clock source, the device can operate while having the gyroscopes
disabled. However, this is only recommended if the user wishes to use the internal temperature sensor in this
mode.
5.6
Sensor Data Registers
The sensor data registers contain the latest gyro and temperature data. They are read-only registers, and
are accessed via the Serial Interface. Data from these registers may be read anytime, however, the interrupt
function may be used to determine when new data is available.
5.7
FIFO
The ITG-1010 contains a 512-byte FIFO register that is accessible via the both the I2C and SPI Serial
Interfaces. The FIFO configuration register determines what data goes into it, with possible choices being
gyro data, temperature readings and FSYNC input. A FIFO counter keeps track of how many bytes of valid
data are contained in the FIFO. The FIFO register supports burst reads. The interrupt function may be used
to determine when new data is available.
5.8
Interrupts
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include
the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources), (2) new data is available to be read (from the FIFO and Data registers), and (3) FIFO overflow.
The interrupt status can be read from the Interrupt Status register.
5.9
Digital-Output Temperature Sensor
An on-chip temperature sensor and ADC are used to measure the device’s die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
5.10
Bias and LDO
The bias and LDO section generates the internal supply and the reference voltages and currents required by
the ITG-1010. Its two inputs are unregulated VDD of 1.71V to 3.6V and a VDDIO logic reference supply
voltage of 1.71V to 3.6V. The LDO output is bypassed by a 0.1µF capacitor at REGOUT.
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6
Digital Interface
I2C Serial Interface
6.1
The internal registers and memory of the ITG-1010 can be accessed using the I2C interface.
Serial Interface
Pin Number
Pin Name
VDDIO
Pin Description
8
9
Digital I/O supply voltage.
AD0 / SDO
SCL / SCLK
SDA / SDI
I2C Slave Address LSB (AD0); SPI serial data output (SDO)
I2C serial clock (SCL); SPI serial clock (SCLK)
I2C serial data (SDA); SPI serial data input (SDI)
23
24
6.1.1 I2C Interface
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the
lines are open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can
be a master or a slave. The master device puts the slave address on the bus, and the slave device with the
matching address acknowledges the master.
The ITG-1010 always operates as a slave device when communicating to the system processor, which thus
acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is
400 kHz.
The slave address of the device is b110100X which is 7 bits long. The LSB bit of the 7 bit address is
determined by the logic level on pin AD0. This allows two ITG-1010 devices to be connected to the same I2C
bus. When used in this configuration, the address of the one of the devices should be b1101000 (pin AD0 is
logic low) and the address of the other should be b1101001 (pin AD0 is logic high). The I2C address is stored
in WHO_AM_I register.
I2C Communications Protocol
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is
defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is
considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to
HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
START and STOP Conditions
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Data Format / Acknowledge
I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per
data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the
acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal
by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and is unable to transmit or receive another byte of data until some other task has been
performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes
when the slave is ready, and releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address
followed by an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from
or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge
signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To
acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line.
Data transmission is always terminated by the master with a STOP condition (P), thus freeing the
communications line. However, the master can generate a repeated START condition (Sr), and address
another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while
SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Complete I2C Data Transfer
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To write the internal ITG-1010 registers, the master transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the device acknowledges the
transfer. Then the master puts the register address (RA) on the bus. After the device acknowledges the
reception of the register address, the master puts the register data onto the bus. This is followed by the ACK
signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last
ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the
device automatically increments the register address and loads the data to the appropriate register. The
following figures show single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
DATA
P
ACK
ACK
To read the internal device registers, the master sends a start condition, followed by the I2C address and a
write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the
device, the master transmits a start signal followed by the slave address and read bit. As a result, the device
sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a
stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9th clock
cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
S
AD+R
AD+R
NACK
ACK
P
ACK
ACK
ACK
ACK DATA
ACK DATA
Burst Read Sequence
Master
Slave
S
AD+W
NACK
P
ACK
DATA
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I2C Terms
Signal
S
Description
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
AD
W
Write bit (0)
R
Read bit (1)
ACK
NACK
RA
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
The internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
6.1.2 SPI interface
SPI is a 4-wire synchronous serial interface that uses two control and two data lines. The ITG-1010 always
operates as a Slave device during standard Master-Slave SPI operation. With respect to the Master, the
Serial Clock output (SCLK), the Data Output (SDO) and the Data Input (SDI) are shared among the Slave
devices. The Master generates an independent Chip Select (/CS) for each Slave device; /CS goes low at the
start of transmission and goes back high at the end. The Serial Data Output (SDO) line, remains in a high-
impedance (high-z) state when the device is not selected, so it does not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. SCLK frequency is 1MHz max for SPI in full read/write capability mode. When the SPI frequency
is set to 20MHz, its operation is limited to reading sensor registers only.
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The
first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first
bit of the first byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation.
The following 7 bits contain the Register Address. In cases of multiple-byte Read/Writes, data is
two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
D7
LSB
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
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SCLK
SDI
SPI Master
SPI Slave 1
SDO
/CS
/CS1
/CS2
SCLK
SDI
SDO
/CS
SPI Slave 2
Typical SPI Master / Slave Configuration
Each SPI slave requires its own Chip Select (/CS) line. SDO, SDI and SCLK lines are shared. Only one /CS
line is active (low) at a time ensuring that only one slave is selected at a time. The /CS lines of other slaves
are held high which causes their respective SDO pins to be high-Z.
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7
Serial Interface Considerations
7.1
Supported Interfaces
The ITG-1010 supports I2C and SPI communication.
7.2 Logic Levels
The I/O logic levels are set to VDDIO. VDDIO may be set to be equal to VDD or to another voltage, such that
it is between 1.71 V and 3.6V at all times. Both I2C and SPI communication support VDDIO.
(0V - VDDIO)
SYSTEM BUS
VDD
VDDIO
VDDIO
ITG-1010
(0V - VDDIO)
INT
System
Processor
(0V - VDDIO)
FSYNC
VDDIO
(0V - VDDIO)
(0V - VDDIO)
(0V, VDDIO)
(0V, VDDIO)
SDA/SDI
SCL/SCLK
AD0/SDO
/CS
SDA
VDDIO
SCL
AD0/SDO
/CS
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8
Assembly
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems
(MEMS) gyros packaged in Quad Flat No leads package (QFN) surface mount integrated circuits.
This preliminary datasheet only provides limited information with respect to ITG-1010 Assembly. Additional
information will be supplied in subsequent versions of the document.
8.1
Orientation of Axes
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier in the figure.
+Z
ITG
-
1010
+Y
+X
Orientation of Axes of Sensitivity and Polarity of Rotation
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8.2
Package Dimensions
DIMENSIONS IN
MILLIMETERS
NOM
SYMBOLS
MIN
MAX
A
A1
b
c
D
D2
E
E2
e
0.85
0.00
0.18
---
2.90
1.75
2.90
1.75
---
0.90
0.02
0.25
0.20 REF
3.00
1.80
3.00
1.80
0.50
0.95
0.05
0.30
---
3.10
1.85
3.10
1.85
---
f (e-b)
K
---
0.30
0.08
---
---
0.00
0.25 REF
0.35
REF.
0.15
0.30
---
---
0.40
---
---
---
L
R
R1
W
y
0.075
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8.3
Package Marking Specification
TOP VIEW
T36D C
XXXXXX
YYWW
Part number
Lot traceability code
Y = Year Code
WW = Work Week
Part number:
Product
ITG-1010
Top Mark
T36D C
8.4
Tape & Reel Specification
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ITG-1010 Product Specification
Reel Dimensions and Package Size
REEL (mm)
PKG
SIZE
L
V
W
Z
3x3
330
102
12.8
2.3
User Direction of
Feed
Package Orientation
Cover Tape
(Anti-Static)
Carrier Tape
(Anti-Static)
Label
Pin 1
Reel
Tape and Reel Specification
Reel Specifications
Quantity Per Reel
5,000
Reels per Pizza Box
Pizza Boxes Per Carton (max)
Pcs/Carton (max)
1
5
25,000
Note: empty pizza boxes are included to ensure that pizza boxes don’t shift.
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8.5
PCB Design Guidelines
The Pad Diagram using a JEDEC type extension with solder rising on the outer edge is shown below. The
Pad Dimensions Table shows pad sizing (mean dimensions) recommended for the product.
JEDEC type extension with solder rising on outer edge
SYMBOLS
DIMENSIONS IN MILLIMETERS
Nominal Package I/O Pad Dimensions
Lead Finger (Pad) Pitch, (Land Pitch)
Lead Finger (Pad) Width
Lead Finger (Pad) Length
Package Width
Package Length
Exposed Pad Width
Exposed Pad Length
NOM
e
b
L
D
E
0.50
0.25
0.35
3.00
3.00
1.80
1.80
D2
E2
I/O Land Design Dimensions (Guidelines )
PCB Land Extent Width
PCB Land Extent Length
D3
E3
c
Tout
Tin
L1
3.70
3.70
0.30
0.35
0.05
0.75
0.30
PCB Land Width
Outward Extension (Land beyond Pad)
Inward Extension (Land beyond Pad)
Land Length
x
Silkscreen Corner Marker Length
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9
Register Map
The register map for the ITG-1010 is listed below.
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
XG_OFFS_
TC_H [9]
XG_OFFS_
TC_H [8]
04
05
04
05
XG_OFFS_TC_H
XG_OFFS_TC_L
R/W
R/W
-
-
-
-
-
-
XG_OFFS_TC_L [7:0]
YG_OFFS_
TC_H [9]
YG_OFFS_
TC_H [8]
07
08
0A
07
08
10
YG_OFFS_TC_H
YG_OFFS_TC_L
ZG_OFFS_TC_H
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
YG_OFFS_TC_L [7:0]
ZG_OFFS_
TC_H [9]
ZG_OFFS_
TC_H [8]
-
-
0B
13
11
19
ZG_OFFS_TC_L
XG_OFFS_USRH
R/W
R/W
ZG_OFFS_TC_L [7:0]
X_OFFS_USR[15:8]
14
15
16
17
18
19
20
21
22
23
24
25
XG_OFFS_USRL
YG_OFFS_USRH
YG_OFFS_USRL
ZG_OFFS_USRH
G_OFFS_USRL
SMPLRT_DIV
R/W
R/W
R/W
R/W
R/W
R/W
X_OFFS_USR[7:0]
Y_OFFS_USR[15:8]
Y_OFFS_USR[7:0]
Z_OFFS_USR[15:8]
Z_OFFS_USR[7:0]
SMPLRT_DIV[7:0]
FIFO
_MODE
1A
1B
23
26
27
35
CONFIG
R/W
R/W
R/W
-
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
GYRO_CONFIG
FIFO_EN
XG_ST
YG_ST
ZG_ST
-
-
FCHOICE_B[1:0]
FS_SEL [1:0]
ZG
TEMP
_FIFO_EN
XG
_FIFO_EN
YG
_FIFO_EN
-
-
-
-
-
_FIFO_EN
FSYNC
_INT
_MODE_EN
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_
INT_LEVEL
37
38
3A
55
56
58
INT_PIN_CFG
INT_ENABLE
INT_STATUS
R/W
R/W
R
INT_LEVEL
INT_OPEN
FIFO
_OFLOW
_EN
FSYNC_INT
_EN
DATA
_RDY_EN
-
-
-
-
-
-
-
-
-
-
FIFO
_OFLOW
_INT
DATA
_RDY_INT
FSYNC_INT
41
42
43
44
45
46
47
48
65
66
67
68
69
70
71
72
TEMP_OUT_H
TEMP_OUT_L
R
R
R
R
R
R
R
R
TEMP_OUT[15:8]
TEMP_OUT[7:0]
GYRO_XOUT[15:8]
GYRO_XOUT[7:0]
GYRO_YOUT[15:8]
GYRO_YOUT[7:0]
GYRO_ZOUT[15:8]
GYRO_ZOUT[7:0]
GYRO_XOUT_H
GYRO_XOUT_L
GYRO_YOUT_H
GYRO_YOUT_L
GYRO_ZOUT_H
GYRO_ZOUT_L
I2C_IF
_DIS
FIFO
_RESET
SIG_COND
_RESET
6A
6B
106
107
USER_CTRL
R/W
R/W
-
FIFO_EN
SLEEP
-
-
-
-
DEVICE
_RESET
PWR_MGMT_1
-
TEMP_DIS
CLKSEL[2:0]
STBY_YG
6C
72
73
74
75
108
114
115
116
117
PWR_MGMT_2
FIFO_COUNTH
FIFO_COUNTL
FIFO_R_W
R/W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
STBY_XG
-
STBY_ZG
-
-
-
FIFO_COUNT[9:8]
FIFO_COUNT[7:0]
FIFO_DATA[7:0]
WHO_AM_I[6:1]
WHO_AM_I
-
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Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal
register value.
In the detailed register tables that follow, register names are in capital letters, while register values are in
capital letters and italicized. For example, the GYRO_XOUT_H register (Register 67) contains the 8 most
significant bits, GYRO_XOUT[15:8], of the 16-bit X-Axis gyroscope measurement, GYRO_XOUT.
The reset value is 0x00 for all registers other than the WHO_AM_I register (Register 117), which resets to
0x68.
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10
Register Descriptions
This section describes the function and contents of each register.
Note: The device will come up in full power mode upon power-up. (i.e. not sleep mode)
10.1
Registers 04-05, 07-08, 10-11- Gyroscope offset Temperature Compensation (TC)
XG_OFFS_TC_H, XG_OFFS_TC_L, YG_OFFS_TC_H, YG_OFFS_TC_L, ZG_OFFS_TC_H,
and ZG_OFFS_TC_L
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
XG_OFFS_TC_H
[8]
XG_OFFS_TC_H [9]
04
04
05
07
05
07
XG_OFFS_TC_L [7:0]
YG_OFFS_TC_L [7:0]
YG_OFFS_TC_H
[8]
YG_OFFS_TC_H [9]
ZG_OFFS_TC_H [9]
08
0A
0B
08
10
11
ZG_OFFS_TC_H
[8]
ZG_OFFS_TC_L [7:0]
Description:
The temperature compensation (TC) registers are used to reduce gyro offset variation due
to temperature change. The TC feature is always enabled. However the compensation only
happens when a non-zero TC coefficient is programed during factory trim which gets loaded
into these registers at power up or after a DEVICE_RESET. If these registers contain a value
of zero, temperature compensation has no effect on the offset of the chip. The TC registers
are 10-bit signed values in 2’s complement format with a resolution of 2.52 mdps/C steps.
If these registers contain a non-zero value after power up, the user may write zeros to them to
see the offset values without TC with temperature variation. Note that doing so may result in
offset values that exceed data sheet “Initial ZRO Tolerance” in other than normal ambient
temperature (~21 °C). The TC coefficients maybe restored by the user with a power up or a
DEVICE_RESET.
Parameters:
XG_OFFS_TC_H/L: 10-bit offset of X gyroscope (2’s complement)
YG_OFFS_TC_H/L: 10-bit offset of Y gyroscope (2’s complement)
ZG_OFFS_TC_H/L: 10-bit offset of Z gyroscope (2’s complement)
10.2
Registers 19 to 24 – Gyroscope offset adjustment
XG_OFFS_USRH, XG_OFFS_USRL, YG_OFFS_USRH, YG_OFFS_USRL, ZG_OFFS_USRH, and
ZG_OFFS_USRL
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
13
14
15
16
19
20
21
22
X_OFFS_USR[15:8]
X_OFFS_USR[7:0]
Y_OFFS_USR[15:8]
Y_OFFS_USR[7:0]
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Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
17
18
23
24
Z_OFFS_USR[15:8]
Z_OFFS_USR[7:0]
Description:
These registers are used to remove DC bias from the sensor outputs. The values in these registers
are subtracted from the gyroscope sensor values before going into the sensor registers (see
registers 67 to 72).
Parameters:
XG_OFFS_USR_H/L: 16-bit offset of X gyroscope (2’s complement)
YG_OFFS_USR_H/L: 16-bit offset of Y gyroscope (2’s complement)
ZG_OFFS_USR_H/L: 16-bit offset of Z gyroscope (2’s complement)
10.3
Register 25 – Sample Rate Divider
SMPRT_DIV
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
19
25
SMPLRT_DIV[7:0]
Description:
This register specifies the divider from the gyroscope output rate that can be used to generate a
reduced Sample Rate. Please note that this register is only effective when FCHOICE_B[1:0] = 2’b00
(Register 27) and DLPF_CFG = 1, 2, 3, 4, 5, or 6 (Register 26).
When FCOICE_B[1:0] = 2’b00 but DLPF_CFG = 0 or 7, the Sample Rate is fixed at 8kHz and the
divider in this register does not apply. When FCHOICE_B[1:0] = 2’b01, 2’b10, or 2’b11, the Sample
Rate is fixed at 32kHz and the divider in this register does not apply.
The sensor register output and FIFO output are both based on the Sample Rate.
When this register is effective under the FCOICE_B and DLPF_CFG settings, the reduced Sample
Rate is generated by the formula below:
Sample Rate = Gyroscope Output Rate / (1 + SMPLRT_DIV)
where Gyroscope Output Rate = 1kHz.
Parameters:
SMPLRT_DIV
8-bit unsigned value. The Sample Rate is determined by dividing the
gyroscope output rate by this value.
10.4
Register 26 – Configuration
CONFIG
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1A
26
-
FIFO_MODE
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
Description:
This register configures the FIFO’s mode of operation, the external Frame Synchronization (FSYNC)
pin sampling and the Digital Low Pass Filter (DLPF) setting. Please note that the DLPF can only be
used when FCHOICE_B[1:0] =2b’00 (Register 27).
When FIFO_MODE is set to 1 and the FIFO is full, additional writes will not be written to the FIFO.
When this bit is equal to 0 and the FIFO is full, additional writes will be written to the FIFO, replacing
the oldest data. In order to enable and disable writing to the FIFO, use the enable bits in Register 35.
For further information regarding the FIFO’s operation, please refer to Register 116.
An external signal connected to the FSYNC pin can be sampled by configuring EXT_SYNC_SET.
Signal changes to the FSYNC pin are latched so that short strobes may be captured. The latched
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FSYNC signal will be sampled at the Sampling Rate, as defined in register 25. After sampling, the
latch will reset to the current FSYNC signal state.
The sampled value will be reported in place of the least significant bit in a sensor data register
determined by the value of EXT_SYNC_SET according to the following table.
EXT_SYNC_SET FSYNC Bit Location
0
1
2
3
4
Input disabled
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
The DLPF is configured by DLPF_CFG, when FCHOICE_B[1:0] = 2b’00. The gyroscope and
temperature sensor are filtered according to the value of DLPF_CFG and FCHOICE_B as shown in
the table below.
FCHOICE_B
Gyroscope
Temperature Sensor
DLPF_CFG
Bandwidth
(Hz)
Delay
(ms)
Bandwidth
Delay
(ms)
<1>
<0>
Fs (kHz)
(Hz)
4000
188
98
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
1
0
0
1
2
3
4
5
6
7
x
x
250
184
92
0.97
2.9
8
1
0.04
1.9
3.9
1
2.8
41
5.9
1
42
4.8
20
9.9
1
20
8.3
10
17.85
33.48
0.17
0.064
0.11
1
10
13.4
18.6
0.04
0.04
0.04
5
1
5
3600
8800
3600
8
4000
4000
4000
32
32
1
Bit 7 is reserved.
Parameters:
FIFO_MODE
When set to 1 and the FIFO is full, additional writes will not be written to the
FIFO.
When equal to 0 and the FIFO is full, additional writes will be written to the
FIFO, replacing the oldest data.
In order to disable writing to the FIFO, use the enable bits in Register 35.
3-bit unsigned value. Configures the FSYNC pin sampling.
3-bit unsigned value. Configures the DLPF setting.
EXT_SYNC_SET
DLPF_CFG
10.5
Register 27 – Gyroscope Configuration
GYRO_CONFIG
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1B
27
XG_ST
YG_ST
ZG_ST
FS_SEL[1:0]
-
FCHOICE_B[1:0]
Description:
This register is used to trigger gyroscope self test and configure the gyroscopes’ full scale range.
Gyroscope self-test permits users to test the mechanical and electrical portions of the gyroscope.
When self-test is activated by setting XG_ST, YG_ST, ZG_ST bits in register 27, the on-board
electronics will actuate the appropriate sensor. This actuation will move the sensor’s proof masses
over a distance equivalent to a pre-defined Coriolis force. This proof mass displacement results in a
change in the sensor output, which is reflected in the output signal. The output signal is used to
observe the self-test response. The self-test response (STR) is stored in the sensor data output
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registers 67 – 72. This self-test-response is used to determine whether the part has passed or failed
self-test
This self-test response must be within the limits provided in product specification document for the
part to pass self-test. Otherwise, the part is deemed to have failed self-test.
FS_SEL selects the full scale range of the gyroscope outputs according to the following table.
FS_SEL
Full Scale Range
± 250 °/s
0
1
2
3
± 500 °/s
± 1000 °/s
± 2000 °/s
FCHOICE_B, in conjunction with DLPF_CFG (Register 26), is used to choose the gyroscope output
setting. For further information regarding the operation of FCHOICE_B, please refer to Section 4.2.
Bit 2 is reserved.
Parameters:
XG_ST
YG_ST
ZG_ST
FS_SEL
FCHOICE_B
Setting this bit causes the X axis gyroscope to perform self test.
Setting this bit causes the Y axis gyroscope to perform self test.
Setting this bit causes the Z axis gyroscope to perform self test.
2-bit unsigned value. Selects the full scale range of gyroscopes.
2-bit unsigned value used to choose the gyroscope output setting.
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10.6
Register 35 – FIFO Enable
FIFO_EN
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TEMP_
FIFO_EN
XG_
FIFO_EN
YG_
FIFO_EN
ZG_
FIFO_EN
23
35
-
-
-
-
Description:
This register determines which sensor measurements are loaded into the FIFO buffer.
Data stored inside the sensor data registers (Registers 65 to 72) will be loaded into the FIFO buffer if
a sensor’s respective FIFO_EN bit is set to 1 in this register. The behavior of FIFO writes when the
FIFO buffer is full can be configured with the FIFO_MODE bit (Register 26). In order to read the data
in the FIFO buffer, the FIFO_EN bit (Register 106) must be enabled.
When a sensor’s FIFO_EN bit is enabled in this register, data from the sensor data registers will be
loaded into the FIFO buffer. The sensors are sampled at the Sample Rate as defined in Register 25.
For further information regarding sensor data registers, please refer to Registers 65 to 72
Bits 3 through 0 are reserved.
Parameters:
TEMP_FIFO_EN
XG_ FIFO_EN
YG_ FIFO_EN
ZG_ FIFO_EN
When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers
65 and 66) to be written into the FIFO buffer.
When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L
(Registers 67 and 68) to be written into the FIFO buffer.
When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L
(Registers 69 and 70) to be written into the FIFO buffer.
When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L
(Registers 71 and 72) to be written into the FIFO buffer.
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10.7
Register 55 – INT Pin / Bypass Enable Configuration
INT_PIN_CFG
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FSYNC
_INT_
MODE_EN
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_
INT_LEVEL
INT_LEVEL
INT_OPEN
-
-
37
55
Description:
This register configures the behavior of the interrupt signals at the INT pins. This register is also
used to enable the FSYNC Pin to be used as an interrupt to the host application processor.
Bits 1 and 0 are reserved.
Parameters:
INT_LEVEL
When this bit is equal to 0, the logic level for the INT pin is active high.
When this bit is equal to 1, the logic level for the INT pin is active low.
When this bit is equal to 0, the INT pin is configured as push-pull.
INT_OPEN
When this bit is equal to 1, the INT pin is configured as open drain.
When this bit is equal to 0, the INT pin emits a 50us long pulse.
LATCH_INT_EN
When this bit is equal to 1, the INT pin is held high until the interrupt is
cleared.
INT_RD_CLEAR
When this bit is equal to 0, interrupt status bits are cleared only by
reading INT_STATUS (Register 58)
When this bit is equal to 1, interrupt status bits are cleared on any
read operation.
FSYNC_INT_LEVEL
When this bit is equal to 0, the logic level for the FSYNC pin (when
used as an interrupt to the host processor) is active high.
When this bit is equal to 1, the logic level for the FSYNC pin (when
used as an interrupt to the host processor) is active low.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt
when it transitions to the level specified by FSYNC_INT_LEVEL.
When a FSYNC interrupt is triggered, the FSYNC_INT bit in Register
58 will be set to 1. An interrupt is sent to the host processor if the
FSYNC interrupt is enabled by the FSYNC_INT_EN bit in Register 56.
When this bit is equal to 0, the FSYNC pin is disabled from causing an
interrupt.
FSYNC_INT_MODE_EN
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10.8
Register 56 – Interrupt Enable
INT_ENABLE
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FIFO
_OFLOW
_EN
FSYNC
_INT_EN
DATA
_RDY_EN
-
-
-
-
-
38
56
Description:
This register enables interrupt generation by interrupt sources.
For information regarding the interrupt status for of each interrupt generation source, please refer to
Register 58.
Bits 7 through 5, 2, and 1 are reserved.
Parameters:
FIFO_OFLOW_EN
When set to 1, this bit enables a FIFO buffer overflow to generate an
interrupt.
FSYNC_INT_EN
When equal to 0, this bit disables the FSYNC pin from causing an interrupt to
the host processor.
When set to 1, this bit enables the FSYNC pin to be used as an interrupt to
the host processor.
DATA_RDY_EN
When set to 1, this bit enables the Data Ready interrupt. The Data Ready
interrupt is triggered when all the sensor registers have been written with the
latest gyro sensor data.
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10.9
Register 58 – Interrupt Status
INT_STATUS
Type: Read Only
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FIFO
_OFLOW
_INT
FSYNC
_INT
DATA
_RDY_INT
-
-
-
-
-
3A
58
Description:
This register shows the interrupt status of each interrupt generation source. Each bit will clear after
the register is read.
For information regarding the corresponding interrupt enable bits, please refer to Register 56.
Bits 7 through 5, 2, and 1 are reserved.
Parameters:
FIFO_OFLOW_INT
FSYNC_INT
This bit automatically sets to 1 when a FIFO buffer overflow interrupt has
been generated.
The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when an FSYNC interrupt has been
generated.
The bit clears to 0 after the registers has been read.
This bit automatically sets to 1 when a Data Ready interrupt is generated.
The bit clears to 0 after the register has been read.
DATA_RDY_INT
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10.10
Registers 65 and 66 – Temperature Measurement
TEMP_OUT_H and TEMP_OUT_L
Type: Read Only
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
41
42
65
66
TEMP_OUT[15:8]
TEMP_OUT[7:0]
Description:
These registers store the most recent temperature sensor measurement.
Temperature measurements are written to these registers at the Sample Rate as defined in Register
25.
These temperature measurement registers, along with the gyroscope measurement registers, are
composed of two sets of registers: an internal register set and a user-facing read register set.
The data within the temperature sensor’s internal register set is always updated at the Sample Rate.
Meanwhile, the user-facing read register set duplicates the internal register set’s data values
whenever the serial interface is idle. This guarantees that a burst read of sensor registers will read
measurements from the same sampling instant. Note that if burst reads are not used, the user is
responsible for ensuring a set of single byte reads correspond to a single sampling instant by
checking the Data Ready interrupt.
The scale factor and offset for the temperature sensor are found in the Electrical Specifications table
in Product Specification document.
Parameters:
TEMP_OUT
16-bit signed value.
Stores the most recent temperature sensor measurement.
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10.11
Registers 67 to 72 – Gyroscope Measurements
GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H, GYRO_YOUT_L, GYRO_ZOUT_H, and
GYRO_ZOUT_L
Type: Read Only
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
43
44
45
46
47
48
67
68
69
70
71
72
GYRO_XOUT[15:8]
GYRO_XOUT[7:0]
GYRO_YOUT[15:8]
GYRO_YOUT[7:0]
GYRO_ZOUT[15:8]
GYRO_ZOUT[7:0]
Description:
These registers store the most recent gyroscope measurements. Gyroscope measurements are
written to these registers at the Sample Rate as defined in Register 25.
The gyroscope sensor registers continuously update at the user selectable ODR sample rate
whenever the serial interface is idle. It is recommended to use burst reads on host interface to
guarantee a read of sensor registers will read measurements from the same sampling instant. Note
that if burst reads are not used, the user is responsible for ensuring a set of single byte reads
correspond to a single sampling instant by checking the Data Ready interrupt. Failing to do so, may
result in reading the low and high byte of the same sensor from different samples which could
appear as noise peaks to the user for example. The following should be considered for single byte
read mode:
1. Data_RDY_INT gets generated any time the sensor registers get updated with the sensor data.
The frequency of this interrupt is the same as the ODR which is user selectable. The INT
Configurations, INT status register and INT pin can be configured using the user register 37h,
38h and 3Ah.
2. The sensor register outputs are 16 bits (2 bytes). Both bytes should be read at the same time in
order to get reliable data using burst mode. If a single byte read is used, the host needs to read
the bytes back to back after Data_RDY_INT is set to ensure both bytes are from same sample.
3. The sensor registers should be read at a faster rate than the selected ODR with the read cycle
preferably completed for all the sensors to get consistent and reliable output.
Each 16-bit gyroscope measurement has a full scale defined in FS_SEL (Register 27). For each full
scale setting, the gyroscopes’ sensitivity per LSB in GYRO_xOUT is shown in the table below:
FS_SEL
Full Scale Range
LSB Sensitivity
± 250 °/s
0
1
2
3
0
1
2
3
± 500 °/s
± 1000 °/s
± 2000 °/s
Parameters:
GYRO_XOUT 16-bit 2’s complement value.
Stores the most recent X axis gyroscope measurement.
GYRO_YOUT 16-bit 2’s complement value.
Stores the most recent Y axis gyroscope measurement.
GYRO_ZOUT 16-bit 2’s complement value.
Stores the most recent Z axis gyroscope measurement.
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10.12
Register 106 – User Control
USER_CTRL
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I2C_IF
_DIS
FIFO
_RESET
SIG_COND
_RESET
-
FIFO_EN
-
-
-
6A
106
Description:
This register allows the user to enable and disable the FIFO buffer and choose the primary I2C
interface. The FIFO buffer, sensor signal paths and sensor registers can also be reset using this
register.
The primary SPI interface will be enabled in place of the disabled primary I2C interface when
I2C_IF_DIS is set to 1.
When the reset bits (FIFO_RESET and SIG_COND_RESET) are set to 1, these reset bits will trigger
a reset and then clear to 0.
Bits 7, 5, 3, and 1 are reserved.
Parameters:
FIFO_EN
When set to 1, this bit enables FIFO operations.
When this bit is cleared to 0, the FIFO buffer is disabled. The FIFO buffer
cannot be read from while disabled. However, it can still be written to. In
order to disable writing to the FIFO, please use the enable bits in Register
35.
The FIFO buffer’s data will not be lost unless the FIFO is reset, or unless the
device is power cycled or soft reset.
I2C_IF_DIS
When set to 1, this bit disables the primary I2C interface and enables the SPI
interface instead.
FIFO_RESET
This bit resets the FIFO buffer when set to 1. It is recommended that
FIFO_EN be 0 when this is done. This bit automatically clears to 0 after the
reset has been triggered.
SIG_COND_RESET When set to 1, this bit resets the signal paths for all sensors (gyroscopes and
temperature sensor). This operation will also clear the sensor registers. This
bit automatically clears to 0 after the reset has been triggered.
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10.13
Register 107 – Power Management 1
PWR_MGMT_1
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DEVICE
_RESET
SLEEP
-
-
TEMP_DIS
CLKSEL[2:0]
6B
107
Description:
This register allows the user to configure the power mode and clock source. It also provides a bit for
resetting the entire device, and a bit for disabling the temperature sensor.
By setting SLEEP to 1, the device can be put into low power sleep mode.
An internal 20MHz oscillator or the gyroscope based clock (PLL) can be selected as the device clock
source. The PLL is the default clock source upon power up. In order for the gyroscope to perform to
spec, the PLL must be selected as the clock source.
When the internal 20MHz oscillator is chosen as the clock source, the device can operate while
having the gyroscopes disabled. However, this is only recommended if the user wishes to use the
internal temperature sensor in this mode.
The clock source can be selected according to the following table.
CLKSEL
Clock Source
0
1
2
3
4
5
6
7
Internal 20MHz oscillator
PLL
PLL
PLL
PLL
PLL
Internal 20MHz oscillator
Reserved
For further information regarding the device clock source, please refer to the relevant Product
Specification document and the Power Mode Transition Descriptions section in the Appendix.
Bits 5 and 4 are reserved.
Parameters:
DEVICE_RESET
When set to 1, this bit resets all internal registers to their default values.
The bit automatically clears to 0 once the reset is done.
The default values for each register can be found in Section 3.
When set to 1, this bit puts the device into sleep mode.
When set to 1, this bit disables the temperature sensor.
3-bit unsigned value. Specifies the clock source of the device.
SLEEP
TEMP_DIS
CLKSEL
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10.14
Register 108 – Power Management 2
PWR_MGMT_2
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
STBY_XG
STBY_YG
STBY_ZG
6C
108
Description:
This register allows the user to put individual axes of the gyroscope into standby mode. Note that in
order to activate any gyro axis again, all gyro axes must first be put into standby mode, and then be
turned on simultaneously.
If the user wishes to put all three gyro axes into standby mode, the internal oscillator must be
selected as the clock source (Register 107).
If all three gyro axes are put into standby mode while the clock source of the device is set to the PLL
(with the gyro drive generating the reference clock), the chip will hang due to an absence of a clock.
As long as one gyro axis is enabled, the drive circuit will remain active and the PLL will provide a
clock.
Bits 7 through 3 are reserved.
Parameters:
STBY_XG
STBY_YG
STBY_ZG
When set to 1, this bit puts the X axis gyroscope into standby mode.
When cleared to 0 after all three gyro axes have been but into standby
mode, the gyroscope turns on.
When set to 1, this bit puts the Y axis gyroscope into standby mode.
When cleared to 0 after all three gyro axes have been but into standby
mode, the gyroscope turns on.
When set to 1, this bit puts the Z axis gyroscope into standby mode.
When cleared to 0 after all three gyro axes have been but into standby
mode, the gyroscope turns on.
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ITG-1010 Product Specification
10.15
Register 114 and 115 – FIFO Count Registers
FIFO_COUNT_H and FIFO_COUNT_L
Type: Read Only
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
72
73
114
115
-
-
-
-
-
-
FIFO_COUNT[9:8]
FIFO_COUNT[7:0]
Description:
These registers keep track of the number of samples currently in the FIFO buffer in terms of the
number of bytes stored.
These registers shadow the FIFO Count value. Both registers are loaded with the current sample
count when FIFO_COUNT_H (Register 114) is read.
Note: Reading only FIFO_COUNT_L will not update the registers to the current FIFO COUNT value.
FIFO_COUNT_H must be accessed first to update the contents of both these registers.
FIFO_COUNT should always be read in high-low order in order to guarantee that the most current
FIFO Count value is read.
Bits 7 through 2 of Register 114 are reserved.
Parameters:
FIFO_COUNT
16-bit unsigned value. Indicates the number of bytes stored in the FIFO
buffer. This number is in turn the number of bytes that can be read from the
FIFO buffer and it is directly proportional to the number of samples available
given the set of sensor data bound to be stored in the FIFO (register 35).
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10.16
Register 116 – FIFO Read Write
FIFO_R_W
Type: Read/Write
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
74
116
FIFO_DATA[7:0]
Description:
This register is used to read and write data from the FIFO buffer.
Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable
flags (see below) are enabled, the contents of registers 65 through 72 will be written in order at the
Sample Rate, based on the description for SMPLRT_DIV, located in Register 25.
The contents of the sensor data registers (Registers 65 to 72) are written into the FIFO buffer when
their corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit
is located in INT_STATUS (Register 58). When the FIFO buffer has overflowed, the treatment of the
new data is determined by the FIFO_MODE bit in Register 26.
The user should check FIFO_COUNT to ensure that the FIFO buffer is not read when empty, and
that more data than available is not read from the FIFO.
Parameters:
FIFO_DATA
8-bit data transferred to and from the FIFO buffer.
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ITG-1010 Product Specification
10.17
Register 117 – Who Am I
WHO_AM_I
Type: Read Only
Register
(Decimal)
Register
(Hex)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
75
117
-
WHO_AM_I[5:0]
-
Description:
This register is used to verify the identity of the device. The contents of WHO_AM_I are the upper 6
bits of the device’s 7-bit I2C address. The least significant bit of the IT devices’s I2C address is
determined by the value of the AD0 pin. The value of the AD0 pin is not reflected in this register.
The default value of the register is 0x68.
Bits 0 and 7 are reserved. (Hard coded to 0)
Parameters:
WHO_AM_I
Contains the 6-bit I2C address of the gyroscope device
The Power-On-Reset value of Bit6:Bit1 is 110 100.
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Document Number: PS-ITG-1010A-00
Revision: 1.1
Release Date: 03/02/2015
ITG-1010 Product Specification
11 Environmental Compliance
The ITG-1010 is RoHS Green and environmental compliant.
Environmental Declaration Disclaimer:
InvenSense believes this environmental information to be correct but cannot guarantee accuracy or completeness. Conformity
documents for the above component constitutes are on file. InvenSense subcontracts manufacturing and the information contained
herein is based on data received from vendors and suppliers, which has not been validated by InvenSense.
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