MAS3529HPR [TDK]
Consumer Circuit, PQCC44, 16.60 X 16.60 MM, 4.15 MM HEIGHT, PLASTIC, LCC-44;
| 型号： | MAS3529HPR |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Consumer Circuit, PQCC44, 16.60 X 16.60 MM, 4.15 MM HEIGHT, PLASTIC, LCC-44 商用集成电路 |
| 文件： | 总72页 (文件大小：1409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MAS 35xyH
Audio Decoder IC Family
S U R R O U N D
P R O L O G I C II
SPATIALIZER
TM
N-2-2 ULTRA
D
I G I T A L
Edition Dec. 4, 2003
6251-589-2PD
MICRONAS
MAS 35xyH
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
5
5
6
7
1.
Introduction
1.1.
1.2.
1.3.
Features
TV System Application
TV Application Details
9
2.
Functional Description
Overview
9
2.1.
9
2.2.
Architecture
9
2.3.
DSP Core
10
10
10
11
11
11
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
14
15
15
15
15
16
16
16
16
18
18
18
18
18
18
19
2.4.
Internal Program ROM and Firmware
RAM and Registers
Clock Management
Interfaces
2.5.
2.6.
2.7.
2
2.7.1.
2.7.2.
2.7.3.
2.7.4.
2.7.4.1.
2.7.5.
2.8.
I C Control Interface
S/PDIF Input Interfaces
S/PDIF Output
Serial Input Interface
Multiline Serial Output
Frame Synchronization
Power-Supply Regions
2.9.
Functional Blocks and Operation
Power-Up Sequence and Default Operation
Input Switching
2.9.1.
2.9.2.
2.9.3.
2.9.4.
2.9.5.
2.9.6.
2.9.7.
2.9.8.
2.9.9.
2.9.10.
2.9.10.1.
2.9.10.2.
2.9.11.
2.9.12.
2.9.13.
2.9.14.
2.9.14.1.
2.9.14.2.
2.9.14.3.
2.9.15.
2.9.16.
2.9.17.
2.10.
Standard Selection and Decoding
Dolby Digital Data Stream
DTS (Digital Theater Systems) Data Stream
MPEG Layer-2 Data Stream
PCM Audio Data
De-emphasis
Dolby Pro Logic II Input Matrix
Dolby Pro Logic II Decoder
Major Operational Modes of Pro Logic II
Additional Operational Modes
Channel Expander
Noise Generator
Virtual Dolby Digital
Post Processing/Bass Management
Extra Stereo Output
Digital Volume
Bass Management
Output Format Selection
S/PDIF Loop-Through
Output Sampling Rate
System Interaction
2.10.1.
2.10.2.
2.10.3.
Minimum Required Interconnections
Required Special Modes in the System
Minimum System Set-Up
2
Dec. 4, 2003; 6251-598-2PD
Micronas
PRELIMINARY DATA SHEET
MAS 35xyH
Contents, continued
Page
Section
Title
20
20
20
20
20
20
21
21
21
23
23
23
23
24
24
24
25
27
27
38
49
3.
Control Interface
3.1.
Start-Up Sequence
2
3.2.
I C Interface Access
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.3.
General
2
I C Registers and Subaddresses
Conventions for the Command Description
The Internal Fixed Point Number Format
2
I C Control Register (Code 6A
)
hex
2
3.4.
I C Data Register (Codes 68
and 69 ) and the MAS 35xyH DSP-Command Syntax
hex hex
3.4.1.
3.4.2.
3.4.3.
3.4.4.
3.4.5.
3.4.6.
3.4.7.
3.5.
Read Register (Code A
)
hex
Write Register (Code B
)
hex
Read Memory (Codes C
and D
)
hex
hex
Short Read Memory (Codes C4
and D4
)
hex
hex
Write Memory (Codes E
and F
)
hex
hex
Short Write Memory (Codes E4
Default Read
and F4
)
hex
hex
Registers
3.6.
Special Memory Locations and User Interface
Status Interface for Decoding
3.6.1.
3.6.2.
3.6.3.
Control Interface for Decoding Operation
Hybrid User Interface Cells
51
51
53
56
56
56
56
56
56
56
56
56
56
57
59
60
60
61
61
62
62
62
63
64
65
4.
Specifications
4.1.
Outline Dimensions
4.2.
Pin Connections and Short Descriptions
Pin Descriptions
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.7.
4.3.8.
4.3.9.
4.4.
Power Supply Pins
Control Lines
General Purpose Input/Output
Clocking
Serial Input Interface
S/PDIF Input Interface
S/PDIF Output Interface
Serial Output Interface
Miscellaneous
Pin Configurations
4.5.
Internal Pin Circuits
4.6.
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
General Recommended Operating Conditions
Reference Frequency Generation and Crystal Recommendations
Characteristics
4.6.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
General Characteristics
2
I C Characteristics
S/PDIF Bus Input Characteristics
S/PDIF Bus Output Characteristics
Micronas
Dec. 4, 2003; 6251-598-2PD
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MAS 35xyH
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
2
66
67
68
4.6.3.5.
4.6.3.6.
4.6.4.
I S Bus Characteristics – Input
2
I S Characteristics – Output
Firmware Characteristics
69
72
5.
6.
Application
Data Sheet History
License Notice:
DTS, DTS Digital Surround, and DTS Virtual 5.1 are trademarks and the "DTS" Logos are registered trademarks of
the Digital Theatre Systems Corporation.
“Dolby Digital”, “Pro Logic ΙΙ”, and the double-D Symbol are trademarks of Dolby Laboratories. Supply of this imple-
mentation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial
or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-
use final product. Companies planning to use this implementation in products must obtain a license from Dolby Lab-
oratories Licensing Corporation before designing such products.
®
Spatializer , Spatializer N-2-2‘, and the circle-in-square device are trademarks of Desper Products, Inc.
4
Dec. 4, 2003; 6251-598-2PD
Micronas
PRELIMINARY DATA SHEET
MAS 35xyH
Audio Decoder IC Family
In a consumer audio application, the MAS 35xyH,
completed by a standard audio codec and power
amplifiers, forms a 5.1 multichannel audio A/V ampli-
fier or receiver. The high integration level of
MAS 35xyH with its S/PDIF on chip, enables the
design of very economic 5.1 home audio sets.
This data sheet applies to the MAS 35xyH family,
version C6, and to following versions.
Release Note: Revision bars indicate significant
changes to the previous edition.
1.1. Features
1. Introduction
– Two multiplexed S/PDIF, IEC-958, IEC 61937, AES/
EBU, EIA-J CP-340 receivers
The Micronas MAS 35xyH family consists of ICs with
various combinations of DTS, Dolby Digital, Dolby
Pro Logic II and MPEG-1 Layer-2 decoders and Virtu-
alizer on a single chip. The family consists by the fol-
lowing members:
– Two freely configurable multiplexed serial inputs
– Decoders for 5.1 Dolby Digital (AC-3),
5.1 DTS, Dolby Pro Logic II and MPEG-1 Layer-2
– Spatializer N-2-2 ULTRA as “Virtual Dolby Digital”-
compliant virtualizer
Table 1–1: MAS 35xyH family
– Handling of PCM input format
Decoder
MAS35xyH Type
– S/PDIF PCM output or loop-through for all inputs
– Lt, Rt encoding or straight downmixing to two chan-
nels (Lo, Ro) simultaneously to 5.1 multichannel
output
3527H
3529H
3530H
DTS
−
−
✓
✓
✓
✓
2
– Multichannel I S output
Dolby Digital
Pro Logic II
−
✓
✓
✓
(four stereo data lines or one 8-channel line)
−
– Dynamic range compression
VDD (Virtual
Dolby Digital)
✓
– Karaoke downmixing
– Delay for center (0…5 ms)
VDS (Virtual
Dolby Surround)
✓
✓
✓
– Delay for surround (two channels, 0…25 ms)
– Bandpass-shaped/white-noise generator
MPEG1 L2
✓
✓
✓
– Bass management according to Dolby specification
(output configuration 0, 1, 2, 3, and DVD) and “Bass
to Center”
N-2-2 ULTRA
optional
optional
optional
2
– I C control
The MAS 35xyH decoder IC acts as a complete imple-
mentation of 5.1 DTS and Dolby Digital/Pro Logic II
decoders. On the chip’s 8-channel output an Lt/Rt or
Lo/Ro downmix is available simultaneously to the mul-
tichannel audio for recording or headphone usage. All
necessary processing units, together with the I/O inter-
faces, have been integrated in a single 44-pin IC.
In a TV application, a two-chip solution of MAS 3527H
and MSP 44x0G results in a Virtual Dolby Digital Sys-
tem, whereas
a
multichannel audio TV uses
MAS 35xyH, MSP 44x0G and DPL 4519G. Due to the
scalable and flexible Micronas system solution, a sin-
gle hardware (PCB) solution, as well as a single TV
software solution, can be used to implement TV audio
systems from stereo only, via Virtual Dolby Digital, to
DTS/Dolby Digital multichannel audio.
Micronas
Dec. 4, 2003; 6251-598-2PD
5
MAS 35xyH
PRELIMINARY DATA SHEET
1.2. TV System Application
The Micronas DTS/Dolby Digital TV system solution
consists of three dedicated integrated circuits:
– The MSP 44x0G is the interface for all TV-sound
and analog input signals. It performs the TV-audio
demodulation and stereo decoding. It has four pairs
of audio D/A-converters, two of them including
sound control facilities, and one additional sub-
woofer D/A converter.
– The DPL 4519G adds three pairs of audio D/A-con-
verters, two of them including sound control facili-
ties, and one additional subwoofer D/A converter.
– The MAS 35xyH performs DTS/Dolby Digital or
MPEG decoding, Pro Logic II decoding for all Stereo
Sources, Virtual Dolby Digital processing for sur-
round sound with 2 speakers.
DVD
S/PDIF out
S/PDIF
DVB
MAS 35xyH
PCM / Dolby Digital
2
MPEG via I S Serial
2
I S/Serial
2
L/(Sub)/R or
L/(C)/R
I S
8 ch
DPL 4519G
SL/SR
2
2
I S
I S SCART
L/(Sub)/R or
L/C/R or C/C
8 ch
2 ch
TV
SIF
Tuner
MSP 44x0G
1...8 ch
VCR
SCART
(TV+Stereo)
Lt/Rt or Lo/Ro
SCART
Fig. 1–1: Configuration of the Micronas DTS Dolby Digital/TV system solution.
6
Dec. 4, 2003; 6251-598-2PD
Micronas
PRELIMINARY DATA SHEET
MAS 35xyH
1.3. TV Application Details
SPDI1
SPDI2
SPDIF In 1/2
PCM
MPEG
AC-3
SPDIF Out
SPDO
L
2
R
Input
SOD3
SOD2
SOD1
SOD
Buffer
Ls
Rs
C/
Sub
'Signal mapping configurations
SID*
SII*
SOI
Lt
Example 1:
SOC
Rt
SIC*
- internal L,C,R
- internal woofer for low freq.
I2S-In: Slave
of L,(C),R
SID
SII
DTS
PLL
- ext.Surroundspeakers SL,SR
- ext.Subwoofer for SUB Channel.
Noise
Gen.
SIC
Exanple 2:
- internal Left and Right used as C
- internal woofer for low freq. of C
- ext.L,R
Amp./
Osc.
18.432 MHz
Synth.
- ext.Surroundspeakers SL,SR
- ext.Subwoofer for SUB Channel.
MAS 35xy H
CLKO
Configuration Examples
I2S-Multichannel Mode
Dolby Digital /
stereo
(6 - 8 Channels, fs=32, 44.1 or 48 kHz,
16,18,....32 Bit)
DTS / ProLogic II
I2S_Inputs
1
2
1
2
3
4
Speaker
I2S_1_L
I2S_1_R
Bass
Treble
---
---
---
Cint
SUBext
(Cint
Lext
SUBext
Rext
I2S_WS3
I2S_CL3
D/A
analog
Volume
Balance
Volume
I2S_2_L
I2S_2_R
)
Bass
Treble
Headphone
D/A
AUDIO_
CL_OUT
---
---
SL
SR
SL
I2S_3_Lt
analog
Volume
Balance
Volume
SR
2-8
I2S_3_Rt
Channel
async.
Input
18.432
MHz
SCART1
L
R
---
---
Lt
Lt
Volume
D/A
Rt
Rt
LT, RT,
L, R
SL
L, R
L, R
I2S_Out_L/R
SL, SR,
C, SUB
C, SUB C, SUB
SR
C
---
8 channels
SL, SR
Lt, Rt
SL, SR
Lt, Rt
SUB
I2S_WS
I2S_CL
DPL 4519 G
Upgrade
Module
Basic
TV-
Lt, Rt, L, R, SL, SR, C, SUB
I2S_Inputs
Sound
System
1
2
3
4
Sound-
Speaker
I2S_WS3
I2S_1_L
I2S_1_R
D/A
L
Subw
R
Lint
Subwint
Rint
Cint
Subwint
Cint
Process.
Balance
Volume
I2S_CL3
analog
Volume
I2S_2_L
I2S_2_R
I2S_WS
I2S_CL
Bass
Treble
Headphone
D/A
L
Lt
Lt
analog
Volume
I2S_3_Lt
I2S_3_Rt
I2S_3_L
Balance
Volume
R
Rt
Rt
18.432
MHz
2-8
SCART1
SCART2
I2S_3_R
I2S_3_SL
I2S_3_SR
I2S_3_C
I2S_3_SUB
Channel
sync.
L
Lt
Lt
Volume
Volume
D/A
D/A
R
Rt
Rt
Input
L
Lt
Lt
R
Rt
Rt
Demod
SIF-IN
I2S_Out_L/R
L, R
L, R
L, R
SCART1_In .
.
A/D
2
.
SCART4_In
MSP 4450 G
Multistandard Sound Processor
Fig. 1–2: Block diagram of the MAS 35xyH TV application with output signal mapping
Micronas
Dec. 4, 2003; 6251-598-2PD
7
MAS 35xyH
PRELIMINARY DATA SHEET
GPIO
MAS 35xyH
S/PDIF out
S/PDIF
2
2
I S
I S
6 x Power Amplifier
Line in
(analog)
L
C
R
L
C
R
Audio Codec
A/D and D/A
Sub
S
L
S
R
Line out
(analog)
Fig. 1–3: Block diagram of an MAS 35xyH 5-1 Multichannel Audio Amplifier/Receiver application
8
Dec. 4, 2003; 6251-598-2PD
Micronas
PRELIMINARY DATA SHEET
MAS 35xyH
2. Functional Description
2.1. Overview
2.2. Architecture
The hardware of the MAS 35xyH consists of a high
performance RISC Digital Signal Processor (DSP) and
appropriate interfaces. Fig. 2–1 shows a hardware
overview of the IC; Fig. 2–2 on page 12 shows the
functional aspects.
The MAS 35xyH is intended for use in consumer audio
applications. It receives S/PDIF or serial data streams
and decodes the DTS Dolby Digital (AC-3), MPEG or
PCM-encoded audio formats.
Due to the automatic format detection, no controller
interaction is needed for the standard operation. On
the other hand, the controller has full access to all vital
information contained in the Dolby Digital or DTS bit
stream. The choice of different output formats, as
defined by Dolby, guarantees a good adaption to vari-
ous listening environments.
2.3. DSP Core
The internal processor is a dedicated audio DSP. All
data input and output actions are based on a ‘non-
cycle-stealing’ background DMA that does not cause
any computational overhead.
MAS 35xyH
DSP-Core
PIO
Interface
GPIO
MAC
ALU
1
2
1
2
S/PDIF
Input
Interface
S/PDIF
Output
Interface
Accumulators
S/PDIF
S/PDIF
ROM
2
Serial
Input
Interface
I S
SOD
Serial Audio
2
Serial Audio
(I S)
D0−RAM D1−RAM
SOD1
SOD2
SOD3
2
Registers
2
I C
I C-Bus
Slave
Interface
to controller
Processor Clock
Divider
18.432 MHz
XTI
Reference Clock
Quartz Osc./
Clock Input
System Clock
Synthesizer
CLKO
Divider
XTO
Fig. 2–1: The MAS 35xyH architecture
Micronas
Dec. 4, 2003; 6251-598-2PD
9
MAS 35xyH
PRELIMINARY DATA SHEET
2.4. Internal Program ROM and Firmware
2.6. Clock Management
The firmware implemented in the program ROM of the
MAS 35xyH provides Dolby Digital, DTS and MPEG-1
Layer-2 audio data decompression as well as handling
of PCM-encoded audio. All Stereo sources (PCM,
MPEG1L2, DD 2/0, DTS 2/0) pass through a Dolby
Pro Logic II decoder. The required downmixing, output
configurations and delay lines for an implementation of
Dolby Digital or DTS and loop-through of unsupported
formats received via the S/PDIF input are implemented
as well.
The MAS 35xyH is driven by a single clock at a fre-
quency of 18.432 MHz. The clock may either be pro-
vided by an external source connected to pin XTO, or
by a crystal connected to XTI and XTO. In this case,
the clock signal is available for other applications at pin
XTO.
The internal reference clock and processor clock are
derived from the 18.432 MHz and synchronized to the
audio sample frequency of the decompressed bit
stream by a PLL. For Dolby Digital decoding, the clock
frequency can be selected as a high or a low value in
configuration memory cell UIC_Out_Clk_Scale
(D0:13DF) by bit[16] – (see Table 3–8 on page 49). It
is highly recommended to use the high system clock.
The resulting processor clocks are given in Table 2–1.
For PCM and MPEG signals, a de-emphasis can be
applied to achieve a flat frequency response.
On power-on, the DSP starts the firmware in an auto-
matic standard detection mode with the first S/PDIF
input selected. Therefore, only minimal controlling is
2
necessary. In addition, the I C interface provides a set
At pin CLKO, a clock output can be provided, e.g., for
additional D/A converters. The output frequency at
CLKO is the reference clock divided by a factor as
selected by bits [18:17] in D0:13DF. By default, CLKO
is disabled.
2
of I C instructions that give access to internal DSP
registers and memory areas.
2.5. RAM and Registers
Table 2–1: Processor clock frequencies and reference
clock frequencies in dependence of bit [16] of
UIC_Out_Clk_Scale (D0:13DF)
The DSP core has access to two RAM banks named
D0 and D1. All RAM addresses can be accessed in a
20-bit or a 16-bit mode via I C bus. For more details,
2
please refer to Section 3.4.on page 21.
Format
f /kHz
Processor Clock/MHz
s
For fast access of internal DSP states, the processor
core has an address space of 256 data registers (see
Section 3.5. on page 25) which can be accessed via
bit[16] = 0
61.44
bit[16] = 1
73.728
2
I C bus.
Dolby
Digital,
DTS,
MPEG,
PCM
48
44.1
32
56.448
40.96
67.7376
49.152
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Dec. 4, 2003; 6251-598-2PD
Micronas
PRELIMINARY DATA SHEET
MAS 35xyH
2.7. Interfaces
2.7.4. Serial Input Interface
2
2.7.1. I C Control Interface
If the serial input interface carries Dolby Digital, MPEG
Layer-2, or PCM, the MAS 35xyH processes the data.
The interface consists of the three pins: SIC, SII, and
SID. For MPEG and Dolby Digital decoding operation,
2
For controlling, a standard I C interface is imple-
mented. A detailed description of all functions can be
found in Section 3. on page 20.
the SII pin must always be connected to V , while for
SS
2
PCM data, the interface acts as an I S type and SII is
used as a word strobe. An example of an input signal
format is shown in Fig. 4–18 on page 66. The data val-
ues are latched with the falling edge of the SIC signal.
It is possible to use a word length of 16 or 32 bits. For
controlling details, please refer to memory address
D0:13D0 (I/O Control) and D0:13DF (Auxiliary Inter-
face Control) in Table 3–7 on page 38.
2.7.2. S/PDIF Input Interfaces
Two multiplexed S/PDIF input interfaces are installed
which are capable of PCM, Dolby Digital, DTS and
MPEG auto-detection. In addition to the signal input
pins SPDI/SPDI2, a reference pin SPREF is provided
to support balanced signal sources or twisted pair
transmission lines. The following features are sup-
ported:
If the MPEG or Dolby Digital signal was formatted (e.g.
to 8-bit or 16-bit words) by the storing or transportation
medium (PC, memory), the serial data has to be sent
“MSB first” as produced by the encoder.
– Fast synchronization on input signal (< 50 ms)
– Burst Mode support for Dolby Digital, DTS and
MPEG bit streams
2.7.4.1. Multiline Serial Output
– Locking on 32, 44.1, 48 kHz sample frequencies
The serial audio output interface of the MAS 35xyH is
a standard I S-like interface consisting of four data
– Incoming first 20 channel status bits are mirrored in
2
Register 56
(see Table 3–5 on page 25)
hex
lines SODx, the word strobe SOI, and the clock signal
SOC. The output bit stream can either carry eight
channels on one line (SOD) or two channels on each
of four lines (SOD, SOD1, SOD2, SOD3). Further, it is
possible to choose between different interface configu-
rations (with word strobe time offset and/or with
inverted SOI signal) and to tristate the output interface.
The serial output generates 32 bits per audio sample,
but only the first 20 bits will carry valid audio data. The
12 trailing bits are set to zero by default (see Fig. 4–20
on page 67).
When the input format is changed (e.g. from Dolby
Digital to MPEG), the synchronization is lost and the
audio output is muted. The automatic standard recog-
nition then checks the new input format and, after suc-
cessful recognition, resumes normal operation.
It is possible to observe the S/PDIF input for valid bit-
streams while processing I²S signals, (see Table 3–6),
Adr. D0:13C7 . Detection whether the interface has
hex
synchronized or not, and what the S/PDIF header
information contains, is possible. This permits the fol-
lowing implementations:
The configuration of the output interface is done in
D0:13D0 and D0:13DF (see Table 3–7 on page 38).
– automatic detection whether signals are connected
to the digital input or not, during normal operation
mode (“hot plug-in”)
2.7.5. Frame Synchronization
– automatic fallback to analog sources when unde-
codable bit streams are detected, with automatic
switchback when the signals are decodable again.
For microprocessor interrupts, a frame synchronization
output pin (SYNC) is provided.
After decoding a valid header, the SYNC pin level
changes to High. Most of the status information (UIS
cells in Table 3–6 on page 27) is updated now. To
generate an edge for the controller, the level changes
to Low during processing the next header. After having
completed this, the SYNC pin level changes to High
again. If the level is Low for more than 1 ms, no decod-
ing is performed. Memory cell UIH_LAST_MESSAGE
(D0:13FF) provides background information thereon.
2.7.3. S/PDIF Output
At pin SPDIFOUT, the baseband audio is provided as
an S/PDIF signal.
Channel status bits in S/PDIF output (especially copy-
right, category code and generation status) can be
configured in D0:13EA (see Table 3–7 on page 38).
Alternatively, this output can mirror the unprocessed
signal of the S/PDIF input (Output_Conf: Register
2E ). This loop-through is necessary for signals
hex
where no internal decoding action is performed.
Micronas
Dec. 4, 2003; 6251-598-2PD
11
MAS 35xyH
PRELIMINARY DATA SHEET
Notes for Dolby Digital:
2.9. Functional Blocks and Operation
After first CRC is done, the SYNC pin level changes to
High, all information for a frame is valid, and decoding
is performed. The SYNC pin level changes to Low
before new status information is written. Please take
For a block diagram of the MAS 35xyH functionality
please see Fig. 2–2.
into
account
that
UIS_DYNRNG
(D0:13B4),
2.9.1. Power-Up Sequence and Default Operation
UIS_DYNRNG2 (D0:13B5), and UIS_KARAOKEFLAG
(D0:13B6) are valid for the audio block only; the SYNC
pin does not signalize their validity.
After applying the appropriate voltages to the three
supply pins and releasing the reset signal, the circuit
starts normal operation with S/PDIF (SPDI) as the
expected input and automatic standard recognition
(Dolby Digital, DTS, MPEG, PCM). No further action is
necessary for default operation or loop-through of
undecodable data streams.
Notes for MPEG:
After processing CRC, the SYNC pin level changes to
High, all information for a frame is valid, and decoding
is performed. The SYNC pin level changes to Low
before evaluating new header information.
A power-on reset can be issued at any time via pin
POR.
2.8. Power-Supply Regions
2.9.2. Input Switching
The MAS 35xyH has three power supply regions. The
VDD/VSS pin pair supplies all digital parts including
the DSP core. The XVDD/XVSS pin pair is connected
to the signal pin output buffers. The AVDD/AVSS sup-
ply is for the clock oscillator, PLL circuits, and system
clock synthesizer.
Both input interfaces, the S/PDIF or the serial input
interface, may carry any of the three data formats:
Dolby Digital (AC-3), MPEG Layer-2, or PCM. The
S/PDIF input may carry DTS data as well. The filling
status of the input buffer represents the data rate and
therefore controls the system clock. The input interface
can be selected in the UIC_IO control D0:13D0.
MAS 35xyH
2
PCM
8
Output
Buffers
2
2
Serial
Inputs
5
2
MPEG1L2
Decoder
2
2
2
2
Lt/Lo
Rt/Ro
L
SOD
2
Input
Buffer
2/0
SOD1
S/PDIF
Inputs
1+1,1/0, 3/0, 2/1,
3/1, 2/2, 3/2
R
AC-3
Decoder
LFE
5
LS
SOD2
SOD3
RS
2
2/0
C
1/0, 3/0, 2/1
3/1, 2/2, 3/2
DTS
SUB
Decoder
LFE
5
6
S/PDIF
Output
Noise
Gen.
Buffer Fill
Information
Processor Clock
Clock/
Crystal
div
Reference Clock
CLKO
Amp./
Oscill.
div
PLL
Synthesizer
18.432 MHz
2
Note: No. of Channels (e.g. 2):
Fig. 2–2: Functionality of the Audio Decoder IC Family MAS 35xyH
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PRELIMINARY DATA SHEET
MAS 35xyH
2.9.3. Standard Selection and Decoding
2.9.5. DTS (Digital Theater Systems) Data Stream
In the default mode, an automatic standard recognition
(auto-detection) selects the decoding algorithm
according to the data format at the S/PDIF input. The
detected standard is shown in the Global Operating
Status (D0:13BB). The standard selection for the I S
inputs can be selected manually in the I/O control
D0:13D0.
The digital input signal must be an S/PDIF source. In
DTS mode, the IC performs:
– Data input with clock synchronization
– S/PDIF channel selection (one of eight possible)
– Decoding of DTS bitstream
2
– Output mode control
If the input contains only a stereo pair (PCM, MPEG,
DD2/0, DTS2/0), it is automatically fed into the
ProLogic II decoder, which generates a 5-channel out-
put by default. The ProLogic II decoder may be deacti-
vated by means of UIC_DPL_STANDARD (D0:13EE).
– Bass Management according to Dolby specification
– Center and surround delays
The controller can select one of eight content channels
depending on availability (D0:13BC). The respective
service information is displayed in cell Bit Stream
Mode (D0:13A2).
2.9.4. Dolby Digital Data Stream
The digital input signal can either be an S/PDIF or an
I S source. In the Dolby Digital mode, the IC performs
the following tasks:
The bit stream elements contain all necessary informa-
tion required to correctly handle the audio. All ele-
ments important for controller actions are displayed in
the status memory (see Table 3–6 on page 27).
2
– Data input with clock synchronization
– S/PDIF channel selection (one of eight possible)
– Decoding of AC-3 bit stream elements
The MAS 35xyH decodes all DTS formats from 1 to
5.1 audio channels. Accordingly, one to six of the out-
put channels are used for the decoded audio. The out-
put mode is selected in D0:13D6. An additional down-
mix pair can either be Dolby-Surround-encoded (Lt,
Rt), or plain stereo (Lo, Ro; D0:13DE).
– Compression control for Dolby Digital signals
(D0:13D7...13D9)
– Output mode control
– Dolby Bass Management
– Center and surround delays
– Level adaption
2.9.6. MPEG Layer-2 Data Stream
In the MPEG mode a valid MPEG-1 Layer-2 data sig-
nal is expected. The steps for decoding are
If the signal source is the S/PDIF input, the controller
can select one of eight content channels depending on
availability (D0:13BC). The respective service informa-
tion is displayed in cell Bit Stream Mode (D0:13A2).
– Clock synchronization to data input
– S/PDIF channel selection (one of eight possible)
– Side information extraction
– Audio data decompression
– Optional de-emphasis
The bit stream elements contain all necessary informa-
tion required to correctly handle the audio. All ele-
ments important for controller actions are displayed in
the status memory (see Table 3–6 on page 27).
– Digital volume
The MAS 35xyH decodes all Dolby Digital formats
from 1 to 5.1 audio channels. Accordingly, one to six of
the output channels are used for the decoded audio.
The output mode is selected in D0:13D6. An additional
downmix pair can either be Dolby Surround encoded
(Lt, Rt) or plain stereo (Lo, Ro; D0:13DE).
If the signal source is the S/PDIF input, the controller
can select one of eight content channels depending on
availability (D0:13BC).
Micronas
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MAS 35xyH
PRELIMINARY DATA SHEET
2.9.7. PCM Audio Data
2.9.10.1. Major Operational Modes of Pro Logic II
Movie Mode
2
PCM data can be received via S/PDIF or I S. When
received via S/PDIF, the sampling frequency will be
detected automatically and mirrored in D0:13A0
(UIS_FS_CODE).
The Movie mode in Pro Logic II is very similar to that of
the original Pro Logic decoder. The main difference is
that it has stereo surround channels and no surround
filter, unlike Pro Logic which has a mono surround
channel and a 7 kHz surround filter. Movie mode is the
standard required for all A/V systems. When an auto-
sound unit has a video screen, it is also considered as
an A/V system. It can simply be called “Pro Logic II.”
2
If the PCM data are received via I S bus, the
MAS 35xyH expects a valid word strobe, and I/O con-
trol (D0:13D0) has to be set as described in Table 3–7.
In this case the de-emphasis must be activated by the
controller if necessary.
Music Mode
2.9.8. De-emphasis
The Music mode offers the users some flexibility to
control the results according to their own taste. Music
mode should not be used with a THX audio processing
mode. Music mode is recommended as the standard
mode for auto-sound music systems (without video)
and is optional for A/V systems. It is recommended
that Music mode be identified as the “Music” version of
Pro Logic II, to distinguish it from the Movie mode.
For the PCM and MPEG formats, a de-emphasis can
be applied to the signal (D0:13E0). This is necessary,
as the possibly following Dolby Pro Logic decoding
requires a flat audio frequency response. For MPEG-
encoded audio and PCM transmitted via S/PDIF, this
block is activated automatically. For proper operation
of PCM signals via I S, the controller has to determine
whether the PCM signals have been pre-emphasized
or not.
2
Virtual Mode
2.9.9. Dolby Pro Logic II Input Matrix
The Virtual mode is usually used when Pro Logic II is
connected to a virtual process for speaker use. How-
ever, there might be some virtualizers for which this
mode does not produce the intended result. For those
virtualizers, Movie mode may give the best surround
effect. Virtual mode is designed to be used with the vir-
tual process developed by Dolby Laboratories. The
Pro Logic II mode should only be called “Pro Logic II”
so that the name “Virtual” can be reserved to describe
the speaker virtualization process itself.
In front of the Pro Logic II processing a matrix is imple-
mented. Normal operation is “Stereo or A/B” for
2 channel inputs, but it is also possible to select only
Sound A or Sound B (Mono Sound on both channels).
This feature is used for bilingual MPEG transmissions.
The required setup must be done by the controller in
D0:13EE.
2.9.10. Dolby Pro Logic II Decoder
Note: To be Virtual-Dolby-Surround-compliant, the
correct Pro Logic II operational mode for the
built-in virtualizer is Movie Mode (not Virtual
Mode).
Every stereo source is automatically routed through
the Dolby Pro Logic II decoder. (DD2/0, DTS2/0,
MPEG, PCM, I2S from MSP44x0G).
The Pro Logic II decoder decodes the stereo signal
into a five channel surround sound signal. Six pre-
defined operational coefficient sets and one customiz-
able set allow different decoder modes for different
sound material (Movie, Music, Virtual compatible, Pro
Logic Emulation, Matrix, Custom and Bypass Mode),
as Dolby proposes in its “Licensee Information Man-
ual: Dolby Pro Logic II, Section 2.2”. A variety of
options and the Dolby Bass Management are used to
adopt the decoder to the used speaker configuration.
Pro Logic Emulation Mode
The Pro Logic Emulation mode offers users the same
robust surround processing as the original Pro Logic,
for those cases where the source content is not of opti-
mum quality, or if there is a desire to hear the program
more “as it used to be.” When this mode is used, it is
called Pro Logic, as before. There is no “Pro Logic I”
mode. The Pro Logic emulation mode is optional.
Dolby does not require PLII products to use the origi-
nal Pro Logic decoding algorithm. However, if the DSP
contains the original Pro Logic code, and if the product
maker would like to use it, this is quite acceptable and
even encouraged. A product must not offer both origi-
nal Pro Logic and the Pro Logic emulation mode.
The required setup must be done by the controller in
D0:13ED and D0:13EE.
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PRELIMINARY DATA SHEET
MAS 35xyH
Matrix Mode
Panorama Mode
The Matrix mode is the same as the Music mode
except that the directional enhancement logic is turned
off. It may be used to enhance mono signals by mak-
ing them seem “larger.” The Matrix mode may also find
use in auto systems, where the fluctuations from poor
FM stereo reception can otherwise cause disturbing
surround signals from a logic decoder. The ultimate
“cure” for poor FM stereo reception may be simply to
force the audio to mono.
In the Music Mode, this control extends the front stereo
image to include the surround speakers for an exciting
“wraparound” effect with side-wall imaging. It is partic-
ularly effective for recordings which have strong left or
right channel elements in the mix, as these are
detected and accentuated by the Panorama process.
According to the LIM for Pro Logic II, Panorama Mode
must only be switched on in Music Mode.
2.9.11. Channel Expander
Custom Mode
The outputs of the PCM/MPEG decoders consist of
two channels each; the output of the Dolby Digital/
DTS decoder may have any number between one and
six (5.1) channels. To unify the output format between
different modes, the audio is always mapped to six
channels.
All settings are user defined
Off (Bypass Mode)
Pro Logic Decoding is switched off.
Lt to L; Rt to R; Sl,Sr and C muted.
2.9.12. Noise Generator
2.9.10.2. Additional Operational Modes
Surround Filter
A bandpass-shaped or white noise signal can be
routed to any combination of the six main output chan-
nels. The required channel sequence must be done by
the controller in D0:13D1. No noise signal is available
at the Extra Stereo Output.
There are two surround filters available in Pro Logic II.
One is the 7 kHz lowpass filter for use with Pro Logic
emulation mode; the other is the shelf filter for use with
Music and Matrix modes. This latter filter is a mild
shelving filter that improves the naturalness of the
sound in Music mode.
2.9.13. Virtual Dolby Digital
In the MAS 35xyH, Spatializer N-2-2 ULTRA is imple-
mented as a Dolby Digital approved virtualizer. It takes
advantage of the most advanced digital sound pro-
cessing techniques available and is designed to pro-
cess DTS, Dolby Digital and Pro Logic II sound tracks.
Using only two (L, R) or three (L, C, R) loudspeakers,
N-2-2 ULTRA produces a realistic surround sound
impression in a large listening area.
Surround Coherence
In the Movie mode, it is important that the surround
speakers be in phase, so that movie sound effects
panned to or across the surrounds will have optimal
localization and imaging. This is achieved with the sur-
round coherence function (Right Surround Channel
Polarity can be inverted). Stereo music content, how-
ever, does not contain panned surround effects, so it
benefits from a more spacious presentation of the
ambient sounds by turning off the surround coherence
function.
In MAS 35xyH, the “TV” version (N-2-2 ULTRA TV) of
N-2-2 ULTRA is available. It is an optimization for play-
back over television loudspeakers. N-2-2 ULTRA TV
takes advantage of the pre-determined listening con-
figuration inherent to TV sets and reduces the control
effort (number of parameters) while maintaining the
highest quality virtual surround sound effect.
Auto-Balance
All MAS 35xyH are shipped without Spatializer N-2-2
ULTRA except otherwise ordered. When an N-2-2
ULTRA version of MAS 35xyH is ordered, it carries a
special marking on the chip for identification.
This operates in the same way as in all previous Pro
Logic decoders to ensure that movie sound tracks
decode optimally.
The N-2-2 ULTRA functionality must be enabled by
writing a “license key” into MAS 35xyH. For informa-
tion on how to obtain this license key from Micronas,
please contact your Micronas sales representative. A
license from Desper Products Inc. is required before a
MAS 35xyH with Spatializer N-2-2 ULTRA can be pur-
chased.
Additional signal processing may be included if Pro
Logic II is allowed to operate fully and without modifi-
cation in name or function. In other words, any addi-
tional signal processing must include a bypass mode
to defeat the processing. When any additional process
works in conjunction with Pro Logic II, it must clearly
be indicated that both processes are working together.
Micronas
Dec. 4, 2003; 6251-598-2PD
15
MAS 35xyH
PRELIMINARY DATA SHEET
2.9.14.3. Bass Management
Note: To be Virtual-Dolby-Surround-compliant, the
correct Pro Logic II operational mode for the
built-in virtualizer is Movie Mode (not Virtual
Mode).
Generally, not all of the five loudspeakers in a Dolby
Digital system can reproduce the full audio bandwidth.
Bass Management allows redirecting low frequencies
to loudspeakers which are capable of reproducing this
frequency range. The MAS 35xyH supports the follow-
ing Bass Management modes:
2.9.14. Post Processing/Bass Management
Bass Management mode 0 (D0:13DA = 8)
The implemented post-processing functions can be
applied to the following audio formats. They are
Attenuation of −15 dB in the SUB channel should be
compensated by a 15 dB gain in the D/A-converter.
– Downmixing to Lo/Ro or surround sound encoding
to Lt/Rt (D0:13DE) for Dolby Digital/DTS multichan-
nel signals
C
C
– Mixing and digital filtering for the different Output
and Bass configurations according to the Dolby Dig-
ital Licensee Information Manual and one additional
Bass Management Configuration called “Bass to
Center” (D0:13D5, D0:13D6, D0:13DA).
R
R
LS
RS
LFE
LS
RS
SUB
−15 dB × 5
−5 dB
– Digital volume control (D0:13E1...13E8) for all audio
formats
+
– Appropriate delay lines for center and surround
channels (D0:13D2...13D4) for Dolby Digital/DTS
multichannel and Pro Logic II processed stereo sig-
nals
Fig. 2–3: Bass Management configuration 0
Bass Management mode 1 (D0:13DA = 9)
Attenuation of −15 dB in the SUB channel should be
compensated by a 15 dB gain in the D/A-converter.
2.9.14.1. Extra Stereo Output
For headphone and VCR recordings, a downmixed
output is provided simultaneously to 5.1 multichannel
output. The downmix can be switched from Lt/Rt (sur-
round-encoded, default) to Lo/Ro (headphone
encoded).
L
L
C
C
R
R
LS
RS
LFE
LS
RS
SUB
Both, the 6-channel output and the Extra Stereo Out-
put, are routed to the serial data output interface.
−15 dB × 5
−5 dB
+
Note: In order to prevent clipping due to the downmix-
ing in the Custom and Line Modes, the High-
Level Cut Compression Scale Factor (D0:13D8)
Fig. 2–4: Bass Management configuration 1
Bass Management mode 2 (D0:13DA = A
must always be left at 7FFFF
when the Extra
hex
)
hex
Stereo Output is used in conjunction with non-
downmixed channels (D0:13D6).
Level adjustment is implemented with −12 db.
−12 dB
+
L
L
−1.5 dB
2.9.14.2. Digital Volume
Level
Adj
C
R
C
−12 dB
−1.5 dB
The digital volume control provided is mainly intended
for balancing purposes and initially set to 0 dB. Volume
control, output configuration, and delays should be set
by the controller according to the actual listening situa-
tion.
+
R
Level
Adj
LS
RS
LFE
LS
RS
SUB
Level
Adj
−15 dB × 3
−5 dB
+
Fig. 2–5: Implementation of configuration 2
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Micronas
PRELIMINARY DATA SHEET
MAS 35xyH
Bass Management mode 3 (D0:13DA = B
)
Bass Management mode 6 (D0:13DA = E
)
hex
hex
L
L
+
L
L
C
C
C
C
R
R
+
R
R
LS
LS
RS
SUB
LS
RS
LS
RS
RS
−15 dB × 3
−4.5 dB × 3
+
LFE
+
−5 dB
−5 dB
+
LFE
SUB
Fig. 2–6: Alternative implementation of configuration 2
Fig. 2–9: Simplified Bass Management for
Multichannel Source Products (Ι)
Bass Management mode 4 (D0:13DA = C
)
hex
Bass Management mode 7 (D0:13DA = F
)
hex
+
L
L
C
C
L
L
−4.5 dB
C
C
+
R
R
R
R
+
LS
RS
LFE
LS
LS
RS
LS
RS
+
RS
SUB
−4,5 dB × 3
+
−10.5 dB
−5 dB
+
LFE
SUB
Fig. 2–7: Implementation of configuration 3 with
subwoofer
Fig. 2–10: Simplified Bass Management for
Multichannel Source Products (ΙΙ)
Bass Management mode 5 (D0:13DA = D
)
hex
Bass Management mode Bass to Center
The analog part of SUB should add a +10 db gain
(D0:13DA = 18
)
hex
+
L
L
−15 dB
L
L
C
C
−15 dB
+
−4.5 dB
C
C
−15 dB
+
R
R
R
R
−15 dB
+
LS
RS
LFE
LS
LS
LS
−15 dB
+
RS
SUB
RS
RS
−5 dB
SUB
LFE
+
Fig. 2–8: Implementation of configuration 3
Fig. 2–11: Bass to Center Mode (B2C) for TV Sets
with large Center and small L / R / Ls / Rs Speakers.
Micronas
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17
MAS 35xyH
PRELIMINARY DATA SHEET
2.9.15. Output Format Selection
2.10. System Interaction
2
The output is an I S bus format with either eight audio
2.10.1. Minimum Required Interconnections
channels on one line (default), or two audio channels
on each of four lines (D0:13D0). If the 4x2 configura-
tion is selected, the clock and word strobe lines SOC
and SOI apply to all four data lines SOD...SOD3. Clock
and word strobe signals can be configured to different
standards (polarity, delay). The data word length is
always 32 bits.
The MAS 35xyH requires the following connections for
normal operation:
– Power supply with adequate blocking capacitors
(VDD, VSS, AVDD, AVSS, XVDD, XVSS)
– Crystal with capacitors or clock input (XTI, XTO)
2
– I C bus and reset line (I2CC, I2CD) and reset line
In the 1x8 format, the output data are in the following
order:
L, LS, C, Lt/Lo, R, RS, Sub, Rt/Ro.
(POR) for controlling
2
– S/PDIF input (SPDI/SPDI2, SPREF) or serial/I S
input (SID, SIC, SII or SID*, SIC*, SII*). In the stan-
2
dard Micronas solution, the I S signal comes from
the MSP 44x0G
2.9.16. S/PDIF Loop-Through
2
– I S output (SOD, SOC, SOI). In the standard config-
By default, an undecodable signal is looped through.
This means that the signal at S/PDIF input is routed to
S/PDIF output without processing – regardless of bit 1
uration, this signal is fed to the DPL 4519G.
Please refer to Fig. 5–1 on page 69 or to the applica-
tion kit for details.
in register 2E
.
hex
This automatism can be disabled by setting bit 12 in
register 2E to “1”. Now, the controller is to choose
via bit 1, whether a PCM audio signal is output (in case
of an undecodable signal the output is muted) or
whether the input data is looped through.
hex
2.10.2. Required Special Modes in the System
The MAS 35xyH interfaces require no configuration.
2
The I S outputs and inputs of the DPL 4519G and the
MSP 44x0G, however, must be configured to send/
accept the 8-channel multiplexed digital PCM data
stream.
2.9.17. Output Sampling Rate
The internally generated system clock is derived from
the filling status of the input data buffer by a PLL. This
clock is synchronous to the original sampling rate and
is used throughout the complete data processing.
Except in the ambiguous case of PCM data at the
serial audio input where the original sampling rate
must be defined (D0:13DB), no controller interaction is
needed for clock operation.
The DPL 4519G may generate up to seven analog sig-
nals (three pairs plus subwoofer). Further audio sig-
nals can be forwarded to the MSP 44x0G for D/A con-
version.
Dolby Pro Logic encoded audio originating from the
MSP 44x0G (TV sound) must be routed to the
MAS 35xyH for Pro Logic II decoding.
The output sampling rate is 32 kHz, 44.1 kHz, or
48 kHz, depending on the source.
Since in the Micronas Dolby Digital TV sound solution
all further signal processing is on a rate of 48 kHz, the
input stage of the DPL 4519G performs the sample
rate conversion if necessary.
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PRELIMINARY DATA SHEET
MAS 35xyH
2.10.3. Minimum System Set-Up
Output (numbers 7 to 10 mean first to fourth pair)
– Select one input pair as source for Aux Output
(numbers 7 to 10 mean first to fourth pair)
2
The following I C command sequence is necessary for
the DPL 4519G:
– Set volume control for Loudspeaker Output
– Set volume control for Aux Output
2
– I C-controlled reset
2
– Write MODUS Register (set I S input to slave
mode)
If there is a multistandard sound processor in the sys-
tem, similar set-up commands are required. For further
details, please refer to the DPL 4519G or the
MSP 44x0G data sheets.
– Write I2S_CONFIG (multisample mode, 32 bits,
clock to 8*32 bits)
– Set I2S3 Resorting Matrix to “left/right eight
MAS 35xyH”. The signal pairs are now in the follow-
ing order: Lt/Rt, L/R, SL/SR, C/Sub
2
If both devices are used on the same I C bus, the
device addresses must be set to different values by
hardware means.
2
2
– Select first I S 3-input pair as source for I S Output
(because of 8*32 bit mode all 4*2 channels will be
looped through to the MSP 44x0G) and set to trans-
parent stereo
The D/A conversion of audio signals may be freely
appointed between the DPL 4519G and the
MSP 44x0G. For an example, please see Table 2–3.
– Select one input pair as source for Loudspeaker
2
Table 2–2: Output configuration matrix. All registers are at I C subaddress 12
of the respective device. Note that
hex
only one code per register applies.
Device
DPL 4519G
MSP 44x0G
Register →
Signal Pair ↓ 00 08hex
Loudsp.
Aux
00 09hex
SCART1
00 0Ahex
Loudsp.
00 08hex
Aux
SCART1
00 0Ahex
SCART2
00 41hex
00 09hex
07 20hex
08 20hex
09 20hex
0A 20hex
Lt/Rt (Lo/Ro) 07 20hex
07 20hex
08 20hex
09 20hex
07 20hex
08 20hex
09 20hex
07 20hex
08 20hex
09 20hex
0A 20hex
07 20hex
08 20hex
09 20hex
07 20hex
08 20hex
09 20hex
L/R
08 20hex
09 20hex
0A 20hex
SL/SR
C/Sub
1)
1)
1)
1)
1)
1)
1)
0A 20hex
0A 20hex
0A 20hex
0A 20hex
1) Use 0A 20hex for C/Sub output, 0A 00hex for Center signal on both outputs, 0A 10hex for Sub signal on both outputs
Table 2–3: Example: In the DPL 4519G use both loudspeaker output channels for center, the auxiliary output for
surround, the SCART1 output for Lt/Rt. In the MSP 44x0G use the loudspeaker output for L/R, both auxiliary output
channels for Sub and the SCART1 output for an additional Lt/Rt-signal.
Device
DPL 4519G
MSP 44x0G
SCART1
Register →
Signal Pair ↓ 00 08hex
Loudsp.
Aux
00 09hex
SCART1
00 0Aahex
Loudsp.
00 08hex
Aux
00 09hex
SCART2
00 41hex
00 0Ahex
Lt/Rt (Lo/Ro)
L/R
07 20hex
07 20hex
08 20hex
SL/SR
09 20hex
C/Sub
0A 00hex
0A 10hex
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MAS 35xyH
PRELIMINARY DATA SHEET
3. Control Interface
3.2.3. Conventions for the Command Description
3.1. Start-Up Sequence
The description of the various controller commands
uses the following formalism:
After power-up and a reset (see Section 3.3. on
page 21), the IC is in its default state (see Table 3–7
on page 38). The controller has to initialize all memory
cells for which a non-default setting is necessary.
– Abbreviations used in the following descriptions:
a
d
n
o
r
address
data value
count value
offset value
register number
don’t care
2
3.2. I C Interface Access
x
3.2.1. General
– A data value is split into 4-bit nibbles which are
numbered zero-bound.
Control communication with the MAS 35xyH is done
via an I C slave interface. The device addresses are
– Data values in nibbles are always shown in hexa-
decimal notation.
2
3A
(write) and 3B
(read) as shown in Table 3–1.
hex
hex
– A hexadecimal 20-bit number d is written, e.g. as
2
I C clock synchronization is used to slow down the
interface if required.
d = 17C63 , its five nibbles are
hex
d0 = 3 , d1 = 6 , d2 = C , d3 = 7 , and
hex
hex
hex
hex
hex
d4 = 1
.
2
– Variables used in the following descriptions:
Table 3–1: I C device address
dev_write
dev_read
data_write 68
data_read 69
3A
3B
device write
device read
data register write
data register read
control register write
hex
hex
hex
hex
A7
0
A6
0
A5
1
A4
1
A3
1
A2
0
A1
1
W/R
0/1
control
6A
hex
– Bus signals
S
P
A
N
Start
Stop
2
3.2.2. I C Registers and Subaddresses
ACK = Acknowledge
NAK = Not acknowledge
The interface uses one level of subaddresses. The
MAS 35xyH interface has 3 subaddresses allocated
for the corresponding I C registers.
2
W Wait = I C clock line is held low while the
MAS 35xyH is processing the current
2
2
I C command
The address 6A
is used for basic control, i.e. reset
hex
and task select. The other addresses are used for data
transfer from/to the MAS 35xyH.
– Symbols in the telegram examples
<
>
dd
xx
Start Condition
Stop Condition
data byte
2
The I C control and data registers of the MAS 35xyH
are 16 bits wide, the MSB is denoted as bit [15]. Trans-
ignore
2
missions via I C bus have to take place in 16-bit words
All telegram numbers are hexadecimal, data origi-
nating from the MAS 35xyH are shown in gray.
Example:
(two byte transfers, MSB sent first); thus for each reg-
ister access two 8-bit data words must be sent or
2
received via I C bus.
<3A 68 dd dd>
write data to DSP
<3A 69 <3B dd dd> read data from DSP
2
Table 3–2: Subaddresses
Fig. 3–1 shows I C bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
2
Sub-
I C-
Function
address with the read command (3B ). Fields with
address Register
hex
signals/data originating from the MAS 35xyH are
marked by a gray background. Note that in some
cases, the data reading process must be concluded by
a NAK condition.
68
data
Controller writes to
MAS 35xyH data register
hex
hex
69
data
Controller reads from
MAS 35xyH data register
6A
control
Controller writes to
hex
MAS 35xyH control register
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PRELIMINARY DATA SHEET
Example: I2C write access
MAS 35xyH
S
dev_write (3Ahex
2
)
W
A
data_write (68hex
)
A
A
high data word
A
low data word
A
P
Example: I C read access
S
dev_write (3Ahex
)
W
A
data_read (69hex
)
S
dev_read (3Bhex
)
W
A
high data word
low data word
A
N
P
W = Wait
A = 0 - Acknowledge (Ack)
N = 1 - Not Acknowledge (NAK)
S = Start
P = Stop
SDA
SCL
1
0
P
S
2
Fig. 3–1: I C bus protocol for the MAS 35xyH (MSB first; data must be stable while clock is high)
2
3.2.4. The Internal Fixed Point Number Format
3.4. I C Data Register (Codes 68
and 69 ) and
hex hex
the MAS 35xyH DSP-Command Syntax
In the following sections, two number representations
are used: The fixed point notation ‘v’ and the 2’s com-
plement number notation ‘r’.
The DSP core of the MAS 35xyH has two RAM-banks
denoted D0 and D1. The word size is 20 bits. All RAM-
addresses can be accessed in a 20-bit or a 16-bit
2
The conversion between the two forms of notation is
easily done (see the following equations).
mode via I C bus. For fast access of internal DSP-
states, the processor core also has an address space
of 256 data registers. All register and RAM addresses
are given in hexadecimal notation.
r = v*524288.0+0.5; (−1.0 ≤ v < 1.0)
(EQ 1)
(EQ 2)
v = r/524288.0; (−524288 < r < 524287)
The control of the DSP in the MAS 35xyH is done via
2
the I C data register by using a special command syn-
2
3.3. I C Control Register (Code 6A
)
hex
tax. These commands allow the controller to access
the DSP registers and RAM cells and thus monitor
internal states, set the parameters for the DSP firm-
ware, control the hardware, and even provide a down-
load of alternative software modules.
S
dev_write
W
A
control
A
d3,d2
A
d1,d0
A
P
2
The I C control register is a write-only register. Its
main purpose is the software reset of the MAS 35xyH.
The software reset is done by writing a 16-bit word to
the MAS 35xyH with bit 8 set. The four least significant
bits are reserved for task selection. In standard Dolby
Digital/MPEG-decoding, these bits must always be set
to 0.
The DSP commands consist of a “Code” which is sent
2
to I C data register together with additional parame-
ters.
S
dev_write
W
A
data_write
A
Code,...
A
...,...
2
A
...
The MAS 35xyH firmware scans the I C interface peri-
odically and checks for pending or new commands.
The commands are then executed by the DSP during
its normal operation without any loss or interruption of
the incoming data or outgoing audio data stream.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms. However, the typical response
time is less than 0.5 ms. Table 3–4 on page 22 shows
the basic controller commands that are available by
the MAS 35xyH.
Table 3–3: Control register bit assignment1)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
x
x
x
x
x
x
x
R
0
0
0
0
T3 T2 T1 T0
1) x = don’t care, R = reset, T3...T0 0 task selection
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MAS 35xyH
PRELIMINARY DATA SHEET
Table 3–4: Basic controller command codes
Code
(hex)
Command
Function
A
B
C
D
E
F
Read from register
Write to register
Controller reads an internal register of the MAS 35xyH.
Controller writes an internal register of the MAS 35xyH.
Controller reads a block of the DSP memory.
Controller reads a block of the DSP memory.
Controller writes a block of the DSP memory.
Controller writes a block of the DSP memory.
Read D0 memory
Read D1 memory
Write D0 memory
Write D1 memory
Table 3–4 gives an overview of the different com-
mands which the DSP-core may receive. The “Code”
is always the first data nibble transmitted after the
“data_write” byte. A second auxiliary code nibble is
used for the short memory access commands.
2
Because of the 16-bit width of the I C-data register, all
actions always transmit telegrams with multiples of 16
data bits.
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MAS 35xyH
3.4.1. Read Register (Code A
)
3.4.3. Read Memory (Codes C
and D
)
hex
hex
hex
The MAS 35xyH has 2 memory areas called D0 and
D1. Both areas have different read and write com-
mands. The memory areas D0 can be read by using
1) send command
S
dev_write
W
A
data_write
data_read
A
A,r1
A
r0,0
W
W
A
N
P
P
the codes C
.
hex
2) get register value
S
dev_write
x,x
W
A
A
A
A
S
dev_read
W
A
1) send command (e.g. Read D0)
x,d4
W
d3,d2
A
d1,d0
S
dev_write
W
A
data_write
A
C,0
A
A
A
0,0
W
W
W
A
A
A
The MAS 35xyH has an address space of 256 DSP-
registers. Some of the registers (r = r1,r0 in the figure
above) are direct control inputs for various hardware
blocks, others control the internal program flow. In
Section 3.5. on page 25, the registers of interest with
respect to the Dolby Digital/MPEG-decoding firmware
are described in detail. In contrast to memory cells,
registers cannot be accessed as a block but must
always be addressed individually.
n3,n2
a3,a2
n1,n0
a1,a0
P
2) get memory value
S
dev_write
x,x
W
A
A
data_read
A
A
S
dev_read
W
A
x,d4
W
d3,d2
A
d1,d0
W
W
A
N
....repeat for n data values....
x,x
A
x,d4
W
A
d3,d2
A
d1,d0
P
Example:
Read the content of register (2E ):
The Read D0 Memory command gives the controller
access to all 20 bits of D0-memory cells of the
MAS 35xyH. The telegram to read three words starting
at location D0:100 is
hex
<3A 68 A2 E0>
<3A 69 <3B xx xd dd dd>
define register
and read
<3A 68 C0 00 00 03 01 00>
<3A 69 <3B xx xd dd dd
xx xd dd dd xx xd dd dd>
3.4.2. Write Register (Code B
)
hex
The Read D1 Memory command (D )is provided to
hex
get information from D1 memory cells of the
MAS 35xyH.
S
dev_write
W
A
data_write
A
B,r1
A
A
r0,d4
d1,d0
W
W
A
A
d3,d2
P
The
controller
writes
the
20-bit
value
3.4.4. Short Read Memory (Codes C4
and D4
)
hex
hex
(d = d4,d3,d2,d1,d0) into the MAS 35xyH register
(r = r1,r0). A list of registers is given in Section 3.5. on
page 25
Because most cells in the Dolby Digital user interface
are only 16 bits wide, it is faster and more convenient
to access the memory locations with a special 16-bit
mode for reading:
Example: Disable automatic S/PDIF loop-through for
DTS by writing the value 1000
into the register with
hex
the number 2E
:
hex
1) send command (e.g. Short Read D0)
<3A 68 B2 E0 10 00>
S
dev_write
W
A
data_write
A
C,4
A
A
A
0,0
W
W
W
A
A
A
n3,n2
a3,a2
n1,n0
a1,a0
P
2) get memory value
S
dev_write
W
A
data_read
A
S
dev_read
W
A
d3,d2
A
d1,d0
W
W
A
N
....repeat for n data values....
d3,d2
A
d1,d0
P
This command is similar to the normal 20-bit read
command and uses the same command codes C
hex
and D
for D0 and D1-memory, respectively, how-
hex
ever, it is followed by a 4
rather than a 0
.
hex
hex
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MAS 35xyH
PRELIMINARY DATA SHEET
The Short Read D1 Memory command works similarly
to the Read D1 Memory command but with the code
3.4.6. Short Write Memory (Codes E4
and F4
)
hex
hex
D
followed by a 4
.
hex
hex
e.g. Short Write D0
2
Example: Read 16 bits of D1:123 has the following I C
protocol:
S
dev_write
W
A
data_write
A
A
A
A
E,4
A
A
A
A
0,0
W
A
A
A
A
n3,n2
a3,a2
d3,d2
n1,n0
a1,a0
d1,d0
W
W
W
<3A 68 D4 00
00 01
read 16 bits from D1
one word to be read
start address
01 23>
....repeat for n data values....
<3A 69 <3B dd dd>
start reading
A
d3,d2
A
d1,d0
W
A
P
3.4.5. Write Memory (Codes E
and F
)
hex
hex
For faster access, only the lower 16 bits of each mem-
ory cell are accessed. The four MSBs of the cell are
The memory areas D0 and D1 can be written by using
cleared. The command uses the same codes E
and
hex
the codes E
and F , respectively.
hex
hex
F
for D0/D1 as for the 20-bit command but followed
hex
by a 4 rather than a 0.
e.g. Write D0
S
dev_write
W
A
data_write
A
E,0
n3,n2
a3,a2
0,0
A
A
A
A
A
0,0
W
W
W
W
W
A
A
A
A
A
3.4.7. Default Read
n1,n0
a1,a0
0,d4
The Default Read command is the fastest way to get
information from the MAS 35xyH. Executing the
Default Read in a polling loop can be used to detect a
special state during decoding.
d3,d2
d1,d0
....repeat for n data values....
0,0
A
A
0,d4
W
W
A
A
S
DW
W
A
data_read
A
S
dev_read
d3,d2
W
A
A
d3,d2
d1,d0
P
d1,d0
W
N
P
With the Write D0/D1 Memory command n 20-bit
memory cells in D0/D1 can be initialized with new
data.
The Default Read command immediately returns the
lower 16 bit content of a specific RAM location as
defined by the pointer D0:FFB. The pointer must be
loaded before the first Default Read action occurs. If
the MSB of the pointer is set, it points to a memory
location in D1 rather than to one in D0.
Example: Write 80234
I C protocol:
to D0:FFB has the following
hex
2
<3A 68 E0 00
00 01
write D0 memory
1 word to write
start address FFB
Example: For watching D1:123, the pointer D0:FFB
0F Fb
hex
must be loaded with 8123
:
hex
00 08
value = 80234
hex
<3A 68 E0 00
00 01
write to D0 memory
one word to write
start address FFB
02 34>
0F Fb
00 08
01 23>
value = 8 ...
hex
...0123
hex
Now the Default Read commands can be issued as
often as desired:
<3A 69 <3B
dd dd>
Default Read command
16 bit content of the
address as defined by the
pointer
<3A 69 <3B dd dd> ... and do it again
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PRELIMINARY DATA SHEET
MAS 35xyH
3.5. Registers
Note: Registers not given in this table must not be
written.
In Table 3–5, the internal registers that are useful for
controlling the MAS 35xyH are listed. They are acces-
sible by Read/Write Register I C commands (see
2
Section 3.4.1. and Section 3.4.2. on page 23).
Table 3–5: Command Register Table
Register
Address
(hex)
R/W Function
Default
(hex)
Name
2E
Loop-through and Sync Pin Control
S/PDIF-Input 00000
Output_Conf
W
bit[12]
0: automatic active loop-through if
the input format at S/PDIF_in cannot be
determined (default)
1: bit[1] controls loop-through
-
bit[11:2]
bit[1]
reserved: do not change!
W
0: normal operation
1: connect SPDI_in to SPDIF OUT
(loop-through)
R
bit[0]
sync bit
in case of AC-3 and MPEG signals, this bit
will be automatically detected and set by
internal software, it will not be set by PCM
signals.
4B
48
W
R
PIO Configuration
00000
PIO_Config
Configuration of pins must be zero.
PIO Data Input
PIO_Data_In
The input level of every PI pin in the input mode can be
read out of this register; the bit number corresponds to
the PI number.
bit[n]
bit[n]
0: input is low
1: input is high
49
W
PIO Data Output
PIO_Data_Out
The output level of every PI pin in the output mode can
be defined by this register; the bit number corresponds to
the PI number.
bit[n]
bit[n]
0: output is low
1: output is high
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MAS 35xyH
PRELIMINARY DATA SHEET
Table 3–5: Command Register Table, continued
Register
Address
(hex)
R/W Function
Default
(hex)
Name
CC
R/W PIO Direction
00000
PIO_Direction
Every bit switches the PI pin with the corresponding num-
ber from input to output.
bit[n]
0: input mode
bit[n]
1: output mode
bit[14:16]
must be zero if PI14, PI15, and PI16 are
used as alternative inputs SID*, SII*, and
SIC*.
56
R
Incoming S/PDIF Channel Status Bits
S/PDIF-Input
SPI0CS
bit[19:0] mirrors first 20 channel status bits
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MAS 35xyH
3.6. Special Memory Locations and User Interface
3.6.1. Status Interface for Decoding
Operation of the DSP and the interfaces can be
observed and controlled via the memory locations of
the user interface. These memory cells are located at
the high end of the D0-RAM.
The following table contains the memory locations of
the firmware status information. Addresses are hexa-
decimal, memory cell content is binary when written
without indicator and hexadecimal when written with a
hex-suffix.
Status cells are written by the DSP and read by the
controller, configuration cells are written by the control-
ler and read by the DSP, hybrid cells can be written
and read by either side.
Note: Memory addresses not given in this table
must not be accessed.
Table 3–6: Status memory cells
Memory
Address
(hex)
Function
Mode
Name
D0:13A0
Sample Rate of Input Bitstream
(Table 5.1 of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_FSCOD
MPEG
PCM
bit[1:0]
00
01
10
11
48 kHz
44.1 kHz
32 kHz
not detected (default)
D0:13A1
Bit Stream Identification (bsid)
Dolby Digital
UIS_BSID
(Section 5.4.2.1 of ATSC Spec. A/52)
bit[4:0]
00 ...1f
current bsid value
hex
hex
Bit streams that have a bsid higher than the decoder’s version number may be
incompatible. In this case, the decoding is inhibited. The version number for
the implemented firmware is 8.
Bit Stream Identification (bsid)
bit[3:0] ...f current bsid value
DTS
0
hex hex
Bit streams that have a bsid higher than the decoder's version number may be
incompatible. In this case, the decoding is inhibited. The version number for
the implemented firmware is 7. Revision 0 - 6 will be compatible with this
specification. Revision 8 -15 will be incompatible with this specification.
Note: see description of D0:13d0 bit 17
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MAS 35xyH
PRELIMINARY DATA SHEET
Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13A2
Bit Stream Mode (bsmod)
Dolby Digital
UIS_BSMOD
(Table 5.2 of ATSC Spec. A/52)
bit[2:0]
000
001
010
011
100
101
110
111
111
main audio service: complete main (CM)
main audio service: music and effects (ME)
associated service: visually impaired (VI)
associated service: hearing impaired (HI)
associated service: dialogue (D)
associated service: commentary (C)
associated service: emergency (E)
acmod = 001, associated service: voice over (VO)
acmod = 010-111, main audio service: karaoke
This information is valid after selecting (D0:13D0) an available (D0:13BC)
channel (data stream) from the S/PDIF input. Prior to this, the bsmod can be
directly derived from the Pc-preambles of the S/PDIF-data (D0:13BD...13C4).
D0:13A3
Audio Coding Mode (acmod)
(Table 5.3 of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_ACMOD
DD:
DTS:
bsmod != ’111’ bsmod = ’111’ (Karaoke)
this column
bit[2:0]
000
001
010
011
100
101
110
111
1+1 Ch1, Ch2
1/0
2/0 L, R
3/0 L, C, R
2/1 L, R, S
3/1 L, C, R, S
2/2 L, R, SL, SR
Voice Over (VO)
C
L, R
L, M, R
L, R, V1
L, M, R, V1
L, R, V1, V2
3/2 L, C, R, SL, SR L, M, R, V1, V2
For user information: indicates the applied main channel.
D0:13A4
Center Mix Level (cmixlev)
Dolby Digital
UIS_CLEV
(Table 5.4 of ATSC Spec. A/52)
bit[1:0]
00
01
10
11
0.707 (−3.0 dB)
0.595 (−4.5 dB)
0.500 (−6.0 dB)
reserved (−6.0 dB),
nominal downmix level of center with
respect to left and right channels
Used in the internal algorithm.
D0:13A5
Surround Mix Level (surmixlev)
Dolby Digital
UIS_SLEV
(Table 5.5 of ATSC Spec. A/52)
bit[1:0]
00
01
10
11
0.707 (−3.0 dB)
0.500 (−6.0 dB)
0
reserved (−6.0 dB),
nominal downmix level of surround channels
Used in the internal algorithm.
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MAS 35xyH
Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13A6
Dolby Surround Mode (dsurmod)
(Table 5.6 of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_DSURMOD
bit[1:0]
00
01
10
11
not indicated
not Dolby Surround encoded
Dolby Surround encoded
reserved (not indicated)
As soon as the audio is Dolby Surround encoded, the controller must activate
the Dolby Pro Logic decoder (e.g. in the DPL 4519G) without any user interac-
tion.
D0:13A7
Low Frequency Effects Channel (lfeon)
(Section 5.4.2.7 of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_LFEON
bit[0]
0
1
LFE off
LFE on
The user may want to choose a different output configuration depending on
the availability of the LFE.
D0:13A8
D0:13AA
Dialogue Nomalization (dialnorm)
(Section 5.4.2.8 of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_DIALNORM
UIS_LANGCOD
bit[4:0]
00
reserved
hex
01 ...
−1 dBFS...
hex
1F
−31dBFS average dialog level
hex
Used in the internal algorithm.
Language Code (langcode, langcod)
Dolby Digital
(Sections 5.4.2.11 and 5.4.2.12 of ATSC Spec. A/52)
bit[15:0]
bit[7:0]
FFFF
langcode = 0 (langcod nonexistent in stream)
langcod
hex
The controller may check all S/PDIF data streams (channels) for the desired
language.
D0:13AB
Mixing Level and Room Type
(audprodie, mixlevel, roomtyp)
Dolby Digital
UIS_MIXLEVEL_
ROOMTYP
(Sections 5.4.2.13, 5.4.2.14 and 5.4.2.15 of ATSC Spec. A/52)
bit[15:0]
FFFF
audprodie = 0 (mixlevel, roomtyp nonexistent in
hex
data stream)
bit[6:2]
bit[1:0]
mixlevel
roomtyp
For user information.
D0:13AC
Dialogue Nomalization 2 for Dual Mono Mode 1+1
(dialnorm2)
Dolby Digital
UIS_DIALNORM2
(Section 5.4.2.16 of ATSC Spec. A/52)
bit[4:0]
01 ...1F
average dialog level −1dB...−31dB
below 100% digital
reserved
hex
hex
00
hex
Used in the internal algorithm.
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13AE
Language Code 2 for Ch2 in
Dolby Digital
UIS_LANGCOD2
Dual Mono Mode 1+1 (langcod2e, langcod2)
(Section 5.4.2.19 and 20 of ATSC Spec. A/52)
bit[15:0]
bit[7:0]
FFFF
langcod2e = 0 (langcod2 nonexistent in stream)
langcod2
hex
Used in the internal algorithm.
D0:13AF
Mixing Level and Room Type for Ch2 in
Dual Mono Mode 1+1 (audprodi2e, mixlevel2, roomtyp2)
(Section 5.4.2.21, 22 and 23 of ATSC Spec. A/52)
Dolby Digital
UIS_MIXLEVEL2_
ROOMTYP2
bit[15:0]
FFFF
audprodi2e = 0 (mixlevel2, roomtyp2 nonexistent
in stream)
hex
bit[6:2]
bit[1:0]
mixlevel2
roomtyp2
For user information.
D0:13B0
D0:13B1
Copyright Bit (copyrightb)
(Section 5.4.2.24of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_COPYRIGHT
B
bit[0]
0
1
not protected
protected by copyright (copy prohibited)
Original Bit Stream (origbs)
Dolby Digital
UIS_ORIGBS
(Section 5.4.2.25 of ATSC Spec. A/52)
bit[0]
0
1
copy of a bit stream
original bit stream
Original Bit Stream (origbs)
DTS
bit[1..0]
01
10
11
first generation
second generation
original bit stream
valid if copyrightb = 0
D0:13B2
Time Code 1
(Section 5.4.2.27of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_TIMECOD1
bit[15:0]
bit[13:0]
bit[13:9]
bit[8:3]
FFFF
timecod1e = 0 (time code 1 nonexistent)
hex
time code 1(first half)
time in hours (0...23 valid)
time in minutes (0...59 valid)
bit[2:0]
time in 8-second increments (0 = 0 seconds)
(1 = 8 seconds)
:
(7 = 56 seconds)
For external synchronization purposes.
Note: DTS: if TIMEF = 0 this value will always be FFFF
hex
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13B3
Time Code 2
(Section 5.4.2.28of ATSC Spec. A/52)
Dolby Digital
DTS
UIS_TIMECOD2
bit[15:0]
bit[13:0]
bit[13:11]
bit[10:6]
bit[5:0]
FFFF
timecod2e = 0 (time code 2 nonexistent)
hex
time code 2 (second half)
time in 8-second increments, see time code 1
time in frames (0...29 valid)
time in 1/6 frames
For external synchronization purposes.
Note: DTS: if TIMEF = 0 this value will always be FFFF
hex
D0:13B4
Dynamic Range Gain Word (dynrnge, dynrng)
Dolby Digital
UIS_DYNRNG
(Section 5.4.3.3 and 5.4.3.4 of ATSC Spec. A/52)
bit[15:0]
bit[7:0]
FFFF
dynrnge = 0 (dynrng nonexistent in stream)
current dynrng / RANGE value
hex
Used in the internal algorithm.
Dynamic Range Gain Word (dynf, RANGE)
DTS
bit[15:0]
bit[19:0]
FFFF
dynf nonexistent in stream
current RANGE value (15bit mantissa, 4bit exp.)
hex
D0:13B5
D0:13B6
Dynamic Range Gain Word 2 for Ch2 in
dual mono mode (dynrng2e, dynrng2)
(Section 5.4.3.5 and 5.4.3.6 of ATSC Spec. A/52)
Dolby Digital
UIS_DYNRNG2
bit[15:0]
bit[7:0]
FFFF
dynrng2e = 0 (dynrng2 nonexistent in stream)
current dynrng value
hex
Used in the internal algorithm.
Karaoke Flag
Dolby Digital
DTS
UIS_
KARAOKEFLAG
bit[0]
0
1
no Karaoke info in bit stream
Karaoke info in bit stream
AUX
UIS_AUX
bit[12:0]
bit[18:13]
Memory address of auxiliary data bytes
Auxiliary data byte count. Present if auxiliary data bytes are
appended at end of frame
bit[19]
Auxiliary data flag
D0:13B7
Frame Count
DolbyDigital
MPEG
UIS_FRAME_
COUNTER
DTS
bit[19:0]
counts 0, 1, 2, 3, 4, ..., 1048575 (= FFFFF ), 1, ...
hex
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13B8
MPEG Header Bits 12...31
MPEG
UIS_MPEG_
HEADER
bit[19]
ID (must be 1 for MPEG-1)
bit[18:17]
Layer
00
01
10
11
reserved
Layer 3
Layer 2
Layer 1
bit[16]
Protection
CRC
no CRC
0
1
bit[15:12]
bit rate (see table in IEC 11172-3, Layer 2)
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
free
32
48
56
64
hex
80
96
112
128
160
192
224
256
320
384
forbidden
bit[11:10]
sampling frequency (MPEG-1 Layer-2)
00
01
10
11
44.1 kHz
48 kHz
32 kHz
reserved
...
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13B8
(continued)
bit[9]
padding bit
private bit
bit[8]
bit[7:6]
Mode
00
01
10
11
stereo
joint stereo
dual channel
reserved
bit[5]
bit[4]
bit[3]
bit[2]
bit[1:0]
Joint Stereo Mode Extension ms_stereo
off
on
0
1
Joint Stereo Mode Extension Intensity Stereo
off
on
0
1
Copyright
not protected
protected
0
1
Original/Copy
copy
original
0
1
Emphasis
none
50/15 µs
reserved
CCITT J.17
00
01
10
11
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
DTS
Name
D0:13B8
(continued)
Protection (CPF)
UIS_DTS_
HEADER
bit[11]
0
1
no CRC
CRC
RATE
bit[10:6]
00
01
02
03
04
05
06
07
08
09
0a
0b
32 kbps
56 kbps
64 kbps
96 kbps
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
112 kbps
128 kbps
192 kbps
557 kbps
256 kbps
320 kbps
384 kbps
448 kbps
512 kbps
576 kbps
640 kbps
768 kbps
960 kbps
1024 kbps
1152 kbps
1280 kbps
1344 kbps
1408 kbps
1411.2 kbps
1472 kbps
1536 kbps
1920 kbps
2048 kbps
3072 kbps
3840 kbps
open
0c
0d
hex
hex
hex
0e
0f
10
11
12
13
14
15
16
17
18
19
1a
1b
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
1c
1d
1e
hex
hex
hex
variable
lossless
1f
PCMR
DTS
bit[5:1]
10
14
18
16 bits
20 bits
24 bits
hex
hex
hex
HDCD
DTS
bit[0]
copy of HDCD in bit stream
D0:13B9
MPEG Status
MPEG
UIS_MPEG_
STATUS
bit[5]
0
1
mono
stereo
bit[4]
1
CRC error
bit[3:2]
bit[1:0]
>0
>0
other decoding error (not enough data)
header error
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
All
Name
D0:13BB
Global Operation Status (GOS)
UIS_GOS
bit[7:5]
GOS_Type
0
GOS_NODEC, not decodable
1
GOS_PCM_WARN, channel status not plausible
2
3
GOS_DATA, data type
GOS_PCM
4...6
7
reserved
GOS_I2S
bit[4:1]
Appl_Type
0
AC-3
1
2
MPEG Layer-2
PCM
3
4
5
time code
noise generator
DTS
15
unknown
bit[0]
0
1
unsynchronized (default)
valid bit stream detected
This status cell reflects the result of the decoding with the parameters given. If
an incorrect input data type (D0:13D0) is selected, the input data stream will
not be decodable.
The GOS_PCM_WARN-flag is set when the S/PDIF-channel status indicates
PCM-encoded audio, but valid synchronization headers (Dolby Digital or
MPEG) are found.
D0:13BC
Bit Stream Information
S/PDIF-Input
UIS_DSI
each bit:
1
0
channel available
channel not available
bit[7]
...
bit[0]
bit stream number 7
bit stream number 0
Available bit streams (channels) in the S/PDIF-data.
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13BD
...
Pc Information of Selected Data Stream (burst_info)
(Section 4.4.3 of Annex B of ATSC Spec. A/52)
S/PDIF-Input
UIS_PC<i>,
i = 0...7
D0:13C4
bit[15:13]
bit[12:8]
bit[7]
0
...7
channel number (data_stream_number)
hex
hex
data_type_dependent, see below
error flag (error_flag)
data may be valid
data burst may contain errors
0
1
bit[6:5]
bit[4:0]
reserved
00
01
02
03
04
05
06
07
08
09
reserved
AC-3 data
reserved
pause
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
MPEG Layer-1
MPEG-1 Layer-2, 3, or MPEG-2 without extension
MPEG-2 data with extension
reserved
MPEG-2 Layer-1 low fs
MPEG-1 Layer-2, 3 low fs
reserved
0A
hex
0B ...D
DTS
hex.
hex.
0E ...1F
reserved
hex.
hex.
This memory cell mirrors the Pc-word of the S/PDIF-preamble (burst_info) of
the selected of eight possible data streams (channels) if available.
Meaning of Field data_type_dependent
Dolby Digital
AC-3: (Section 4.7 of Annex B of ATSC Spec. A/52)
bit[12,11]
bit[10:8]
00
reserved, shall be ’00’
value of bsmod as described in D0:13A2
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Table 3–6: Status memory cells, continued
Memory
Address
(hex)
Function
Mode
Name
D0:13C7
S/PDIF Status
S/PDIF-Input
UIS_SP_STATUS
bit[15]
S/PDIF Input is synchronized while processing I2S
D0:13D0 [9] = 0 S/PDIF Input selected
0
bit is always 0 (to be compatible with MAS 3528E)
D0:13D0 [9] = 1 I²S Input selected
0
1
S/PDIF Input not synchronized; no valid bit stream
S/PDIF Input in sync; valid bit stream. Further information
about the signal can be obtained from UIS_DSI and
UIS_PC<i>; i=0..7.
bit[3:2]
bit[1]
Parity Error (only valid when processing S/PDIF Input)
0
no error
>0
parity error
Data Mode
0
1
PCM
compressed audio data
bit[0]
S/PDIF Copy Active
0
1
inactive
active
D0:13FC
D0:1FF7
D0:1FFF
MAS 35xyH Type
All
All
All
UIS_MASH_TYPE
bit[15:0] 30
MAS 3530H-C6
MAS 3529H-C6
MAS 3527H-C6
dec
dec
dec
29
27
MAS 35xyH Version
UIS_MASH_
VERSION
bit[15:0] 0201
0203
MAS 35xyH-B3
MAS 35xyH-C4
MAS 35xyH-C6
hex
hex
hex
0206
Version Number
UIS_VERSION
Returns the version number of the ROM-code as ASCII
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3.6.2. Control Interface for Decoding Operation
The following table gives the writable memory
addresses of the control interface for the decoding
firmware.
Table 3–7: Configuration memory cells
Memory
Address
(hex)
Function
Mode Reset
Name
Value
(hex)
D0:13D0
I/O Control
00000 UIC_IO_CONTROL
Version Number Check
DTS
bit[17]
VerNum Check
0
DTS version number not checked
1
DTS version number checked
for VerNum 0-7 bitstream is decoded;
for VerNum 8-15 bitstream is not decoded
Soft Mute
All
bit[15]
Soft Mute
0
1
Soft mute off
Soft mute on
This switch is provided for user-controlled fast audio mute.
CRC Check
Dolby Digital
MPEG
bit[14]
CRC1
0
1
CRC1 on
CRC1 off
bit[13]
CRC2
0
1
CRC2 on
CRC2 off
Dolby Digital:
CRC1 protects the header and 3/5 of the data, CRC2 protects the
remaining 2/5 of the data. It is recommended that both AC-3 CRC-
checks are enabled which yields to an automatic mute upon detec-
tion of an error. However, under special operating conditions (noisy
channel), it may be advantageous to turn one (preferably CRC2) or
both CRC-checks off. In this case, it is important to decrease the lis-
tening volume to prevent hearing injuries and damages to the equip-
ment.
MPEG:
For MPEG, only CRC1 is applied. It is recommended to enable
CRC1 to avoid strong digital noise in case of deranged or unreliable
signals.
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Value
Name
(hex)
D0:13D0
S/PDIF Channel Select
S/PDIF
00000 UIC_IO_CONTROL
(continued)
bit[12:10]
000
S/PDIF channel select
Channel 0
...
111
Channel 7
The S/PDIF may carry up to eight channels of compressed audio.
Their content is shown in the S/PDIF-Pc-preambles
(D0:13B8...13BF).
Input and Mode Selection
All
bit[18, 7:6]
Input data type
000
001
010
011
100
Auto-detection
AC-3 (Dolby Digital)
MPEG Layer-2
PCM
DTS
2
bit[9]
bit[8]
S/PDIF or I S Input Select
0
1
S/PDIF input
2
I S input
2
I S input select
I S input at SID (word mode)
Continuous data stream at SID
(SII connected to ground)
2
0
1
2
Output Interface Mode I S word strobe polarity
All
bit[5]
bit[5]
bit[1]
0
1
low = right, high = left
high = right, low = left
0
1
default
2
I S output mode: invert word strobe
2
I S output channels
0
1
1 × 8 channels
4 × 2 channels
The clock and word strobe outputs SOC
and SOI apply to all 4 data outputs
SOD...SOD3
2
bit[0]
I S word strobe alignment
0
1
WS changes at data word boundary
WS changes one clock cycle in advance
2
Input Interface Mode
I S word strobe alignment
All
bit[4]
0
1
WS changes at data word boundary
WS changes one clock cycle in advance
2
bit[3]
I S word strobe polarity
0
1
low = right, high = left
high = right, low = left
bit[2]
0
1
default
invert clock
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Name
Value
(hex)
D0:13D1
Noise Generator
All
00000 UIC_NOISE
(Sec. 4.10.2 of Dolby Digital Licensee Information Manual Issue 3)
bit[7]
bit[6]
0
1
Noise generator off
Noise generator on
Noise type
0
1
White noise
Band-pass shaped noise
bit[5:0]
000001
000010
000100
001000
010000
100000
000000
L
C
R
LS
RS
LFE
No channel selected
By combining the appropriate bits, more than one channel can out-
put noise. The noise type can be selected between white and band-
pass filtered with a maximum between 500 and 1000 Hz. The
required stepping actions have to be initiated by the controller.
D0:13D2
D0:13D3
Center Channel Delay
(Sec. 4.10.1 of Dolby Digital LIM Issue 3)
Dolby Digital
DTS
Dolby Pro Logic II
00000 UIC_C_DELAY
bit [2:0]
000
...
0 ms
5 ms
101
Left Surround Channel Delay
(Sec. 4.10.1 of Dolby Digital LIM Issue 3
and Sec. 2.1.4 of Pro Logic II LIM Issue 1)
Dolby Digital
DTS
Dolby Pro Logic II
00001 UIC_SL_DELAY
Dolby Digital
Pro Logic II
all Modes
Music Mode
Matrix Mode
Movie Mode
PL Emulation
bit[3:0]
0000
1111
0 ms
...
15 ms
10 ms
...
25 ms
For Dolby Pro Logic II in Movie and in Pro Logic Emulation Mode,
the delay is automatically extended by 10 ms.
D0:13D4
Right Surround Channel Delay
(Sec. 4.10.1 of Dolby Digital LIM Issue 3
and Sec. 2.1.4 of Pro Logic II LIM Issue 1)
Dolby Digital
DTS
Dolby Pro Logic II
00000 UIC_SR_DELAY
Dolby Digital
Pro Logic II
all Modes
Music Mode
Matrix Mode
Movie Mode
PL Emulation
bit[3:0]
0000
1111
0 ms
...
15 ms
10 ms
...
25 ms
For Dolby Pro Logic II in Movie and in Pro Logic Emulation Mode,
the delay is automatically extended by 10 ms.
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Value
Name
(hex)
D0:13D5
LFE Channel Enable
Dolby Digital
DTS
00001 UIC_OUT_LFE
bit[0]
Route LFE Channel to subwoofer output
(if it exists in stream)
enable LFE
1
0
disable LFE
The subwoofer output is assembled from the LFE and the other
channels depending on the Output Configuration. This switch dis-
ables only content coming from the LFE.
D0:13D6
Output Mode Control (Downmix)
(Section 7.8 of ATSC Spec. A/52)
Dolby Digital
DTS
00007 UIC_OUT_MODE_
CTRL
Dolby Pro Logic II
bit[4:3]
Dual mono setting of Dolby C decoder,
applicable only if Audio Coding Mode
is dual mono (acmod = 0). The actual
mixing depends on the number of
available output channels (speakers).
Stereo (straight output of both channels)
Left Mono (channel 1)
00
01
10
11
Right Mono (channel 2)
Mixed Mono (sum of both channels)
bit[2:0]
Listening Mode Selector
Defines the number of available (desired)
output channels (loudspeakers).
2/0 L, R Dolby Surround compatible
000
001
010
011
100
101
110
111
1/0
C
2/0 L, R
3/0 L, C, R
2/1 L, R, S
3/1 L, C, R, S
2/2 L, R, SL, SR
3/2 L, C, R, SL, SR
These downmixing options are independent of the setting of the
Extra Stereo Output (D0:13DE).
Undesired channels can be muted by setting the volume to zero or
by muting the outputs in the DPL 4519G or MSP 44x0G, respec-
tively.
Only listening modes 1/0, and 2/0 should be used if dual mono is
transmitted.
Note: other values or combinations of bits must not be written, bits
not mentioned must be set to 0.
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Name
Value
(hex)
D0:13D7
Compression Control
(Operational Modes, Dialog Normalization)
Dolby Digital
00001 UIC_
COMPRESSION_
(Sec. 3.7 of Dolby Digital Licensee Information Manual, Issue 3)
CONTROL
bit[1:0]
Setting of Dolby C decoder
Custom Mode 0 (analog dialog
normalization)
Custom Mode 1 (internal digital dialog
normalization)
00
01
10
11
Line Mode
Compression RF out
The implemented dynamic range compression uses the transmitted
variables dynrng, compr, and dialnorm. In Line Mode and in the Cus-
tom Modes, the dynamic compression may be scaled down by using
the user-controlled high-level cut and low-level boost factors.
Note that in Custom Mode 0, the effect of dynrng must be imple-
mented in the analog part of the audio equipment.
Note that in the Custom Mode downmix, an internal digital attenua-
tion of 11 dB is applied that must be compensated externally.
D0:13D8
High-Level Cut Compression Scale Factor
Dolby Digital
7FFFF UIC_CUT_X
(Sec. 3.7 and Sec. 4.11.9 of Dolby Digital Licensee Information Man-
ual, Issue 3)
bit[19:0]
00000
(full dynamic)...7FFFF
(full compression)
hex
hex
This factor scales down potential attenuation (i.e. dynamic compres-
sion) of loud portions of the audio as defined by dynrng. High-Level
Cut is only used in Line Mode (except in downmix) and in the Cus-
tom Modes.
Note: In order to prevent clipping due to the downmixing in the Cus-
tom and Line Modes, the High-Level Cut Compression Scale Factor
must always be left at 7FFFF
when the Extra Stereo Output
hex
(D0:13DE) is used in conjunction with non-downmixed channels
(D0:13D6).
Please refer to section 4.5.8. of Dolby Digital Licensee Information
Manual, Issue 3.
D0:13D9
Low-Level Boost Compression Boost Factor
Dolby Digital
7FFFF UIC_BOOST_Y
(Sec. 3.7 and Sec. 4.11.9 of Dolby Digital Licensee Information Man-
ual, Issue 3)
bit[19:0]
00000
(full dynamic)...7FFFF
(full compression)
hex
hex
This factor scales down potential amplification (i.e. dynamic com-
pression) of weak portions of the audio as defined by dynrng. Low-
Level Boost is only used in Line Mode and in the Custom Modes.
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Value
Name
(hex)
D0:13DA
Bass Management
All
00000 UIC_POST_
(see chapter 2.9.10.3.;Sec. 4.7 of Dolby Digital Licensee Information
Manual Issue 3)
PROCESSING
bit[4:0]
00000 Direct loop-through of all six channels
without channel mixing
01000 Dolby Configuration 0
01001 Dolby Configuration 1
01010 Dolby Configuration 2
01011 Dolby Alternative Configuration 2
01100 Dolby Configuration 3 (No SubwooferOut)
01101 Dolby Configuration 3 (Subwoofer Out)
01110 Multichannel Source Products (Ι)
01111 Multichannel Source Products (ΙΙ)
11000 B2C (Bass to Center)
Note: If Bass Management is enabled, high processor clock must be
selected (D0:13DF; bit16=1)
The LFE-content can be disabled in D0:13D5.
The output configurations can be used for all input formats. How-
ever, for MPEG and PCM-data, only the L and R input channels will
carry information.
Cross-Over Frequency (LP and complementary HP)
All
UIC_CROSSOVER
_FREQ
bit[15:8]
0
5
100 Hz (compatible with Type 2)
dec
50 Hz
100 Hz
150 Hz
200 Hz
250 Hz
300 Hz
350 Hz
400 Hz
min. cross-over frequency.
dec
10
15
20
25
30
35
40
dec
dec
dec
dec
dec
dec
dec
max. cross-over frequency
D0:13DD
D0:13DE
Karaoke Mode
Dolby Digital
00003 UIC_KARAOKE_
MODE
bit[1:0]
00
01
10
11
no vocals
vocal 1
vocal 2
vocal 1 (left) + vocal 2 (right)
Extra Stereo Output (Lt/Rt or Lo/Ro)
DolbyDigital
(surround encoded)
00000 UIC_DOWNMIX_
MODE
bit[0]
0
1
Lt/Rt stereo output
Lo/Ro stereo output
For headphone operation, the 2-channel output can be switched to
the Lo/Ro-mode.
Note: In order to prevent clipping due to the downmixing in the Cus-
tom and Line Modes, the High-Level Cut Compression Scale Factor
(D0:13D8) must always be left at 7FFFF
when the Extra Stereo
hex
Output is used in conjunction with non-downmixed channels
(D0:13D6).
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Name
Value
(hex)
D0:13DF
Output Clock Scaling
All
80004 UIC_OUT_CLK_
SCALE
bit[19]
CLKO off
0
1
enable CLKO
disable CLKO
bit[18:17]
Division factor applied to the internal
reference clock
(see Table 2–2 on page 19) for the
CLKO-output
0
1
2
3
divide reference clock by 1
divide by 2
divide by 4
divide by 8
bit[16]
Low/high system clock for Dolby Digital
(please refer to Table 2–1 on page 10)
61/56/40 MHz for 48/44.1/32 kHz
73/67/49 MHz for 48/44.1/32 kHz
0
1
Sets the processor clock and the output clock at pin CLKO. The
clock frequencies are coupled to the audio data sampling rate of the
input signal by a PLL.
The high clock frequencies have to be used if the internal Dolby Dig-
ital Bass Management is used.
Auxiliary Interface Control
All
UIC_AUX_
INTERFACE_CTRL
bit[11]
Tristate SO* (SOI, SOC, SOD, SOD1..3)
0
1
enable SO* output
tristate SO* output
bit[10:7]
bit[6]
0
reserved (set to 0)
S/PDIF input select
select SPDI input
select SPDI2 input
0
1
bit[5:3]
bit[2]
0
reserved (set to 0)
SO* Impedance
low impedance
high impedance
0
1
bit[1]
Serial input select
0
1
select SID, SII, SIC
select SID*, SII*, SIC*
bit[0]
0
reserved
Input/output interface selections.
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MAS 35xyH
Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Value
Name
(hex)
D0:13E0
PCM/MPEG De-emphasis Control
MPEG/PCM
00000 UIC_DEEMPHASE
_CONTROL
bit[1:0]
De-emphasis
00
automatic detection (only for PCM via
S/PDIF and all MPEG-inputs, no deem-
phasis if PCM via I S-input is selected)
2
01
10
11
50/15 µs de-emphasis
no de-emphasis
J17 de-emphasis
PCM-signals coming via the serial interface do not contain embed-
ded de-emphasis information. The correct de-emphasis must there-
fore be initiated by the controller.
PCM-signals coming via the S/PDIF-interface and MPEG-data
streams contain such information. In this case, the automatic detec-
tion should be enabled to achieve the correct de-emphasis.
Volume Control
All
D0:13E1
D0:13E2
D0:13E3
D0:13E4
D0:13E5
D0:13E6
D0:13E7
D0:13E8
Volume left channel
Volume center channel
Volume right channel
Volume surround left channel
Volume surround right channel
Volume subwoofer channel
Volume stereo left channel
Volume stereo right channel
07300 UIC_L_VOLUME
(all)
UIC_C_VOLUME
UIC_R_VOLUME
UIC_SL_VOLUME
UIC_SR_VOLUME
UIC_LFE_
VOLUME
UIC_L_ST_
VOLUME
UIC_R_ST_
VOLUME
bit[15:8]
7F
...
+12 dB
0 dB
hex
73
...
hex
01
00
−114 dB
mute
hex
hex
The resolution is 1 dB/step.
D0:13EA
S/PDIF Channel Status Bits Control
All
01904 UIC_CHANNEL
_STATUS
bit[15]
bit[14:8]
bit[7:6]
bit[5:3]
bit[2]
L-bit (generation status)
category code
should be “0”
should be “0”
cp-bit (copyright protection)
should be “0” for PCM output
should be “0” for consumer use
bit[1]
bit[0]
These bits control the status word in the S/PDIF output. This control
is inactive if S/PDIF loop-through is selected.
Note: It must be made sure that bits 2, 8, .., 15 are set correctly.
Incorrect settings may affect the ability to make digital copies.
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Name
Value
(hex)
D0:13EE
Operational Modes
(Sec. 2.2 of Pro Logic II LIM Issue 1)
Dolby Pro Logic II
00000 UIC_DPL_
STANDARD
Pro Logic II Standard Modes
bit[2:0]
000
001
010
011
100
Movie Mode
Autobalance
Surround Filter
Surround Coherence (RS Inv.) enabled
Panorama Mode
enabled
No
disabled
disabled
neutral (3)
Center Width Control
Dimension Control
Music Mode
Autobalance
Surround Filter
Surround Coherence (RS Inv.) disabled
Panorama Mode
disabled
Shelf
User defined
User defined
User defined
Center Width Control
Dimension Control
Virtual compatible Mode
Autobalance
Surround Filter
Surround Coherence (RS Inv.) disabled
Panorama Mode
enabled
No
disabled
disabled
neutral (3)
Center Width Control
Dimension Control
Pro Logic Emulation
Autobalance
Surround Filter
Surround Coherence (RS Inv.) disabled
Panorama Mode
enabled
7-kHz LP
disabled
disabled
neutral (3)
Center Width Control
Dimension Control
Matrix Mode
Autobalance
Surround Filter
disabled
Shelf
Surround Coherence (RS Inv.) disabled
Panorama Mode
Center Width Control
Dimension Control
disabled
disabled
neutral (3)
101
110
− (do not use!)
Custom Mode
Surround Filter
User defined
Surround Coherence (RS Inv.) User defined
Autobalance
User defined
User defined
User defined
User defined
Panorama Mode
Center Width Control
Dimension Control
111
Off (Bypass Mode)
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MAS 35xyH
Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Value
Name
(hex)
D0:13EE
Operational Modes
Dolby Pro Logic II
00000
(continued) (Sec. 2.2 of Pro Logic II LIM Issue 1)
Surround Filter
UIC_DPL_MODE_
SURR_FILT
bit[4:3]
00
01
10
No
Shelf
7kHz LPF
Surround Coherence
UIC_DPL_MODE_
RS_POL
bit[5]
0
1
RS Polarity Inversion disabled
RS Polarity Inversion enabled
Auto-Balance
UIC_DPL_MODE_
AUTO_BAL
bit[6]
0
1
enabled
disabled
Panorama Mode
UIC_DPL_MUSIC_
PANORAMA
bit[7]
0
1
disabled
enabled
Pro Logic II Input Matrix
UIC_DPL_MATRIX
bit[9:8]
00
01
10
Stereo or AB
Sound A
Sound B
D0:13ED
Music Mode Controls
Dolby Pro Logic II
06060
(Sec. 2.1 of Pro Logic II LIM Issue 1)
UIC_DPL_MUSIC_
CENTER_WIDTH
Center Width Control
see also “Table 2-2 Center Width Control Levels” of LIM Dolby Pro Logic II
Control
Angle
00.0°
20.8°
28.0°
C Lev.(dB) L/R Lev.(dB)
bit[7:5]
000
001
010
0
1
2
0.0
off
-0.6
-1.1
-1.8
-4.6
-6.6
-9.0
off
-12
-9.6
-7.6
-4.8
-4.1
-3.6
-3.0
011 3 (default) 36.0°
100
101
110
111
4
5
6
7
54.0°
62.0°
69.2°
90.0°
This control allows center-channel sounds to be positioned between
the center speaker and the left/right speakers over a range of eight
steps. Step “3” uses a combination of all three front speakers to give
the best vocal imaging and most seamless soundstage presenta-
tion, and is recommended for most recordings. Step “0” places all
center sound in the center speaker. Step “7” places all center sound
equally in the left/right speakers, just as in conventional stereo.
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Table 3–7: Configuration memory cells, continued
Memory
Address
(hex)
Function
Mode Reset
Name
Value
(hex)
D0:13ED
Music Mode Controls
Dolby Pro Logic II
06060
(continued) (Sec. 2.1 of Pro Logic II LIM Issue 1)
UIC_DPL_MUSIC_
DIMENSION
Dimension Control
bit[15:13] 000
0
1
2
Most Center
001
010
011 3 (default) Neutral
100
101
110
4
5
6
Most Surround
This control allows the user to gradually adjust the sound field either
towards the front or the rear. This can be useful to help achieving the
desired balance from all the speakers with certain recordings that
may contain either too much or too little spatial effect. Step “3” is the
recommended setting, which has no effect on the sound. Steps 2, 1,
and 0 gradually move the sound forward, and steps 4, 5, and 6
move the sound towards the surrounds.
Note: Center Width Control and Dimension Control with higher reso-
lution may be implemented in firmware in a later version of the
MAS 35xyH. Therefore, bits[4:0] and bits[12:8] must be set to 0.
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3.6.3. Hybrid User Interface Cells
Table 3–8: Hybrid User Interface Cells
Memory
Address
(hex)
Function
Reset
Value
(hex)
Name
D0:13FF
Message Constants
All
00000 UIH_LAST_
MESSAGE
Messages
bit[19:0]
0
no error
8
all errors with an error number higher or equal to
this error number cause a restart
9
S/PDIF: sync lost during look for Pa, Pb, Pc, Pd
S/PDIF: sync lost during operation
Data Stream Error (Pa not correct)
Data Stream Error (Pb not correct)
Data Stream Error (Pc not correct)
Data Stream Error (Pd to big)
10
11
12
13
14
15
16
2
I S time-out error
2
no input data type selected in I S input mode
(i.e. auto-detection is ON)
input type over S/PDIF changed from pcm to data
AC-3: initial waiting time out
AC-3: sync waiting time out
AC-3: sync lost
AC-3: header corrupted
AC-3: CRC1 wait time-out
AC-3: CRC1 fail
AC-3: CRC2 wait time-out
AC-3: CRC2 fail
selected bit-stream-number not available
PCM recognition inconsistent, restart
DATA TYPE in BurstInfo not AC-3, PCM, MPEG, or
DTS.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AC-3 - Sampling frequency changed
invalid exponents detected
S/PDIF: Input type chosen manually (not autodetected)
AC3: Input buffer overrun
- the input pointer overwrites the actual frame
S/PDIF input parity error
33
40
41
42
43
44
45
46
47
48
49
MPEG: sampling frequency changed
MPEG no header found
MPEG: no Layer 2 header found
MPEG: restart forced
MPEG: not enough data to decode
MPEG: S/PDIF error
MPEG: decoding error
MPEG: input time-out
MPEG: sync error
MPEG: data rate too high (probably PCM input)
50
51
52
53
...
LM_USER_CHANGE
LM_IO_CONTROL
LM_NOISE
LM_C_DELAY
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Table 3–8: Hybrid User Interface Cells, continued
Memory
Address
(hex)
Function
Reset
Value
(hex)
Name
D0:13FF
(continued)
54
55
56
57
58
59
60
61
62
63
64
65
66
LM_SL_DELAY
LM_RL_DELAY
LM_OUT_LFE
LM_OUT_MODE_CONTROL
LM_COMPRESSION_CONTROL
LM_CUT_X
LM_BOOST_Y
LM_POST_PROCESSING
LM_SAMP_FREQ
LM_OUTN_CHANNELS
LM_KARAOKE_MODE
LM_DOWNMIX_MODE
LM_OUT_CLK_SCALE
00000 UIH_LAST_
MESSAGE
70
PCM: Sampling frequency changed in PCM Mode
80
DTS: LOST_SYNC
81
DTS: WRONG_DSYNC
82
DTS: NBLKS_ERROR
83
DTS: FSIZE_ERROR
84
DTS: SFREQ_ERROR
85
DTS: FS_CHANGED
86
DTS: PCMR_ERROR
87
88
DTS: VERNUM_ERROR
DTS: PCHS_ERROR
89
DTS: SUBS_ERROR
90
91
DTS: VQSUBS_ERROR
DTS: JOINX_ERROR
92
DTS: SSC_ERROR
93
94
DTS: ABITSHuff_ERROR
DTS: BLCK_ERROR
95
DTS: AUXCT_ERROR
96
97
98
99
100
101
102
103
104
105
106
107
DTS: SCALESHuff_ERROR
DTS: AUDIOHuff_ERROR
DTS: AUDIOHuff1_ERROR
DTS: NOT_VALID_BS; sync found,but not the next one
DTS: TIMEOUT_DISCARD
DTS: TIMEOUT_FINDSYNC
DTS: TIMEOUT_READBYTES
DTS: TIMEOUT_SPDIFWAIT1
DTS: TIMEOUT_SPDIFWAIT2
DTS: TIMEOUT_512INPUT
DTS: UNSUPPORTED_BS_TYPE; if bs_type=24 or 14
DTS: UNKNOWN_ERROR
The latest message that occurred is displayed in this cell. The con-
troller should frequently (e.g. once per frame) check and clear this
memory location.
After reading the message it is recommended to clear this cell (by
writing a “0”) to see whether this message occurs again.
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4. Specifications
4.1. Outline Dimensions
Fig. 4–1:
3
PMQFP80-11: Plastic Metric Quad Flat Package, 80 leads, 14 × 20 × 2.7 mm , high standoff
Ordering code: QA
Weight approximately 1.68 g
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PRELIMINARY DATA SHEET
Fig. 4–2:
3
PLCC44-4: Plastic Leaded Chip Carrier, 44 leads, 16.6 × 16.6 × 4.15 mm , die down, heat slug
Ordering code: PR
Weight approximately 2.61 g
PLCC44-4 is not intended for use in new designs.
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4.2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
LV = If not used, leave vacant
OBL = obligatory, pin must be connected as described in application information
VDD: connect to positive supply
VSS: connect to ground
PLCC44-4 is not intended for use in new designs.
Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
PMQFP PLCC
80-11
44-4
1
7
AVSS
NC
SUPPLY
OBL
Ground supply for analog circuits
2
−
3
−
NC
4
6
TE
IN
VSS
IN
Test enable
OBL
5
5
POR
I2CC
I2CD
NC
IN
2
6
4
IN/OUT
IN/OUT
OBL
OBL
I C clock line
2
7
3
I C data line
8
−
9
−
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
−
NC
2
VDD
VDD
VSS
VSS
NC
SUPPLY
SUPPLY
SUPPLY
SUPPLY
OBL
OBL
OBL
OBL
Positive supply for digital parts
Positive supply for digital parts
Ground supply for digital parts
Ground supply for digital parts
−
1
−
−
−
NC
44
43
42
41
40
−
SYNC
TP
OUT
OUT
OUT
OUT
IN
LV
LV
LV
LV
LV
Reserved for frame synchronization
Test pin
TP
Test pin
TP
Test pin
SPDI2
NC
S/PDIF input 2
−
NC
−
NC
39
SPREF
IN
LV
S/PDIF input (reference)
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Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
PMQFP PLCC
80-11
44-4
38
−
26
SPDI
NC
IN
LV
S/PDIF input 1
27
28
−
NC
LV
29
−
NC
LV
30
−
NC
LV
31
37
TP
IN
VDD
VDD
VSS
VSS
VSS
VSS
Test pin
32
33
34
35
36
36
35
34
33
32
TP
IN
Test pin
1)
1)
1)
1)
PI19
PI18
PI17
SIC* (PI16)
IN (OUT)
IN (OUT)
IN (OUT)
IN (OUT)
PIO data [19]
PIO data [18]
PIO data [17]
PIO data[16], SIC* = alternative input
for SIC
1)
37
38
31
30
SII* (PI15)
SID* (PI14)
IN (OUT)
IN (OUT)
VSS
VSS
PIO data [15], SII* = alternative input
for SII
1)
PIO data [14], SID* = alternative input
for SID
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
−
NC
LV
1)
29
−
PI13
NC
IN (OUT)
VSS
LV
PIO data [13]
−
NC
LV
1)
28
27
26
25
24
−
PI12
SOD
SOI
SOC
PI8
IN (OUT)
OUT
VSS
OBL
OBL
OBL
VSS
LV
PIO data [12]
Serial output data
Serial output frame identification
Serial output clock
PIO data [8]
OUT
OUT
1)
IN (OUT)
NC
−
NC
LV
−
NC
LV
−
NC
LV
−
NC
LV
−
NC
LV
−
XVDD
SUPPLY
OBL
Positive supply for output buffers
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MAS 35xyH
Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
PMQFP PLCC
80-11
44-4
23
22
−
55
XVDD
XVSS
XVSS
SID
SUPPLY
SUPPLY
SUPPLY
IN
OBL
OBL
OBL
VSS
VSS
VSS
VSS
LV
Positive supply for output buffers
Ground for output buffers
Ground for output buffers
Serial input data
56
57
58
21
20
19
59
SII
IN
Serial input frame identification
Serial input clock
60
SIC
IN
1)
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
−
18
−
PI4
IN (OUT)
PIO data [4]
NC
−
NC
LV
−
NC
LV
17
16
15
14
−
SPDIFOUT
SOD3
SOD2
SOD1
NC
OUT
OUT
OUT
OUT
LV
S/PDIF output
LV
Serial output data 3
Serial output data 2
Serial output data 1
LV
LV
LV
−
NC
LV
−
NC
LV
−
NC
LV
−
NC
LV
−
NC
LV
−
NC
LV
13
12
11
10
CLKO
TP
OUT
OUT
LV
DSP clock output
Test pin
LV
NC
LV
78
XTO
IN/OUT
OBL
Quartz oscillator pin 2,
input for external clock
79
80
9
8
XTI
IN
LV
Quartz oscillator pin 1
AVDD
SUPPLY
OBL
Supply for analog circuits
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PRELIMINARY DATA SHEET
4.3. Pin Descriptions
4.3.5. Serial Input Interface
4.3.1. Power Supply Pins
SID
SII
SIC
IN
IN
IN
Connection of all power supply pins is mandatory for
the functioning of the MAS 35xyH.
Data, frame indication, and clock line of the standard
2
I S (word mode) serial input interface.
VDD
VSS
SUPPLY
SUPPLY
PI16
PI15
PI14
SIC*
SII*
SID*
IN
IN
IN
The VDD/VSS pair is internally connected with all digi-
tal modules of the MAS 35xyH.
The SIC*, SID*, and SII* are alternative serial input
lines. This interface can be selected in memory cell
D0:13D0.
XVDD
XVSS
SUPPLY
SUPPLY
The XVDD/XVSS pins are internally connected with
the pin output buffers.
4.3.6. S/PDIF Input Interface
AVDD
AVSS
SUPPLY
SUPPLY
SPDI
SPDI2
SPREF
IN
IN
IN
The AVDD/AVSS pair is connected internally with the
analog blocks of the MAS 35xyH, i.e. clock synthesizer
and supply voltage supervision circuits.
Input lines (SPDI/SPDI2) and ground reference line
(SPREF) of the S/PDIF-input interfaces. One of the
two alternate input lines is selected by in D0:13DF.
4.3.2. Control Lines
I2CC
I2CD
SCL
SDA
IN/OUT
IN/OUT
4.3.7. S/PDIF Output Interface
2
Standard I C control lines.
SPDIFOUT
OUT
S/PDIF-output line.
4.3.3. General Purpose Input/Output
PI4, PI8, PI12...PI19
4.3.8. Serial Output Interface
IN/OUT
General purpose input/output pins. PI14 to PI16 can
be used as alternative I S bus inputs. Function is con-
trolled by the registers PIO_Config, PIO_Direction,
PIO_Data_Out, PIO_Data_In.
SOD
SOD1
SOD2
SOD3
SOI
OUT
OUT
OUT
OUT
OUT
OUT
2
SOC
4.3.4. Clocking
Data, frame indication, and clock line of the serial out-
put interface. The SOI indicates whether the left or the
right audio sample is transmitted. Besides the two
modes, it is possible to reconfigure the interface.
XTO
IN
This is the clock input of the MAS 35xyH. The nominal
clock frequency is 18.432 MHz.
XTI
IN
4.3.9. Miscellaneous
This connection is needed for the quartz oscillator.
POR
IN
CLKO
OUT
The POR pin is used to reset the digital parts of the
MAS 35xyH. POR is a low active signal.
The CLKO is an oversampling clock that is synchro-
nized to the digital audio data (SOD) and the frame
identification (SOI).
TE
IN
The TE pin is for production test only and must be con-
nected with VSS in all applications.
SYNC
The SYNC pin is set while decoding Dolby Digital or
MPEG. Only during header processing, there is a short
Low period (20...300 µs depending on the audio for-
mat)
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4.4. Pin Configurations
NC
NC
XVDD
XVDD
XVSS
XVSS
SID
NC
NC
NC
NC
PI8
SII
SOC
SOI
SIC
PI4
SOD
PI12
NC
NC
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SPDIFOUT 65
SOD3 66
SOD2 67
SOD1 68
NC 69
40 PI13
39 NC
38 SID*
37 SII*
36 SIC*
35 PI17
34 PI18
33 PI19
32 TP
NC 70
NC 71
NC 72
MAS 35xyH
NC 73
NC 74
31 TP
NC 75
30 NC
29 NC
28 NC
27 NC
26 SPDI
25 SPREF
CLKO 76
TP 77
XTO 78
XTI 79
AVDD 80
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AVSS
NC
NC
NC
NC
NC
SPDI2
TE
POR
I2CC
I2CD
TP
TP
TP
SYNC
NC
NC
NC
NC
NC
VSS
VSS
VDD
VDD
Fig. 4–3: PMQFP80-11 package
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PRELIMINARY DATA SHEET
VSS
VDD
SYNC
TP
I2CD
I2CC
POR
TP
TP
TE
SPDI2
6
5
4
3
2
1
44 43 42 41 40
AVSS
AVDD
XTI
7
8
9
39 SPREF
38 SPDI
37 TP
XTO 10
N.C. 11
36 TP
35 PI19
34 PI18
33 PI17
32 PI16
31 PI15
30 PI14
29 PI13
TP 12
MAS 35xyH
CLKO 13
SOD1 14
SOD2 15
SOD3 16
SPDIFOUT 17
18 19 20 21 22 23 24 25 26 27 28
PI4
PI12
SIC
SOD
SII
SOI
SOC
SID
XVSS
PI8
XVDD
Fig. 4–4: PLCC44-4 package
PLCC44-4 is not intended for use in new designs.
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PRELIMINARY DATA SHEET
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4.5. Internal Pin Circuits
VDD
P
TTLIN
N
Fig. 4–5: Input pins PCS, PR
VSS
Fig. 4–10: Input/Output pins SIC, SII, SID
VDD
Fig. 4–6: Input pin TE
N
VSS
Fig. 4–7: Input pin POR
Fig. 4–11: Input/Output pins I2CC, I2CD
AVDD
VDD
P
P
P
XTI
N
P
N
XTO
VSS
N
N
Fig. 4–12: Output pins CLKO,SYNC
Enable
AVSS
VDD
Fig. 4–8: Clock oscillator XTI, XTO
SPDI,
−
SPDI2
+
SPREF
VDD
P
VDD
Bias
Fig. 4–13: S/PDIF Input
N
VSS
Fig. 4–9: Input/Output pins SOD1, SOD2, SOD3,
SPDIFOUT, PI4, PI8, SOC, SOI, SOD, PI12...PI19
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MAS 35xyH
PRELIMINARY DATA SHEET
4.6. Electrical Characteristics
Abbreviations:
tbd = to be defined
vacant = not applicable
positive current values mean current flowing into the chip
4.6.1. Absolute Maximum Ratings
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso-
lute maximum-rated voltages to this high-impedance circuit.
All voltages listed are referenced to ground (0 V, V ) except where noted.
SS
All GND pins must be connected to a low-resistive ground plane close to the IC.
PLCC44-4 is not intended for use in new designs.
Table 4–1: Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Limit Values
Max.
Unit
Min.
1)
T
Ambient Operating Temperature
PMQFP80-11
PLCC44-4
−
°C
A
2)
0
0
65
65
T
T
Case Operating Temperature
PMQFP80-11
PLCC44-4
−
−
°C
°C
C
S
0
0
105
105
Storage Temperature
−40
125
P
Power Dissipation
PMQFP80-11
PLCC44-4
VDD,
XVDD,
AVDD
MAX
1550
1250
mW
mW
V
Supply Voltage
−0.3
−0.5
6.0
0.5
V
V
SUP
∆V
Voltage differences within supply
domains
SUP
V
Input Voltage
Input Current
Output Voltage
Output Current
all digital pins
all digital pins
all digital pins
all digital pins
−0.3
−20
V
+0.3
+0.3
V
I
SUP
I
20
mA
V
I
V
−0.3
V
SUP
O
I
250
mA
O
1)
Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power con-
sumption allowed for this package
2)
A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the “Abso-
lute Maximum Ratings” must not be exceeded at worst case conditions of the application.
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PRELIMINARY DATA SHEET
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4.6.2. Recommended Operating Conditions (T = 0 to +65 °C)
A
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteris-
tics” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.
All voltages listed are referenced to ground (0 V, V ) except where noted.
SS
All GND pins must be connected to a low-resistive ground plane close to the IC.
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Keep VDD = AVDD = XVDD during all power-up and power-down sequences.
PLCC44-4 is not intended for use in new designs.
4.6.2.1. General Recommended Operating Conditions
Symbol
Parameter
Pin Name
Limit Values
Unit
Min.
Typ.
Max.
T
Ambient Operating Temperature
PMQFP80-11
−
−
°C
A
1)
65
PLCC44-4
0
0
65
T
Case Operating Temperature
PMQFP80-11
PLCC44-4
−
°C
C
105
105
P
V
Power Dissipation
PMQFP80-11
PLCC44-4
VDD, XVDD,
AVDD
MAX
SUP
2)
2)
1550
1250
mW
mW
Supply Voltage
VDD, XVDD,
AVDD
4.75
5.0
5.25
V
3)
V
V
Input Voltage Low
POR
I2CC,
I2CD
0.5
V
V
IL
3)
Input Voltage High
2.6
V
IH
3)
V
V
Input Voltage Low (digital)
PI<i>,
SII,
SIC,
SID,
PR,
0.5
V
ILD
3)
Input Voltage High (digital)
IHD
SUPD
0.5
TE,
1)
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the
“Recommended Operating Conditions” must not be exceeded at worst case conditions of the application.
2)
3)
P
variation: user-determined by application circuit for I/Os
MAX
Input levels at V = 4.5 V...5.5 V
DD
Micronas
Dec. 4, 2003; 6251-598-2PD
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MAS 35xyH
PRELIMINARY DATA SHEET
4.6.2.2. Reference Frequency Generation and Crystal Recommendations
Symbol
Parameter
Pin Name
Limit Values
Unit
Min.
Typ.
Max.
External Clock Input Recommendations
CLK
CLK
Clock frequency
Clock amplitude
XTO
18.432
MHz
F
0.7
3.5
80
V
pp
Amp
Crystal Recommendations
T
Ambient temperature range
XTI, XTO
−20
°C
AC
f
Load resonance frequency at
18.432
MHz
P
C = 12 pF
I
∆f/f
∆f/f
Accuracy of frequency adjust-
ment
−50
−50
50
50
ppm
ppm
S
Frequency variation vs. temper-
ature
S
R
C
Equivalent series resistance
Shunt (parallel) capacitance
12
3
30
7
Ω
EQ
0
pF
4.6.3. Characteristics at T = 0 to 65 °C, V = 5.0 V, f
= 18.432 MHz
A
DD
Crystal
4.6.3.1. General Characteristics
Symbol
Parameter
Pin Name
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
Supply Current
ISUP
Current consumption
all
210
mA
5.0 V, audio sampling
frequency 48 kHz
Dolby Digital, 61 MHz
fproc
supply pins
Digital Outputs and Inputs
ODigL
ODigH
Output low voltage
Output high voltage
PI<i>,
SOI,
SOC,
0.5
V
V
at Iload = 1 mA
at Iload = 1 mA
VSUP
−0.5
SOD,
SOD1,
SOD2,
SOD3,
EOD,
RTR,
RTW,
CLKO
SPDIF-OUT
CDigI
Input capacitance
all
7
1
pF
µA
digital Inputs
IDLeak
Input leakage current
−1
0 V < Vpin < VSUP
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Dec. 4, 2003; 6251-598-2PD
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PRELIMINARY DATA SHEET
MAS 35xyH
2
4.6.3.2. I C Characteristics
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Test Conditions
Min.
Max.
RON
Output resistance
I2C bus frequency
I2CC,
I2CD
60
Ω
Iload = 5 mA,
VDD = 4.5 V
fI2C
I2CC
400
kHz
ns
tI2C1
I2C START condition setup
time
I2CC,
I2CD
300
300
tI2C2
I2C STOP condition setup
time
I2CC,
I2CD
ns
tI2C3
tI2C4
tI2C5
I2C clock low pulse time
I2C clock high pulse time
I2CC
I2CC
I2CC
1250
1250
80
ns
ns
ns
I2C data hold time before
rising edge of clock
tI2C6
I2C data hold time after
falling edge of clock
I2CC
80
ns
V
VI2COL
II2COH
tI2COL1
tI2COL2
I2C output low voltage
I2CC,
I2CD
0.3
1
ILOAD = 5 mA
VI2CH = 5.5 V
I2C output high leakage
current
I2CC,
I2CD
µA
ns
ns
I2C data output hold time
after falling edge of clock
I2CC,
I2CD
20
I2C data output setup time
before rising edge of clock
I2CC,
I2CD
250
fI2C = 400kHz
1/f
I2C
t
t
I2C3
I2C4
H
L
I2CC
t
t
t
t
I2C2
I2C1
I2C5
I2C6
H
L
I2CD as input
t
t
IC2OL1
I2COL2
H
L
I2CD as output
2
Fig. 4–14: I C timing diagram
Micronas
Dec. 4, 2003; 6251-598-2PD
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MAS 35xyH
PRELIMINARY DATA SHEET
4.6.3.3. S/PDIF Bus Input Characteristics
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Test Conditions
Min.
Max.
VS
fs1
fs2
fs3
tp
Signal amplitude
Biphase frequency
Biphase frequency
Biphase frequency
Biphase period
Rise time
SPDI,
SPDI2,
200
500
1000
mVpp
MHz
MHz
MHz
ns
SPDI,
SPDI2
3.072
2.822
2.048
326
±1000 ppm, fs = 48 kHz
SPDI,
SPDI2
±1000 ppm,
fs = 44.1 kHz
SPDI,
SPDI2
±1000 ppm, fs = 32 kHz
SPDI,
SPDI2
at fs = 48 kHz,
(highest sampling rate)
tr
SPDI,
SPDI2
0
65
65
60
ns
at fs = 48 kHz,
(highest sampling rate)
tf
Fall time
SPDI,
SPDI2
0
ns
at fs = 48 kHz,
(highest sampling rate)
Duty-cycle
SPDI,
40
50
%
at “1” and fs = 48 kHz
SPDI2
t
f
t
r
90%
10%
90%
10%
V
S
t
p
Fig. 4–15: Timing of the S/PDIF-input
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PRELIMINARY DATA SHEET
MAS 35xyH
4.6.3.4. S/PDIF Bus Output Characteristics
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Test Conditions
Min.
Max.
fs1
fs2
fs3
tp
Biphase frequency
Biphase frequency
Biphase frequency
Biphase period
SPDIFOUT
SPDIFOUT
SPDIFOUT
SPDIFOUT
3.072
MHz
MHz
MHz
ns
fs = 48 kHz
fs = 44.1 kHz
fs = 32 kHz
2.822
2.048
326
at fs = 48 kHz,
(highest sampling rate)
tr
tf
Rise time
Fall time
SPDIFOUT
SPDIFOUT
SPDIFOUT
0
0
2
2
ns
ns
%
Cload = 10 pF
Cload = 10 pF
Duty-cycle
50
at “1” and fs = 48 kHz
t
f
t
r
90%
10%
90%
10%
V
S
t
p
Fig. 4–16: Timing of the S/PDIF output
Micronas
Dec. 4, 2003; 6251-598-2PD
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MAS 35xyH
PRELIMINARY DATA SHEET
2
4.6.3.5. I S Bus Characteristics – Input
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Test Conditions
Min.
Max.
tSICLK
I2S clock input clock period
SIC
960
ns
ns
ns
Burst mode, mean data
rate < 150 kbit/s
tSIDDS
I2S data setup time before
falling edge of clock
SIC, SID
50
tSICLK
−100
tSIDDH
tSIIDS
I2S data hold time
SIC, SID
SIC, SII
50
50
I2S word strobe setup time
before falling(/rising) edge of
clock
tSICLK ns
−100
tSIIDH
tbw
I2S word strobe hold time
Burst wait time
SIC, SII
50
ns
ns
SIC,
SID
480
TSICLK
H
L
SIC
H
L
(SII)
SID
H
L
TSIDDS
TSIDDH
Fig. 4–17: Serial input of continuous data stream (SII must be held down). Data values are latched with falling clock
per default.
V
V
h
...
SIC
...
l
data valid at
falling edge of clock
V
V
h
SID
SII
...
31
30 29 28 27 26 25 ... 7
0
6 5 4 3 2 1 0
31 30 29 28 27 26 25
7
6
5
4
3
2
1
l
V
V
h
right 32-bit audio sample
left 32-bit audio sample
I2S
l
2
Fig. 4–18: Serial input of I S signal (PCM). Data values are latched with rising clock per default.
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Dec. 4, 2003; 6251-598-2PD
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PRELIMINARY DATA SHEET
MAS 35xyH
2
4.6.3.6. I S Characteristics – Output
Symbol
Parameter
Pin Name
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
tSCLKO
tSOISS
tSOODC
I2S clock output frequency
SOC
325
ns
ns
ns
48 kHz sample rate
2×32 bits/sample
I2S word strobe hold time
after falling edge of clock
SOC,
SOI
10
10
tSCLK
O/2
I2S data hold time after
falling edge of clock
SOC,
SOD
tSCLK
O/2
TSCLKO
H
L
SOC
H
L
SOI
TSOISS
TSOISS
H
L
SOD
TSOODC
2
Fig. 4–19: I S-output. Data values are valid with rising clock per default.
V
V
h
...
...
SOC
l
V
h
SOD
SOI
...
31
30 29 28 27 26 25 ... 7
0
6 5 4 3 2 1 0
31 30 29 28 27 26 25
7
6
5
4
3
2
1
V
l
V
V
h
right 32-bit audio sample
left 32-bit audio sample
l
Fig. 4–20: Schematic timing of the SDO interface in 32 bit/sample mode
Micronas
Dec. 4, 2003; 6251-598-2PD
67
MAS 35xyH
PRELIMINARY DATA SHEET
Detail A
Detail B
0
19 20
31 32
51 52
63 64
SCLOCK
SSYNC
SDATA
MSB
LSB (20-bit)
MSB
LSB (20-bit)
MSB
Subframe 1 (left) Audio Data
Aux Data “A” Subframe 1 (right) Audio Data Aux Data “B”
Subframe 1
Fig. 4–21: Serial interface format for multichannel mode.
4.6.4. Firmware Characteristics
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Test Conditions
Min.
Max.
Synchronization Times for Dolby Digital Mode
tDDsync
Synchronization on Dolby
Digital Bit Streams
140
120
ms
fs = 48 kHz, AC-3
fs = 48 kHz, MPEG
Synchronization Times for MPEG-Mode
tmpgsync
Synchronization on MPEG
Bit Streams
48
ms
Ranges
PLLRange
Tracking range of sampling
clock recovery PLL
−200
200
ppm
68
Dec. 4, 2003; 6251-598-2PD
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PRELIMINARY DATA SHEET
MAS 35xyH
5. Application
CTRL
4µ7
+5VD
SPDIF
SPDIF
4µ7
IC1
MAS
35xyH
PI16
PI15
PI14
PI14
SPDO
SPDIF out
4µ7
+5VD
10µ/16V
100n
10µ/16V
4µ7
+5VD
1n
Surround R
1n
Surround L
1n
Center
1n
1n
1n
IC2
TP
22µ
DPL
4519G
22µ
22µ
NC
NC
NC
22µ
10µ/16V
330n
330n
330n
330n
+8V
330n
4µ7
100µH
10µ/16V
+5VA
330n
10µ/16V
33µ/16V
Fig. 5–1: Part 1 of the application circuit diagram.
For details please refer to the Micronas Digital Multichannel Audio application kit
Micronas
Dec. 4, 2003; 6251-598-2PD
69
MAS 35xyH
PRELIMINARY DATA SHEET
Fig. 5–2: Part 2 of the application diagram.
For details please refer to the Micronas Digital Multichannel Audio application kit.
70
Dec. 4, 2003; 6251-598-2PD
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PRELIMINARY DATA SHEET
MAS 35xyH
Micronas
Dec. 4, 2003; 6251-598-2PD
71
MAS 35xyH
PRELIMINARY DATA SHEET
6. Data Sheet History
1. Preliminary Data Sheet: “MAS 3529H Audio
Decoder IC Family”, Sept. 24, 2002, 6251-598-1PD.
First release of the preliminary data sheet.
2. Preliminary Data Sheet: “MAS 35xyH Audio
Decoder IC Family”, Dec. 4, 2003, 6251-598-2PD.
Second release of the preliminary data sheet.
Major changes:
– Specification for PMQFP80-11 package added.
– New package diagram for PLCC44-4
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-598-2PD
72
Dec. 4, 2003; 6251-598-2PD
Micronas
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