MSP3405QG [TDK]
Consumer Circuit, CMOS, PQFP44, PLASTIC, QFP-44;
| 型号： | MSP3405QG |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Consumer Circuit, CMOS, PQFP44, PLASTIC, QFP-44 |
| 文件： | 总94页 (文件大小：1056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MSP 34x5G
Multistandard
Sound Processor Family
Edition July 11, 2000
6251-480-2PD
MICRONAS
MSP 34x5G
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
5
6
6
7
1.
Introduction
1.1.
1.2.
1.3.
Features of the MSP 34x5G Family and Differences to MSPD
MSP 34x5G Version List
MSP 34x5G Versions and their Application Fields
8
2.
Functional Description
9
2.1.
Architecture of the MSP 34x5G Family
Sound IF Processing
9
2.2.
9
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.3.
Analog Sound IF Input
9
Demodulator: Standards and Features
Preprocessing of Demodulator Signals
Automatic Sound Select
10
10
10
12
12
12
12
12
12
13
13
13
13
14
14
14
Manual Mode
Preprocessing for SCART and I2S Input Signals
Source Selection and Output Channel Matrix
Audio Baseband Processing
Automatic Volume Correction (AVC)
Loudspeaker Outputs
2.4.
2.5.
2.5.1.
2.5.2.
2.5.3.
2.6.
Quasi-Peak Detector
SCART Signal Routing
2.6.1.
2.6.2.
2.7.
SCART DSP In and SCART Out Select
Stand-by Mode
I2S Bus Interface
2.8.
ADR Bus Interface
2.9.
Digital Control I/O Pins and Status Change Indication
Clock PLL Oscillator and Crystal Specifications
2.10.
15
15
15
15
16
16
17
17
17
17
17
17
17
17
20
21
21
21
23
25
3.
Control Interface
3.1.
I2C Bus Interface
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.5.
3.1.5.1.
3.1.5.2.
3.1.5.3.
3.1.5.4.
3.2.
Device and Subaddresses
Internal Hardware Error Handling
Description of CONTROL Register
Protocol Description
Proposals for General MSP 34x5G I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I2C-Controlling
MSP 34x5G Programming Interface
User Registers Overview
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
Description of User Registers
STANDARD SELECT Register
Refresh of STANDARD SELECT Register
STANDARD RESULT Register
Write Registers on I2C Subaddress 10hex
Read Registers on I2C Subaddress 11hex
2
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Contents, continued
Page
Section
Title
26
36
37
37
37
37
37
38
38
38
3.3.2.6.
3.3.2.7.
3.4.
Write Registers on I2C Subaddress 12hex
Read Registers on I2C Subaddress 13hex
Programming Tips
3.5.
Examples of Minimum Initialization Codes
B/G-FM (A2 or NICAM)
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
3.5.6.
BTSC-Stereo
BTSC-SAP with SAP at Loudspeaker Channel
FM-Stereo Radio
Automatic Standard Detection
Software Flow for Interrupt driven STATUS Check
40
40
42
45
47
51
53
53
54
54
54
55
56
57
57
58
59
60
61
63
65
65
66
69
4.
Specifications
4.1.
Outline Dimensions
4.2.
Pin Connections and Short Descriptions
Pin Description
4.3.
4.4.
Pin Configurations
4.5.
Pin Circuits
4.6.
Electrical Characteristics
4.6.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.2.4.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
4.6.3.5.
4.6.3.6.
4.6.3.7.
4.6.3.8.
4.6.3.9.
4.6.3.10.
Absolute Maximum Ratings
Recommended Operating Conditions
General Recommended Operating Conditions
Analog Input and Output Recommendations
Recommendations for Analog Sound IF Input Signal
Crystal Recommendations
Characteristics
General Characteristics
Digital Inputs, Digital Outputs
Reset Input and Power-Up
I2C Bus Characteristics
I2S-Bus Characteristics
Analog Baseband Inputs and Outputs, AGNDC
Sound IF Input
Power Supply Rejection
Analog Performance
Sound Standard Dependent Characteristics
72
72
73
74
74
75
75
5.
Appendix A: Overview of TV Sound Standards
NICAM 728
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
A2 Systems
BTSC-Sound System
Japanese FM Stereo System (EIA-J)
FM Satellite Sound
FM-Stereo Radio
76
77
78
78
6.
Appendix B: Manual/Compatibility Mode
6.1.
6.2.
6.3.
Demodulator Write and Read Registers for Manual/Compatibility Mode
DSP Write and Read Registers for Manual/Compatibility Mode
Manual/Compatibility Mode: Description of Demodulator Write Registers
Micronas
3
MSP 34x5G
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
78
78
79
80
80
81
83
84
84
86
86
86
86
87
87
87
87
88
88
88
88
88
88
89
89
89
89
89
90
90
90
90
90
6.3.1.
6.3.1.1.
6.3.1.2.
6.3.2.
6.3.3.
6.3.4.
6.3.5.
6.3.6.
6.3.7.
6.4.
Automatic Switching between NICAM and Analog Sound
Function in Automatic Sound Select Mode
Function in Manual Mode
A2 Threshold
Carrier-Mute Threshold
Register AD_CV
Register MODE_REG
FIR-Parameter, Registers FIR1 and FIR2
DCO-Registers
Manual/Compatibility Mode: Description of Demodulator Read Registers
NICAM Mode Control/Additional Data Bits Register
Additional Data Bits Register
6.4.1.
6.4.2.
6.4.3.
6.4.4.
6.4.5.
6.4.6.
6.4.7.
6.5.
CIB Bits Register
NICAM Error Rate Register
PLL_CAPS Readback Register
AGC_GAIN Readback Register
Automatic Search Function for FM-Carrier Detection in Satellite Mode
Manual/Compatibility Mode: Description of DSP Write Registers
Additional Channel Matrix Modes
6.5.1.
6.5.2.
6.5.3.
6.5.4.
6.5.5.
6.5.6.
6.5.7.
6.6.
Volume Modes of SCART1 Output
FM Fixed Deemphasis
FM Adaptive Deemphasis
NICAM Deemphasis
Identification Mode for A2 Stereo Systems
FM DC Notch
Manual/Compatibility Mode: Description of DSP Read Registers
Stereo Detection Register for A2 Stereo Systems
DC Level Register
6.6.1.
6.6.2.
6.7.
Demodulator Source Channels in Manual Mode
Terrestric Sound Standards
6.7.1.
6.7.2.
6.8.
SAT Sound Standards
Exclusions of Audio Baseband Features
Compatibility Restrictions to MSP 34x0D
6.9.
92
92
93
7.
Appendix D: Application Information
Phase Relationship of Analog Outputs
Application Circuit
7.1.
7.2.
94
94
8.
9.
Appendix E: MSP 34x5G Version History
Data Sheet History
License Notice:
“Dolby Pro Logic” is a trademark of Dolby Laboratories.
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec-
tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to
use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
4
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Multistandard Sound Processor Family
EIA-J. The MSP 34x5G has optimum stereo perfor-
mance without any adjustments.
Release Note: Revision bars indicate significant
changes to the previous edition. The hardware and
software description in this document is valid for
the MSP 34x5G version B8 and following versions.
All MSP 34xxG versions are pin compatible to the
MSP 34xxD. Only minor modifications are necessary
to adapt a MSP 34xxD controlling software to the
MSP 34xxG. The MSP 34x5G further simplifies con-
trolling software. Standard selection requires a single
I2C transmission only.
1. Introduction
The MSP 34x5G family of single-chip Multistandard
Sound Processors covers the sound processing of all
analog TV standards worldwide, as well as the NICAM
digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to pro-
cessed analog AF-out, is performed in a single chip.
Figure 1–1 shows a simplified functional block diagram
of the MSP 34x5G.
Note: The MSP 34x5G version has reduced control
registers and less functional pins. The remaining regis-
ters are software-compatible to the MSP 34x0G. The
pinning is compatible to the MSP 34x0G.
The MSP 34x5G has built-in automatic functions: The
IC is able to detect the actual sound standard automat-
ically (Automatic Standard Detection). Furthermore,
pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/
stereo/bilingual; no I2C interaction is necessary (Auto-
matic Sound Selection).
This new generation of TV sound processing ICs now
includes versions for processing the multichannel tele-
vision sound (MTS) signal conforming to the standard
recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction is per-
formed alignment-free.
The MSP 34x5G can handle very high FM deviations
even in conjunction with NICAM processing. This is
especially important for the introduction of NICAM in
China.
Other processed standards are the Japanese FM-FM
multiplex standard (EIA-J) and the FM-Stereo-Radio
standard.
The ICs are produced in submicron CMOS technology.
The MSP 34x5G is available in the following packages:
PSDIP64, PSDIP52, PMQFP44, PLQFP64, and
PQFP80.
Current ICs have to perform adjustment procedures in
order to achieve good stereo separation for BTSC and
Loud-
speaker
Sound
De-
modulator
Pre-
processing
Loud-
speaker
Sound IF1
ADC
DAC
Processing
2
I S1
2
Prescale
I S
2
I S2
SCART1
DAC
SCART
DSP
Input
SCART2
MONO
ADC
Prescale
SCART
Output
Select
Select
SCART1
Fig. 1–1: Simplified functional block diagram of MSP 34x5G
Micronas
5
MSP 34x5G
PRELIMINARY DATA SHEET
1.1. Features of the MSP 34x5G Family and Differences to MSPD
Feature (New features not available for MSPD are shaded gray.)
3405
X
3415
X
3425
X
3445
X
3455
X
3465
X
2
Standard Selection with single I C transmission
Automatic Standard Detection of terrestrial TV standards
Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
Automatic Carrier Mute function
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Interrupt output programmable (indicating status change)
Loudspeaker channel with volume, balance, bass, treble, loudness
AVC: Automatic Volume Correction
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Spatial effect for loudspeaker channel
X
X
X
X
X
Two Stereo SCART (line) inputs, one Mono input; one Stereo SCART outputs
Complete SCART in/out switching matrix
X
X
X
X
X
X
X
X
X
X
2
2
Two I S inputs; one I S output
X
X
X
X
X
All analog Mono sound carriers including AM-SECAM L
All analog FM-Stereo A2 and satellite standards
X
X
X
X
X
X
X
X
All NICAM standards
X
X
Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
ASTRA Digital Radio (ADR) together with DRP 3510A
Demodulation of the BTSC multiplex signal and the SAP channel
Alignment free digital DBX noise reduction for BTSC Stereo and SAP
Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP
BTSC stereo separation (MSP 3425/45G also EIA-J) significantly better than spec.
SAP and stereo detection for BTSC system
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Korean FM-Stereo A2 standard
X
X
Alignment-free Japanese standard EIA-J
Demodulation of the FM-Radio multiplex signal
1.2. MSP 34x5G Version List
Version
Status
Description
MSP 3405G
MSP 3415G
MSP 3425G
MSP 3445G
MSP 3455G
MSP 3465G
available
available
available
available
available
available
FM Stereo (A2) Version
NICAM and FM Stereo (A2) Version
NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), and Japanese EIA-J system)
NTSC Version (A2 Korea, BTSC with DBX noise reduction, and Japanese EIA-J system)
Global Stereo Version (all sound standards)
Global Mono Version (all sound standards)
6
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
1.3. MSP 34x5G Versions and their Application Fields
Table 1–1 provides an overview of TV sound standards
that can be processed by the MSP 34x5G family. In
addition, the MSP 34x5G is able to handle the terres-
trial FM-Radio standard. With the MSP 34x5G, a com-
plete multimedia receiver covering all TV sound stan-
dards together with terrestrial and satellite radio sound
can be built; even ASTRA Digital Radio can be pro-
cessed (with a DRP 3510A coprocessor).
Table 1–1: TV Stereo Sound Standards covered by the MSP 34x5G IC Family (details see Appendix A)
MSP Version
TV-
System
Position of Sound
Carrier /MHz
Sound
Modulation
Color
System
Broadcast e.g. in:
5.5/5.7421875
5.5/5.85
FM-Stereo (A2)
PAL
Germany
B/G
FM-Mono/NICAM
AM-Mono/NICAM
FM-Mono/NICAM
FM-Stereo (A2, D/K1)
FM-Stereo (A2, D/K2)
FM-Stereo (A2, D/K3)
PAL
Scandinavia, Spain
France
L
I
6.5/5.85
SECAM-L
PAL
6.0/6.552
UK, Hong Kong
Slovak. Rep.
currently no broadcast
Poland
6.5/6.2578125
6.5/6.7421875
6.5/5.7421875
6.5/5.85
SECAM-East
PAL
D/K
SECAM-East
FM-Mono/NICAM (D/K, NICAM) PAL
FM-Mono
China, Hungary
6.5
7.02/7.2
7.38/7.56
etc.
FM-Stereo
Europe Sat.
ASTRA
Satellite
PAL
ASTRA Digital Radio (ADR)
with DRP 3510A
4.5/4.724212
FM-Stereo (A2)
FM-FM (EIA-J)
NTSC
Korea
M/N
4.5
NTSC
Japan
4.5
BTSC-Stereo + SAP
FM-Stereo Radio
NTSC, PAL
USA, Argentina
USA, Europe
FM-Radio
10.7
3465
All standards as above, but Mono demodulation only.
33 34 39 MHz
4.5 9 MHz
SAW Filter
Sound
Tuner
IF
Mixer
Loudspeaker
1
Mono
MSP 34x5G
Vision
Demo-
dulator
2
2
2
SCART1
SCART2
SCART1
SCART Output
SCART
Inputs
Composite
Video
2
2
I S1
ADR
I S2
Dolby
ADR
Decoder
DRP 3510A
Pro Logic
Processor
DPL 351xA
Fig. 1–2: Typical MSP 34x5G application
Micronas
7
Automatic
Standard Selection
Deemphasis:
Sound Select
DACM_L
DACM_R
Loud-
speaker
Channel
Matrix
FM/AM
AGC
Volume
D
A
FM/AM
Stereo or A/B
Stereo or A
Stereo or B
50/75 µs,
J17
DBX/MNR
Panda1
0
1
3
4
Bass/
Treble
Loud-
ness
Spatial
Effects
Balance
AVC
ANA_IN1+
Σ
DEMODULATOR
(incl. Carrier Mute)
A
D
Prescale
(0E
)
(08
)
(29
)
(02
(03
)
)
(04
)
(05
)
(01
)
(00
)
hex
hex
hex
hex
hex
hex
hex
hex
hex
Decoded
Standards:
− NICAM
− A2
NICAM
Deemphasis
J17
Beeper
(14
)
hex
Prescale
− AM
− BTSC
− EIA-J
− SAT
(10
)
hex
2
Standard
and Sound
Detection
I C
− FM-Radio
Read
Register
ADR-Bus
Interface
2
2
I S1
I S
2
2
I S
I S
Channel
Matrix
I2S_DA_OUT
I2S_DA_IN1
I2S_DA_IN2
5
6
Interface
Interface
Prescale
(0B
)
(16
)
hex
hex
2
I S2
2
I S
Interface
Prescale
2
(12
)
Quasi-Peak
Channel
Matrix
hex
I C
Quasi-Peak
Detector
Read
Register
(19
)
hex
(1A
)
hex
(0C
)
hex
Volume
SCART
D
A
SCART1
Channel
Matrix
SCART1_L/R
2
A
D
Prescale
(0A
)
(07
)
hex
(0D
)
hex
hex
SC1_OUT_L
SC1_OUT_R
(13
)
hex
SC1_IN_L
SC1_IN_R
SC2_IN_L
SC2_IN_R
MONO_IN
(13
)
hex
Fig. 2–1: Signal flow block diagram of the MSP 34x5G (input and output names correspond to pin names).
PRELIMINARY DATA SHEET
MSP 34x5G
2.1. Architecture of the MSP 34x5G Family
BTSC-Mono + SAP: Detection and FM demodulation
of the aural carrier resulting in the MTS/MPX signal.
Detection and evaluation of the pilot carrier, detection
and FM demodulation of the SAP-subcarrier. Process-
ing of the DBX noise reduction or Micronas Noise
Reduction (MNR).
Fig. 2–1 on page 8 shows a simplified block diagram of
the IC. The block diagram contains all features of the
MSP 3455G. Other members of the MSP 34x5G family
do not have the complete set of features: The demodu-
lator handles only a subset of the standards presented
in the demodulator block; NICAM processing is only
possible in the MSP 3415G and MSP 3455G (see
dashed block in Fig. 2–1).
Japan Stereo: Detection and FM demodulation of the
aural carrier resulting in the MPX signal. Demodulation
and evaluation of the identification signal and FM
demodulation of the (L-R)-carrier.
2.2. Sound IF Processing
FM-Satellite Sound: Demodulation of one or two FM
carriers. Processing of high-deviation mono or narrow
bandwidth mono, stereo, or bilingual satellite sound
according to the ASTRA specification.
2.2.1. Analog Sound IF Input
The input pins ANA_IN1+ and ANA_IN− offer the pos-
sibility to connect sound IF (SIF) sources to the
MSP 34x5G. The analog-to-digital conversion of the
preselected sound IF signal is done by an A/D-con-
verter. An analog automatic gain circuit (AGC) allows a
wide range of input levels. The high-pass filter formed
by the coupling capacitor at pin ANA_IN1+ (see
Section 7. “Appendix D: Application Information” on
page 92) is sufficient in most cases to suppress video
components. Some combinations of SAW filters and
sound IF mixer ICs, however, show large picture com-
ponents on their outputs. In this case, further filtering is
recommended.
FM-Stereo-Radio: Detection and FM demodulation of
the aural carrier resulting in the MPX signal. Detection
and evaluation of the pilot carrier and AM demodula-
tion of the (L-R)-carrier.
The demodulator blocks of all MSP 34x5G versions
have identical user interfaces. Even completely differ-
ent systems like the BTSC and NICAM systems are
controlled the same way. Standards are selected by
means of MSP Standard Codes. Automatic processes
handle standard detection and identification without
controller interaction. The key features of the
MSP 34x5G demodulator blocks are
2.2.2. Demodulator: Standards and Features
Standard Selection: The controlling of the demodula-
tor is minimized: All parameters, such as tuning fre-
quencies or filter bandwidth, are adjusted automati-
cally by transmitting one single value to the
STANDARD SELECT register. For all standards, spe-
cific MSP standard codes are defined.
The MSP 34x5G is able to demodulate all TV sound
standards worldwide including the digital NICAM sys-
tem. Depending on the MSP 34x5G version, the fol-
lowing demodulation modes can be performed:
A2-Systems: Detection and demodulation of two sep-
arate FM carriers (FM1 and FM2), demodulation and
evaluation of the identification signal of carrier FM2.
Automatic Standard Detection: If the TV sound stan-
dard is unknown, the MSP 34x5G can automatically
detect the actual standard, switch to that standard, and
respond the actual MSP standard code.
NICAM-Systems: Demodulation and decoding of the
NICAM carrier, detection and demodulation of the ana-
log (FM or AM) carrier. For D/K-NICAM, the FM carrier
may have a maximum deviation of 384 kHz.
Automatic Carrier Mute: To prevent noise effects or
FM identification problems in the absence of an FM
carrier, the MSP 34x5G offers a configurable carrier
mute feature, which is activated automatically if the TV
sound standard is selected by means of the STAN-
DARD SELECT register. If no FM carrier is detected at
one of the two MSP demodulator channels, the corre-
sponding demodulator output is muted. This is indi-
cated in the STATUS register.
Very high deviation FM-Mono: Detection and robust
demodulation of one FM carrier with a maximum devi-
ation of 540 kHz.
BTSC-Stereo: Detection and FM demodulation of the
aural carrier resulting in the MTS/MPX signal. Detec-
tion and evaluation of the pilot carrier, AM demodula-
tion of the (L-R)-carrier and detection of the SAP sub-
carrier. Processing of the DBX noise reduction or
Micronas Noise Reduction (MNR).
Micronas
9
MSP 34x5G
PRELIMINARY DATA SHEET
2.2.3. Preprocessing of Demodulator Signals
– “Stereo or A” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broad-
cast, it contains language A (on left and right).
The NICAM signals must be processed by a deempha-
sis filter and adjusted in level. The analog demodu-
lated signals must be processed by a deemphasis fil-
ter, adjusted in level, and dematrixed. The correct
deemphasis filters are already selected by setting the
standard in the STANDARD SELECT register. The
level adjustment has to be done by means of the FM/
AM and NICAM prescale registers. The necessary
dematrix function depends on the selected sound
standard and the actual broadcasted sound mode
(mono, stereo, or bilingual). It can be manually set by
the FM Matrix Mode register or automatically by the
Automatic Sound Selection.
– “Stereo or B” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broad-
cast, it contains language B (on left and right).
Fig. 2–2 and Table 2–2 show the source channel
assignment of the demodulated signals in case of
Automatic Sound Select mode for all sound standards.
Note: The analog primary input channel contains the
signal of the mono FM/AM carrier or the L+R signal of
the MPX carrier. The secondary input channel con-
tains the signal of the 2nd FM carrier, the L-R signal of
the MPX carrier, or the SAP signal.
2.2.4. Automatic Sound Select
LS Ch.
Matrix
In the Automatic Sound Select mode, the dematrix
function is automatically selected based on the identifi-
cation information in the STATUS register. No I2C inter-
action is necessary when the broadcasted sound
mode changes (e.g. from mono to stereo).
primary
channel
FM/AM
0
1
FM/AM
secondary
channel
Prescale
Stereo or A/B
Automatic
Sound
Select
Output-Ch.
matrices
must be set
once to
NICAM
NICAM A
NICAM B
Stereo or A
Stereo or B
3
4
stereo.
The demodulator supports the identification check by
switching between mono-compatible standards (stan-
dards that have the same FM-Mono carrier) automati-
cally and non-audible. If B/G-FM or B/G-NICAM is
selected, the MSP will switch between these stan-
dards. The same action is performed for the standards:
D/K1-FM, D/K2-FM, and D/K-NICAM. Switching is only
done in the absence of any stereo or bilingual identifi-
cation. If identification is found, the MSP keeps the
detected standard.
Prescale
Fig. 2–2: Source channel assignment of demodulated
signals in Automatic Sound Select Mode
2.2.5. Manual Mode
Fig. 2–3 shows the source channel assignment of
demodulated signals in case of manual mode. If man-
ual mode is required, more information can be found in
Section 6.7. “Demodulator Source Channels in Manual
Mode” on page 90.
In case of high bit-error rates, the MSP 34x5G auto-
matically falls back from digital NICAM sound to ana-
log FM or AM mono.
Table 2–1 summarizes all actions that take place when
Automatic Sound Select is switched on.
LS Ch.
Matrix
primary
channel
FM/AM
FM/AM
0
1
FM-Matrix
To provide more flexibility, the Automatic Sound Select
block prepares four different source channels of
demodulated sound (Fig. 2–2). By choosing one of the
four demodulator channels, the preferred sound mode
can be selected for each of the output channels (loud-
speaker, headphone, etc.). This is done by means of
the Source Select registers.
secondary
channel
Prescale
Output-Ch.
matrices
must be set
according to
the standard.
NICAM
NICAM A
NICAM B
NICAM
(Stereo or A/B)
Prescale
Fig. 2–3: Source channel assignment of demodulated
signals in Manual Mode
The following source channels of demodulated sound
are defined:
– “FM/AM” channel: Analog mono sound, stereo if
available. In case of NICAM, analog mono only
(FM or AM mono).
– “Stereo or A/B” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broad-
cast, it contains both languages A (left) and B
(right).
10
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 2–1: Performed actions of the Automatic Sound Selection
Selected TV Sound Standard
Performed Actions
B/G-FM, D/K-FM, M-Korea,
and M-Japan
Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four
demodulator source channels according to Table 2–2.
B/G-NICAM, L-NICAM, I-NICAM,
D/K-NICAM
Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four
demodulator source channels according to Table 2–2.
In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches
back to NICAM if possible. A hysteresis prevents periodical switching.
B/G-FM, B/G-NICAM
or
Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and non-
audible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound
carrier.
Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the
absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP
keeps the corresponding standard.
D/K1-FM, D/K2-FM, D/K3-FM,
and D/K-NICAM
BTSC-STEREO, FM Radio
M-BTSC-SAP
Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator
source channels according to Table 2–2. Detection of the SAP carrier.
In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP
switches automatically to SAP (see Table 2–2).
Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select
Source Channels in Automatic Sound Select Mode
Broadcasted Selected
Broadcasted
Sound Mode
FM/AM
(source select: 0)
Stereo or A/B
(source select: 1)
Stereo or A
(source select: 3)
Stereo or B
(source select: 4)
Sound
MSP Standard
Standard
Code3)
M-Korea
B/G-FM
D/K-FM
M-Japan
02
MONO
Mono
Mono
Mono
Stereo
A
Mono
Stereo
B
03, 081)
04, 05, 07, 0B1)
30
STEREO
Stereo
Stereo
BILINGUAL:
Left = A
Languages A and B
Right = B
Right = B
B/G-NICAM
L-NICAM
08, 032)
09
NICAM not available or analog Mono
error rate too high
analog Mono
analog Mono
analog Mono
I-NICAM
0A
0B, 042), 052)
0C
MONO
analog Mono
analog Mono
analog Mono
NICAM Mono
NICAM Stereo
NICAM Mono
NICAM Stereo
NICAM A
NICAM Mono
NICAM Stereo
NICAM B
D/K-NICAM
D/K-NICAM
(with high
STEREO
deviation FM)
BILINGUAL:
Languages A and B
Left = NICAM A
Right = NICAM B
20, 21
20
MONO
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Mono
Stereo
Mono
Stereo
SAP
STEREO
MONO + SAP
STEREO + SAP
MONO + SAP
BTSC
21
Left = Mono
Right = SAP
Left = Mono
Right = SAP
STEREO + SAP
Left = Mono
Right = SAP
Left = Mono
Right = SAP
Mono
SAP
FM Radio
40
MONO
Mono
Mono
Mono
Mono
STEREO
Stereo
Stereo
Stereo
Stereo
1)
The Automatic Sound Select process will automatically switch to the mono compatible analog standard.
The Automatic Sound Select process will automatically switch to the mono compatible digital standard.
The MSP Standard Codes are defined in Table 3–7 on page 20.
2)
3)
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11
MSP 34x5G
PRELIMINARY DATA SHEET
2.3. Preprocessing for SCART and
I2S Input Signals
2.5. Audio Baseband Processing
2.5.1. Automatic Volume Correction (AVC)
The SCART and I2S inputs need only be adjusted in
level by means of the SCART and I2S prescale regis-
ters.
Different sound sources (e.g. terrestrial channels, SAT
channels, or SCART) fairly often do not have the same
volume level. Advertisements during movies usually
have a higher volume level than the movie itself. This
results in annoying volume changes. The AVC solves
this problem by equalizing the volume level.
2.4. Source Selection and Output Channel Matrix
The Source Selector makes it possible to distribute all
source signals (one of the demodulator source chan-
nels or SCART) to the desired output channels (loud-
speaker, etc.). All input and output signals can be pro-
cessed simultaneously. Each source channel is
identified by a unique source address.
To prevent clipping, the AVC’s gain decreases quickly
in dynamic boost conditions. To suppress oscillation
effects, the gain increases rather slowly for low level
inputs. The decay time is programmable by means of
the AVC register (see page 30).
For each output channel, the sound mode can be set
to sound A, sound B, stereo, or mono by means of the
output channel matrix.
For input signals ranging from −24 dBr to 0 dBr, the
AVC maintains a fixed output level of −18 dBr. Fig. 2–4
shows the AVC output level versus its input level. For
prescale and volume registers set to 0 dB, a level of
0 dBr corresponds to full scale input/output. This is
If Automatic Sound Select is on, the output channel
matrix can stay fixed to stereo (transparent) for demod-
ulated signals.
– SCART input/output 0 dBr = 2.0 Vrms
– Loudspeaker output 0 dBr = 1.4 Vrms
output level
[dBr]
−18
−24
input level
[dBr]
−30
−24
−18
−12
−6
0
Fig. 2–4: Simplified AVC characteristics
2.5.2. Loudspeaker Outputs
The following baseband features are implemented in
the loudspeaker output channels: bass/treble, loud-
ness, balance, and volume. A square wave beeper can
be added to the loudspeaker channel.
2.5.3. Quasi-Peak Detector
The quasi-peak readout register can be used to read
out the quasi-peak level of any input source. The fea-
ture is based on following filter time constants:
attack time: 1.3 ms
decay time: 37 ms
12
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
2.6. SCART Signal Routing
2.7. I2S Bus Interface
2.6.1. SCART DSP In and SCART Out Select
The MSP 34x5G has a synchronous master/slave
input/output interface running on 32 kHz.
The SCART DSP Input Select and SCART Output
Select blocks include full matrix switching facilities. To
design a TV set with two pairs of SCART-inputs and
one pair of SCART-outputs, no external switching
hardware is required. The switches are controlled by
the ACB user register (see page 34).
The interface accepts two formats:
1. I2S_WS changes at the word boundary
2. I2S_WS changes one I2S-clock period before the
word boundaries.
All I2S options are set by means of the MODUS and
the I2S_CONFIG registers.
2.6.2. Stand-by Mode
The synchronous I2S bus interface consists of five
pins:
If the MSP 34x5G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP
(‘Stand-by’-mode), the SCART switches maintain
their position and function. This allows the copying
from selected SCART-inputs to SCART-outputs in the
TV set’s stand-by mode.
– I 2 S _ D A _ I N 1 , I 2 S _ D A _ I N 2 :
I2S serial data input: 16, 18....32 bits per sample
– I2S_DA_OUT:
I2S serial data output: 16, 18...32 bits per sample
– I2S_CL:
In case of power on or starting from stand-by (switch-
ing on the DVSUP and AVSUP, RESETQ going high
2 ms later), all internal registers except the ACB regis-
ter (page 34) are reset to the default configuration (see
Table 3–5 on page 18). The reset position of the ACB
register becomes active after the first I2C transmission
into the Baseband Processing part (subaddress
12hex). By transmitting the ACB register first, the reset
state can be redefined.
I2S serial clock
– I2S_WS:
I2S word strobe signal defines the left and right
sample
If the MSP 34x5G serves as the master on the I2S
interface, the clock and word strobe lines are driven by
the IC. In this mode, only 16 or 32 bits per sample can
be selected. In slave mode, these lines are input to the
IC and the MSP clock is synchronized to 576 times the
I2S_WS rate (32 kHz). NICAM operation is not possi-
ble in slave mode.
An I2S timing diagram is shown in Fig. 4–28 on
page 62.
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MSP 34x5G
PRELIMINARY DATA SHEET
2.8. ADR Bus Interface
2.10. Clock PLL Oscillator and
Crystal Specifications
For the ASTRA Digital Radio System (ADR), the
MSP 3405G, MSP 3415G, and MSP 3455G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x5G should be provided on a
feature connector:
The MSP 34x5G derives all internal system clocks
from the 18.432-MHz oscillator. In NICAM mode, the
clock is phase-locked to the corresponding source.
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note, that for the
phase-locked mode (NICAM, I2S slave), crystals with
tighter tolerance are required.
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
Remark on using the crystal:
– I2S_WS
External capacitors at each crystal pin to ground are
required. They are necessary for tuning the open-loop
frequency of the internal PLL and for stabilizing the fre-
quency in closed-loop operation. The higher the
capacitors, the lower the resulting clock frequency. The
nominal free running frequency should match
18.432 MHz as closely as possible.
– I2S_CL
– ADR_CL, ADR_WS, ADR_DA
For more details, please refer to the DRP 3510A data
sheet.
2.9. Digital Control I/O Pins and
Status Change Indication
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 34). This enables the controlling of external
hardware switches or other devices via I2C-bus.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 23).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 25).
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary; I2C-bus interactions are reduced to a
minimum (see STATUS register on page 25 and
MODUS register on page 23).
14
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PRELIMINARY DATA SHEET
MSP 34x5G
3. Control Interface
typical response time is about 0.3 ms. If the MSP can-
not accept another complete byte of data until it has
performed some other function (for example, servicing
an internal interrupt), it will hold the clock line I2C_CL
LOW to force the transmitter into a wait state. The
positions within a transmission where this may happen
are indicated by ’Wait’ in section Section 3.1.4. The
maximum wait period of the MSP during normal opera-
tion mode is less than 1 ms.
3.1. I2C Bus Interface
3.1.1. Device and Subaddresses
The MSP 34x5G is controlled via the I2C bus slave
interface.
The IC is selected by transmitting one of the
MSP 34x5G device addresses. In order to allow up to
three MSP ICs to be connected to a single bus, an
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 34x5G responds to different device addresses. A
device address pair is defined as a write address and a
read address (see Table 3–1).
3.1.2. Internal Hardware Error Handling
In case of any hardware problems (e.g. interruption of
the power supply of the MSP), the MSP’s wait period is
extended to 1.8 ms. After this time period elapses, the
MSP releases data and clock lines.
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condi-
tion, reading of the addressed data is completed by
sending the device read address and reading two
bytes of data. Refer to Section 3.1.4. for the I2C bus
protocol and to Section 3.4. “Programming Tips” on
page 37 for proposals of MSP 34x5G I2C telegrams.
See Table 3–2 for a list of available subaddresses.
Indication and solving the error status:
To indicate the error status, the remaining acknowl-
edge bits of the actual I2C-protocol will be left high.
Additionally, bit[14] of CONTROL is set to one. The
MSP can then be reset via the I2C bus by transmitting
the RESET condition to CONTROL.
Indication of reset:
Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CON-
TROL register by the controller via I2C bus.
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I2C bus is shown in
Fig. 4–27 on page 60.
Due to the internal architecture of the MSP 34x5G, the
IC cannot react immediately to an I2C request. The
Table 3–1: I2C Bus Device Addresses
ADR_SEL
Low
High
Read
Left Open
Read
89hex
Mode
Write
Read
Write
Write
MSP device address
80hex
81hex
84hex
85hex
88hex
Table 3–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Read/Write
Write: Software reset of MSP (see Table 3–3)
Read: Hardware error status of MSP
TEST
0000 0001
0001 0000
0001 0001
0001 0010
0001 0011
01
10
11
12
13
Write
Write
Write
Write
Write
only for internal use
WR_DEM
RD_DEM
WR_DSP
RD_DSP
write address demodulator
read address demodulator
write address DSP
read address DSP
Micronas
15
MSP 34x5G
PRELIMINARY DATA SHEET
3.1.3. Description of CONTROL Register
Table 3–3: CONTROL as a Write Register
Name
Subaddress
Bit[15] (MSB)
Bits[14:0]
CONTROL 00hex
1 : RESET
0 : normal
0
Table 3–4: CONTROL as a Read Register
Name
Subaddress
Bit[15] (MSB)
Bit[14]
Bits[13:0]
CONTROL 00hex
RESET status after last reading of
CONTROL:
Internal hardware status:
0 : no error occured
not of interest
1 : internal error occured
0 : no reset occured
1 : reset occured
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be reset.
3.1.4. Protocol Description
Write to DSP or Demodulator
S
write
device
address
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK
high low high low
P
Read from DSP or Demodulator
S
write
device
address
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK
high low
S
P
read
device
address
Wait ACK data-byte- ACK data-byte NAK
high low
P
Write to Control or Test Registers
S
write
device
address
Wait ACK sub-addr ACK data-byte ACK data-byte ACK
high low
Read from Control Register
S
write
device
address
Wait ACK
00hex
ACK
S
read
device
address
Wait ACK data-byte- ACK data-byte NAK
high low
P
Note: S =
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
P =
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from MSP indicating internal error state
Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.
This waiting time is max. 1 ms
16
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
1
0
I2C_DA
S
P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.5. Proposals for General MSP 34x5G
I2C Telegrams
3.2. Start-Up Sequence:
Power-Up and I2C-Controlling
3.1.5.1. Symbols
After POWER-ON or RESET (see Fig. 4–26), the IC is
in an inactive state. All registers are in the RESET
position (see Table 3–5 and Table 3–6), the analog
outputs are muted. The controller has to initialize all
registers for which a non-default setting is necessary.
daw
dar
<
write device address (80hex, 84hex or 88hex)
read device address (81hex, 85hex or 89hex
Start Condition
)
>
Stop Condition
aa
dd
Address Byte
Data Byte
3.3. MSP 34x5G Programming Interface
3.3.1. User Registers Overview
3.1.5.2. Write Telegrams
The MSP 34x5G is controlled by means of user regis-
ters. The complete list of all user registers are given in
the following tables. The registers are partitioned into
the Demodulator section (Subaddress 10hex for writ-
ing, 11hex for reading) and the Baseband Processing
sections (Subaddress 12hex for writing, 13hex for read-
ing).
<daw 00 d0 00>
write to CONTROL register
write data into demodulator
write data into DSP
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
3.1.5.3. Read Telegrams
<daw 00 <dar dd dd>
read data from
CONTROL register
Write and read registers are 16 bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I2C bus have
to take place in 16-bit words (two byte transfers, with the
most significant byte transferred first). All write registers,
except the demodulator write registers are readable.
<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP
3.1.5.4. Examples
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
<80 00 80 00>
RESET MSP statically
Clear RESET
<80 00 00 00>
<80 10 00 20 00 03>
Set demodulator to stand. 03hex
For reasons of software compatibility to the
MSP 34x5D, an Manual/Compatibility Mode is avail-
able. More read and write registers together with a
detailed description of the expert mode can be found in
“Appendix B: Manual/Compatibility Mode” on page 76.
<80 11 02 00 <81 dd dd> Read STATUS
<80 12 00 08 01 20> Set loudspeaker channel
source to NICAM and
Matrix to STEREO
More examples of typical application protocols are
listed in Section 3.4. “Programming Tips” on page 37.
An overview of all MSP 34x5G Write Registers is
shown in Table 3–5; all Read Registers are given in
Table 3–6
Micronas
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MSP 34x5G
PRELIMINARY DATA SHEET
.
Table 3–5: List of MSP 34x5G Write Registers
Write Register
Address Bits
(hex)
Description and Adjustable Range
Reset
See
Page
2
I C Sub-Address = 10
; Registers are not readable
hex
STANDARD SELECT
MODUS
00 20
00 30
00 40
[15:0]
[15:0]
[15:0]
Initial Programming of complete Demodulator
00 00
00 00
00 00
21
23
24
2
Demodulator, Automatic and I S options
2
2
I S CONFIGURATION
Configuration of I S options
2
2
I C Sub-Address = 12
; Registers are all readable by using I C Sub-Address = 13
hex
hex
Volume loudspeaker channel
00 00
[15:8]
[7:0]
[+12 dB ... −114 dB, MUTE]
MUTE
29
Volume / Mode loudspeaker channel
1/8 dB Steps,
00
hex
Reduce Volume / Tone Control / Compromise
Balance loudspeaker channel [L/R]
00 01
[15:8]
[0..100 / 100 % and 100 /0..100 %]
[−127..0 / 0 and 0 / −127..0 dB]
100 %/100 % 30
linear mode
Balance mode loudspeaker
Bass loudspeaker channel
Treble loudspeaker channel
Loudness loudspeaker channel
Loudness filter characteristic
[7:0]
[Linear mode / logarithmic mode]
[+20 dB ... −12 dB]
00 02
00 03
00 04
[15:8]
[15:8]
[15:8]
[7:0]
0 dB
31
31
32
[+15 dB ... −12 dB]
0 dB
[0 dB ... +17 dB]
0 dB
[NORMAL, SUPER_BASS]
[−100 %...OFF...+100 %]
[SBE, SBE+PSE]
NORMAL
OFF
Spatial effect strength loudspeaker ch. 00 05
Spatial effect mode/customize
[15:8]
[7:0]
33
SBE+PSE
MUTE
Volume SCART1 output channel
Loudspeaker source select
Loudspeaker channel matrix
SCART1 source select
00 07
00 08
[15:8]
[15:8]
[7:0]
[+12 dB ... −114 dB, MUTE]
34
28
28
28
28
28
28
28
28
27
26
27
27
27
34
35
27
30
2
2
[FM/AM, NICAM, SCART, I S1, I S2]
FM/AM
SOUNDA
FM/AM
SOUNDA
FM/AM
SOUNDA
FM/AM
SOUNDA
[SOUNDA, SOUNDB, STEREO, MONO...]
2
2
00 0A
00 0B
00 0C
[15:8]
[7:0]
[FM/AM, NICAM, SCART, I S1, I S2]
SCART1 channel matrix
[SOUNDA, SOUNDB, STEREO, MONO...]
2
2
2
I S source select
[15:8]
[7:0]
[FM/AM, NICAM, SCART, I S1, I S2]
2
I S channel matrix
[SOUNDA, SOUNDB, STEREO, MONO...]
2
2
Quasi-peak detector source select
Quasi-peak detector matrix
Prescale SCART input
Prescale FM/AM
[15:8]
[7:0]
[FM/AM, NICAM, SCART, I S1, I S2]
[SOUNDA, SOUNDB, STEREO, MONO...]
00 0D
00 0E
[15:8]
[15:8]
[7:0]
[00
[00
... 7F
... 7F
]
]
00
00
hex
hex
hex
hex
hex
hex
FM matrix
[NO_MAT, GSTERERO, KSTEREO]
NO_MAT
Prescale NICAM
00 10
00 12
[15:8]
[15:8]
[15:0]
[15:0]
[15:8]
[15:8]
[00
[00
... 7F ] (MSP 3410G, MSP 3450G only)
00
10
00
hex
hex
hex
hex
hex
hex
2
Prescale I S2
... 7F
]
hex
ACB : SCART Switches a. D_CTR_I/O 00 13
Bits[15:0]
Beeper
00 14
00 16
00 29
[00
[00
... 7F ]/[00
... 7F ]
hex
0/0
hex
hex
hex
hex
2
Prescale I S1
... 7F
]
10
off
hex
hex
Automatic Volume Correction
[off, on, decay time]
18
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 3–6: List of MSP 34x5G Read Registers
Read Register
Address Bits
(hex)
Description and Adjustable Range
See
Page
2
I C Sub-Address = 11
; Registers are not writable
hex
STANDARD RESULT
00 7E
[15:0]
Result of Automatic Standard Detection (see Table 3–8)
(MSP 3415G, MSP 3440G, MSP 3455G only)
25
25
STATUS
02 00
[15:0]
Monitoring of internal settings e.g. Stereo, Mono, Mute etc.
2
I C Sub-Address = 13
; Registers are not writable
hex
Quasi-peak readout left
Quasi-peak readout right
MSP hardware version code
MSP major revision code
MSP product code
00 19
00 1A
00 1E
[15:0]
[00 ... 7FFF
]
16 bit two’s complement
] 16 bit two’s complement
hex
36
36
36
36
36
36
hex
hex
[15:0]
[15:8]
[7:0]
[00 ... 7FFF
hex
[00 ... FF
]
]
]
]
hex
hex
hex
hex
hex
[00 ... FF
hex
00 1F
[15:8]
[7:0]
[00 ... FF
hex
MSP ROM version code
[00 ... FF
hex
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MSP 34x5G
PRELIMINARY DATA SHEET
3.3.2. Description of User Registers
Table 3–7: Standard Codes for STANDARD SELECT register
MSP Standard Code TV Sound Standard
(Data in hex)
Sound Carrier
Frequencies in MHz
MSP 34x5G Version
Automatic Standard Detection
Starts Automatic Standard Detection and
00 01
all
sets detected standard
Standard Selection
00 02
00 03
00 04
00 05
00 06
M-Dual FM-Stereo
4.5/4.724212
5.5/5.7421875
6.5/6.2578125
6.5/6.7421875
6.5
3405, -15, -25, -45, -55
3405, -15, -55
1)
B/G-Dual FM-Stereo
2)
D/K1-Dual FM-Stereo
D/K2-Dual FM-Stereo
2)
3)
D/K -FM-Mono with HDEV3 , not detectable by
Automatic Standard Detection, for China
3)
HDEV3 SAT-Mono (i.e. Eutelsat, s. Table 6–18)
00 07
00 08
00 09
00 0A
00 0B
00 0C
D/K3-Dual FM-Stereo
6.5/5.7421875
5.5/5.85
1)
B/G-NICAM-FM
3415, -55
L-NICAM-AM
I-NICAM-FM
6.5/5.85
6.0/6.552
6.5/5.85
2)
D/K-NICAM-FM
4)
D/K-NICAM-FM with HDEV2 , not detectable by
6.5/5.85
Automatic Standard Detection, for China
3)
00 0D
D/K-NICAM-FM with HDEV3 , not detectable by
6.5/5.85
4.5
Automatic Standard Detection, for China
00 20
00 21
00 30
00 40
00 50
00 51
BTSC-Stereo
3425, -45, -55
BTSC-Mono + SAP
M-EIA-J Japan Stereo
4.5
3425, -45, -55
3425, -45, -55
3405, -15, -55
FM-Stereo Radio
10.7
SAT-Mono (see Table 6–18)
SAT-Stereo (see Table 6–18)
SAT ADR (Astra Digital Radio)
6.5
7.02/7.20
6.12
00 60
1)
In case of Automatic Sound Select, the B/G-codes 3
and 8
are equivalent.
hex
hex
2)
3)
4)
In case of Automatic Sound Select, the D/K-codes 4 , 5 , 7 , and B
are equivalent.
hex hex hex
hex
HDEV3: Max. FM deviation must not exceed 540 kHz
HDEV2: Max. FM deviation must not exceed 360 kHz
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Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
3.3.2.1. STANDARD SELECT Register
3.3.2.2. Refresh of STANDARD SELECT Register
The TV sound standard of the MSP 34x5G demodula-
tor is determined by the STANDARD SELECT Regis-
ter. There are two ways to use the STANDARD
SELECT Register:
A general refresh of the STANDARD SELECT register
is not allowed. However, the following method
enables watching the MSP 34x5G “alive” status and
detection of accidental resets (only versions B6 and
later):
– Setting up the demodulator for a TV sound standard
by sending the corresponding standard code with a
single I2C bus transmission.
– After Power-on, bit[15] of CONTROL will be set; it
must be read once to enable the reset-detection
feature.
– Starting the Automatic Standard Detection for ter-
restrial TV standards. This is the most comfortable
way to set up the demodulator (not for MSP 3435G).
Within 0.5 s the detection and setup of the actual TV
sound standard is performed. The detected stan-
dard can be read out of the STANDARD RESULT
register by the control processor. This feature is rec-
ommended for the primary setup of a TV set. Out-
puts should be muted during Automatic Standard
Detection.
– Reading of the CONTROL register and checking
the reset indicator bit[15] .
– If bit[15] is “0”, any refresh of the STANDARD
SELECT register is not allowed.
– If bit[15] is “1”, indicating a reset, a refresh of the
STANDARD SELECT register and all other MSPG
registers is required.
The Standard Codes are listed in Table 3–7.
3.3.2.3. STANDARD RESULT Register
Selecting a TV sound standard via the STANDARD
SELECT register initializes the demodulator. This
includes: AGC-settings and carrier mute, tuning fre-
quencies, FIR-filter settings, demodulation mode (FM,
AM, NICAM), deemphasis and identification mode.
If Automatic Standard Detection is selected in the
STANDARD SELECT register, status and result of the
Automatic Standard Detection process can be read out
of the STANDARD RESULT register. The possible
results are based on the mentioned Standard Code
and are listed in Table 3–8.
TV stereo sound standards that are unavailable for a
specific MSP version are processed in analog mono
sound of the standard. In that case, stereo or bilingual
processing will not be possible.
In cases where no sound standard has been detected
(no standard present, too much noise, strong interfer-
ers, etc.) the STANDARD RESULT register contains
00 00hex. In that case, the controller has to start further
actions (for example set the standard according to a
preference list or by manual input).
For a complete setup of the TV sound processing from
analog IF input to the source selection, the transmis-
sions as shown in Section 3.5. are necessary.
As long as the STANDARD RESULT register contains
a value greater than 07 FFhex, the Automatic Standard
Detection is still active. During this period, the MODUS
and STANDARD SELECT register must not be written.
The STATUS register will be updated when the Auto-
matic Standard Detection has finished
For reasons of software compatibility to the
MSP 34x5D, a Manual/Compatibility mode is available.
A detailed description of this mode can be found on
page 76.
If a present sound standard is unavailable for a specific
MSP-version, it detects and switches to the analog
mono sound of this standard.
Example:
The MSPs 3425G and 3445G will detect a B/G-NICAM
signal as standard 3 and will switch to the analog FM-
Mono sound.
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MSP 34x5G
PRELIMINARY DATA SHEET
Table 3–8: Results of the Automatic Standard
Detection
Broadcasted Sound
Standard
STANDARD RESULT Register
Read 007Ehex
Automatic Standard
Detection could not
find a sound standard
0000hex
B/G-FM
B/G-NICAM
I
0003hex
0008hex
000Ahex
FM-Radio
0040hex
M-Korea
M-Japan
M-BTSC
0002hex (if MODUS[14,13]=00)
0020hex (if MODUS[14,13]=01)
0030hex (if MODUS[14,13]=10)
0009hex (if MODUS[12]=0)
0004hex (if MODUS[12]=1)
L-AM
D/K1
D/K2
D/K3
L-NICAM
D/K-NICAM
0009hex (if MODUS[12]=0)
000Bhex (if MODUS[12]=1)
>07FFhex
Automatic Standard
Detection still active
22
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PRELIMINARY DATA SHEET
MSP 34x5G
3.3.2.4. Write Registers on I2C Subaddress 10hex
Table 3–9: Write registers on I2C subaddress 10hex
Register
Address
Function
Name
00 20hex
STANDARD SELECTION Register
STANDARD_SEL
Defines TV-Sound or FM-Radio Standard
bit[15:0] 00 01hex start Automatic Standard Detection
00 02hex MSP Standard Codes (see Table 3–7)
...
00 40hex
00 30hex
MODUS Register
MODUS
Preference in Automatic Standard Detection:
bit[15]
0
undefined, must be 0
bit[14:13]
detected 4.5 MHz carrier is interpreted as:1)
standard M (Korea)
standard M (BTSC)
standard M (Japan)
chroma carrier (M/N standards are ignored)
0
1
2
3
bit[12]
detected 6.5 MHz carrier is interpreted as:1)
standard L (SECAM)
standard D/K1, D/K2, D/K3, or D/K NICAM
0
1
General MSP 34x5G Options
bit[11:9]
bit[8]
0
undefined, must be 0
0/1
0/1
enable analog sound IF input ANA_IN_1+
bit[7]
active/tristate state of audio clock output pin
AUD_CL_OUT
bit[6]
bit[5]
I2S word strobe alignment
WS changes at data word boundary
WS changes one clock cycle in advance
master/slave mode of I2S interface (must be set to 0
(= Master) in case of NICAM mode)
active/tristate state of I2S output pins
0
1
0/1
0/1
0
bit[4]
bit[3]
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register.
see also: MODUS[1])
1
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
bit[2]
bit[1]
0
undefined, must be 0
0/1
disable/enable STATUS change indication by means of
the digital I/O pin D_CTR_I/O_1
Necessary condition: MODUS[3] = 0 (active)
bit[0]
0/1
off/on: Automatic Sound Select
1) Valid at the next start of Automatic Standard Detection.
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MSP 34x5G
PRELIMINARY DATA SHEET
Table 3–9: Write registers on I2C subaddress 10hex, continued
Register
Address
Function
Name
00 40hex
I2S CONFIGURATION Register
I2S_CONFIG
bit[15:1]
0
not used, must be set to “0”
bit[0]
I2S_CL frequency and I2S data sample length for
master mode
0
1
2 x 16 bit (1.024 MHz)
2 x 32 bit (2.048 MHz))
24
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PRELIMINARY DATA SHEET
MSP 34x5G
3.3.2.5. Read Registers on I2C Subaddress 11hex
Table 3–10: Read Registers on I2C Subaddress 11hex
Register
Address
Function
Name
00 7Ehex
STANDARD RESULT Register
STANDARD_RES
Readback of the detected TV sound or FM-Radio Standard
bit[15:0] 00 00hex Automatic Standard Detection could not find
a sound standard
00 02hex MSP Standard Codes (see Table 3–8)
...
00 40hex
07 FFhex Automatic Standard Detection still active
02 00hex
STATUS Register
STATUS
Contains all user relevant internal information about the status of the MSP
bit[15:10]
bit[8]
undefined
0/1
“1” indicates bilingual sound mode or SAP present
(internally evaluated from received analog or digital iden-
tification signals)
bit[7]
bit[6]
0/1
0/1
“1” indicates independent mono sound
(only for NICAM on MSP 3415G and MSP 3455G)
mono/stereo indication
(internally evaluated from received analog or digital iden-
tification signals)
bit[5,9]
00
01
10
analog sound standard (FM or AM) active
this pattern will not occur
digital sound (NICAM) available (MSP 3415G and
MSP 3455G only)
11
bad reception condition of digital sound (NICAM) due to:
a. high error rate
b. unimplemented sound code
c. data transmission only
bit[4]
bit[3]
bit[2]
0/1
0/1
low/high level of digital I/O pin D_CTR_I/O_1
low/high level of digital I/O pin D_CTR_I/O_0
0
1
detected secondary carrier (2nd A2 or SAP sub-carrier)
no secondary carrier detected
bit[1]
0
1
detected primary carrier (Mono or MPX carrier)
no primary carrier detected
bit[0]
undefined
If STATUS change indication is activated by means of MODUS[1]: Each
change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high
level. Reading the STATUS register resets D_CTR_I/O_1.
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MSP 34x5G
PRELIMINARY DATA SHEET
3.3.2.6. Write Registers on I2C Subaddress 12hex
Table 3–11: Write Registers on I2C Subaddress 12hex
Register
Address
Function
Name
PREPROCESSING
00 0Ehex FM/AM Prescale
PRE_FM
bit[15:8] 00hex
Defines the input prescale gain for the demodulated
...
FM or AM signal
7Fhex
00hex
off (RESET condition)
For all FM modes except satellite FM and AM-mode, the combinations of pres-
cale value and FM deviation listed below lead to internal full scale.
FM mode
bit[15:8] 7Fhex
48hex
28 kHz FM deviation
50 kHz FM deviation
75 kHz FM deviation
100 kHz FM deviation
150 kHz FM deviation
180 kHz FM deviation (limit)
30hex
24hex
18hex
13hex
FM high deviation mode (HDEV2, MSP Standard Code = Chex
)
bit[15:8] 30hex
14hex
150 kHz FM deviation
360 kHz FM deviation (limit)
FM very high deviation mode (HDEV3, MSP Standard Code = 6 and Dhex
)
bit[15:8] 20hex
1Ahex
450 kHz FM deviation
540 kHz FM deviation (limit)
Satellite FM with adaptive deemphasis
bit[15:8] 10hex recommendation
AM mode (MSP Standard Code = 9)
bit[15:8] 7Chex recommendation for SIF input levels from
0.1 Vpp to 0.8 Vpp
(Due to the AGC being switched on, the AM-output level
remains stable and independent of the actual SIF-level in
the mentioned input range)
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
(continued)
FM Matrix Modes
FM_MATRIX
00 0Ehex
Defines the dematrix function for the demodulated FM signal
bit[7:0]
00hex
01hex
02hex
03hex
no matrix (used for bilingual and unmatrixed stereo sound)
German stereo (Standard B/G)
Korean stereo (also used for BTSC, EIA-J and FM Radio)
sound A mono (left and right channel contain the mono
sound of the FM/AM mono carrier)
04hex
sound B mono
In case of Automatic Sound Select = on, the FM Matrix Mode is set automati-
cally. Writing to the FM/AM prescale register (00 0Ehex high part) is still allowed.
In order not to disturb the automatic process, the low part of any I2C transmis-
sion to this register is ignored. Therefore, any FM-Matrix readback values may
differ from data written previously.
In case of Automatic Sound Select = off, the FM Matrix Mode must be set as
shown in Table 6–17 of Appendix B.
To enable a Forced Mono Mode for all analog stereo systems by overriding the
internal pilot or identification evaluation, the following steps must be transmitted:
1. MODUS with bit[0] = 0 (Automatic Sound Select off)
2. FM Presc./Matrix with FM Matrix = Sound A Mono (SAP: Sound B Mono)
3. Select FM/AM source channel, with channel matrix set to “Stereo” (transparent)
00 10hex
NICAM Prescale
PRE_NICAM
Defines the input prescale value for the digital NICAM signal
bit[15:8] 00hex ... 7Fhex prescale gain
examples:
00hex
20hex
5Ahex
7Fhex
off
0 dB gain
9 dB gain (recommendation)
+12 dB gain (maximum gain)
00 16hex
00 12hex
I2S1 Prescale
I2S2 Prescale
PRE_I2S1
PRE_I2S2
Defines the input prescale value for digital I2S input signals
bit[15:8] 00hex ... 7Fhex prescale gain
examples:
00hex
10hex
7Fhex
off
0 dB gain (recommendation, RESET condition)
+18 dB gain (maximum gain)
00 0Dhex
SCART Input Prescale
PRE_SCART
Defines the input prescale value for the analog SCART input signal
bit[15:8] 00hex ... 7Fhex prescale gain
examples:
00hex
19hex
7Fhex
off (RESET condition)
0 dB gain (2 VRMS input leads to digital full scale)
+14 dB gain (400 mVRMS input leads to digital full scale)
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MSP 34x5G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SOURCE SELECT AND OUTPUT CHANNEL MATRIX
Source for:
00 08hex
00 0Ahex
00 0Bhex
00 0Chex
Loudspeaker Output
SCART1 DA Output
I2S Output
SRC_MAIN
SRC_SCART1
SRC_I2S
Quasi-Peak Detector
SRC_QPEAK
bit[15:8]
0
“FM/AM”: demodulated FM or AM mono signal
“Stereo or A/B”: demodulator Stereo or A/B signal
1
(in manual mode, this source is identical to the NICAM
source in the MSP 3410D)
3
4
“Stereo or A”: demodulator Stereo Sound or
Language A (only defined for Automatic Sound Select)
“Stereo or B”: demodulator Stereo Sound or
Language B (only defined for Automatic Sound Select)
2
5
6
SCART input
I2S1 input
I2S2 input
For demodulator sources, see Table 2–2.
Matrix Mode for:
Loudspeaker Output
SCART1 DA Output
I2S Output
00 08hex
00 0Ahex
00 0Bhex
00 0Chex
MAT_MAIN
MAT_SCART1
MAT_I2S
Quasi-Peak Detector
MAT_QPEAK
bit[7:0]
00hex
10hex
20hex
30hex
Sound A Mono (or Left Mono) (RESET condition)
Sound B Mono (or Right Mono)
Stereo (transparent mode)
Mono (sum of left and right inputs divided by 2)
special modes are available (see Section 6.5.1. on page 88)
In Automatic Sound Select mode, the demodulator source channels are set
according to Table 2–2. Therefore, the matrix modes of the corresponding out-
put channels should be set to “Stereo” (transparent).
28
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
LOUDSPEAKER PROCESSING
00 00hex
Volume Loudspeaker
VOL_MAIN
bit[15:8] volume table with 1 dB step size
7Fhex
7Ehex
...
+12 dB (maximum volume)
+11 dB
74hex
73hex
72hex
...
+1 dB
0 dB
−1 dB
02hex
01hex
00hex
FFhex
−113 dB
−114 dB
Mute (RESET condition)
Fast Mute (needs about 75 ms until the signal is com-
pletely ramped down)
bit[7:5]
higher resolution volume table
0
+0 dB
1
+0.125 dB increase in addition to the volume table
...
7
+0.875 dB increase in addition to the volume table
bit[4]
0
must be set to 0
bit[3:0]
clipping mode
0
1
2
reduce volume
reduce tone control
compromise mode
With large scale input signals, positive volume settings may lead to signal clipping.
The MSP 34x5G loudspeaker volume function is divided into a digital and an
analog section. With Fast Mute, volume is reduced to mute position by digital
volume only. Analog volume is not changed. This reduces any audible DC
plops. To turn volume on again, the volume step that has been used before Fast
Mute was activated must be transmitted.
If the clipping mode is set to “Reduce Volume”, the following rule is used: To
prevent severe clipping effects with bass or treble boosts, the internal volume is
automatically limited to a level where, in combination with either bass or treble
setting, the amplification does not exceed 12 dB.
If the clipping mode is “Reduce Tone Control”, the bass or treble value is
reduced if amplification exceeds 12 dB.
If the clipping mode is “Compromise Mode”, the bass or treble value and volume
are reduced half and half if amplification exceeds 12 dB.
Example:
Vol.: +6 dB
Bass: +9 dB Treble: +5 dB
Red. Volume
Red. Tone Con.
Compromise
3
6
4.5
9
6
7.5
5
5
5
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PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 29hex
Automatic Volume Correction (AVC) Loudspeaker Channel
bit[15:12] 00hex
08hex
AVC off (and reset internal variables)
AVC on
AVC
bit[11:8] 08hex
04hex
8 sec decay time
4 sec decay time (recommended)
2 sec decay time
AVC_DECAY
02hex
01hex
20 ms decay time (should be used for approx. 100 ms
after channel change)
Note: AVC should not be used in any Dolby Prologic mode (with DPL35xx),
except in PANORAMA or 3D-PANORAMA mode, when only the loudspeaker
output is active.
00 01hex
Balance Loudspeaker Channel
BAL_MAIN
bit[15:8] Linear Mode
7Fhex
7Ehex
...
Left muted, Right 100%
Left 0.8%, Right 100%
01hex
00hex
FFhex
...
Left 99.2%, Right 100%
Left 100%, Right 100%
Left 100%, Right 99.2%
82hex
81hex
Left 100%, Right 0.8%
Left 100%, Right muted
bit[15:8] Logarithmic Mode
7Fhex
7Ehex
...
Left −127 dB, Right 0 dB
Left −126 dB, Right 0 dB
01hex
00hex
FFhex
...
Left −1 dB, Right 0 dB
Left 0 dB, Right 0 dB
Left 0 dB, Right −1 dB
81hex
80hex
Left 0 dB, Right −127 dB
Left 0 dB, Right −128 dB
bit[3:0]
Balance Mode
0hex
1hex
linear
logarithmic
Positive balance settings reduce the left channel without affecting the right
channel; negative settings reduce the right channel leaving the left channel
unaffected.
30
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 02hex
Bass Loudspeaker Channel
BASS_MAIN
bit[15:8] extended range
7Fhex
78hex
70hex
68hex
+20 dB
+18 dB
+16 dB
+14 dB
bit[15:8] normal range
60hex
58hex
...
+12 dB
+11 dB
08hex
00hex
F8hex
...
+1 dB
0 dB
−1 dB
A8hex
A0hex
−11 dB
−12 dB
Higher resolution is possible: An LSB step in the normal range results in a gain
step of about 1/8 dB, in the extended range about 1/4 dB.
With positive bass settings, internal clipping may occur even with overall volume
less than 0 dB. This will lead to a clipped output signal. Therefore, it is not rec-
ommended to set bass to a value that, in conjunction with volume, would result
in an overall positive gain.
00 03hex
Treble Loudspeaker Channel
TREB_MAIN
bit[15:8] 78hex
+15 dB
+14 dB
70hex
...
08hex
00hex
F8hex
...
+1 dB
0 dB
−1 dB
A8hex
A0hex
−11 dB
−12 dB
Higher resolution is possible: An LSB step results in a gain step of about 1/8 dB.
With positive treble settings, internal clipping may occur even with overall vol-
ume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not
recommended to set treble to a value that, in conjunction with volume, would
result in an overall positive gain.
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PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 04hex
Loudness Loudspeaker Channel
LOUD_MAIN
bit[15:8] Loudness Gain
44hex
40hex
...
+17 dB
+16 dB
04hex
00hex
+1 dB
0 dB
bit[7:0]
Loudness Mode
00hex
04hex
normal (constant volume at 1kHz)
Super Bass (constant volume at 2kHz)
Higher resolution of Loudness Gain is possible: An LSB step results in a gain
step of about 1/4 dB.
Loudness increases the volume of low and high frequency signals, while keep-
ing the amplitude of the 1 kHz reference frequency constant. The intended loud-
ness has to be set according to the actual volume setting. Because loudness
introduces gain, it is not recommended to set loudness to a value that, in con-
junction with volume, would result in an overall positive gain.
The corner frequency for bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up. The point of constant vol-
ume is shifted from 1 kHz to 2 kHz.
32
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 05hex
Spatial Effects Loudspeaker Channel
SPAT_MAIN
bit[15:8] Effect Strength
7Fhex
3Fhex
...
Enlargement 100%
Enlargement 50%
01hex
00hex
FFhex
...
Enlargement 1.5%
Effect off
reduction 1.5%
C0hex
80hex
reduction 50%
reduction 100%
bit[7:4]
bit[3:0]
Spatial Effect Mode
0hex Stereo Basewidth Enlargement (SBE) and
Pseudo Stereo Effect (PSE). (Mode A)
2hex
Stereo Basewidth Enlargement (SBE) only. (Mode B)
Spatial Effect High-Pass Gain
0hex
2hex
4hex
6hex
8hex
max high-pass gain
2/3 high-pass gain
1/3 high-pass gain
min high-pass gain
automatic
There are several spatial effect modes available:
In Mode A (low byte = 00hex), the spatial effect depends on the source mode. If
the incoming signal is mono, Pseudo Stereo Effect is active; for stereo signals,
Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The
strength of the effect is controllable by the upper byte. A negative value reduces
the stereo image. A strong spatial effect is recommended for small TV sets
where loudspeaker spacing is rather close. For large screen TV sets, a more
moderate spatial effect is recommended.
In Mode B, only Stereo Basewidth Enlargement is effective. For mono input sig-
nals, the Pseudo Stereo Effect has to be switched on.
It is worth mentioning that all spatial effects affect amplitude and phase
response. With the lower 4 bits, the frequency response can be customized. A
value of 0hex yields a flat response for center signals (L = R) but a high-pass
function for L or R only signals. A value of 6hex has a flat response for L or R
only signals but a low-pass function for center signals. By using 8hex, the fre-
quency response is automatically adapted to the sound material by choosing an
optimal high-pass gain.
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MSP 34x5G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SCART OUTPUT CHANNEL
00 07hex Volume SCART1 Output Channel
VOL_SCART1
bit[15:8] volume table with 1 dB step size
7Fhex
7Ehex
...
+12 dB (maximum volume)
+11 dB
74hex
73hex
72hex
...
+1 dB
0 dB
−1 dB
02hex
01hex
00hex
−113 dB
−114 dB
Mute (RESET condition)
bit[7:5]
bit[4:0]
higher resolution volume table
0
+0 dB
1
+0.125 dB increase in addition to the volume table
...
7
+0.875 dB increase in addition to the volume table
01hex
this must be 01hex
SCART SWITCHES AND DIGITAL I/O PINS
00 13hex ACB Register
ACB_REG
Defines the level of the digital output pins and the position of the SCART switches
bit[15]
0/1
low/high of digital output pin D_CTR_I/O_0
(MODUS[3]=0)
bit[14]
0/1
low/high of digital output pin D_CTR_I/O_1
(MODUS[3]=0)
bit[13:5] SCART DSP Input Select
xxxx00xx0 SCART1 to DSP input (RESET position)
xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in
the channel matrix mode for the corresponding output
channels)
xxxx10xx0 SCART2 to DSP input
xxxx11xx1 mute DSP input
bit[13:5] SCART1 Output Select
xx00xxx0x undefined (RESET position)
xx01xxx0x SCART2 input to SCART1 output
xx10xxx0x MONO input to SCART1 output
xx11xxx0x SCART1 DA to SCART1 output
xx01xxx1x SCART1 input to SCART1 output
xx11xxx1x mute SCART1 output
The RESET position becomes active at the time of the first write transmission
on the control bus to the audio processing part. By writing to the ACB register
first, the RESET state can be redefined.
34
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PRELIMINARY DATA SHEET
MSP 34x5G
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
BEEPER
00 14hex
Beeper Volume and Frequency
BEEPER
bit[15:8] Beeper Volume
00hex
7Fhex
off
maximum volume
bit[7:0]
Beeper Frequency
01hex
40hex
FFhex
16 Hz (lowest)
1 kHz
4 kHz
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MSP 34x5G
PRELIMINARY DATA SHEET
3.3.2.7. Read Registers on I2C Subaddress 13hex
Table 3–12: Read Registers on I2C Subaddress 13hex
Register
Address
Function
Name
QUASI-PEAK DETECTOR READOUT
00 19hex
00 1Ahex
Quasi-Peak Detector Readout Left
Quasi-Peak Detector Readout Right
QPEAK_L
QPEAK_R
bit[15:0] 0hex ... 7FFFhex values are 16 bit two’s complement (only positive)
MSP 34X5G VERSION READOUT REGISTERS
00 1Ehex MSP Hardware Version Code
MSP_HARD
bit[15:8] 02hex
MSP 34x5G - B8
A change in the hardware version code defines hardware optimizations that
may have influence on the chip’s behavior. The readout of this register is iden-
tical to the hardware version code in the chip’s imprint.
MSP Major Revision Code
MSP_REVISION
MSP_PRODUCT
bit[7:0]
07hex
MSP 34x5G - B8
The major revision code of the MSP 34x5G is 7.
00 1Fhex
MSP Product Code
bit[15:8] 0Fhex
19hex
MSP 3415G - B8
MSP 3425G - B8
MSP 3445G - B8
MSP 3455G - B8
MSP 3465G - B8
2Dhex
37hex
41hex
By means of the MSP product code, the control processor is able to decide
which TV sound standards have to be considered.
MSP ROM Version Code
MSP_ROM
bit[7:0]
44hex
45hex
46hex
48hex
MSP 34x5G - A4
MSP 34x5G - B5
MSP 34x5G - B6
MSP 34x5G - B8
A change in the ROM version code defines internal software optimizations,
that may have influence on the chip’s behavior, e.g. new features may have
been included. While a software change is intended to create no compatibility
problems, customers that want to use the new functions can identify new
MSP 34x5G versions according to this number.
To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of
40hex is added to the ROM version code of the chip’s imprint.
36
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PRELIMINARY DATA SHEET
MSP 34x5G
3.4. Programming Tips
3.5. Examples of Minimum Initialization Codes
This section describes the preferred method for initial-
izing the MSP 34x5G. The initialization is grouped into
four sections:
Initialization of the MSP 34x5G according to these list-
ings reproduces sound of the selected standard on the
loudspeaker output. All numbers are hexadecimal. The
examples have the following structure:
– SCART Signal Path (analog signal path)
– Demodulator Input
1. Perform an I2C controlled reset of the IC.
2. Write MODUS register
– SCART and I2S Inputs
(with Automatic Sound Select).
– Output Channels
3. Set Source Selection for loudspeaker channel
(with matrix set to STEREO).
See Fig. 2–1 on page 8 for a complete signal flow.
4. Set Prescale
(FM and/or NICAM and dummy FM matrix).
SCART Signal Path
5. Write STANDARD SELECT register.
1. Select analog input for the SCART baseband pro-
cessing (SCART DSP Input Select) by means of the
ACB register.
6. Set Volume loudspeaker channel to 0 dB.
2. Select the source for each analog SCART output
(SCART Output Select) by means of the ACB regis-
ter.
3.5.1. B/G-FM (A2 or NICAM)
<80 00 80 00>
<80 00 00 00>
// Softreset
<80 10 00 30 20 03> // MODUS-Register: Automatic = on
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
Demodulator Input
<80 12 00 0E 24 03> // FM/AM-Prescale = 24hex,
FM-Matrix = MONO/SOUNDA
For a complete setup of the TV sound processing from
analog IF input to the source selection, the following
steps must be performed:
<80 12 00 10 00 5A> // NICAM-Prescale = 5A
hex
<80 10 00 20 00 03> // Standard Select: A2 B/G or NICAM B/G
or
<80 10 00 20 00 08>
1. Set MODUS register to the preferred mode and
Sound IF input.
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB
2. Set preferred prescale (FM and NICAM) values.
3. Write STANDARD SELECT register.
3.5.2. BTSC-Stereo
<80 00 80 00>
<80 00 00 00>
// Softreset
4. If Automatic Sound Select is not active:
Choose FM matrix repeatedly according to the
sound mode indicated in the STATUS register.
<80 10 00 30 20 03> // MODUS-Register: Automatic = on
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03> // FM/AM-Prescale = 24
,
hex
SCART and I2S Inputs
FM-Matrix = Sound A Mono
<80 10 00 20 00 20> // Standard Select: BTSC-STEREO
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB
1. Set preferred prescale for SCART.
2. Set preferred prescale for I2S inputs
(set to 0 dB after RESET).
3.5.3. BTSC-SAP with SAP at Loudspeaker Channel
<80 00 80 00>
<80 00 00 00>
// Softreset
Output Channels
<80 10 00 30 20 03> // MODUS-Register: Automatic = on
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
1. Select the source channel and matrix for each out-
put channel.
<80 12 00 0E 24 03> // FM/AM-Prescale = 24
,
hex
2. Set audio baseband processing.
FM-Matrix = Sound A Mono
<80 10 00 20 00 21> // Standard Select: BTSC-SAP
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB
3. Select volume for each output channel.
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37
MSP 34x5G
PRELIMINARY DATA SHEET
3.5.4. FM-Stereo Radio
<80 00 80 00>
// Softreset
<80 00 00 00>
<80 10 00 30 20 03> // MODUS-Register: Automatic = on
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03> // FM/AM-Prescale = 24
,
hex
FM-Matrix = Sound A Mono
<80 10 00 20 00 40> // Standard Select: FM-STEREO-RADIO
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB
3.5.5. Automatic Standard Detection
A detailed software flow diagram is shown in Fig. 3–2
on page 39.
<80 00 80 00>
<80 00 00 00>
// Softreset
<80 10 00 30 20 03> // MODUS-Register: Automatic = on
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03> // FM/AM-Prescale = 24
,
hex
FM-Matrix = Sound A Mono
<80 12 00 10 00 5A> // NICAM-Prescale = 5A
hex
<80 10 00 20 00 01> // Standard Select:
Automatic Standard Detection
// Wait till STANDARD RESULT contains a value ≤ 07FF
// IF STANDARD RESULT contains 0000
// do some error handling
// ELSE
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB
3.5.6. Software Flow for Interrupt driven STATUS
Check
A detailed software flow diagram is shown in Fig. 3–2
on page 39.
If the D_CTR_I/O_1 pin of the MSP 34x5G is con-
nected to an interrupt input pin of the controller, the fol-
lowing interrupt handler can be applied to be automati-
cally called with each status change of the
MSP 34x5G. The interrupt handler may adjust the TV
display according to the new status information.
Interrupt Handler:
<80 11 02 00 <81 dd dd> // Read STATUS
// adjust TV-display with given status information
// Return from Interrupt
38
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Write MODUS Register
:
Example for the essential bits:
[0] = 1
[1] = 1
[8] = 0
Automatic Sound Select = on
Enable interrupt if STATUS changes
ANA_IN1+ is selected
Define Preference for Automatic Standard
Detection:
[12] = 0
If 6.5 MHz, set SECAM-L
[14:13] = 3 Ignore 4.5 MHz carrier
Write SOURCE SELECT Settings
Example:
set loudspeaker Source Select to "Stereo or A"
set headphone Source Select to "Stereo or B"
set SCART_Out Source Select to "Stereo or A/B"
set Channel Matrix mode for all outputs to "Stereo"
Write FM/AM-Prescale
Write NICAM-Prescale
Write 01 into
STANDARD SELECT Register
(Start Automatic Standard Detection)
set previous standard or
set standard manually according
picture information
Result = 0
yes
?
no
expecting interrupt from MSP
In case of interrupt from
MSP to controller:
Read STATUS
Adjust TV-Display
If bilingual, adjust Source Select setting if required
Fig. 3–2: Software flow diagram for a minimum demodulator setup for a European multistandard set applying the
Automatic Sound Select feature
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MSP 34x5G
PRELIMINARY DATA SHEET
4. Specifications
4.1. Outline Dimensions
SPGS703000-1(P64)/1E
64
33
SPGS703000-1(P52)/1E
52
27
1
32
1
26
±0.1
19.3
±0.1
15.6
±0.1
57.7
±0.1
47.0
±0.05
18
±0.1
14
±0.06
0.28
±0.06
0.28
±0.5
±0.05
20.3
1
±1
±0.05
16.3
1
±0.06
0.48
±0.06
0.48
1.778
31 x 1.778 = 55.1
1.778
25 x 1.778 = 44.4
±0.1
±0.1
Fig. 4–1:
Fig. 4–2:
64-Pin Plastic Shrink Dual Inline Package
(PSDIP64)
52-Pin Plastic Shrink Dual Inline Package
(PSDIP52)
Weight approximately 9.0 g
Dimensions in mm
Weight approximately 5.5 g
Dimensions in mm
± 0.1
23 x 0.8 = 18.4
± 0.04
0.17
0.8
64
41
40
65
25
80
± 0.05
1.3
1
24
± 0.1
2.7
± 0.1
20
± 0.15
23.2
0.1
±0.2
3
SPGS705000-3(P80)/1E
Fig. 4–3:
80-Pin Plastic Quad Flat Pack Package
(PQFP80)
Weight approximately 1.6 g
Dimensions in mm
40
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
± 0.1
15 x 0.5 = 7.5
0.5
± 0.055
0.145
48
33
49
64
32
17
1
16
± 0.05
1.4
1.75
± 0.1
± 0.2
10
12
0.1
± 0.1
1.5
D0025/3E
Fig. 4–4:
64-Pin Plastic Low-Profile Quad Flat Pack
(PLQFP64)
Weight approximately 0.35 g
Dimensions in mm
± 0.1
10 x 0.8 = 8
0.8
± 0.06
0.17
33
23
34
22
12
44
1
11
± 0.1
2.0
± 0.2
± 0.1
10
13.2
0.1
± 0.2
2.15
SPGS706000-5(P44)/1E
Fig. 4–5:
44-Pin Plastic Metric Quad Flat Pack
(PMQFP44)
Weight approximately 0.4 g
Dimensions in mm
Micronas
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MSP 34x5G
PRELIMINARY DATA SHEET
4.2. Pin Connections and Short Descriptions
NC = not connected; leave vacant
LV = if not used, leave vacant
DVSS: if not used, connect to DVSS
X = obligatory; connect as described in circuit diagram
AHVSS: connect to AHVSS
Pin No.
Pin Name
Type
Connection Short Description
(if not used)
PQFP
80-pin
PLQFP PMQFP PSDIP
PSDIP
52-pin
64-pin
44-pin
64-pin
1
64
–
8
–
NC
LV
X
Not connected
I2C clock
2
1
2
3
4
5
6
7
8
12
13
14
15
16
17
–
9
7
I2C_CL
I2C_DA
I2S_CL
I2S_WS
I2S_DA_OUT
I2S_DA_IN1
ADR_DA
ADR_WS
ADR_CL
DVSUP
DVSUP
DVSUP
DVSS
IN/OUT
IN/OUT
3
10
11
12
13
14
15
16
17
–
8
X
I2C data
4
9
LV
LV
LV
LV
LV
LV
LV
X
I2S clock
5
10
11
12
13
14
15
–
I2S word strobe
I2S data output
I2S1 data input
ADR data output
ADR word strobe
ADR clock
6
7
8
9
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
18
–
9
Digital power supply +5 V
Digital power supply +5 V
Digital power supply +5 V
Digital ground
Digital ground
Digital ground
I2S2-data input
Not connected
Not connected
Not connected
Power-on-reset
Not connected
Not connected
Not connected
Not connected
−
–
–
–
X
−
19
20
–
18
–
16
–
X
10
−
X
–
–
DVSS
X
−
–
19
20
21
22
23
24
–
17
18
19
–
DVSS
X
11
12
13
14
15
16
−
21
–
I2S_DA_IN2
NC
LV
LV
LV
LV
X
–
NC
–
–
NC
22
–
20
–
RESETQ
NC
IN
LV
LV
LV
LV
–
–
–
NC
−
23
24
25
26
21
22
NC
17
NC
42
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Pin No.
Pin Name
Type
Connection Short Description
(if not used)
PQFP
80-pin
PLQFP PMQFP PSDIP
PSDIP
52-pin
64-pin
44-pin
64-pin
26
18
25
27
23
VREF2
X
Reference ground 2
high-voltage part
27
28
29
30
31
32
33
34
35
19
20
21
22
23
24
−
26
27
–
28
29
30
31
32
–
24
25
–
DACM_R
DACM_L
NC
OUT
OUT
LV
LV
LV
LV
LV
LV
LV
LV
X
Loudspeaker out, right
Loudspeaker out, left
Not connected
–
26
–
NC
Not connected
–
NC
Not connected
–
–
NC
Not connected
–
33
34
35
27
28
29
NC
Not connected
25
26
28
29
NC
Not connected
VREF1
Reference ground 1
high-voltage part
36
37
38
39
27
28
29
30
30
31
32
33
36
37
38
39
30
31
32
33
SC1_OUT_R
SC1_OUT_L
NC
OUT
OUT
LV
LV
LV
X
SCART 1 output, right
SCART 1 output, left
Not connected
AHVSUP
Analog power supply
8.0 V
40
41
42
43
44
45
31
32
−
34
–
40
–
34
–
CAPL_M
NC
X
Volume capacitor MAIN
Not connected
LV
LV
X
–
–
–
NC
Not connected
−
–
–
–
AHVSS
AHVSS
AGNDC
Analog ground
−
35
36
41
42
35
36
X
Analog ground
33
X
Analog reference voltage
high-voltage part
46
47
48
49
50
51
52
53
54
34
−
–
–
–
NC
LV
Not connected
–
43
44
45
46
47
–
–
NC
LV
Not connected
35
36
37
38
40
41
42
–
–
NC
LV
Not connected
–
–
NC
LV
Not connected
–
37
38
–
NC
LV
Not connected
–
NC
LV
Not connected
–
ASG
SC2_IN_L
SC2_IN_R
AHVSS
LV
Analog Shield Ground
SCART 2 input, left
SCART 2 input, right
37
38
49
50
39
40
IN
IN
LV
Micronas
43
MSP 34x5G
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Type
Connection Short Description
(if not used)
PQFP
80-pin
PLQFP PMQFP PSDIP
PSDIP
52-pin
64-pin
44-pin
64-pin
55
56
57
58
43
39
51
–
ASG
AHVSS
Analog Shield Ground
SCART 1 input, left
SCART 1 input, right
44
45
46
40
41
42
52
53
54
41
42
43
SC1_IN_L
SC1_IN_R
VREFTOP
IN
IN
LV
LV
X
Reference voltage IF
A/D converter
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
–
−
–
–
–
NC
LV
LV
X
Not connected
Mono input
47
−
43
–
55
–
44
–
MONO_IN
AVSS
AVSS
NC
IN
Analog ground
Analog ground
Not connected
Not connected
Analog power supply +5 V
Analog power supply +5 V
IF input 1
48
−
44
–
56
–
45
–
X
LV
LV
X
−
–
–
–
NC
−
–
–
–
AVSUP
AVSUP
ANA_IN1+
ANA_IN−
NC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
40
1
57
58
59
60
61
62
63
64
1
46
47
48
49
50
51
52
1
X
2
IN
IN
LV
LV
LV
X
3
IF common
–
Not connected
Test pin
4
TESTEN
XTAL_IN
XTAL_OUT
TP
IN
5
IN
X
Crystal oscillator
Crystal oscillator
Test pin
6
OUT
X
7
LV
LV
LV
LV
–
2
NC
Not connected
Not connected
Not connected
D_CTR_I/O_1
D_CTR_I/O_0
I2C Bus address select
Standby (low-active)
Not connected
–
2
–
NC
–
3
–
NC
8
4
3
D_CTR_I/O_1 IN/OUT LV
D_CTR_I/O_0 IN/OUT LV
9
5
4
10
11
–
6
5
ADR_SEL
STANDBYQ
NC
IN
IN
X
7
6
X
48
–
LV
44
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.3. Pin Description
Pin 26, VREF2 – Reference Ground 2
Reference analog ground. This pin must be connected
separately to the single ground point (AHVSS). VREF2
serves as a clean ground and should be used as the
reference for analog connections to the loudspeaker
and headphone outputs.
Pin numbers refer to the 80-pin PQFP package
Pin 1, NC – Pin not connected
Pin 2, I2C_CL – I2C Clock Input/Output (Fig. 4–12)
Via this pin the I2C bus clock signal has to be supplied.
The signal can be pulled down by the MSP in case of
wait conditions.
Pins 27, 28, DACM_R/L – Loudspeaker Outputs
(Fig. 4–23)
Output of the loudspeaker signal. A 1nF capacitor to
AHVSS must be connected to these pins. The DC off-
set on these pins depends on the selected loud-
speaker volume.
Pin 3, I2C_DA – I2C Data Input/Output (Fig. 4–12)
Via this pin the I2C bus data is written to or read from
the MSP.
Pins 29, 30, 31, 32, 33, 34, NC – Pins not connected
Pin 4, I2S_CL – I2S Clock Input/Output (Fig. 4–17)
Clock line for the I2S bus. In master mode, this line is
driven by the MSP; in slave mode, an external I2S
clock has to be supplied.
Pin 35, VREF1 – Reference Ground 1
Reference analog ground. This pin must be connected
separately to the single ground point (AHVSS). VREF1
serves as a clean ground and should be used as the
reference for analog connections to the SCART out-
puts.
Pin 5, I2S_WS – I2S Word Strobe Input/Output
(Fig. 4–17)
Word strobe line for the I2S bus. In master mode, this
line is driven by the MSP; in slave mode, an external
I2S word strobe has to be supplied.
Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs
(Fig. 4–25)
Output of the SCART1 signal. Connections to these
pins must use a 100 ohm series resistor and are
intended to be AC coupled.
Pin 6, I2S_DA_OUT – I2S Data Output (Fig. 4–11)
Output of digital serial sound data of the MSP on the
I2S bus.
Pin 38, NC – Pin not connected
Pin 7, I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–13)
First input of digital serial sound data to the MSP via
the I2S bus.
Pin 39, AHVSUP* – Analog Power Supply High Voltage
Power is supplied via this pin for the analog circuitry of
the MSP (except IF input). This pin must be connected
to the +8V supply.
Pin 8, ADR_DA – ADR Bus Data Output (Fig. 4–11)
Output of digital serial data to the DRP 3510A via the
ADR bus.
Pin 40, CAPLM – Volume Capacitor Loudspeakers
(Fig. 4–20)
Pin 9, ADR_WS – ADR Bus Word Strobe Output
(Fig. 4–11)
Word strobe output for the ADR bus.
A 10µF capacitor to AHVSUP must be connected to
this pin. It serves as smoothing filter for loudspeaker
volume changes in order to suppress audible plops.
The value of the capacitor can be lowered to 1µF if
faster response is required. The area encircled by the
trace lines should be minimized, keep traces as short
as possible. This input is sensitive for magnetic induc-
tion.
Pins 11, 12, 13, DVSUP* – Digital Supply Voltage
Power supply for the digital circuitry of the MSP. Must
be connected to a +5-V power supply.
Pins 14, 15, 16, DVSS* – Digital Ground
Ground connection for the digital circuitry of the MSP
Pins 41, 42, NC – Pins not connected.
Pin 17, I2S_DA_IN2 – I2S Data Input 2 (Fig. 4–13)
Second input of digital serial sound data to the MSP
via the I2S bus.
Pins 43, 44, AHVSS* – Ground for Analog Power Sup-
ply High Voltage
Ground connection for the analog circuitry of the MSP
(except IF input).
Pins 18, 19, 20, NC – Pins not connected
Pins 45, AGNDC – Internal Analog Reference Voltage
This pin serves as the internal ground connection for
the analog circuitry (except IF input). It must be con-
nected to the VREF pins with a 3.3 µF and a 100 nF
capacitor in parallel. This pins shows a DC level of typ-
ically 3.73 V.
Pin 21, RESETQ – Reset Input (Fig. 4–13)
In the steady state, high level is required. A low level
resets the MSP 34x0G.
Pins 22, 23, 24, 25, NC – Pins not connected
Micronas
45
MSP 34x5G
PRELIMINARY DATA SHEET
Pin 46, 47, 48, 49, 50, 51 NC – Pins not connected.
Pins71, 72, XTAL_IN, XTAL_OUT – Crystal Input and
Output Pins (Fig. 4–18)
Pin 52, ASG – Analog Shield Ground 2
Analog ground (AHVSS) should be connected to this
pin to reduce cross coupling between SCART inputs.
These pins are connected to an 18.432 MHz crystal
oscillator which is digitally tuned by integrated shunt
capacitances. An external clock can be fed into
XTAL_IN. The audio clock output signal AUD_CL_OUT
is derived form the oscillator. External capacitors at
each crystal pin to ground (AVSS) are required. It
should be verified by layout, that no supply current for
the digital circuitry is flowing through the ground con-
nection point.
Pins 53, 54, SC2_IN_L/R – SCART2 Inputs
(Fig. 4–22)
The analog input signal for SCART2 is fed to this pin.
Analog input connection must be AC coupled.
Pin 55, ASG – Analog Shield Ground 1
Analog ground (AHVSS) should be connected to this
pin to reduce cross coupling between SCART inputs.
Pin 73, TP – Test pin
Pins 74, 75, 76, NC – Pins not connected
Pins 56, 57, SC1_IN_L/R – SCART1 Inputs
(Fig. 4–22)
The analog input signal for SCART1 is fed to this pin.
Analog input connection must be AC coupled.
Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/
Output Pins (Fig. 4–17)
These pins serve as general purpose input/output
pins. Pin D_CTR_I/O_1 can be used as an interrupt
request pin to the controller.
Pin 58, VREFTOP – Reference Voltage IF AD Con-
verter (Fig. 4–19)
Via this pin, the reference voltage for the IF AD con-
verter is decoupled. It must be connected to AVSS
pins with a 10µF and a 100nF capacitor in parallel.
Traces must be kept short.
Pin 79, ADR_SEL – I2C Bus Address Select
(Fig. 4–16)
By means of this pin, one of 3 device addresses for the
MSP can be selected. The pin can be connected to
ground (I2C device addresses 80/81hex), to +5V supply
(84/85hex) or left open (88/89hex).
Pin 59, NC – Pin not connected
Pin 60, MONO_IN – Mono Input (Fig. 4–22)
The analog mono input signal is fed to this pin. Analog
input connection must be AC coupled.
Pin 80, STANDBYQ – Standby
In normal operation, this pin must be high. If the
MSP 34x5G is switched off by first pulling STANDBYQ
low and then (after >1µs delay) switching off DVSUP
and AVSUP, but keeping AHVSUP (‘Standby’-mode),
the SCART switches maintain their position and func-
tion.
Pins 61, 62, AVSS* – Ground for Analog Power Supply
Voltage
Ground connection for the analog IF input circuitry of
the MSP.
* Application Note:
Pins 63, 64, NC – Pins not connected
All ground pins should be connected to one low-resis-
tive ground plane. All supply pins should be connected
separately with short and low-resistive lines to the
power supply. Decoupling capacitors from DVSUP to
DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are
recommended as closely as possible to these pins.
Decoupling of DVSUP and DVSS is most important.
We recommend using more than one capacitor. By
choosing different values, the frequency range of
active decoupling can be extended. In our application
boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF. The
capacitor with the lowest value should be placed near-
est to the DVSUP and DVSS pins.
Pins 65, 66, AVSUP* – Analog Power Supply Voltage
Power is supplied via this pin for the analog IF input cir-
cuitry of the MSP. This pin must be connected to the
+5 V supply.
Pin 67, ANA_IN1+ – IF Input 1 (Fig. 4–19)
The analog sound if signal is supplied to this pin.
Inputs must be AC coupled. This pin is designed as
symmetrical input: ANA_IN1+ is internally connected
to one input of a symmetrical op amp, ANA_IN− to the
other.
Pin 68, ANA_IN− – IF Common (Fig. 4–19)
This pin serves as a common reference for ANA_IN1/
2+ inputs.
The ASG pins should be connected as closely as pos-
sible to the MSP ground. If they are lead with the SC1
or SC2 input lines as shielding lines, they should not
be connected to ground at the SCART connector.
Pin 69, NC – Pin not connected
Pin 70, TESTEN – Test Enable Pin (Fig. 4–13)
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
46
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.4. Pin Configurations
NC
NC
1
2
3
4
5
6
7
8
9
64 TP
TP
NC
1
2
3
4
5
6
7
8
9
52 XTAL_OUT
51 XTAL_IN
50 TESTEN
49 NC
63 XTAL_OUT
62 XTAL_IN
61 TESTEN
60 NC
NC
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
STANDBYQ
I2C_CL
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
STANDBYQ
NC
48 ANA_IN−
47 ANA_IN1+
46 AVSUP
45 AVSS
59 ANA_IN−
58 ANA_IN1+
57 AVSUP
56 AVSS
I2C_DA
I2C_CL
I2S_CL
44 MONO_IN
43 VREFTOP
42 SC1_IN_R
41 SC1_IN_L
40 SC2_IN_R
39 SC2_IN_L
38 NC
I2C_DA 10
I2S_CL 11
I2S_WS 12
I2S_DA_OUT 13
I2S_DA_IN1 14
ADR_DA 15
ADR_WS 16
ADR_CL 17
DVSUP 18
DVSS 19
55 MONO_IN
54 VREFTOP
53 SC1_IN_R
52 SC1_IN_L
51 ASG
I2S_WS 10
I2S_DA_OUT 11
I2S_DA_IN1 12
ADR_DA 13
ADR_WS 14
ADR_CL 15
DVSUP 16
DVSS 17
50 SC2_IN_R
49 SC2_IN_L
48 NC
37 NC
36 AGNDC
35 AHVSS
34 CAPL_M
33 AHVSUP
32 NC
47 NC
I2S_DA_IN2 18
NC 19
46 NC
I2S_DA_IN2 20
NC 21
45 NC
RESETQ 20
NC 21
44 NC
NC 22
43 NC
NC 22
31 SC1_OUT_L
30 SC1_OUT_R
29 VREF1
28 NC
NC 23
42 AGNDC
41 AHVSS
40 CAPL_M
39 AHVSUP
38 NC
VERF2 23
DACM_R 24
DACM_L 25
NC 26
RESETQ 24
NC 25
NC 26
27 NC
VREF2 27
DACM_R 28
DACM_L 29
NC 30
37 SC1_OUT_L
36 SC1_OUT_R
35 VREF1
34 NC
Fig. 4–7: 52-pin PSDIP package
NC 31
NC 32
33 NC
Fig. 4–6: 64-pin PSDIP package
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MSP 34x5G
PRELIMINARY DATA SHEET
SC2_IN_L
SC2_IN_R
ASG
SC1_IN_L
SC1_IN_R
VREFTOP
NC
ASG
NC
NC
NC
NC
NC
NC
MONO_IN
AVSS
AGNDC
AHVSS
AHVSS
NC
AVSS
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVSUP 65
AVSUP 66
ANA_IN1+ 67
ANA_IN− 68
NC 69
40 CAPL_M
39 AHVSUP
38 NC
37 SC1_OUT_L
36 SC1_OUT_R
35 VREF1
34 NC
TESTEN 70
XTAL_IN 71
XTAL_OUT 72
TP 73
33 NC
MSP 34x5G
32 NC
NC 74
31 NC
NC 75
30 NC
NC 76
29 NC
D_CTR_I/O_1 77
D_CTR_I/O_0 78
ADR_SEL 79
STANDBYQ 80
28 DACM_L
27 DACM_R
26 VREF2
25 NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
I2C_CL
I2C_DA
I2S_CL
I2S_WS
I2S_DA_OUT
I2S_DA_IN1
ADR_DA
ADR_WS
ADR_CL
DVSUP
DVSUP
NC
NC
RESETQ
NC
NC
NC
I2S_DA_IN2
DVSS
DVSS
DVSS
DVSUP
Fig. 4–8: 80-pin PQFP package
48
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
SC2_IN_L
ASG
NC
SC2_IN_R
ASG
SC1_IN_L
NC
NC
SC1_IN_R
NC
VREFTOP
NC
MONO_IN
AGNDC
AVSS
AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVSUP 49
ANA_IN1+ 50
ANA_IN− 51
NC 52
32 CAPL_M
31 AHVSUP
30 NC
29 SC1_OUT_L
28 SC1_OUT_R
27 VREF1
26 NC
TESTEN 53
XTAL_IN 54
XTAL_OUT 55
TP 56
25 NC
MSP 34x5G
NC 57
24 NC
NC 58
23 NC
NC 59
22 NC
D_CTR_I/OUT1 60
D_CTR_I/OUT0 61
ADR_SEL 62
STANDBYQ 63
NC 64
21 DACM_L
20 DACM_R
19 VREF2
18 NC
17 NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
I2C_CL
RESETQ
I2C_DA
I2S_CL
I2S_WS
I2S_DA_OUT
I2S_DA_IN1
ADR_DA
ADR_WS
NC
NC
NC
I2S_DA_IN2
DVSS
DVSUP
ADR_CL
Fig. 4–9: 64-pin PLQFP package
Micronas
49
MSP 34x5G
PRELIMINARY DATA SHEET
NC
VREF1
SC1_OUT_R
SC1_OUT_L
NC
DACM_L
DACM_R
VREF2
NC
AHVSUP
NC
33 32 31 30 29 28 27 26 25 24 23
CAPL_M 34
AHVSS 35
22 RESETQ
21 I2S_DA_IN2
20 DVSS
AGNDC 36
SC2_IN_L 37
SC2_IN_R 38
ASG 39
19 DVSUP
18 ADR_CL
17 I2S_DA_IN1
16 I2S_DA_OUT
15 I2S_WS
14 I2S_CL
MSP 34x5G
SC1_IN_L 40
SC1_IN_R 41
VREFTOP 42
MONO_IN 43
AVSS 44
13 I2C_DA
12 I2C_CL
1
2
3
4
5
6
7
8
9
10 11
AVSUP
STANDBYQ
ANA_IN1+
ANA_IN−
TESTEN
XTAL_IN
ADR_SEL
D_CTR_I/O0
D_CTR_I/O1
TP
XTAL_OUT
Fig. 4–10: 44-pin PMQFP package
50
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.5. Pin Circuits
Pin numbers refer to the PQFP80 package.
DVSUP
P
DVSUP
23 k
N
23 k
GND
GND
ADR_SEL
Fig. 4–11: Output Pins 6, 8, 9, and 10
(I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL)
Fig. 4–16: Input Pin 79 (ADR_SEL)
DVSUP
P
N
GND
Fig. 4–12: Input/Output Pins 2 and 3
(I2C_CL, I2C_DA)
N
GND
Fig. 4–17: Input/Output Pins 4, 5, 77, and 78
(I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
Fig. 4–13: Input Pins 7, 17, and 80
(I2S_DA_IN1/2, STANDBYQ)
P
500 k
3−30 pF
N
>300 k
DVSS
3−30 pF
Fig. 4–14: Input Pin 21 (RESETQ)
Fig. 4–18: Output/Input Pins 71 and 72
(XTAL_IN, XTAL_OUT)
AVSUP
200 k
Fig. 4–15: Input Pin 70 (TESTEN)
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MSP 34x5G
PRELIMINARY DATA SHEET
ANA_IN1+
125 k
≈ 3.75 V
A
D
Fig. 4–24: Pin 45 (AGNDC)
ANA_IN1−
VREFTOP
26 pF
120 k
Fig. 4–19: Input Pins 58, 67, and 68
(VREFTOP, ANA_IN1+, ANA_IN−)
300
≈ 3.75 V
0...2 V
Fig. 4–25: Output Pins 36 and 37 (SC_1_OUT_R/L)
Fig. 4–20: Capacitor Pin 40 (CAPL_M)
24 k
≈ 3.75 V
Fig. 4–21: Input Pin 60 (MONO_IN)
40 k
≈ 3.75 V
Fig. 4–22: Input Pins 53, 54, 56, 57 (SC2-1_IN_L/R)
AHVSUP
0...1.2 mA
3.3 k
Fig. 4–23: Output Pins 27 and 28 (DACM_R/L)
52
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
TA
Parameter
Pin Name
–
Min.
0
Max.
Unit
°C
°C
V
Ambient Operating Temperature
Storage Temperature
First Supply Voltage
Second Supply Voltage
Third Supply Voltage
701)
125
9.0
6.0
6.0
0.5
TS
–
−40
−0.3
−0.3
−0.3
−0.5
VSUP1
VSUP2
VSUP3
dVSUP23
AHVSUP
DVSUP
AVSUP
V
V
Voltage between AVSUP
and DVSUP
AVSUP,
DVSUP
V
PTOT
Package Power Dissipation
PSDIP64
PSDIP52
AHVSUP,
DVSUP,
AVSUP
1300
1200
1000
960
mW
PQFP80
PLQFP64
PMQFP441)
960
VIdig
IIdig
Input Voltage, all Digital Inputs
Input Current, all Digital Pins
Input Voltage, all Analog Inputs
−0.3
−20
VSUP2+0.3
+20
V
–
mA2)
V
VIana
SCn_IN_s,3)
MONO_IN
−0.3
VSUP1+0.3
IIana
Input Current, all Analog Inputs
SCn_IN_s,3)
MONO_IN
−5
+5
mA2)
4) 5)
4) 5)
IOana
IOana
Output Current, all SCART Outputs SC1_OUT_s3)
,
,
4)
4)
4)
4)
Output Current, all Analog Outputs
except SCART Outputs
DACM_s3)
ICana
Output Current, other pins
connected to capacitors
CAPL_M,
AGNDC
1)
For MSP 34x5G-Ax versions only: PMQFP44 ambient operating temperature limited to 65 °C.
positive value means current flowing into the circuit
“n” means “1” or “2”, “s” means “L” or “R”
The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground.
Total chip power dissipation must not exceed absolute maximum rating.
2)
3)
4)
5)
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Micronas
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MSP 34x5G
PRELIMINARY DATA SHEET
4.6.2. Recommended Operating Conditions
at TA = 0 to 70 °C
4.6.2.1. General Recommended Operating Conditions
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VSUP1
First Supply Voltage
(8-V Operation)
AHVSUP
7.6
8.0
8.7
V
First Supply Voltage
(5-V Operation)
4.75
5.0
5.25
V
VSUP2
VSUP3
tSTBYQ1
Second Supply Voltage
Third Supply Voltage
DVSUP
AVSUP
4.75
4.75
1
5.0
5.0
5.25
5.25
V
V
STANDBYQ Setup Time before
Turn-off of Second Supply Voltage
STANDBYQ,
DVSUP
µs
4.6.2.2. Analog Input and Output Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
3.3
Max.
Unit
µF
CAGNDC
AGNDC-Filter-Capacitor
Ceramic Capacitor in Parallel
AGNDC
−20%
−20%
−20%
100
330
nF
CinSC
DC-Decoupling Capacitor in front of SCn_IN_s1)
SCART Inputs
nF
VinSC
VinMONO
RLSC
SCART Input Level
2.0
2.0
VRMS
VRMS
kΩ
Input Level, Mono Input
SCART Load Resistance
SCART Load Capacitance
Main Volume Capacitor
Main Filter Capacitor
MONO_IN
SC1_OUT_s1)
10
CLSC
6.0
nF
CVMA
CAPL_M
10
1
µF
CFMA
DACM_s1)
−10%
+10%
nF
1)
“n” means “1” or “2”, “s” means “L” or “R”
54
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.2.3. Recommendations for Analog Sound IF Input Signal
Symbol
Parameter
Pin Name
Min.
−20%
−20%
0
Typ.
10
Max.
Unit
µF
CVREFTOP
VREFTOP-Filter-Capacitor
Ceramic Capacitor in Parallel
VREFTOP
100
nF
FIF_FMTV
Analog Input Frequency Range
for TV applications
ANA_IN1+,
ANA_IN−
9
MHz
FIF_FMRADIO
Analog Input Frequency for
FM-Radio Applications
10.7
MHz
VIF_FM
VIF_AM
RFMNI
Analog Input Range FM/NICAM
Analog Input Range AM/NICAM
0.1
0.1
0.8
3
Vpp
Vpp
0.45
0.8
Ratio: NICAM Carrier/FM Carrier
(unmodulated carriers)
BG:
I:
−20
−23
−7
−10
0
0
dB
dB
RAMNI
Ratio: NICAM Carrier/AM Carrier
(unmodulated carriers)
−25
−11
0
dB
RFM
Ratio: FM-Main/FM-Sub Satellite
7
7
dB
dB
RFM1/FM2
Ratio: FM1/FM2
German FM-System
RFC
Ratio: Main FM Carrier/
Color Carrier
15
–
–
–
–
–
dB
dB
RFV
Ratio: Main FM Carrier/
Luma Components
15
PRIF
Passband Ripple
–
±2
dB
dB
SUPHF
Suppression of Spectrum
15
–
above 9.0 MHz (not for FM Radio)
FMMAX
Maximum FM-Deviation (approx.)
normal mode
±180
±360
±540
kHz
kHz
kHz
HDEV2: high deviation mode
HDEV3: very high deviation mode
Micronas
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MSP 34x5G
PRELIMINARY DATA SHEET
4.6.2.4. Crystal Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
General Crystal Recommendations
fP
Crystal Parallel Resonance Fre-
18.432
MHz
quency at 12 pF Load Capacitance
RR
C0
CL
Crystal Series Resistance
8
25
Ω
Crystal Shunt (Parallel) Capacitance
External Load Capacitance1)
6.2
7.0
pF
XTAL_IN,
XTAL_OUT
PSDIP
approx. 1.5
pF
pF
P(L,M)QFP approx. 3.3
Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock)
fTOL
Accuracy of Adjustment
−20
−20
+20
+20
ppm
ppm
DTEM
Frequency Variation
versus Temperature
C1
Motional (Dynamic) Capacitance
19
24
fF
fCL
Required Open Loop Clock
18.431
18.433 MHz
Frequency (Tamb = 25 °C)
Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I2S clock possible)
fTOL
Accuracy of Adjustment
−30
−30
+30
+30
ppm
ppm
DTEM
Frequency Variation
versus Temperature
C1
Motional (Dynamic) Capacitance
15
fF
18.4305
18.4335
fCL
Required Open Loop Clock
MHz
Frequency (Tamb = 25 °C)
Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I2S clock possible)
fTOL
Accuracy of Adjustment
−100
−50
+100
+50
ppm
ppm
DTEM
Frequency Variation
versus Temperature
fCL
Required Open Loop Clock
18.429
18.435 MHz
Frequency (Tamb = 25 °C)
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF)
VXCA External Clock Amplitude XTAL_IN 0.7
Vpp
1)External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-
quency of the internal PLL and to stabilize the frequency in closed-loop operation.
Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested
values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.
To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the frequency
at ADR_CL-pin. Measurement at XTAL_IN/OUT pins is not possible. Change the capacitor size until the free run-
ning frequency matches 18.432/3 = 6.144 MHz as closely as possible. The higher the capacity, the lower the
resulting clock frequency.
56
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.3. Characteristics
at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values
at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values,
TJ = Junction Temperature
MAIN (M) = Loudspeaker Channel
4.6.3.1. General Characteristics
Symbol
Supply
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
I
First Supply Current (active)
(AHVSUP = 8 V)
AHVSUP
SUP1A
Analog Volume for Main and Aux at 0 dB
17.1
11.2
24.6
16.1
mA
mA
Analog Volume for Main and Aux at −30 dB
First Supply Current (active)
(AHVSUP = 5 V)
Analog Volume for Main and Aux at 0 dB
11.4
7.5
16.4
10.7
mA
mA
Analog Volume for Main and Aux at −30 dB
I
I
I
Second Supply Current (active)
MSP 34x5G version A4
MSP 34x5G version B5 and later
DVSUP
AVSUP
AHVSUP
SUP2A
SUP3A
SUP1S
95
65
102
85
mA
mA
Third Supply Current (active)
MSP 34x5G version A4
MSP 34x5G version B5 and later
25
35
35
45
mA
mA
First Supply Current
(AHVSUP = 8 V)
5.6
7.7
mA
STANDBYQ = low
STANDBYQ = low
(standby mode) at T = 27 °C
j
First Supply Current
(AHVSUP = 5 V)
3.7
5.1
mA
(standby mode) at T = 27 °C
j
Clock
f
Clock Input Frequency
Clock High to Low Ratio
XTAL_IN
18.432
MHz
%
CLOCK
D
45
55
50
CLOCK
JITTER
t
Clock Jitter (verification not
provided in production test)
ps
V
DC-Voltage Oscillator
2.5
0.4
V
xtalDC
t
Oscillator Startup Time at
XTAL_IN,
2
ms
Startup
VDD Slew-rate of 1 V/1 µs
XTAL_OUT
Micronas
57
MSP 34x5G
PRELIMINARY DATA SHEET
4.6.3.2. Digital Inputs, Digital Outputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Digital Input Levels
V
V
Digital Input Low Voltage
STANDBYQ
D_CTR_I/O_0/1
0.2
V
DIGIL
SUP2
Digital Input High Voltage
MSP 34x5G version A4
MSP 34x5G version B5 and later
DIGIH
0.8
0.5
V
V
SUP2
SUP2
Z
Input Impedance
5
1
pF
DIGI
I
Digital Input Leakage Current
−1
µA
0 V < U
< DVSUP
INPUT
DLEAK
D_CTR_I/O_0/1: tri-state
V
V
Digital Input Low Voltage
ADR_SEL
0.2
V
V
DIGIL
SUP2
Digital Input High Voltage
Input Current Address Select Pin
0.8
DIGIH
SUP2
I
−500
−220
µA
µA
pF
µA
U
U
= DVSS
ADRSEL
ADR_SEL
220
500
5
= DVSUP
ADR_SEL
Z
Input Capacitance
Input Low Current
TESTEN
TESTEN
I
−60
U
= AVSS
TESTEN
TESTEN
Digital Output Levels
V
V
Digital Output Low Voltage
Digital Output High Voltage
D_CTR_I/O_0
D_CTR_I/O_1
0.4
V
V
IDDCTR = 1 mA
DCTROL
DCTROH
4.0
IDDCTR = −1 mA
58
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.3.3. Reset Input and Power-Up
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RESETQ Input Levels
V
V
Reset High-Low Transition Voltage RESETQ
Reset Low-High Transition Voltage
Input Capacitance
0.3
0.4
0.55
5
V
V
RHL
RLH
RES
RES
SUP2
0.45
SUP2
Z
pF
I
Input High Current
20
µA
U
= DVSUP
RESETQ
DVSUP
AVSUP
4.5V
t/ms
Low-to-High
Threshold
RESETQ
Note: The reset should
not reach high level
before the oscillator has
started. This requires a
reset delay of >2 ms
0.45×DVSUP
0.3...0.45×DVSUP
High-to-Low
Threshold
0.45 x DVSUP means
2.25 Volt with
DVSUP = 5.0 V
t/ms
Reset Delay
>2 ms
Internal
Reset
High
Low
t/ms
Fig. 4–26: Power-up sequence
Micronas
59
MSP 34x5G
PRELIMINARY DATA SHEET
4.6.3.4. I2C Bus Characteristics
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
2
V
V
I C-Bus Input Low Voltage
I2C_CL,
I2C_DA
0.3
V
I2CIL
I2CIH
I2C1
SUP2
SUP2
2
I C-Bus Input High Voltage
0.6
120
120
55
V
2
t
t
t
I C Start Condition Setup Time
ns
ns
ns
2
I C Stop Condition Setup Time
I2C2
2
I C-Data Setup Time
I2C5
before Rising Edge of Clock
2
t
I C-Data Hold Time
55
ns
I2C6
after Falling Edge of Clock
2
t
t
f
I C-Clock Low Pulse Time
I2C_CL
500
500
ns
I2C3
I2C4
I2C
2
I C-Clock High Pulse Time
ns
2
I C-BUS Frequency
1.0
0.4
1.0
MHz
V
2
V
I C-Data Output Low Voltage
I2C_CL,
I2C_DA
I
= 3 mA
I2COL
I2COH
I2COL
2
I
t
t
I C-Data Output
µA
V
= 5 V
I2COH
High Leakage Current
2
I C-Data Output Hold Time
15
ns
ns
I2COL1
I2COL2
after Falling Edge of Clock
2
I C-Data Output Setup Time
100
f
= 1 MHz
I2C
before Rising Edge of Clock
1/FI2C
TI2C4
TI2C3
I2C_CL
TI2C1
TI2C5
TI2C6
TI2C2
I2C_DA as input
I2C_DA as output
TI2COL2
TI2COL1
Fig. 4–27: I2C bus timing diagram
60
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.3.5. I2S-Bus Characteristics
Symbol
Parameter
Pin Name
Min.
0.5
−1
Typ.
Max.
Unit
Test Conditions
V
V
Input Low Voltage
Input High Voltage
Input Impedance
Input Leakage Current
I2S_CL
I2S_WS
I2S_DA_IN1/2
0.2
V
V
I2SIL
I2SIH
SUP2
SUP2
Z
5
pF
µA
V
I2SI
I
1
0 V < U
< DVSUP
INPUT
LEAKI2S
2
V
V
I S Output Low Voltage
I2S_CL
I2S_WS
I2S_DA_OUT
0.4
I
= 1 mA
I2SOL
I2SOH
I2SOL
I2SOH
2
I S Output High Voltage
V
V
I
= −1 mA
SUP2
− 0.3
2
f
f
I S-Word Strobe Output Frequency I2S_WS
32.0
1.024
1.0
kHz
I2SOWS
2
I S-Clock Output Frequency
I2S_CL
MHz
I2SOCL
2
R
I S-Clock Output High/Low-Ratio
0.9
12
1.1
I2S10/I2S20
s_I2S
2
t
t
t
I S Input Setup Time
I2S_CL
I2S_DA_IN1/2
ns
ns
ns
for details see Fig. 4–28
2
before Rising Edge of Clock
“I S timing diagram”
2
I S Input Hold Time
40
h_I2S
d_I2S
after Rising Edge of Clock
2
I S Output Delay Time
I2S_CL
28
C = 30 pF
L
after Falling Edge of Clock
I2S_WS
I2S_DA_OUT
2
f
f
I S-Word Strobe Input Frequency
I2S_WS
I2S_CL
32.0
kHz
I2SWS
2
I S-Clock Input Frequency
1.024
MHz
I2SCL
2
R
I S-Clock Input Ratio
0.9
1.1
I2SCL
Micronas
61
MSP 34x5G
PRELIMINARY DATA SHEET
1/F
I2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1
Detail C
I2S_CL
Detail A
I2S_DA_IN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit left channel
16/32 bit right channel
Detail B
I2S_DA_OUT R LSB
L MSB
L LSB R MSB
R LSB L LSB
16/32 bit right channel
Data: MSB first, I2S master
1/F
I2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1
Detail C
I2S_CL
Detail A
I2S_DA_IN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16,18...32 bit left channel
16, 18...32 bit right channel
16, 18...32 bit left channel
Detail B
I2S_DA_OUT R LSB
L MSB
L LSB R MSB
R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S slave
Detail C
Detail A,B
1/F
I2SCL
I2S_CL
I2S_CL
T
T
h_I2S
s_I2S
T
s_I2S
I2S_DA_IN1/2
I2S_WS as INPUT
T
d_I2S
T
d_I2S
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4–28: I2S timing diagram
62
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Ground
V
AGNDC Open Circuit Voltage
(AHVSUP = 8 V)
AGNDC
3.77
2.51
125
83
V
R
≥10 MΩ
load
AGNDC0
AGNDC Open Circuit Voltage
(AHVSUP = 5 V)
V
R
AGNDC Output Resistance
(AHVSUP = 8 V)
70
47
180
120
kΩ
kΩ
3 V ≤ V
≤ 4 V
outAGN
AGNDC
AGNDC Output Resistance
(AHVSUP = 5 V)
Analog Input Resistance
1)
R
R
SCART Input Resistance
SCn_IN_s
25
15
40
24
58
35
kΩ
kΩ
f
f
= 1 kHz, I = 0.05 mA
= 1 kHz, I = 0.1 mA
inSC
signal
signal
from T = 0 to 70 °C
A
MONO Input Resistance
MONO_IN
inMONO
from T = 0 to 70 °C
A
Audio Analog-to-Digital-Converter
1)
V
Effective Analog Input Clipping
Level for Analog-to-Digital-
Conversion
SCn_IN_s,
MONO_IN
2.00
1.13
2.25
1.51
V
V
f
= 1 kHz
AICL
RMS
signal
(AHVSUP = 8 V)
Effective Analog Input Clipping
Level for Analog-to-Digital-
Conversion
RMS
(AHVSUP = 5 V)
SCART Output
1)
R
SCART Output Resistance
SC1_OUT_s
f
f
= 1 kHz, I = 0.1 mA
signal
outSC
at T = 27 °C
200
200
330
460
500
Ω
Ω
j
from T = 0 to 70 °C
A
dV
Deviation of DC-Level at SCART
Output from AGNDC Voltage
−70
+70
mV
dB
dB
OUTSC
1)
A
Gain from Analog Input
to SCART Output
SCn_IN_s
−1.0
−0.5
+0.5
+0.5
= 1 kHz
signal
SCtoSC
MONO_IN
→
SC1_OUT_s
1)
1)
f
Frequency Response from Analog
Input to SCART Output
bandwidth: 20 Hz to 20000 Hz
with resp. to 1 kHz
rSCtoSC
V
Effective Signal Level at
SCART-Output during full-scale
digital input signal from DSP
(AHVSUP = 8 V)
SC1_OUT_s
1.8
1.9
2.0
V
f
= 1 kHz
signal
outSC
RMS
RMS
Effective Signal Level at
SCART-Output during full-scale
digital input signal from DSP
(AHVSUP = 5 V)
1.17
1.27
1.37
V
1)
“n” means “1”or “2”;
“s” means “L” or “R”
Micronas
63
MSP 34x5G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Main Output
1
R
Main Output Resistance
DACM_s )
f
= 1 kHz, I = 0.1 mA
outMA
signal
at T = 27 °C
2.1
2.1
3.3
4.6
5.0
kΩ
kΩ
j
from T = 0 to 70 °C
A
V
DC-Level at Main-Output
for Analog Volume at 0 dB
for Analog Volume at −30 dB
(AHVSUP = 8 V)
outDCMA
1.80
2.04
61
2.28
V
mV
DC-Level at Main-Output
for Analog Volume at 0 dB
for Analog Volume at −30 dB
(AHVSUP = 5 V)
1.12
1.23
1.36
40
1.60
1.51
V
mV
V
Effective Signal Level at Main-
Output during full-scale digital input
signal from DSP for Analog Volume
at 0 dB
1.37
V
f
= 1 kHz
outMA
RMS
signal
(AHVSUP = 8 V)
Effective Signal Level at Main-
Output during full-scale digital input
signal from DSP for Analog Volume
at 0 dB
0.76
0.90
1.04
V
RMS
(AHVSUP = 5 V)
1)
“s” means “L” or “R”
64
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.3.7. Sound IF Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
R
Input Impedance
ANA_IN1+,
ANA_IN−
1.5
6.8
2
9.1
2.5
11.4
kΩ
kΩ
Gain AGC = 20 dB
Gain AGC = 3 dB
IFIN
DC
DC
DC Voltage at VREFTOP
DC Voltage on IF Inputs
VREFTOP
2.4
1.3
2.65
1.5
2.75
1.7
V
V
VREFTOP
ANA_IN
ANA_IN1+,
ANA_IN−
XTALK
Crosstalk Attenuation
3 dB Bandwidth
ANA_IN1+,
ANA_IN−
40
10
dB
IF
f
= 1 MHz
signal
BW
MHz
dB
IF
Input Level = −2 dBr
AGC
AGC Step Width
0.85
4.6.3.8. Power Supply Rejection
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
PSRR: Rejection of Noise on AHVSUP at 1 kHz
PSRR
AGNDC
AGNDC
80
70
dB
dB
2
From Analog Input to I S Output
MONO_IN,
SCn_IN_s
1)
From Analog Input to
SCART Output
MONO_IN,
SCn_IN_s
SCn_OUT_s
70
dB
1)
1)
1)
2
From I S Input to SCART Output
SCn_OUT_s
60
80
dB
dB
2
1)
From I S Input to MAIN or AUX
DACM_s
Output
1)
“n” means “1” or “2”;
“s” means “L” or “R”
Micronas
65
MSP 34x5G
PRELIMINARY DATA SHEET
4.6.3.9. Analog Performance
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Specifications for AHVSUP = 8 V
SNR
Signal-to-Noise Ratio
2
from Analog Input to I S Output
MONO_IN,
SCn_IN_s
85
93
85
88
96
88
dB
dB
dB
Input Level = −20 dB with
1)
resp. to V
, f = 1 kHz,
AICL sig
unweighted
20 Hz...16 kHz
from Analog Input to
SCART Output
MONO_IN,
Input Level = −20 dB,
1)
SCn_IN_s
→
f
= 1 kHz,
sig
unweighted
20 Hz...20 kHz
1)
1)
SCn_OUT_s
2
from I S Input to SCART Output
SCn_OUT_s
Input Level = −20 dB,
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
2
1)
from I S Input to Main Output
DACM_s
Input Level = −20 dB,
for Analog Volume at 0 dB
for Analog Volume at −30 dB
85
78
88
83
dB
dB
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
THD
Total Harmonic Distortion
2
from Analog Input to I S Output
MONO_IN,
SCn_IN_s
0.01
0.01
0.01
0.01
0.03
0.03
0.03
0.03
%
%
%
%
Input Level = −3 dBr with
1)
resp. to V
, f = 1 kHz,
AICL sig
unweighted
20 Hz...15 kHz
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s
→
Input Level = −3 dBr,
f
= 1 kHz,
sig
unweighted
20 Hz...20 kHz
1)
1)
SCn_OUT_s
2
from I S Input to SCART Output
SCn_OUT_s
Input Level = −3 dBr,
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
2
1)
from I S Input to Main Output
DACM_s
Input Level = −3 dBr,
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
1)
“n” means “1” or “2”;
“s” means “L” or “R”
66
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Specifications for AHVSUP = 5 V
SNR
Signal-to-Noise Ratio
2
from Analog Input to I S Output
MONO_IN,
SCn_IN_s
82
90
82
85
93
85
dB
dB
dB
Input Level = −20 dB with
1)
resp. to V
, f = 1 kHz,
AICL sig
unweighted
20 Hz...15 kHz
from Analog Input to
SCART Output
MONO_IN,
Input Level = −20 dB,
1)
SCn_IN_s
→
f
= 1 kHz,
sig
unweighted
20 Hz...20 kHz
1)
1)
SCn_OUT_s
2
from I S Input to SCART Output
SCn_OUT_s
Input Level = −20 dB,
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
2
1)
from I S Input to Main Output
DACM_s
Input Level = −20 dB,
for Analog Volume at 0 dB
for Analog Volume at −30 dB
82
75
85
80
dB
dB
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
THD
Total Harmonic Distortion
2
from Analog Input to I S Output
MONO_IN,
SCn_IN_s
0.03
0.1
0.1
0.1
0.1
%
%
%
%
Input Level = −3 dBr with
1)
resp. to V
, f = 1 kHz,
AICL sig
unweighted
20 Hz...15 kHz
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s
→
Input Level = −3 dBr,
f
= 1 kHz,
sig
unweighted
20 Hz...20 kHz
1)
1)
SCn_OUT_s
2
from I S Input to SCART Output
SCn_OUT_s
Input Level = −3 dBr,
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
2
1)
from I S Input to Main Output
DACM_s
Input Level = −3 dBr,
f
= 1 kHz,
sig
unweighted
20 Hz...15 kHz
1)
“n” means “1” or “2”;
“s” means “L” or “R”
Micronas
67
MSP 34x5G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
CROSSTALK Specifications
XTALK
Crosstalk Attenuation
Input Level = −3 dB,
f
= 1 kHz, unused
sig
analog inputs connected to
ground by Z < 1 kΩ
between left and right channel within
unweighted
SCART Input/Output pair (L→R, R→L)
20 Hz...20 kHz
1)
SCn_IN → SC1_OUT
80
80
80
80
dB
dB
dB
dB
2
SC1_IN or SC2_IN → I S Output
2
SC3_IN → I S Output
2
I S Input → SC1_OUT
between left and right channel within
Main or AUX Output pair
unweighted
20 Hz...15 kHz
2
I S Input → DACM
75
dB
between SCART Input/Output pairs
(unweighted
20 Hz...20 kHz
D = disturbing program
O = observed program
same signal source on left
and right disturbing
channel, effect on each
observed output channel
1)
D: MONO/SCn_IN → SC1_OUT
100
95
dB
dB
dB
dB
1)
O: MONO/SCn_IN → SC1_OUT
1)
D: MONO/SCn_IN → SC1_OUT or unsel.
1)
2
O: MONO/SCn_IN → I S Output
1)
D: MONO/SCn_IN → SC1_OUT
100
100
2
O: I S Input → SC1_OUT
1)
D: MONO/SCn_IN → unselected
2
O: I S Input → SC1_OUT
Crosstalk between Main and AUX Output pairs
(unweighted
20 Hz...15 kHz)
same signal source on left
and right disturbing
channel, effect on each
observed output channel
2
I S Input → DACM
90
dB
XTALK
Crosstalk from Main or AUX Output to SCART Output
and vice versa
(unweighted
20 Hz...20 kHz)
same signal source on left
and right disturbing
channel, effect on each
observed output channel
D = disturbing program
O = observed program
1)
D: MONO/SCn_IN/DSP → SC1_OUT
O: I S Input → DACM
80
85
95
95
dB
dB
dB
dB
SCART output load
resistance 10 kΩ
2
1)
D: MONO/SCn_IN/DSP → SC1_OUT
SCART output load
resistance 30 kΩ
2
O: I S Input → DACM
2
D: I S Input → DACM
1)
O: MONO/SCn_IN → SC1_OUT
2
D: I S Input → DACM
2
O: I S Input → SC1_OUT
1)
“n” means “1” or “2”;
“s” means “L” or “R”
68
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
4.6.3.10. Sound Standard Dependent Characteristics
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
NICAM Characteristics (MSP Standard Code = 8)
dV
Tolerance of Output Voltage
of NICAM Baseband Signal
DACM_s,
SC1_OUT_s
−1.5
+1.5
dB
dB
2.12 kHz, Modulator input
level = 0 dBref
NICAMOUT
1)
S/N
S/N of NICAM Baseband Signal
72
NICAM: −6 dB, 1 kHz, RMS
unweighted
NICAM
0 to 15 kHz, Vol = 9 dB
NIC_Presc = 7F
Output level 1 V
DACp_s
hex
at
RMS
THD
BER
Total Harmonic Distortion + Noise
of NICAM Baseband Signal
0.1
%
2.12 kHz, Modulator input
level = 0 dBref
NICAM
NICAM
−7
NICAM: Bit Error Rate
1
10
FM+NICAM, norm conditions
fR
NICAM Frequency Response,
20...15000 Hz
−1.0
+1.0
dB
Modulator input
level = −12 dB dBref; RMS
NICAM
XTALK
NICAM Crosstalk Attenuation (Dual)
NICAM Channel Separation (Stereo)
80
80
dB
dB
NICAM
SEP
NICAM
FM Characteristics (MSP Standard Code = 3)
dV
Tolerance of Output Voltage
of FM Demodulated Signal
DACM_s,
SC1_OUT_s
−1.5
+1.5
dB
1 FM-carrier, 50 µs, 1 kHz,
40 kHz deviation; RMS
FMOUT
1)
S/N
S/N of FM Demodulated Signal
73
dB
%
1 FM-carrier 5.5 MHz, 50 µs,
1 kHz, 40 kHz deviation;
RMS, unweighted
0 to 15 kHz (for S/N);
full input range, FM-Pres-
FM
THD
Total Harmonic Distortion + Noise
of FM Demodulated Signal
0.1
FM
cale = 46 , Vol = 0 dB
hex
→ Output Level 1 V
at
RMS
DACp_s
fR
FM Frequency Responses,
20...15000 Hz
−1.0
80
+1.0
dB
dB
dB
1 FM-carrier 5.5 MHz,
50 µs, Modulator input
level = −14.6 dBref; RMS
FM
XTALK
FM Crosstalk Attenuation (Dual)
FM Channel Separation (Stereo)
2 FM-carriers 5.5/5.74 MHz,
50 µs, 1 kHz, 40 kHz
deviation; Bandpass 1 kHz
FM
SEP
DACM_s,
SC1_OUT_s
50
2 FM-carriers 5.5/5.74 MHz,
50 µs, 1 kHz, 40 kHz
deviation; RMS
FM
1)
1)
AM Characteristics (MSP Standard Code = 9)
S/N
S/N of AM Demodulated Signal
measurement condition: RMS/Flat
MSP 34x5G Version A4 to B5
MSP 34x5G Version B6 and later
DACM_s,
SC1_OUT_s
SIF level: 0.1−0.8 V
pp
AM(1)
AM-carrier 54% at 6.5 MHz
Vol = 0 dB, FM/AM
prescaler set for
44
55
dB
dB
output = 0.5 V
at
RMS
Loudspeaker out;
S/N
S/N of AM Demodulated Signal
measurement condition: QP/CCIR
MSP 34x5G Version A4 to B5
MSP 34x5G Version B6 and later
AM(2)
Standard Code = 09
no video/chroma
components
hex
35
45
dB
dB
THD
Total Harmonic Distortion + Noise
of AM Demodulated Signal
AM
MSP 34x5G Version A4 to B5
MSP 34x5G Version B6 and later
0.8
0.6
%
%
fR
AM Frequency Response
50...12000 Hz
−2.5
+1.0
dB
AM
1) “s” means “L” or “R”
Micronas
69
MSP 34x5G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code = 20 , 21
)
hex
hex
S/N
S/N of BTSC Stereo Signal
S/N of BTSC-SAP Signal
DACM_s,
SC1_OUT_s
68
57
dB
dB
1 kHz L or R or SAP, 100%
modulation, 75 µs
BTSC
1)
deemphasis, RMS
unweighted 0 to 15 kHz
THD
THD+N of BTSC Stereo Signal
THD+N of BTSC SAP Signal
0.1
0.5
%
%
1 kHz L or R or SAP, 100%
75 µs EIM , DBX NR, RMS
unweighted
0 to 15 kHz
BTSC
2)
fR
Frequency Response of BTSC
Stereo, 50 Hz...12 kHz
−1.0
−1.0
1.0
1.0
dB
dB
L or R or SAP,
1%...66% EIM , DBX NR
BTSC
2)
Frequency Response of BTSC-
SAP, 50 Hz...9 kHz
XTALK
Stereo → SAP
SAP → Stereo
76
80
dB
dB
1 kHz L or R or SAP, 100%
modulation, 75 µs
deemphasis, Bandpass 1
kHz
BTSC
2)
SEP
Stereo Separation
50 Hz...10 kHz
50 Hz...12 kHz
L or R 1%...66% EIM , DBX
NR
BTSC
35
30
dB
dB
FM
Pilot deviation threshold
Stereo off → on
ANA_IN1+
ANA_IN1+
4.5 MHz carrier modulated
pil
with f = 15.743 kHz
h
3.2
1.2
3.5
1.5
kHz
kHz
SIF level = 100 mV
pp
Stereo on → off
indication: STATUS Bit[6]
f
Pilot Frequency Range
15.563
15.843 kHz
standard BTSC stereo signal,
sound carrier only
Pilot
BTSC Characteristics (MSP Standard Code = 20 , 21
)
hex
hex
with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components)
S/N
S/N of BTSC Stereo Signal
S/N of BTSC-SAP Signal
DACM_s,
SC1_OUT_s
64
55
dB
dB
1 kHz L or R or SAP, 100%
modulation, 75 µs
BTSC
1)
deemphasis, RMS
unweighted 0 to 15 kHz
THD
THD+N of BTSC Stereo Signal
THD+N of BTSC SAP Signal
0.15
0.8
%
%
1 kHz L or R or SAP, 100%
75 µs EIM , DBX NR, RMS
unweighted
0 to 15 kHz
BTSC
2)
fR
Frequency Response of BTSC
Stereo, 50 Hz...12 kHz
−1.0
−1.0
1.0
1.0
dB
dB
L or R or SAP,
1%...66% EIM , DBX NR
BTSC
2)
Frequency Response of BTSC-
SAP, 50 Hz...9 kHz
XTALK
Stereo → SAP
SAP → Stereo
75
75
dB
dB
1 kHz L or R or SAP, 100%
modulation, 75 µs
deemphasis, Bandpass 1
kHz
BTSC
2)
SEP
Stereo Separation
50 Hz...10 kHz
50 Hz...12 kHz
L or R 1%...66% EIM , DBX
NR
BTSC
35
30
dB
dB
1)
“s” means “L” or “R”
2)
EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,
when the DBX encoding process is replaced by a 75-µs preemphasis network.
70
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Symbol
Parameter
Pin Name
)
Min.
Typ.
Max.
Unit
Test Conditions
EIA-J Characteristics (MSP Standard Code = 30
hex
S/N
S/N of EIA-J Stereo Signal
S/N of EIA-J Sub-Channel
DACM_s,
SC1_OUT_s
60
60
dB
dB
1 kHz L or R,
EIAJ
1)
100% modulation,
75 µs deemphasis,
RMS unweighted
0 to 15 kHz
THD
THD+N of EIA-J Stereo Signal
THD+N of EIA-J Sub-Channel
0.2
0.3
%
%
EIAJ
fR
Frequency Response of EIA-J
Stereo, 50 Hz...12 kHz
−1.0
−1.0
1.0
1.0
dB
dB
100% modulation,
75 µs deemphasis
EIAJ
Frequency Response of EIA-J
Sub-Channel, 50 Hz...12 kHz
XTALK
Main → SUB
Sub → MAIN
66
80
dB
dB
1 kHz L or R, 100%
modulation, 75 µs
deemphasis,
EIAJ
Bandpass 1 kHz
SEP
Stereo Separation
50 Hz...5 kHz
50 Hz...10 kHz
EIA-J Stereo Signal, L or R
100% modulation
EIAJ
35
28
dB
dB
FM-Radio Characteristics (MSP Standard Code = 40
)
hex
S/N
S/N of FM-Radio Stereo Signal
DACM_s,
SC1_OUT_s
68
dB
%
1 kHz L or R, 100%
modulation, 75 µs
deemphasis, RMS
unweighted
UKW
1)
THD
THD+N of FM-Radio Stereo Signal
0.1
UKW
0 to 15 kHz
fR
Frequency Response of
FM-Radio Stereo
50 Hz...15 kHz
L or R, 1%...100%
modulation, 75 µs
deemphasis
UKW
−1.0
45
+1.0
dB
dB
SEP
Stereo Separation 50 Hz...15 kHz
Pilot Frequency Range
UKW
f
ANA_IN1+
18.844
19.125 kHz
standard FM radio
stereo signal
Pilot
1)
“n” means “1” or “2”;
“s” means “L” or “R”
Micronas
71
MSP 34x5G
PRELIMINARY DATA SHEET
5. Appendix A: Overview of TV Sound Standards
5.1. NICAM 728
Table 5–1: Summary of NICAM 728 sound modulation parameters
Specification
I
B/G
L
D/K
Carrier frequency of
digital sound
6.552 MHz
5.85 MHz
5.85 MHz
5.85 MHz
Transmission rate
Type of modulation
728 kbit/s
Differentially encoded quadrature phase shift keying (DQPSK)
by means of Roll-off filters
Spectrum shaping
Roll-off factor
1.0
0.4
0.4
6.5 MHz AM mono
0.4
Carrier frequency of
analog sound component
6.0 MHz
5.5 MHz
6.5 MHz
FM mono
FM mono
FM mono
terrestrial
10 dB
cable
Power ratio between
vision carrier and
analog sound carrier
10 dB
10 dB
13 dB
7 dB
16 dB
13 dB
Power ratio between
analog and modulated
digital sound carrier
17 dB
11 dB
China/
Hungary
Poland
7 dB
12 dB
Table 5–2: Summary of NICAM 728 sound coding characteristics
Characteristics
Values
32 kHz
2
Audio sampling frequency
Number of channels
Initial resolution
14 bit/sample
Companding characteristics
Coding for compressed samples
Preemphasis
near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks
2’s complement
CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz)
+12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
Audio overload level
72
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
5.2. A2 Systems
Table 5–3: Key parameters for A2 Systems of Standards B/G, D/K, and M
Characteristics
Sound Carrier FM1
Sound Carrier FM2
D/K
TV-Sound Standard
Carrier frequency in MHz
B/G
D/K
M
B/G
M
5.5
6.5
4.5
5.7421875 6.2578125 4.724212
6.7421875
5.7421875
Vision/sound power difference
Sound bandwidth
13 dB
20 dB
40 Hz to 15 kHz
Preemphasis
50 µs
±27/±50 kHz
75 µs
50 µs
75 µs
Frequency deviation (nom/max)
Transmission Modes
±17/±25 kHz
±27/±50 kHz
±15/±25 kHz
Mono transmission
mono
mono
Stereo transmission
(L+R)/2
language A
(L+R)/2
R
(L−R)/2
Dual sound transmission
Identification of Transmission Mode
Pilot carrier frequency
language B
54.6875 kHz
±2.5 kHz
55.0699 kHz
Max. deviation portion
Type of modulation / modulation depth
Modulation frequency
AM / 50%
mono: unmodulated
stereo: 117.5 Hz
dual: 274.1 Hz
149.9 Hz
276.0 Hz
Micronas
73
MSP 34x5G
PRELIMINARY DATA SHEET
5.3. BTSC-Sound System
Table 5–4: Key parameters for BTSC-Sound Systems
Aural
BTSC-MPX-Components
Carrier
(L+R)
Pilot
(L−R)
2 fh
SAP
Prof. Ch.
6.5 fh
Carrier frequency (fh = 15.734 kHz)
Sound bandwidth in kHz
Preemphasis
4.5 MHz
Baseband
0.05 - 15
75 µs
fh
5 fh
0.05 - 15
DBX
0.05 - 12
DBX
0.05 - 3.4
150 µs
3 kHz
Max. deviation to Aural Carrier
73 kHz
(total)
25 kHz1)
5 kHz
50 kHz1)
15 kHz
Max. Freq. Deviation of Subcarrier
Modulation Type
10 kHz
FM
3 kHz
FM
AM
1) Sum does not exceed 50 kHz due to interleaving effects
5.4. Japanese FM Stereo System (EIA-J)
Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J
Aural
Carrier
FM
EIA-J-MPX-Components
(L+R)
(L−R)
Identification
Carrier frequency (fh = 15.793 kHz)
Sound bandwidth
4.5 MHz
Baseband
0.05 - 15 kHz
75 µs
2 fh
3.5 fh
−
0.05 - 15 kHz
75 µs
Preemphasis
none
2 kHz
Max. deviation portion to Aural Carrier
47 kHz
25 kHz
20 kHz
Max. Freq. Deviation of Subcarrier
Modulation Type
10 kHz
FM
60%
AM
Transmitter-sided delay
Mono transmission
20 µs
0 µs
0 µs
L+R
−
unmodulated
982.5 Hz
922.5 Hz
Stereo transmission
Bilingual transmission
L+R
L−R
Language A
Language B
74
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
5.5. FM Satellite Sound
Table 5–6: Key parameters for FM Satellite Sound
Carrier Frequency
Maximum
FM Deviation
Sound Mode
Bandwidth
Deemphasis
6.5 MHz
85 kHz
50 kHz
50 kHz
50 kHz
Mono
15 kHz
15 kHz
15 kHz
15 kHz
50 µs
7.02/7.20 MHz
7.38/7.56 MHz
7.74/7.92 MHz
Mono/Stereo/Bilingual
Mono/Stereo/Bilingual
Mono/Stereo/Bilingual
adaptive
adaptive
adaptive
5.6. FM-Stereo Radio
Table 5–7: Key parameters for FM-Stereo Radio Systems
Aural
FM-Radio-MPX-Components
Carrier
(L+R)
Pilot
(L−R)
2 fp
RDS/ARI
Carrier frequency (fp = 19 kHz)
Sound bandwidth in kHz
10.7 MHz
Baseband
0.05 - 15
fp
3 fh
0.05 - 15
Preemphasis:
− USA
− Europe
75 µs
50 µs
75 µs
50 µs
Max. deviation to Aural Carrier
75 kHz
(100%)
90%1)
10%
90%1)
5%
1) Sum does not exceed 90% due to interleaving effects.
Micronas
75
MSP 34x5G
PRELIMINARY DATA SHEET
6. Appendix B: Manual/Compatibility Mode
To adapt the modes of the STANDARD SELECT regis-
ter to individual requirements and for reasons of com-
patibility to the MSP 34x5D, the MSP 34x5G offers
an Manual/Compatibility Mode, which provides sophis-
ticated programming of the MSP 34x5G.
Using the STANDARD SELECT register generally pro-
vides
a more economic way to program the
MSP 34x5G and will result in optimal behavior. There-
fore, it is not recommend to use the Manual/Com-
patibility mode. In those cases, where the
MSP 34x0D is to be substituted by the MSP 34x5G,
the tips given in Section 6.9. have to be obeyed by the
controller software.
76
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
Table 6–1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!
Demodulator
Write Registers
Address MSP-
Description
Reset
Mode
Page
(hex)
Version
AUTO_FM/AM
00 21
3415,
3455
1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of 00 00
Automatic Switching between NICAM and FM/AM in case of bad NICAM
reception
78
1)
2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic
Switching between NICAM and FM/AM in case of bad NICAM reception
A2_Threshold
CM_Threshold
AD_CV
00 22
00 24
00 BB
00 83
all
A2 Stereo Identification Threshold
00 19
80
80
81
83
hex
all
Carrier-Mute Threshold
00 2A
00 00
hex
all
SIF-input selection, configuration of AGC, and Carrier-Mute Function
MODE_REG
3415,
3455
Controlling of MSP-Demodulator and Interface options. As soon as this 00 00
register is applied, the MSP 34x5G works in the MSP 34x5D compatibility
mode.
1)
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only
MSP 34x5D features are available; the use of MODUS and STATUS register
is not allowed.
The MSP 34x5G is reset to the normal mode by first programming the
MODUS register followed by transmitting a valid standard code to the
STANDARD SELECTION register.
FIR1
FIR2
00 01
00 05
FIR1-filter coefficients channel 1 (6 8 bit)
FIR2-filter coefficients channel 2 (6 8 bit), + 3 8 bit offset (total 72 bit)
00 00
00 00
84
84
DCO1_LO
DCO1_HI
00 93
00 9B
Increment channel 1 Low Part
Increment channel 1 High Part
DCO2_LO
DCO2_HI
00 A3
00 AB
Increment channel 2 Low Part
Increment channel 2 High Part
1)
not in BTSC, EIA-J, and FM-Radio mode
Note: All registers except AUTO_FM/AM, A2_Threshold, and CM-Threshold are initialized during STANDARD SELECTION and are
automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
Table 6–2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
Demodulator
Address MSP-
Description
Page
Read Registers
(hex)
00 23
00 38
00 3E
00 57
02 1F
02 1E
Version
C_AD_BITS
ADD_BITS
CIB_BITS
3415,
3455
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits
NICAM: bit [10:3] of additional data bits
NICAM: CIB1 and CIB2 control bits
NICAM error rate, updated with 182 ms
Not for customer use.
86
86
86
87
87
87
ERROR_RATE
PLL_CAPS
AGC_GAIN
Not for customer use.
Micronas
77
MSP 34x5G
PRELIMINARY DATA SHEET
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6–3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
Write Register
Address Bits
(hex)
Operational Modes and Adjustable Range
Reset
Mode
Page
Volume SCART1 channel: Ctrl. mode
FM Fixed Deemphasis
FM Adaptive Deemphasis
Identification Mode
00 07
00 0F
[7:0]
[15:8]
[7:0]
[7:0]
[7:0]
[Linear mode / logarithmic mode]
[50 µs, 75 µs, J17, OFF]
[OFF, WP1]
00
88
88
88
89
89
hex
50 µs
OFF
B/G
00 15
00 17
[B/G, M]
FM DC Notch
[ON, OFF]
ON
Table 6–4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
Additional Read
Registers
Address Bits
(hex)
Output Range
Page
Stereo detection register for
A2 Stereo Systems
00 18
[15:8]
[80 ... 7F
]
8 bit two’s complement
89
hex
hex
DC level readout FM1/Ch2-L
DC level readout FM2/Ch1-R
00 1B
00 1C
[15:0]
[15:0]
[8000 ... 7FFF
]
16 bit two’s complement
16 bit two’s complement
89
89
hex
hex
[8000 ... 7FFF
]
hex
hex
6.3. Manual/Compatibility Mode:
Selected Sound
NICAM
Description of Demodulator Write Registers
6.3.1. Automatic Switching between NICAM and
Analog Sound
In case of bad NICAM reception or loss of the
NICAM-carrier, the MSP 34x5G offers an Automatic
Switching (fall back) to the analog sound (FM/AM-
mono), without the necessity for the controller of reading
and evaluating any parameters. If a proper NICAM sig-
nal returns, switching back to this source is performed
automatically as well. The feature evaluates the NICAM
ERROR_RATE and switches, if necessary, all output
channels which are assigned to the NICAM-source, to
the analog source, and vice versa.
analog
sound
ERROR_RATE
threshold/2
threshold
Fig. 6–1: Hysteresis for Automatic Switching
6.3.1.1. Function in Automatic Sound Select Mode
The Automatic Sound Select feature (MODUS[0]=1)
includes the procedure mentioned above. By default, the
internal ERROR_RATE threshold is set to 700dec. i.e.:
An appropriate hysteresis algorithm avoids oscillating
effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11]
(Addr: 0023 hex) provide information about the actual
NICAM-FM/AM-status.
– NICAM → analog Sound if ERROR_RATE > 700
– analog Sound → NICAM if ERROR_RATE < 700/2
The ERROR_RATE value of 700 corresponds to a
BER of approximately 5.46*10-3 /s
78
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Individual configuration of the threshold can be done
using Table 6–5, whereby the bits 0 and 11 of
AUTO_FM are ignored. We recommend to use the
internal setting used by the standard selection.
6.3.1.2. Function in Manual Mode
If the manual mode (MODUS[0]=0) is required, the
activation and configuration of the Automatic Switching
feature has to be done as described in Table 6–5.
Note, that the channel matrix of the corresponding out-
put-channels must be set according to the
NICAM-mode and need not to be changed in the FM/
AM-fallback case.
The optimum NICAM sound can be assigned to the
MSP output channels by selecting one of the “Stereo or
A/B”, “Stereo or A”, or “Stereo or B” source channels
Example:
Required threshold = 500: bits[10:1] = 00 1111 1010
Table 6–5: Coding of Automatic NICAM/Analog Sound Switching;
Reset Status: Mode 0;
Automatic Sound Select is on (MODUS[0] = 1)
Mode
Description
AUTO_FM [11:0]
ERROR_RATE- Source Select:
Threshold/dec
Addr. = 00 21
Input at NICAM Path1)
hex
1
Automatic Switching with
internal threshold
bit[11]
bit[10:1] = 0
= must be 0
700
NICAM or FM/AM,
depending on
(Default, if Automatic Sound
Select is on)
bit[0]
= ignored
ERROR_RATE
2
Automatic Switching with
external threshold
(Customizing of Automatic
bit[11]
bit[10:1] = 25...1000
= threshold/2
= must be 0
set by customer;
recommended
range: 50...2000
Sound Select)
bit[0]
= ignored
1)
The NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels
(see Table 2–2 on page 11).
Table 6–6: Coding of Automatic NICAM/Analog Sound Switching;
Reset Status: Mode 0;
Automatic Sound Select is off (MODUS[0] = 0)
Mode
Description
AUTO_FM [11:0]
ERROR_RATE- Source Select:
Addr. = 00 21
Threshold/dec
Input at NICAM Path
hex
0
Forced NICAM
(Automatic Switching disabled)
bit[11]
bit[10:1] = 0
= 0
none
always NICAM; Mute in
case of no NICAM available
bit[0]
= 0
= 0
1
2
3
Automatic Switching with
internal threshold
(Default, if Automatic Sound
bit[11]
700
NICAM or FM/AM,
depending on
ERROR_RATE
bit[10:1] = 0
bit[0]
= 1
Select is on)
Automatic Switching with
external threshold
(Customizing of Automatic
bit[11]
= 0
set by customer;
recommended
range: 50...2000
bit[10:1] = 25...1000
= threshold/2
Sound Select)
bit[0]
= 1
Forced Analog Mono
bit[11]
= 1
none
always FM/AM
(Automatic Switching disabled)
bit[10:1] = 0
bit[0] = 1
Micronas
79
MSP 34x5G
PRELIMINARY DATA SHEET
6.3.2. A2 Threshold
The threshold between Stereo/Bilingual and Mono
Identification for the A2 Standard has been made pro-
grammable according to the user’s preferences. An
internal hysteresis ensures robustness and stability.
Table 6–7: Write Register on I2C Subaddress 10hex : A2 Threshold
Register
Address
Function
Name
THRESHOLDS
00 22hex (write)
A2 THRESHOLD Register
A2_THRESH
Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual
detection
bit[15:12]
must be set to 0
bit[11:0] 7F0hex
force Mono Identification
...
190hex
...
default setting after reset
0A0hex
minimum Threshold for stable detection
recommended range : 0A0hex...3C0hex
6.3.3. Carrier-Mute Threshold
The Carrier-Mute threshold has been made program-
mable according to the user’s preferences. An internal
hysteresis ensures stable behavior.
Table 6–8: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold
Register
Address
Function
Name
THRESHOLDS
00 24hex (write)
Carrier-Mute THRESHOLD Register
CM_THRESH
Defines threshold for the carrier mute feature
bit[15:12]
must be set to 0
bit[11:0] 000hex
Carrier-Mute always ON (both channels muted)
...
02Ahex
...
default setting after reset
7FFhex
Carrier-Mute always OFF (both channels forced
on)
recommended range : 014hex...050hex
80
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
6.3.4. Register AD_CV
The use of this register is no longer recommended.
Use it only in cases where compatibility to the
MSP 34x5D is required. Using the STANDARD
SELECTION register together with the MODUS regis-
ter provides a more economic way to program the
MSP 34x5G
Table 6–9: AD_CV Register; reset status: all bits are “0”
AD_CV
(00 BBhex
Automatic setting by
STANDARD SELECT Register
)
Bit
[0]
Function
Settings
2-8, 0A-51hex
9
not used
must be set to 0
0
0
[1:6]
Reference level in case of Automatic Gain
Control = on (see Table 6–10). Constant gain
factor when Automatic Gain Control = off
(see Table 6–11).
101000
100011
[7]
[8]
[9]
Determination of Automatic Gain or
Constant Gain
0 = constant gain
1 = automatic gain
1
X
1
1
X
1
Selection of Sound IF source
(identical to MODUS[8])
0 = ANA_IN1+
MSP-Carrier-Mute Feature
0 = off: no mute
1 = on: mute as de-
scribed in Section 2.2.2.
[10:15]
not used
must be set to 0
0
0
X: not affected while choosing the TV sound standard by means of the STANDARD SELECT Register
Table 6–10: Reference values for active AGC (AD_CV[7] = 1)
Application
Input Signal Contains
AD_CV [6:1]
Ref. Value
AD_CV [6:1]
in decimal
Range of Input Signal
at pin ANA_IN1+
Terrestrial TV
1)
− Dual Carrier FM
− NICAM/FM
− NICAM/AM
2 FM Carriers
101000
101000
100011
40
40
35
0.10 − 3 Vpp
1)
1 FM and 1 NICAM Carrier
1 AM and 1 NICAM Carrier
0.10 − 3 Vpp
0.10 − 1.4 Vpp
(recommended: 0.10 − 0.8 Vpp
)
− NICAM only
1 NICAM Carrier only
1 or more FM Carriers
010100
100011
20
35
0.05 − 1.0 Vpp
1)
SAT
0.10 − 3 Vpp
1)
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear.
Micronas
81
MSP 34x5G
PRELIMINARY DATA SHEET
Table 6–11: AD_CV parameters for constant input gain (AD_CV[7]=0)
Step
AD_CV [6:1]
Constant Gain
Gain
Input Level at pin ANA_IN1+ and ANA_IN2+
maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1)
0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
3.00 dB
1
2
3
4
5
6
7
8
3.85 dB
4.70 dB
5.55 dB
6.40 dB
7.25 dB
8.10 dB
8.95 dB
9.80 dB
10.65 dB
11.50 dB
12.35 dB
13.20 dB
14.05 dB
14.90 dB
15.75 dB
16.60 dB
17.45 dB
18.30 dB
19.15 dB
20.00dB
9
10
11
12
13
14
15
16
17
18
19
20
maximum input level: 0.14 Vpp
1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear.
82
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
6.3.5. Register MODE_REG
Only MSP 34x5D features are available; the use of
MODUS and STATUS register is not allowed. The
MSP 34x5G is reset to the normal mode by first pro-
gramming the MODUS register, followed by transmit-
ting a valid standard code to the STANDARD SELEC-
TION register.
Note: The use of this register is no longer recom-
mended. It should be used only in cases where soft-
ware compatibility to the MSP 34x5D is required.
Using the STANDARD SELECTION register together
with the MODUS register provides a more economic
way to program the MSP 34x5G.
The register ‘MODE_REG’ contains the control bits
determining the operation mode of the MSP 34x5G in
the MSP 34x5D Compatibility Mode; Table 6–12
explains all bit positions.
As soon as this register is applied, the MSP 34x5G
works in the MSP 34x5D Compatibility Mode. In this
mode: BTSC, EIA-J, and FM-Radio are disabled.
Table 6–12: Control word ‘MODE_REG’; reset status: all bits are “0”
MODE_REG 00 83hex
Automatic setting by
STANDARD SELECT Register
Bit
[0]
[1]
Function
not used
Comment
Definition
2 - 5
0
8,A,B
9
0
X
0 : must be used
0
DCTR_TRI
Digital control out
0/1 tri-state
0 : active
1 : tri-state
X
X
[2]
[3]
[4]
[5]
[6]
not used
not used
not used
not used
NICAM
1 : recommended
X
X
X
X
0
X
X
X
X
1
X
X
X
X
1
0 : strongly recommended!
0 : strongly recommended!
Mode of MSP-Ch1
Mode of MSP-Ch2
0 : FM
1 : Nicam
[7]
[8]
not used
FM AM
0 : must be used
0
0
0
0
0
1
0 : FM
1 : AM
[9]
HDEV
High Deviation Mode
(channel matrix must be
sound A)
0 : normal
1 : high deviation mode
0
0
0
[11:10]
[12]
not used
0 : must be used
0
0
0
MSP-Ch1 Gain
see also Table 6–14
see also Table 6–14
0 : Gain = 6 dB
1 : Gain = 0 dB
0
0
0
[13]
FIR1-Filter
Coeff. Set
0 : use FIR1
1 : use FIR2
1
0
0
[14]
[15]
not used
AM-Gain
0 : recommended
0
1
0
1
0
1
Gain for AM
Demodulation
0 : 0 dB (default. of MSPB)
1 : 12 dB (recommended)
X: not affected by
short-programming
Micronas
83
MSP 34x5G
PRELIMINARY DATA SHEET
Table 6–13: Loading sequence for FIR-coefficients
The loading sequences must be obeyed. To change a
coefficient set, the complete block FIR1 or FIR2 must
be transmitted.
FIR1 00 01hex (MSP-Ch1: NICAM/FM2)
Note: For compatibility with MSP 3415B, IMREG1 and
IMREG2 have to be transmitted. The value for
IMREG1 and IMREG2 is 004. Due to the partitioning to
8-bit units, the values 04hex, 40hex, and 00hex arise.
No.
1
Symbol Name
Bits
8
Value
NICAM/FM2_Coeff. (5)
NICAM/FM2_Coeff. (4)
NICAM/FM2_Coeff. (3)
NICAM/FM2_Coeff. (2)
NICAM/FM2_Coeff. (1)
NICAM/FM2_Coeff. (0)
2
8
3
8
6.3.7. DCO-Registers
see Table 6–14
4
8
Note: The use of this register is no longer recom-
mended. It should be used only in cases where soft-
ware compatibility to the MSP 34x5D is required.
Using the STANDARD SELECTION register together
with the MODUS register provides a more economic
way to program the MSP 34x5G.
5
8
6
8
FIR2 00 05hex (MSP-Ch2: FM1/AM)
No.
1
Symbol Name
IMREG1
Bits
8
Value
04hex
40hex
00hex
When selecting a TV-sound standard by means of the
STANDARD SELECT register, all frequency tuning is
performed automatically.
2
IMREG1 / IMREG2
IMREG2
8
IF manual setting of the tuning frequency is required, a
set of 24-bit registers determining the mixing frequen-
cies of the quadrature mixers can be written manually
into the IC. In Table 6–15, some examples of DCO reg-
isters are listed. It is necessary to divide them up into
low part and high part. The formula for the calculation
of the registers for any chosen IF-Frequency is as fol-
lows:
3
8
4
FM/AM_Coef (5)
FM/AM_Coef (4)
FM/AM_Coef (3)
FM/AM_Coef (2)
FM/AM_Coef (1)
FM/AM_Coef (0)
8
5
8
6
8
see Table 6–14
7
8
8
8
INCRdec = int(f/fs 224)
9
8
with: int = integer function
f
= IF-frequency in MHz
fS = sampling frequency (18.432 MHz)
6.3.6. FIR-Parameter, Registers FIR1 and FIR2
Conversion of INCR into hex-format and separation of
the 12-bit low and high parts lead to the required regis-
ter values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI
or LO for MSP-Ch2).
Note: The use of this register is no longer recom-
mended. Use it only in cases where software compati-
bility to the MSP 34x5D is required. Using the STAN-
DARD SELECTION register together with the MODUS
register provides a more economic way to program the
MSP 34x5G.
Data shaping and/or FM/AM bandwidth limitation is
performed by a pair of linear phase Finite Impulse
Response filters (FIR-filter). The filter coefficients are
programmable and either are configured automatically
by the STANDARD SELECT register or written manu-
ally by the control processor via the control bus. Two
not necessarily different sets of coefficients are
required: one for MSP-Ch1 (NICAM or FM2) and one
for MSP-Ch2 (FM1 = FM-mono). In Table 6–14 several
coefficient sets are proposed.
To load the FIR-filters, the following data values are to
be transferred
8
bits at
a
time embedded
LSB-bound in a 16-bit word.
84
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Table 6–14: 8-bit FIR-coefficients (decimal integer) for MSP 34x0D; reset status: all coefficients are “0”
Coefficients for FIR1 00 01hex and FIR2 00 05hex
Terrestrial TV Standards
FM - Satellite
FIR filter corresponds to a
band-pass with a band-
width of B = 130 to 500 kHz
B
fc
frequency
B/G-, D/K-
NICAM-FM
I-
L-
B/G-, D/K-,
M-Dual FM
130
kHz
180
kHz
200
kHz
280
kHz
380
kHz
500
kHz
Auto-
search
NICAM-FM
NICAM-AM
FIR1
−2
FIR2
FIR1
FIR2
FIR1
−2
FIR2
−4
FIR2
3
FIR2
73
FIR2
FIR2
FIR2
−8
−8
4
FIR2
−1
FIR2
−1
−1
−8
2
FIR2
−1
−1
−8
2
Coef(i)
3
2
3
9
3
0
1
2
3
4
5
−8
18
27
48
66
72
4
−6
−4
40
94
18
27
48
66
72
−8
−12
−9
18
27
48
66
72
0
53
18
28
47
55
64
1
18
27
48
66
72
1
−9
−10
10
−10
10
64
−16
5
23
119
101
127
1
36
78
107
1
50
50
79
65
59
126
1
59
126
0
86
86
126
123
1
0
0
0
0
0
0
Mode-
REG[12]
1
1
1
1
1
1
1
0
Mode-
REG[13]
For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3415B is also possible.
Table 6–15: DCO registers for the MSP 34x5G; reset status: DCO_HI/LO = “0000”
DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex
Freq. MHz
DCO_HI/hex
DCO_LO/hex
Freq. MHz
DCO_HI/hex
DCO_LO/hex
4.5
03E8
000
5.04
5.5
5.58
5.7421875
0460
04C6
04D8
04FC
0000
038E
0000
00AA
5.76
5.85
5.94
0500
0514
0528
0000
0000
0000
6.0
6.2
6.5
6.552
0535
0561
05A4
05B0
0555
0C71
071C
0000
6.6
6.65
6.8
05BA
05C5
05E7
0AAA
0C71
01C7
7.02
7.38
0618
0668
0000
0000
7.2
0640
0690
0000
0000
7.56
Micronas
85
MSP 34x5G
PRELIMINARY DATA SHEET
6.4. Manual/Compatibility Mode:
Table 6–16: NICAM operation modes as defined by
Description of Demodulator Read Registers
the EBU NICAM 728 specification
Note: The use of these register is no longer recom-
mended. It should be used only in cases where soft-
ware compatibility to the MSP 34x5D is required.
Using the STANDARD SELECTION register together
with the STATUS register provides a more economic
way to program the MSP 34x5G and to retrieve infor-
mation from the IC.
C4 C3 C2 C1 Operation Mode
0
0
0
0
0
0
0
0
1
0
1
0
Stereo sound (NICAMA/B),
independent mono sound (FM1)
Two independent mono signals
(NICAMA, FM1)
Three independent mono channels
(NICAMA, NICAMB, FM1)
All registers except C_AD_BITs are 8 bit wide. They
can be read out of the RAM of the MSP 34x5G if the
MSP 34x5D compatibility mode is required.
0
1
0
0
1
0
1
0
Data transmission only; no audio
Stereo sound (NICAMA/B), FM1
carries same channel
All transmissions take place in 16-bit words. The valid
8-bit data are the 8 LSBs of the received data word.
1
1
0
0
0
1
1
0
One mono signal (NICAMA). FM1
carries same channel as NICAMA
If the Automatic Sound Select feature is not used, the
NICAM or FM-identification parameters must be read
and evaluated by the controller in order to enable
appropriate switching of the channel select matrix of
the baseband processing part. The FM-identification
registers are described in Section 6.6.1. To handle the
NICAM-sound and to observe the NICAM-quality, at
least the registers C_AD_BITS and ERROR_RATE
must be read and evaluated by the controller. Addi-
tional data bits and CIB bits, if supplied by the NICAM
transmitter, can be obtained by reading the registers
ADD_BITS and CIB_BITS.
Two independent mono channels
(NICAMA, NICAMB). FM1 carries
same channel as NICAMA
1
x
0
1
1
x
1
x
Data transmission only; no audio
Unimplemented sound coding
option (not yet defined by EBU
NICAM 728 specification)
AUTO_FM: monitor bit for the AUTO_FM Status:
0: NICAM source is NICAM
1: NICAM source is FM
Note: It is no longer necessary to read out and evalu-
ate the C_AD_BITS. All evaluation is performed in the
MSP and indicated in the STATUS register.
6.4.1. NICAM Mode Control/Additional Data Bits
Register
NICAM operation mode control bits and A[2:0] of the
additional data bits.
6.4.2. Additional Data Bits Register
Format:
Contains the remaining 8 of the 11 additional data bits.
The additional data bits are not yet defined by the
NICAM 728 system.
MSB
C_AD_BITS 00 23hex
LSB
11
...
...
7
6
5
4
3
2
1
0
Auto
_FM
A[2] A[1] A[0]
C4
C3
C2
C1
S
Format:
MSB
7
ADD_BITS 00 38hex
LSB
0
6
5
4
3
2
1
Important: “S” = bit[0] indicates correct NICAM-syn-
chronization (S = 1). If S = 0, the MSP 3415/3455G
has not yet synchronized correctly to frame and
sequence, or has lost synchronization. The remaining
read registers are therefore not valid. The MSP mutes
the NICAM output automatically and tries to synchro-
nize again as long as MODE_REG[6] is set.
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
6.4.3. CIB Bits Register
Cib bits 1 and 2 (see NICAM 728 specifications).
Format:
The operation mode is coded by C4-C1 as shown in
Table 6–16.
MSB
CIB_BITS 00 3Ehex
LSB
0
7
x
6
x
5
x
4
x
3
x
2
x
1
CIB1
CIB2
86
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
6.4.4. NICAM Error Rate Register
6.4.7. Automatic Search Function for FM-Carrier
Detection in Satellite Mode
ERROR_RATE
Error free
00 57hex
0000hex
07FFhex
The AM demodulation ability of the MSP 3415G and
MSP 3455G offers the possibility to calculate the “field
strength” of the momentarily selected FM carrier,
which can be read out by the controller. In SAT receiv-
ers, this feature can be used to make automatic FM
carrier search possible.
maximum error rate
Average error rate of the NICAM reception in a time
interval of 182 ms, which should be close to 0. The ini-
tial and maximum value of ERROR_RATE is 2047.
This value is also active if the NICAM bit of
MODE_REG is not set. Since the value is achieved by
filtering, a certain transition time (approx. 0.5 sec) is
unavoidable. Acceptable audio may have error rates
up to a value of 700 int. Individual evaluation of this
value by the controller and an appropriate threshold
may define the fallback mode from NICAM to FM/
AM-mono in case of poor NICAM reception.
For this, the MSP has to be switched to AM-mode
(MODE_REG[8]), FM-Prescale must be set to
7Fhex= +127dec
,
and the FM DC notch (see
Section 6.5.7.) must be switched off. The sound-IF fre-
quency range must now be “scanned” in the
MSP-channel 2 by means of the programmable
quadrature mixer with an appropriate incremental fre-
quency (i.e. 10 kHz). After each incrementation, a field
strength value is available at the quasi-peak detector
output (quasi-peak detector source must be set to
FM), which must be examined for relative maxima by
the controller. This results in either continuing search
or switching the MSP back to FM demodulation mode.
The bit error rate per second (BER) can be calculated
by means of the following formula:
BER= ERROR_RATE * 12.3*10−6 /s
During the search process, the FIR2 must be loaded
with the coefficient set “AUTOSEARCH”, which
enables small bandwidth, resulting in appropriate field
strength characteristics. The absolute field strength
value (can be read out of “quasi peak detector output
FM1”) also gives information on whether a main FM
carrier or a subcarrier was detected; and as a practical
consequence, the FM bandwidth (FIR1/2) and the
deemphasis (50 µs or adaptive) can be switched
accordingly.
6.4.5. PLL_CAPS Readback Register
It is possible to read out the actual setting of the
PLL_CAPS. In standard applications, this register is
not of interest for the customer.
PLL_CAPS
02 1Fhex L
minimum frequency
nominal frequency
1111 1111
FFhex
56hex
Due to the fact that a constant demodulation frequency
offset of a few kHz, leads to a DC level in the demodu-
lated signal, further fine tuning of the found carrier can
be achieved by evaluating the “DC Level Readout
FM1”. Therefore, the FM DC Notch must be switched
on, and the demodulator part must be switched back to
FM-demodulation mode.
0101 0110
RESET
maximum frequency
PLL_CAPS
0000 0000
00hex
02 1Fhex
H
PLL open
xxxx xxx0
xxxx xxx1
For a detailed description of the automatic search
function, please refer to the corresponding MSP Win-
dows software.
PLL closed
6.4.6. AGC_GAIN Readback Register
It is possible to read out the actual setting of
AGC_GAIN in Automatic Gain Mode. In standard
applications, this register is not of interest for the cus-
tomer
.
AGC_GAIN
02 1Ehex
max. amplification
(20 dB)
0001 0100
14hex
00hex
min. amplification
(3 dB)
0000 0000
Micronas
87
MSP 34x5G
PRELIMINARY DATA SHEET
6.5. Manual/Compatibility Mode:
Description of DSP Write Registers
6.5.2. Volume Modes of SCART1 Output
Volume Mode SCART1
00 07hex
[3:0]
6.5.1. Additional Channel Matrix Modes
linear
0000
RESET
0hex
Loudspeaker Matrix
SCART1 Matrix
I2S Matrix
00 08hex
00 0Ahex
00 0Bhex
00 0Chex
L
L
L
L
logarithmic
0001
1hex
Linear Mode
Volume SCART1
OFF
Quasi-Peak
Detector Matrix
00 07hex
H
0000 0000
RESET
00hex
SUM/DIFF
0100 0000
0101 0000
0110 0000
0111 0000
1000 0000
1001 0000
40hex
50hex
60hex
70hex
80hex
90hex
AB_XCHANGE
PHASE_CHANGE_B
PHASE_CHANGE_A
A_ONLY
0 dB gain
(digital full scale (FS) to 2
VRMS output)
0100 0000
40hex
+6 dB gain (−6 dBFS to 2
VRMS output)
0111 1111
7Fhex
B_ONLY
6.5.3. FM Fixed Deemphasis
This table shows more modes for the channel matrix
registers.
FM Deemphasis
00 0Fhex
H
50 µs
0000 0000
RESET
00hex
The sum/difference mode can be used together with
the quasi-peak detector to determine the sound mate-
rial mode. If the difference signal on channel B (right)
is near to zero, and the sum signal on channel A (left)
is high, the incoming audio signal is mono. If there is a
significant level on the difference signal, the incoming
audio is stereo.
75 µs
J17
0000 0001
0000 0100
0011 1111
01hex
04hex
3Fhex
OFF
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Auto-
matic Sound Select (MODUS[0]=1) is on.
6.5.4. FM Adaptive Deemphasis
FM Adaptive
00 0Fhex
L
Deemphasis WP1
OFF
WP1
0000 0000
RESET
00hex
3Fhex
0011 1111
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Auto-
matic Sound Select (MODUS[0]=1) is on.
6.5.5. NICAM Deemphasis
A J17 Deemphasis is always applied to the NICAM sig-
nal. It is not switchable.
88
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
6.5.6. Identification Mode for A2 Stereo Systems
6.6. Manual/Compatibility Mode:
Description of DSP Read Registers
Identification Mode
00 15hex
L
All readable registers are 16-bit wide. Transmissions
via I2C bus have to take place in 16-bit words. Some of
the defined 16-bit words are divided into low and high
byte, thus holding two different control entities.
Standard B/G
(German Stereo)
0000 0000
RESET
00hex
Standard M
(Korean Stereo)
0000 0001
0011 1111
01hex
3Fhex
These registers are not writable.
Reset of Ident-Filter
6.6.1. Stereo Detection Register
for A2 Stereo Systems
To shorten the response time of the identification algo-
rithm after a program change between two FM-Stereo
capable programs, the reset of the ident-filter can be
applied.
Stereo Detection
Register
00 18hex
H
Stereo Mode
Reading
(two’s complement)
Sequence:
1. Program change
MONO
near zero
2. Reset ident-filter
STEREO
positive value (ideal
reception: 7Fhex
)
3. Set identification mode back to standard B/G or M
4. Wait approx. 500 ms
BILINGUAL
negative value (ideal
reception: 80hex)
5. Read stereo detection register
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Auto-
matic Sound Select (MODUS[0]=1) is on.
Note: It is no longer necessary to read out and evalu-
ate the A2 identification level. All evaluation is per-
formed in the MSP and indicated in the STATUS regis-
ter.
6.5.7. FM DC Notch
6.6.2. DC Level Register
The DC compensation filter (FM DC Notch) for FM
input can be switched off. This is used to speed up the
automatic search function (see Section 6.4.7.). In nor-
mal FM-mode, the FM DC Notch should be switched
on.
DC Level Readout
FM1 (MSP-Ch2)
00 1Bhex
00 1Chex
H+L
H+L
DC Level Readout
FM2 (MSP-Ch1)
FM DC Notch
00 17hex
L
DC Level
[8000hex ... 7FFFhex]
values are 16 bit two’s
complement
ON
0000 0000
Reset
00hex
OFF
0011 1111
3Fhex
The DC level register measures the DC component of
the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
FM frequencies fine tuning. A too low demodulation
frequency (DCO) results in a positive DC-Level and
vice versa. For further processing, the DC content of
the demodulated FM signals is suppressed. The time
constant τ, defining the transition time of the DC Level
Register, is approximately 28 ms.
Micronas
89
MSP 34x5G
PRELIMINARY DATA SHEET
6.7. Demodulator Source Channels in Manual Mode
6.7.1. Terrestric Sound Standards
6.8. Exclusions of Audio Baseband Features
In general, all functions can be switched independently.
Two exceptions exist:
Table 6–17 shows the source channel assignment of
the demodulated signals in case of manual mode for
all terrestric sound standards. See Table 2–2 for the
assignment in the Automatic Sound Select mode. In
manual mode for terrestric sound standards, only two
demodulator sources are defined.
1. NICAM cannot be processed simultaneously with
the FM2 channel.
2. FM adaptive deemphasis cannot be processed
simultaneously with FM-identification.
6.9. Compatibility Restrictions to MSP 34x0D
6.7.2. SAT Sound Standards
The MSP 34x5G is fully hardware compatible to the
MSP 34x5D. However, to substitute a MSP 34x5D by
the corresponding MSP 34x5G, the controller software
has to be adapted slightly:
Table 6–18 shows the source channel assignment of
the demodulated signals for SAT sound standards.
1. The register FM-Matrix (00 0Ehex low part) must be
changed from “no matrix (00hex)” to “sound A mono
(03hex)” during mono transmission of all TV-sound
standards (see also Table 6–17).
2. With the MSP 34x5G, the STANDARD SELECTION
initializes the FM-deemphasis, which is not the case
for the MSP 34x5D. So, if STANDARD SELECTION
is applied, this I2C instruction can be omitted.
90
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
Table 6–17: Manual Sound Select Mode for Terrestric Sound Standards
Source Channels of Sound Select Block
Broadcasted
Sound
Standard
Selected MSP Broadcasted
FM Matrix
FM/AM
Stereo or A/B
Standard
Sound Mode
(use 0 for channel select) (use 1 for channel select)
Code
B/G-FM
D/K-FM
M-Korea
M-Japan
03
04, 05
02
30
MONO
Sound A Mono
Mono
Mono
STEREO
German Stereo
Korean Stereo
Stereo
Stereo
BILINGUAL,
No Matrix
Left = A
Left = A
Languages A and B
Right = B
Right = B
B/G-NICAM
L-NICAM
I-NICAM
D/K-NICAM
D/K-NICAM
(with high
08
09
0A
0B
0C
NICAM not available Sound A Mono1) analog Mono
or NICAM error rate
too high
no sound
with AUTO_FM:
analog Mono
MONO
Sound A Mono1) analog Mono
Sound A Mono1) analog Mono
Sound A Mono1) analog Mono
NICAM Mono
NICAM Stereo
deviation FM)
STEREO
BILINGUAL,
Left = NICAM A
Right = NICAM B
Languages A and B
MONO
Sound A Mono
Korean Stereo
Sound A Mono
Korean Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
Mono
Stereo
STEREO
20
MONO + SAP
STEREO + SAP
MONO
BTSC
Sound A Mono
No Matrix
Mono
Mono
STEREO
21
40
MONO + SAP
STEREO + SAP
MONO
Left = Mono
Right = SAP
Left = Mono
Right = SAP
Sound A Mono
Korean Stereo
Mono
Mono
FM-Radio
STEREO
Stereo
Stereo
1) Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!
Table 6–18: Manual Sound Select Modes for SAT-Modes (FM Matrix is set automatically)
Source Channels of Sound Select Block for SAT-Modes
Broadcasted Selected
Broadcasted
Sound Mode
FM/AM
(source select: 0)
Stereo or A/B
(source select: 1)
Stereo or A
(source select: 3)
Stereo or B
(source select: 4)
Sound
MSP Standard
Code
Standard
6, 50
MONO
Mono
Mono
Mono
Mono
hex
51
STEREO
BILINGUAL
Stereo
Stereo
Stereo
A (FM1)
Stereo
B (FM2)
hex
FM SAT
Left = A (FM1)
Left = A (FM1)
Right = B (FM2)
Right = B (FM2)
Micronas
91
MSP 34x5G
PRELIMINARY DATA SHEET
7. Appendix D: Application Information
7.1. Phase Relationship of Analog Outputs
The user does not need to correct output phases when
using the loudspeaker output directly. The SCART1
output has opposite phase.
The following schematics shows the phase relation-
ship of all analog inputs and outputs.
Loudspeaker
SCART1-Ch.
Audio
Baseband
Processing
SCART1
SCART1
SCART
DSP
SCART2
Input
Select
MONO
SCART
Output Select
MONO, SCART1...2
Fig. 7–1: Phase diagram of the MSP 34x5G
92
Micronas
PRELIMINARY DATA SHEET
MSP 34x5G
7.2. Application Circuit
Signal GND
C s. section 4.6.2.
10
µF
100
nF
8 V (5 V)
-
100 p
56 p
IF 1 IN
Tuner
+
ANA_IN1+
18.432
MHz
3.3 100
µF nF
Alternative circuit for
ANA_IN1+ for more
attenuation of video
components:
+
1 K
+
10 µF
56 pF
56 pF
1 µF
DACM_L 29
DACM_R 28
55 MONO_IN
330 nF
Loudspeaker
1 µF
1 µF
1 nF
1 nF
52 SC1_IN_L
330 nF
53 SC1_IN_R
330 nF
AHVSS
51 ASG
49 SC2_IN_L
330 nF
330 nF
50 SC2_IN_R
MSP 34x5G
100Ω
100Ω
22 µF
5 V
SC1_OUT_L 37
SC1_OUT_R 36
+
+
7 STANDBYQ
6 ADR_SEL
22 µF
5 V
DVSS
DVSS
10 I2C_DA
9 I2C_CL
16 ADR_WS
17 ADR_CL
15 ADR_DA
D_CTR_I/O_0 5
D_CTR_I/O_1 4
12 I2S_WS
11 I2S_CL
14 I2S_DA_IN1
20 I2S_DA_IN2
TESTEN 61
13 I2S_DA_OUT
AHVSS
Note:
220
pF
470
pF
470
pF
Decoupling capacitors from
RESETQ
(from Controller, see section 4.6.3.3.)
470
pF
1.5
nF
10
µF
1.5
nF
10
1.5
nF
10
µF
− DVSUP to DVSS,
− AVSUP to AVSS, and
− AHVSUP to AHVSS
are recommended as closely
as possible to supply pins (see
application note on page 46).
µF
5 V
5 V
8 V
(5 V)
Note: Pin numbers refer to the PSDIP64 package.
Micronas
93
MSP 34x5G
PRELIMINARY DATA SHEET
8. Appendix E: MSP 34x5G Version History
MSP 3435G-A2
9. Data Sheet History
1. Preliminary data sheet: “MSP 34x5G Multistandard
Sound Processor Family, Edition Oct. 26, 1998, 6251-
480-1PD. First release of the preliminary data sheet.
First release for BTSC-Stereo/SAP and FM-Radio.
2. Preliminary data sheet: “MSP 34x5G Multistandard
Sound Processor Family”, Edition July 11, 2000, 6251-
480-2PD. Second release of the preliminary data
sheet.Major changes:
MSP 34x5G-B5
– additional package PLQFP64
– section 4.: specification for PLQFP64 package
added
– digital input specification changed as of version B5
and later (see Section 4.6. on page 53)
– specification for version B5 and B6 added
(see Appendix E: Version History)
– max. analog high supply voltage AHVSUP 8.7 V.
– supply currents changed as of version B5 and later
(see Section 4.6.3. on page 57)
– reset description modified
– I2S and ADR functionality added
– programmable A2 and carrier mute thresholds
– new D/K standard 0Dhex: HDEV3 and NICAM
– MSP 3425G and MSP 3465G added
– Multistandard controller software flow diagram
added
– additional preference in Automatic Standard Detec-
tion
MSP 34x5G-B6
– improved AM-performance (see page 69)
– new D/K standard for Poland
(see Table 3–7 on page 20)
– improved I2C hardware problem handling
(see Section 3.1.2. on page 15)
– faster system-D/K-loop for stereo detection
– extended features in the CONTROL register
(see Section 3.1.3. on page 16)
MSP 34x5G-B8
– faster A2-identification for all standards (mono/ste-
reo/bilingual detection)
– faster carrier mute
– EIA-J identification: faster stereo/bilingual to mono
transition time
– J17 FM-deemphasis implemented
– input specification for RESETQ and TESTEN
changed
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-480-2PD
94
Micronas
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