MSP3410DPP_技术文档

MSP 34x0D

PRELIMINARY DATA SHEET

Contents

Page

Section

Title

5

1.

Introduction

1.1.

1.2.

Common Features of MSP 34x0D

Specific Features of MSP 3410D

6

2.

Basic Features of the MSP 34x0D

Demodulator and NICAM Decoder Section

DSP Section (Audio Baseband Processing)

Analog Section

2.1.

2.2.

2.3.

7

3.

Application Fields of the MSP 34x0D

NICAM plus FM/AM-Mono

3.1.

3.2.

German 2-Carrier System (Dual-FM System)

10

11

12

13

15

16

4.

Architecture of the MSP 34x0D

Demodulator and NICAM Decoder Section

Analog Sound IF – Input Section

Quadrature Mixers

4.1.

4.1.1.

4.1.2.

4.1.3.

4.1.4.

4.1.5.

4.1.6.

4.1.7.

4.1.8.

4.1.9.

4.1.10.

4.2.

Low-pass Filtering Block for Mixed Sound IF Signals

Phase and AM Discrimination

Differentiators

Low-pass Filter Block for Demodulated Signals

High-Deviation FM Mode

FM Carrier Mute Function in the Dual-Carrier FM Mode

DQPSK Decoder

NICAM Decoder

Analog Section

4.2.1.

4.2.2.

4.3.

SCART Switching Facilities

Stand-by Mode

DSP Section (Audio Baseband Processing)

Dual-Carrier FM Stereo/Bilingual Detection

Audio PLL and Crystal Specifications

ADR Bus Interface

4.3.1.

4.4.

4.5.

4.6.

Digital Control Output Pins

I²S Bus Interface

4.7.

17

18

19

20

5.

I²C Bus Interface: Device and Subaddresses

Protocol Description

5.1.

5.2.

Proposal for MSP 34x0D I²C Telegrams

5.2.1.

5.2.2.

5.2.3.

5.2.4.

5.3.

Symbols

Write Telegrams

Read Telegrams

Examples

Start-Up Sequence: Power-Up and I²C-Controlling

2

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MSP 34x0D

Contents, continued

Page

Section

Title

21

22

23

24

25

27

28

30

31

32

33

35

6.

Programming the Demodulator and NICAM Decoder Section

6.1.

Short-Programming and General Programming of the Demodulator Part

Demodulator Write Registers: Table and Addresses

Demodulator Read Registers: Table and Addresses

Demodulator Write Registers for Short-Programming: Functions and Values

Demodulator Short-Programming

6.2.

6.3.

6.4.

6.4.1.

6.4.2.

6.5.

AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono

Demodulator Write Registers for the General Programming Mode: Functions and Values

Register ‘AD_CV’

6.5.1.

6.5.2.

6.5.3.

6.5.4.

6.6.

Register ‘MODE_REG’

FIR Parameter

DCO Registers

Demodulator Read Registers: Functions and Values

Autodetection of Terrestrial TV Audio Standards

C_AD_BITS

6.6.1.

6.6.2.

6.6.3.

6.6.4.

6.6.5.

6.6.6.

6.6.7.

6.6.8.

6.6.9.

6.7.

ADD_BITS [10...3] 0038_hex

CIB_BITS

ERROR_RATE 0057_hex

CONC_CT (for compatibility with MSP 3410B)

FAWCT_IST (for compatibility with MSP 3410B)

PLL_CAPS

AGC_GAIN

Sequences to Transmit Parameters and to Start Processing

Software Proposals for Multistandard TV Sets

Multistandard Including System B/G with NICAM/FM-Mono only

Multistandard Including System I with NICAM/FM-Mono only

Multistandard Including System B/G with NICAM/FM-Mono and German DUAL-FM

Satellite Mode

6.8.

6.8.1.

6.8.2.

6.8.3.

6.8.4.

6.8.5.

Automatic Search Function for FM Carrier Detection

37

39

40

41

42

43

44

45

46

7.

Programming the DSP Section (Audio Baseband Processing)

DSP Write Registers: Table and Addresses

DSP Read Registers: Table and Addresses

DSP Write Registers: Functions and Values

Volume – Loudspeaker and Headphone Channel

Balance – Loudspeaker and Headphone Channel

Bass – Loudspeaker and Headphone Channel

Treble – Loudspeaker and Headphone Channel

Loudness – Loudspeaker and Headphone Channel

Spatial Effects – Loudspeaker Channel

Volume – SCART1 and SCART2 Channel

Channel Source Modes

7.1.

7.2.

7.3.

7.3.1.

7.3.2.

7.3.3.

7.3.4.

7.3.5.

7.3.6.

7.3.7.

7.3.8.

7.3.9.

7.3.10.

7.3.11.

7.3.12.

7.3.13.

Channel Matrix Modes

SCART Prescale

FM/AM Prescale

FM Matrix Modes (see also Table 4–1)

FM Fixed Deemphasis

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PRELIMINARY DATA SHEET

Contents, continued

Page

Section

Title

46

47

48

49

50

51

7.3.14.

7.3.15.

7.3.16.

7.3.17.

7.3.18.

7.3.19.

7.3.20.

7.3.21.

7.3.22.

7.3.23.

7.3.24.

7.3.25.

7.4.

FM Adaptive Deemphasis

NICAM Prescale

NICAM Deemphasis

I²S1 and I²S2 Prescale

ACB Register

Beeper

Identification Mode

FM DC Notch

Mode Tone Control

Automatic Volume Correction (AVC)

Subwoofer Channel

Equalizer Loudspeaker Channel

Exclusions for the Audio Baseband Features

Phase Relationship of Analog Outputs

DSP Read Registers: Functions and Values

Stereo Detection Register

Quasi-Peak Detector

7.5.

7.6.

7.6.1.

7.6.2.

7.6.3.

7.6.4.

7.6.5.

7.6.6.

7.6.7.

DC Level Register

MSP Hardware Version Code

MSP Major Revision Code

MSP Product Code

MSP ROM Version Code

52

8.

Differences between MSP 3400C, MSP 3400D, MSP 3410B, and MSP 3410D

55

57

60

64

66

67

71

9.

Specifications

9.1.

Outline Dimensions

9.2.

Pin Connections and Short Descriptions

Pin Configurations

9.3.

9.4.

Pin Circuits (pin numbers refer to PLCC68 package)

Electrical Characteristics

9.5.

9.5.1.

9.5.2.

9.5.3.

Absolute Maximum Ratings

Recommended Operating Conditions

Characteristics

77

79

80

10.

11.

12.

Application Circuit

Appendix A: MSP 34x0D Version History

Data Sheet History

4

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PRELIMINARY DATA SHEET

MSP 34x0D

Multistandard Sound Processors

1.1. Common Features of MSP 34x0D

– AVC: Automatic Volume Correction

– Subwoofer Output

Release Notes: The hardware description in this

document is valid for the MSP 34x0D version B3

and following versions. Revision bars indicate sig-

nificant changes to the previous edition.

– 5-band graphic equalizer (as in MSP 3400C)

– Enhanced spatial effect (pseudostereo/basewidth

enlargement as in MSP 3400C)

1. Introduction

– headphone channel with balance, bass, treble, loud-

ness

The MSP 34x0D is designed as a single-chip Multi-

standard Sound Processor for applications in analog

and digital TV sets, satellite receivers, video recorders,

and PC cards.

– balance for loudspeaker and headphone channels

in dB units (optional)

– D/A converters for SCART2 out

The MSP 34x0D, again, improves function integration:

The full TV sound processing, starting with analog

sound IF signal-in, down to processed analog AF-out, is

performed in a single chip. It covers all European

TV standards (some examples are shown in Table 3–1).

– improved oversampling filters (as in MSP 3400C)

– Four SCART inputs

– Full SCART in/out matrix without restrictions

– SCART volume in dB units (optional)

– Additional I²S input (as in MSP 3400C)

– New FM identification (as in MSP 3400C)

– Demodulator short programming

– Autodetection for terrestrial TV sound standards

– Improved carrier mute algorithm

– Improved AM demodulation

The MSP 3400D is fully pin and software-compatible

to the MSP 3410D, but is not able to decode NICAM. It

is also compatible to the MSP 3400C.

The IC is produced in submicron CMOS technology,

combined with high-performance digital signal pro-

cessing. The MSP 34x0D is available in the following

packages: PLCC68, PSDIP64, PSDIP52, PQFP80,

and PLQFP64.

– ADR together with DRP 3510A

Note: The MSP 3410D version is fully downward-com-

patible to the MSP 3410B, the MSP 3400B, and the

MSP 3400C. To achieve full software-compatibility with

these types, the demodulator part must be programmed

as described in the data sheet of the MSP 3410B.

– Dolby Pro Logic together with DPL 351xA

– Reduction of necessary controlling

– Less external components

– Significant reduction of radiation

1.2. Specific Features of MSP 3410D

– All NICAM standards

– Precise bit-error rate indication

– Automatic switching from NICAM to FM/AM or vice-

versa

– Improved NICAM synchronization algorithm

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MSP 34x0D

PRELIMINARY DATA SHEET

2. Basic Features of the MSP 34x0D

2.2. DSP Section (Audio Baseband Processing)

– flexible selection of audio sources to be processed

2.1. Demodulator and NICAM Decoder Section

– two digital input and one output interface via I²S bus

for external DSP processors, featuring surround

sound, ADR etc.

The MSP 34x0D is designed to perform demodulation

of FM or AM-Mono TV sound. Alternatively, two-carrier

FM systems according to the German or Korean terres-

trial specs or the satellite specs can be processed with

the MSP 34x0D.

– digital interface to process ADR (ASTRA Digital

Radio) together with DRP 3510A

– performance of all deemphasis systems including

adaptive Wegener Panda 1 without external compo-

nents or controlling

Digital demodulation and decoding of NICAM-coded

TV stereo sound, is done only by the MSP 3410.

– digitally performed FM identification decoding and

The MSP 34x0D offers a powerful feature to calculate

the carrier field strength which can be used for auto-

matic standard detection (terrestrial) and search algo-

rithms (satellite). The IC may be used in TV sets, as

well as in satellite tuners and video recorders. It offers

profitable multistandard capability, including the follow-

ing advantages:

dematrixing

– digital baseband processing: volume, bass, treble,

5-band equalizer, loudness, pseudostereo, and

basewidth enlargement

– simple controlling of volume, bass, treble, equalizer

etc.

– two selectable analog inputs (TV and SAT-IF

sources)

2.3. Analog Section

– Automatic Gain Control (AGC) for analog IF input.

Input range: 0.10–3 V_pp

– four selectable analog pairs of audio baseband

inputs (= four SCART inputs)

– integrated A/D converter for sound-IF inputs

input level: ≤2 V_RMS

,

– all demodulation and filtering is performed on chip

input impedance: ≥25 kΩ

and is individually programmable

– one selectable analog mono input (i.e. AM sound):

– easy realization of all digital NICAM standards (B/G,

input level: ≤2 V_RMS

,

I, L, and D/K) with MSP 3410.

input impedance: ≥15 kΩ

– FM demodulation of all terrestrial standards (incl.

– two high-quality A/D converters, S/N-Ratio: ≥85 dB

identification decoding)

– 20 Hz to 20 kHz bandwidth for

– FM demodulation of all satellite standards

– no external filter hardware is required

SCART-to-SCART copy facilities

– MAIN (loudspeaker) and AUX (headphones): two

pairs of fourfold oversampled D/A-converters

output level per channel: max. 1.4 V_RMS

output resistance: max. 5 kΩ

– only one crystal clock (18.432 MHz) is necessary

– FM carrier level calculation for automatic search

algorithms and carrier mute function

S/N-ratio: ≥85 dB at maximum volume

max. noise voltage in mute mode: ≤10 µV

(BW: 20 Hz ...16 kHz)

– high-deviation FM-Mono mode (max. deviation:

approx. ±360 kHz)

– two pairs of fourfold oversampled D/A converters

supplying two selectable pairs of SCART outputs.

2

ADR

3

I S

I C

output level per channel: max. 2 V_RMS

,

output resistance: max. 0.5 kΩ,

S/N-Ratio: ≥85 dB (20 Hz ... 16 kHz)

5

2

1

2

Loudspeaker

OUT

Sound IF 1

Sound IF 2

MONO IN

Subwoofer

OUT

2

Headphones

OUT

SCART1 IN

SCART2 IN

SCART3 IN

SCART4 IN

MSP 34x0D

SCART1

OUT

SCART2

OUT

Fig. 2–1: Main I/O signals of the MSP 34x0D

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MSP 34x0D

3. Application Fields of the MSP 34x0D

In the case of NICAM/FM (AM) mode, there are three

different audio channels available: NICAM A,

NICAM B, and FM/AM-Mono. NICAM A and B may

belong either to a stereo or to a dual-language trans-

mission. Information about operation mode and the

quality of the NICAM signal can be read by the CCU

via the control bus. In the case of low quality (high bit-

error rate), the CCU may decide to switch to the ana-

log FM/AM-Mono sound. Alternatively, an automatic

NICAM-FM/AM switching may be applied.

In the following sections, a brief overview of the two

main TV sound standards, NICAM 728 and German

FM-Stereo, demonstrates the complex requirements of

a multistandard audio IC.

3.1. NICAM plus FM/AM-Mono

According to the British, Scandinavian, Spanish, and

French TV standards, high-quality stereo sound is

transmitted digitally. The systems allow two high-qual-

ity digital sound channels to be added to the already

existing FM/AM channel. The sound coding follows the

format of the so-called Near Instantaneous Compand-

ing System (NICAM 728). Transmission is performed

using Differential Quadrature Phase Shift Keying

(DQPSK). Table 3–2 provides some specifications of

the sound coding (NICAM); Table 3–3 offers an over-

view of the modulation parameters.

3.2. German 2-Carrier System (Dual-FM System)

Since September 1981, stereo and dual-sound pro-

grams have been transmitted in Germany using the

2-carrier system. Sound transmission consists of the

already existing first sound carrier and a second sound

carrier additionally containing an identification signal.

More details of this standard are given in Tables 3–1

and 3–4. For D/K and M-Korea, very similar systems

are used.

Table 3–1: TV standards

TV System

Position of Sound

Carrier /MHz

Sound

Modulation

Color System

Country

B/G

L

5.5/5.7421875

5.5/5.85

FM-Stereo

PAL

Germany

Scandinavia, Spain

France

FM-Mono/NICAM

AM-Mono/NICAM

FM-Mono/NICAM

FM-Stereo

PAL

6.5/5.85

SECAM-L

PAL

I

6.0/6.552

UK

D/K

6.5/6.2578125 D/K1

6.5/6.7421875 D/K2

6.5/5.85 D/K-NICAM

SECAM-East

USSR

FM-Mono/NICAM

Hungary

M

4.5

FM-Mono

NTSC

USA

M-Korea

4.5/4.724212

FM-Stereo

Korea

Satellite

6.5

7.02/7.2

FM-Mono

FM-Stereo

PAL

Europe (ASTRA)

Note: NICAM demodulation cannot be done with the MSP 3400D

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MSP 34x0D

PRELIMINARY DATA SHEET

Table 3–2: Summary of NICAM 728 sound coding characteristics

Characteristics

Values

32 kHz

2

Audio sampling frequency

Number of channels

Initial resolution

14 bits/sample

Companding characteristics

near instantaneous, with compression to 10 bits/sample in 32-sample

(1 ms) blocks

Coding for compressed samples

Preemphasis

2’s complement

CCITT recommendation J.17 (6.5 dB attenuation at 800 Hz)

Audio overload level

+12 dBm measured at the unity gain frequency of the preemphasis

network (2 kHz)

Table 3–3: Summary of NICAM 728 sound modulation parameters

Specification

I

B/G

L

D/K

Carrier frequency of

digital sound

6.552 MHz

5.85 MHz

Transmission rate

Type of modulation

728 kbit/s

Differentially encoded quadrature phase shift keying (DQPSK)

by means of Roll-off filters 1.0

Spectrum shaping

Roll-off factor

1.0

0.4

6.5 MHz AM mono

terrestrial cable

0.4

Carrier frequency of

analog sound component FM mono

6.0 MHz

5.5 MHz

FM mono

6.5 MHz

FM-Mono

Power ratio between

vision carrier and

analog sound carrier

10 dB

13 dB

7 dB

10 dB

16 dB

13 dB

Power ratio between

analog and modulated

digital sound carrier

17 dB

11 dB

Hungary

12 dB

Poland

7 dB

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PRELIMINARY DATA SHEET

MSP 34x0D

Table 3–4: Key parameters for B/G, D/K, and M 2-carrier sound system

Sound Carriers

Carrier FM1

D/K

Carrier FM2

D/K

20 dB

B/G

M

B/G

M

Vision/sound power ratio

Sound bandwidth

13 dB

40 Hz to 15 kHz

Preemphasis

50 µs

±50 kHz

75 µs

50 µs

±50 kHz

75 µs

Frequency deviation

Sound Signal Components

Mono transmission

±25 kHz

mono

(L+R)/2

language A

mono

Stereo transmission

Dual-sound transmission

(L+R)/2

R

(L−R)/2

language B

Identification of Transmission Mode on Carrier FM2

Pilot carrier frequency in kHz

Type of modulation

54.6875

55.0699

AM

Modulation depth

50 %

Modulation frequency

mono: unmodulated

stereo: 117.5 Hz

149.9 Hz

276.0 Hz

dual:

274.1 Hz

33 34 39 MHz

5

9

MHz

According to the mixing characteristics

of the sound IF mixer, the sound IF

filter may be omitted.

SAW Filter

Sound IF Filter

Sound

IF

Mixer

Tuner

Loudspeaker

1

Mono

Subwoofer

Headphone

Vision

Demo-

dulator

MSP 34x0D

2

SCART1

SCART2

SCART3

SCART4

SCART

Inputs

Composite

Video

2

SCART1

SCART2

SCART

Outputs

2

I S1

ADR

I S2

Dolby

ADR

Pro Logic

Processor

DPL35xxA

Decoder

DRP3510A

Fig. 3–1: Typical MSP 34x0D application

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MSP 34x0D

PRELIMINARY DATA SHEET

4. Architecture of the MSP 34x0D

4.1. Demodulator and NICAM Decoder Section

Fig. 4–1 shows a simplified block diagram of the IC. Its

4.1.1. Analog Sound IF – Input Section

architecture is split into three main functional blocks:

The input pins ANA_IN1+, ANA_IN2+, and ANA_IN−

offer the possibility to connect two different sound IF

(SIF) sources to the MSP 34x0D. By means of bit [8] of

AD_CV (see Table 6–5 on page 25), either terrestrial

or satellite sound IF signals can be selected. The ana-

log-to-digital conversion of the preselected sound IF

signal is done by an A/D converter whose output is

used to control an analog automatic gain circuit (AGC)

providing an optimal level for a wide range of input lev-

els. It is possible to switch between automatic gain

control and a fixed (setable) input gain. In the optimal

case, the input range of the A/D converter is com-

pletely covered by the sound IF source. Some combi-

nations of SAW filters and sound IF mixer ICs, how-

ever, show large picture components on their outputs.

In this case, filtering is recommended. It was found,

that the high-pass filters formed by the coupling capac-

itors at pins ANA_IN1+ and ANA_IN2+ and the IF

impedance (as shown in the application diagram) are

sufficient in most cases.

1. demodulator and NICAM decoder section

2. digital signal processing (DSP) section performing

audio baseband processing

3. analog section containing two A/D-converters,

nine D/A-converters, and SCART Switching Facili-

ties.

I2S_DA_OUT

I2S_CL

AUD_CL_OUT XTAL_OUT

XTAL_IN

ADR-Bus

I2S_DA_IN1

I2S_DA_IN2 I2S_WS

2

Crystal PLL

I S Interface

2

Sound IF

I2S1/2L/R I2S_L/R

D_CTR_OUT0/1

DACM_L

Demodulator

& NICAM

Decoder

FM1/AM

FM2

LOUD-

SPEAKER L

D/A

ANA_IN1+

ANA_IN2+

Loudspeaker

DACM_R

NICAM A

NICAM B

LOUD-

SPEAKER R

SUBWOOFER

DACM_SUB

Mono

IDENT

Subwoofer

DSP

MONO_IN

D/A

HEADPHONE L

DACA_L

SC1_IN_L

Headphone

DACA_R

SCART1

SC1_IN_R

HEADPHONE R

A/D

SCARTL

SCARTR

SC2_IN_L

D/A

SCART1_L

SCART1_R

SC1_OUT_L

SCART2

SC2_IN_R

SCART 1

SC1_OUT_R

D/A

SCART2_L

SCART2_R

SC3_IN_L

SC2_OUT_L

SCART 2

SC2_OUT_R

SCART3

SC3_IN_R

SC4_IN_L

SCART Switching Facilities

SCART4

SC4_IN_R

Fig. 4–1: Architecture of the MSP 34x0D

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MSP 34x0D

4.1.2. Quadrature Mixers

4.1.3. Low-pass Filtering Block

for Mixed Sound IF Signals

The digital input coming from the integrated A/D con-

verter may contain audio information at a frequency

range of theoretically 0 to 9 MHz corresponding to the

selected standards. By means of two programmable

quadrature mixers, two different audio sources, for

example NICAM and FM-Mono, may be shifted into

baseband position. In the following, the two main

channels are provided to process either:

Data shaping and/or FM bandwidth limitation is per-

formed by a linear phase finite impulse response (FIR)

filter. Just like the oscillators’ frequency, the filter coeffi-

cients are programmable and are written into the IC by

the CCU via the control bus. Thus, for example, differ-

ent NICAM versions can easily be implemented. Two

not necessarily different sets of coefficients are

required, one for MSP-Ch1 (NICAM or FM2) and one

for MSP-Ch2 (FM1 = FM-mono). In a corresponding

table several coefficient sets are proposed.

– NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2)

simultaneously or, alternatively:

– FM-Mono (Ch2)

– FM2 (MSP-Ch1) and FM1 (MSP-Ch2).

Two programmable registers, to be divided up into a

low and a high part, determine frequency of the oscilla-

tor, which corresponds to the frequency of the desired

audio carrier.

DCO1

ADR

MSP3410D only

MODE_REG[6]

Oscillator

NICAMA

DQPSK

Decoder

NICAM

Decoder

FIR1

NICAMB

Phase

Phase and

AM Dis-

crimination

Mixer

Lowpass

Differen-

tiator

FM2

Mute

Lowpass

VREFTOP

MSP sound IF channel 1

(MSP-Ch1: FM2, NICAM)

Carrier

Detect

AD_CV[7:1]

AGC

Amplitude

IDENT

Mixer

ANA_IN1+

ANA_IN2+

AD_CV[9]

AD

Carrier

Detect

AD_CV[8]

MSP sound IF channel 2

(MSP-Ch2: FM1, AM)

Amplitude

ANA_IN-

Mute

Lowpass

FM1/AM

Phase and

AM Dis-

crimination

Mixer

Lowpass

FIR2

Differen-

tiator

Phase

MODE_REG[8]

FRAME

Pins

Oscillator

DCO2

Internal signal lines (see fig. 4–2)

Demodulator Write Registers

NICAMA

DCO2

Fig. 4–2: Architecture of demodulator and NICAM decoder section

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PRELIMINARY DATA SHEET

4.1.4. Phase and AM Discrimination

4.1.8. FM Carrier Mute Function

in the Dual-Carrier FM Mode

The filtered sound IF signals are demodulated by

means of the phase and amplitude discriminator block.

On the output, the phase and amplitude is available for

further processing. AM signals are derived from the

amplitude information, whereas the phase information

serves for FM and NICAM (DQPSK) demodulation.

To prevent noise effects or FM identification problems

in the absence of one of the two FM carriers, the

MSP 34x0D offers a carrier detection feature, which

must be activated by means of AD_CV[9]. If no FM

carrier is available at the MSPD channel 1, the corre-

sponding channel FM2 is muted. If no FM carrier is

available at the MSPD channel 2, the corresponding

channel FM1 is muted.

4.1.5. Differentiators

FM demodulation is completed by differentiating the

phase information output.

4.1.9. DQPSK Decoder

In case of NICAM mode, the phase samples are

decoded according the DQPSK-coding scheme. The

output of this block contains the original NICAM bit-

stream.

4.1.6. Low-pass Filter Block

for Demodulated Signals

The demodulated FM and AM signals are further low-

pass filtered and decimated to a final sampling fre-

quency of 32 kHz. The usable bandwidth of the final

baseband signals is about 15 kHz.

4.1.10. NICAM Decoder

Before any NICAM decoding can start, the MSP must

lock to the NICAM frame structure by searching and

synchronizing to the so-called frame alignment words

(FAW).

4.1.7. High-Deviation FM Mode

By means of MODE_REG [9], the maximum FM devi-

ation can be extended to approximately ±360 kHz.

Since this mode can be applied only for the MSP

sound IF channel 2, the corresponding matrices in the

baseband processing must be set to sound A. Apart

from this, the coefficient sets 380 kHz FIR2 or 500 kHz

FIR2 must be chosen for the FIR2. In relation to the

normal FM mode, the audio level of the high-deviation

mode is reduced by 6 dB. The FM prescaler should be

adjusted accordingly. In high-deviation FM mode, nei-

ther FM-Stereo nor FM identification nor NICAM pro-

cessing is possible simultaneously.

To reconstruct the original digital sound samples, the

NICAM bitstream has to be descrambled, deinter-

leaved, and rescaled. Also, bit-error detection and cor-

rection (concealment) is performed in this block.

To facilitate the Central Control Unit CCU to switch the

(e.g.) TV set to the actual sound mode, control infor-

mation on the NICAM mode and bit error rate are sup-

plied by the NICAM decoder. It can be read out via the

I²C bus.

An automatic switching facility (AUTO_FM) between

NICAM and FM/AM reduces the amount of

CCU instructions in case of bad NICAM reception.

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MSP 34x0D

4.2. Analog Section

selected SCART inputs to SCART outputs in the

TV set’s stand-by mode.

4.2.1. SCART Switching Facilities

In case of power-on start or starting from stand-by, the

IC switches automatically to the default configuration,

shown in Fig. 4–3. This action takes place after the

first I²C transmission into the DSP part. By transmitting

the ACB register first, the individual default setting

mode of the TV set can be defined.

The analog input and output sections include full matrix

switching facilities, which are shown in Fig. 4–3. To

design a TV set with four pairs of SCART inputs and

two pairs of SCART outputs, no external switching

hardware is required.

The switches are controlled by the ACB bits defined in

the audio processing interface (see section 7.3.18. on

page 47).

4.3. DSP Section (Audio Baseband Processing)

All audio baseband functions are performed by digital

signal processing (DSP). The DSP functions are

grouped into three processing parts: input preprocess-

ing, channel source selection, and channel postpro-

cessing (see Fig. 4–5 and section 7.).

SCART_IN

ACB[5,9,8]

SC1_IN_L/R

to Audio Baseband

SC2_IN_L/R

SC3_IN_L/R

SC4_IN_L/R

MONO_IN

Processing (DSP_IN)

A

D

The input preprocessing is intended to prepare the

various signals of all input sources in order to form a

standardized signal at the input to the channel selec-

tor. The signals can be adjusted in volume, are pro-

cessed with the appropriate deemphasis, and are

dematrixed if necessary.

SCARTL/R

S1

Mute

ACB[6,11,10]

Having prepared the signals that way, the channel

selector makes it possible to distribute all possible

source signals to the desired output channels.

SCART_OUT

The ability to route in an external coprocessor for spe-

cial effects, like surround processing and sound field

processing, is of special importance. Routing can be

done with each input source and output channel via

the I²S inputs and outputs.

SC1_OUT_L/R

S2

Mute

All input and output signals can be processed simulta-

neously with the exception that FM2 cannot be pro-

cessed at the same time as NICAM. FM identification

and adaptive deemphasis are also not possible simul-

taneously. Note, that the NICAM input signals are only

available in the MSP 3410D version.

ACB[7,13,12]

SCART_OUT

from Audio Baseband

Processing (DSP_OUT)

SC2_OUT_L/R

D

A

4.3.1. Dual-Carrier FM Stereo/Bilingual Detection

SCART1_L/R

SCART2_L/R

For the terrestrial dual-FM carrier systems, audio infor-

mation can be transmitted in three modes: mono, ste-

reo, or bilingual. To obtain information about the current

audio operation mode, the MSP 34x0D detects the so-

called identification signal. Information is supplied via

the Stereo Detection Register to an external CCU.

S3

Mute

Fig. 4–3: SCART switching facilities (see 7.3.18.).

Switching positions show the default configuration

after power-on reset

Stereo

Level

Detection

Detect

Filter

4.2.2. Stand-by Mode

AM

Demodu-

lation

Stereo

Detection

Register

IDENT

−

If the MSP 34x0D is switched off by first pulling

STANDBYQ low, and then disconnecting the 5 V, but

keeping the 8 V power supply (‘Stand-by’-mode), the

switches S1, S2, and S3 (see Fig. 4–3) maintain their

position and function. This facilitates the copying from

Bilingual

Detection

Filter

Level

Detect

Fig. 4–4: Stereo/bilingual detection

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MSP 34x0D

Table 4–1: Some examples for recommended channel assignments for demodulator and audio processing part

Mode

MSP Sound IF-

Channel 1

MSP Sound IF-

Channel 2

FM-

Matrix

Channel-

Select

Channel

Matrix

B/G-Stereo

FM2 (5.74 MHz): R

FM1 (5.5 MHz): (L+R)/2

FM1 (5.5 MHz): Sound A

B/G Stereo

No Matrix

Speakers: FM

Stereo

B/G-Bilingual

FM2 (5.74 MHz): Sound B

Speakers: FM

H. Phone: FM

Speakers: Sound A

H. Phone: Sound B

NICAM-I-ST/

FM-mono

NICAM (6.552 MHz)

FM (6.0 MHz): mono

FM (6.5 MHz): mono

No Matrix

Speakers: NICAM

H. Phone: FM

Speakers: Stereo

H. Phone: Sound A

Sat-Mono

not used

No Matrix

Speakers: FM

Sound A

Stereo

Sat-Stereo

Sat-Bilingual

7.2 MHz: R

7.02 MHz:

L

7.38 MHz: Sound C

7.02 MHz: Sound A

6.552 MHz

Speakers: FM

H. Phone: FM

Speakers: Sound A

H. Phone: Sound B=C

Sat-High Dev.

Mode

don’t care

No Matrix

Speakers: FM

H. Phone: FM

Speakers: Sound A

H. Phone: Sound A

4.4. Audio PLL and Crystal Specifications

4.5. ADR Bus Interface

The MSP 34x0D requires a 18.432 MHz (12 pF, paral-

lel) crystal. The clock supply of the whole system

depends on the MSP 34x0D operation mode:

For the ASTRA Digital Radio System (ADR), the

MSP 34x0D performs preprocessing, as there are car-

rier selection and filtering. Via the 3-line ADR bus, the

resulting signals are transferred to the DRP 3510A,

where the source decoding is performed. To be pre-

pared for an upgrade to ADR with an additional DRP

board, the following lines of MSP 34x0D should be

provided on a feature connector:

1. FM-Stereo, FM-Mono:

The system clock runs free on the crystal’s

18.432 MHz.

2. NICAM:

An integrated clock PLL uses the 364 kHz baud

rate, accomplished in the NICAM demodulator block

to lock the system clock to the bit rate, respectively,

32-kHz sampling rate of the NICAM transmitter. As

a result, the whole audio system is supplied with a

controlled 18.432 MHz clock.

– AUD_CL_OUT

– I2S_DA_IN1 or I2S_DA_IN2

– I2S_DA_OUT

– I2S_WS

3. I²S slave operation:

– I2S_CLK

In this case, the system clock is locked to a synchro-

nizing signal (I2S_CL, I2S_WS) supplied by the

coprocessor chip.

– ADR_CL

– ADR_WS

– ADR_DA

Remark on using the crystal:

External capacitors at each crystal pin to ground are

required (see General Crystal Recommendations on

page 69).

4.6. Digital Control Output Pins

The static level of two output pins of the MSP 34x0D

(D_CTR_OUT0/1) is switchable between HIGH and

LOW by means of the I²C bus. This enables the con-

trolling of external hardware-controlled switches or

other devices via I²C bus (see section 7.3.18. on page

47).

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4.7. I²S Bus Interface

The I²S bus interface consists of five pins:

1. I2S_DA_IN1, I2S_DA_IN2:

By means of this standardized interface, additional

feature processors can be connected to the

MSP 34x0D. Two possible formats are supported: The

standard mode (MODE_REG[4]=0) selects the SONY

format, where the I2S_WS signal changes at the word

boundaries. The so-called PHILIPS format, which is

characterized by a change of the I2S_WS signal one

I2S_CL period before the word boundaries, is selected

by setting MODE_REG[4]=1.

For input, four channels (two channels per line,

2*16 bits) per sampling cycle (32 kHz) are transmit-

ted.

2. I2S_DA_OUT:

For output, two channels (2*16 bits) per sampling

cycle (32 kHz) are transmitted.

3. I2S_CL:

Gives the timing for the transmission of I²S serial

data (1.024 MHz).

The MSP 34x0D normally serves as the master on the

I²S interface. Here, the clock and word strobe lines are

4. I2S_WS:

driven

by

the

MSP 34x0D.

By

setting

The I2S_WS word strobe line defines the left and

right sample.

MODE_REG[3]=1, the MSP 34x0D is switched to a

slave mode. Now, these lines are input to the

MSP 34x0D and the master clock is synchronized to

576 times the I2S_WS rate (32 kHz). NICAM operation

is not possible in this mode.

A precise I²S timing diagram is shown in Fig. 4–6.

(Data: MSB first)

F_I2SWS

I2S_WS

SONY Mode

PHILIPS Mode

PHILIPS/SONY Mode programmable by MODE_REG[4]

Detail C

I2S_CL

Detail A

I2S_DAIN

R LSB L MSB

L LSB R MSB

R LSB L LSB

16 bit left channel

16 bit right channel

Detail B

I2S_DAOUT

R LSB L MSB

L LSB R MSB

R LSB L LSB

16 bit left channel

Detail C

Detail A,B

1/F_I2SCL

I2S_CL

T_I2S1

T_I2S2

T_I2SWS1

T_I2SWS2

I2S_WS as INPUT

I2S_DA_IN

T_I2S3

T_I2S4

T_I2S5

T_I2S6

I2S_WS as OUTPUT

I2S_DA_OUT

Fig. 4–6: I²S bus timing diagram

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MSP 34x0D

5. I²C Bus Interface: Device and Subaddresses

Due to the internal architecture of the MSP 34x0D, the

IC cannot react immediately to an I²C request. The typ-

ical response time is about 0.3 ms for the DSP proces-

sor part and 1 ms for the demodulator part if NICAM

processing is active. If the receiver (MSP) can’t receive

another complete byte of data until it has performed

some other function; for example, servicing an internal

interrupt, it can hold the clock line I2C_CL LOW to

force the transmitter into a wait state. The positions

within a transmission where this may happen are indi-

cated by ’Wait’ in section 5.1. The maximum wait

period of the MSP during normal operation mode is

less than 1 ms.

As a slave receiver, the MSP 34x0D can be controlled

via I²C bus. Access to internal memory locations is

achieved by subaddressing. The demodulator and the

DSP processor parts have two separate subaddress-

ing register banks.

In order to allow for more MSP 34x0D ICs to be con-

nected to the control bus, an ADR_SEL pin has been

implemented. With ADR_SEL pulled to HIGH, LOW, or

left open, the MSP 34x0D responds to changed device

addresses. Thus, three identical devices can be

selected.

I²C bus error caused by MSP hardware problems:

In case of any internal error, the MSPs wait period is

extended to 1.8 ms. Afterwards, the MSP does not

acknowledge (NAK) the device address. The data line

will be left HIGH by the MSP and the clock line will be

released. The master can then generate a STOP con-

dition to abort the transfer.

By means of the RESET bit in the CONTROL register,

all devices with the same device address are reset.

The IC is selected by asserting a special device

address in the address part of an I²C transmission. A

device address pair is defined as a write address (80,

84, or 88_hex) and a read address (81, 85, or 89_hex

)

(see Table 5–1). Writing is done by sending the device

write address, followed by the subaddress byte, two

address bytes, and two data bytes. Reading is done by

sending the device write address, followed by the sub-

address byte and two address bytes. Without sending

a stop condition, reading of the addressed data is com-

pleted by sending the device read address (81, 85, or

89_hex) and reading two bytes of data (see Fig. 5–1:

“I²C Bus Protocol” and section 5.2. “Proposal for

MSP 34x0D I²C Telegrams”).

By means of NAK, the master is able to recognize the

error state and to reset the IC via I²C bus. While trans-

mitting the reset protocol (see section 5.2.4. on page

19) to ‘CONTROL’, the master must ignore the not-

acknowledge bits (NAK) of the MSP.

A general timing diagram of the I²C Bus is shown in

Fig. 5–2 on page 19.

Table 5–1: I²C Bus Device Addresses

ADR_SEL

Low

Read

81 hex

High

Read

85 hex

Left Open

Read

89 hex

Mode

Write

MSP device address

80 hex

84 hex

88 hex

Table 5–2: I²C Bus Subaddresses

Name

Binary Value

Hex Value

Mode

W

Function

CONTROL

TEST

0000 0000

0000 0001

0001 0000

0001 0001

0001 0010

0001 0011

00

01

10

11

12

13

software reset

W

only for internal use

WR_DEM

RD_DEM

WR_DSP

RD_DSP

W

write address demodulator

read address demodulator

write address DSP

W

read address DSP

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PRELIMINARY DATA SHEET

Table 5–3: Control Register (Subaddress: 00 hex)

Name

Subaddress

MSB

14

13..1

LSB

CONTROL

00 hex

1 : RESET

0 : normal

0

5.1. Protocol Description

Write to DSP or Demodulator

S

write

device

address

Wait

ACK

subaddr

ACK

addr byte

high

ACK

addr byte

low

ACK

data byte

high

ACK

data byte

low

ACK

P

Read from DSP or Demodulator

S

write

device

address

Wait ACK

subaddr

ACK addr byte ACK addr byte ACK

high low

S

read

device

address

Wait

ACK data byte ACK data byte NAK

high low

P

Write to Control or Test Registers

S

write

device

address

Wait ACK

subaddr

ACK

data byte high

ACK

data byte low

ACK

P

Note: S =

I²C bus Start Condition from master

I²C bus Stop Condition from master

P =

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (=MSP, gray)

or master (=CCU, hatched)

NAK = Not-Acknowledge Bit: HIGH on I2C_DA from master (=CCU, hatched) to indicate ‘End of Read’

or from MSP indicating internal error state

Wait = I²C clock line held low by the slave (=MSP) while interrupt is serviced (<1.8 ms)

1

0

I2C_DA

S

P

I2C_CL

Fig. 5–1: I²C bus protocol

(MSB first; data must be stable while clock is high)

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PRELIMINARY DATA SHEET

(Data: MSB first)

MSP 34x0D

1

f_I2C

T_I2C4

T_I2C3

I2C_CL

T_I2C1

T_I2C5

T_I2C6

T_I2C2

I2C_DA as input

T_I2COL2

T_I2COL1

I2C_DA as output

Fig. 5–2: I²C bus timing diagram

5.2. Proposal for MSP 34x0D I²C Telegrams

5.2.1. Symbols

daw

dar

<

>

aa

dd

write device address

read device address

start condition

stop condition

address byte

data byte

5.2.2. Write Telegrams

write to CONTROL register

write data into demodulator

write data into DSP

5.2.3. Read Telegrams

<daw 11 aa aa <dar dd dd> read data from demodulator

<daw 13 aa aa <dar dd dd> read data from DSP

5.2.4. Examples

<80 00 80 00>

<80 00 00 00>

RESET MSP statically

clear RESET

<80 12 00 08 01 20>

set loudspeaker channel source

to NICAM and matrix to STEREO

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PRELIMINARY DATA SHEET

5.3. Start-Up Sequence: Power-Up and I²C-Controlling

After power-on or RESET (see Fig. 5–3), the IC is in

an inactive state. The CCU has to transmit the

required coefficient set for a given operation via the

I²C bus. Initialization should start with the demodulator

part. If required for any reason, the audio processing

part can be loaded before the demodulator part.

DVSUP

AVSUP

4.5 V

t/ms

Low-to-High

Threshold

RESETQ

0.7×DVSUP

0.45...0.55×DVSUP

High-to-Low

Threshold

t/ms

Reset Delay

>2 ms

Internal

Reset

High

Low

t/ms

Note: The reset should

not reach high level be-

fore the oscillator has

started. This requires a

reset delay of >2 ms

Power-Up Reset: Threshold and Timing

(Note: 0.7×DVSUP means 3.5 Volt with DVSUP=5.0 Volt)

Fig. 5–3: Power-up sequence

20

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MSP 34x0D

6. Programming the Demodulator

and NICAM Decoder Section

6.1. Short-Programming and General

Programming of the Demodulator Part

The demodulator part of the MSP 34x0D can be pro-

grammed in two different modes:

1. Demodulator Short-Programming provides a com-

fortable way to set up the demodulator for many terres-

trial TV sound standards with one single I²C bus trans-

mission. The coding is listed in section 6.4.1. If a

parameter does not coincide with the individual pro-

gramming concept, it simply can be overwritten by

using the General Programming Mode. Some bits of

the registers AD_CV (see section 6.5.1. on page 25)

and MODE_REG (see section 6.5.2. on page 27) are

not affected by the short-programming. They must be

transmitted once if their reset status does not fit. The

Demodulator Short-Programming is not compatible to

MSP 3410B and MSP 3400C.

Autodetection for terrestrial TV standards is part of

the Demodulator Short-Programming. This feature

enables the detection and set-up of the actual TV

sound standard within 0.5 s. Since the detected stan-

dard is readable by the control processor, the Autode-

tection feature is mainly recommended for the primary

set-up of a TV set: after having once determined the

corresponding TV channels, their sound standards can

be stored and later on programmed by the Demodula-

tor Short-Programming (see section 6.4.1. on page 23

and section 6.6.1. on page 32).

2. General Programming ensures the software-com-

patibility to other MSPs. It offers a very flexible way to

apply all of the MSP 34x0D demodulator facilities. All

registers except 0020_hex(Demodulator Short-Pro-

gramming) have to be written with values correspond-

ing to the individual requirements. For satellite applica-

tions, with their many variations, this mode must be

selected.

All transmissions on the control bus are 16 bits wide.

However, data for the demodulator part have only 8 or

12 significant bits. These data have to be inserted

LSB-bound and filled with zero bits into the 16-bit

transmission word. Table 4–1 explains how to assign

FM carriers to the MSP Sound IF channels and the

corresponding matrix modes in the audio processing

part.

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6.2. Demodulator Write Registers: Table and Addresses

Table 6–1: Demodulator Write Registers; Subaddress: 10_hex; these registers are not readable!

Demodulator

Write Registers

Address

(hex)

Function

Demodulator

Short-

Programming

0020

Write into this register to apply Demodulator Short Programming (see sec-

tion 6.4.1. on page 23). If the internal setting coincidences with the individ-

ual requirements no more of the remaining Demodulator Write Registers

have to be transferred.

AUTO_FM/AM

0021

Only for NICAM: Automatic switching between NICAM and FM/AM in case

of bad NICAM reception (see section 6.4.2. on page 24)

Write Registers necessary for General Programming Mode only

AD_CV

00BB

input selection, configuration of AGC, Mute Function and selection of

A/D converter, FM Carrier Mute on/off

MODE_REG

0083

mode register

FIR1

FIR2

0001

0005

filter coefficients channel 1 (6 × 8 bit)

filter coefficients channel 2 (6 × 8 bit), + 3 × 8 bit offset (total 72 bits)

DCO1_LO

DCO1_HI

0093

009B

increment channel 1 low part

increment channel 1 high part

DCO2_LO

DCO2_HI

00A3

00AB

increment channel 2 low part

increment channel 2 high part

PLL_CAPS

001F

switchable PLL capacitors to tune open-loop frequency; to use only if

NICAM of MODE_REG = 0 ; normally not of interest for the customer

6.3. Demodulator Read Registers: Table and Addresses

Table 6–2: Demodulator Read Registers; Subaddress: 11_hex; these registers are not writable!

Demodulator

Read Registers

Address

(hex)

Function

Result of

007E

(see Table 6–13)

Autodetection

C_AD_BITS

ADD_BITS

CIB_BITS

0023

0038

003E

0057

0058

0025

021F

021E

NICAM Sync bit, NICAM C bits, and three LSBs of additional data bits

NICAM: bit [10:3] of additional data bits

NICAM: CIB1 and CIB2 control bits

ERROR_RATE

CONC_CT

FAWCT_IST

PLL_CAPS

AGC_GAIN

NICAM error rate, updated with 182 ms

only to be used in MSPB compatibility mode

Not for customer use.

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MSP 34x0D

6.4. Demodulator Write Registers for Short-Programming: Functions and Values

In the following, the functions of some registers are explained and their (default) values are defined:

6.4.1. Demodulator Short-Programming

Table 6–3: MSP 34x0D Demodulator Short-Programming

Demodulator Short-Programming 0020_hex

TV Sound Standard

Internal Setting

Description

Code

(hex)

AD_CV²⁾

MODE_

DCO1

(MHz)

DCO2

(MHz)

FIR1/2

Coefficients

Identifica-

tion

(see Table 6–5) REG²⁾

(see

Mode

Table 6–8)

Autodetection

M Dual-FM

0001

0002

Detects and sets one of the standards listed below, if available. Results are to be

read out of the demodulator read register “Result of Autodetection” (section 6.6.1.)

AD_CV- FM M1

4.72421

4.5

Reset, then

Standard M

seeTable 6–11:

Terrestrial TV

Standards

B/G Dual-FM

D/K1 Dual-FM

D/K2 Dual-FM

0003

0004

0005

AD_CV-FM

M1

5.74218

6.25781

6.74218

5.5

6.5

Reset, then

Standard

B/G

0006/

0007

reserved for future dual-FM standards

AUTO_

FM/AM

B/G NICAM FM

L NICAM AM

I NICAM FM

0008

0009

000A

000B

>000B

AD_CV-FM

AD_CV-AM

AD_CV-FM

M2

M3

M2

5.85

6.552

5.85

5.5

6.5

6.0

6.5

seeTable 6–11:

Terrestrial TV

Standards

1)

D/K NICAM FM

reserved for future NICAM Standards

1)

corresponds to the actual setting of AUTO_FM (Address = 0021_hex

bits of AD_CV or MODE_REG, which are not affected by the short-programming, must be transmitted

separately if their reset status does not fit.

)

2)

Note: All parameters in the DSP section (Audio Baseband Processing), except the identification mode register,

are not affected by the Demodulator Short-Programming. They still have to be defined by the control pro-

cessor.

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6.4.2. AUTO_FM/AM: Automatic Switching

between NICAM and FM/AM-Mono

There are two possibilities to define the threshold

deciding for NICAM or FM/AM-Mono (see Table 6–4):

1. default value of the MSPD (internal threshold = 700,

i.e. switch to FM/AM if ERROR_RATE > 700)

In case of bad NICAM transmission or loss of the

NICAM carrier, the MSPD offers a comfortable mode to

switch back to the FM/AM-Mono signal. If automatic

switching is active, the MSP internally evaluates the

ERROR_RATE. All output channels which are assigned

to the NICAM source are switched back to the

FM/AM-Mono source without any further CCU instruc-

tion, if the NICAM carrier fails or the ERROR_RATE

exceeds the definable threshold.

2. definable by the customer (recommendable range:

threshold = 50...2000, i.e. Bits [10...1] = 25...1000).

Note: The auto_FM feature is only active if the NICAM

bit of MODE_REG is set.

Note, that the channel matrix of the corresponding out-

put channels must be set according to the NICAM

mode and need not be changed in the FM/AM fall-back

case. An appropriate hysteresis algorithm avoids oscil-

lating effects. The MSB of the Register C_AD_BITS

(Addr: 0023_hex) informs about the actual NICAM

FM/AM Status (see section 6.6.2. on page 32).

Table 6–4: Coding of automatic NICAM FM/AM switching (reset status: mode 0)

Mode

Auto_FM [11...0]

Addr. = 0021_hex

Selected Sound at the Threshold

NICAM Channel Select

Comment

0

Bit [0]

Bits [11...1] = 0

= 0

always NICAM

none

Compatible to MSP 3410B,

i.e. automatic switching is

disabled

default

1

2

Bit [0]

Bit [11...1] = 0

= 1

NICAM or FM/AM,

depending on

ERROR_RATE

700 dec

automatic switching with

internal threshold

Bit [0]

Bit [10...1] = 25..1000 int

= threshold/2

= 1

NICAM or FM/AM,

depending on

ERROR_RATE

set by

customer

automatic switching with

external threshold

Bit [11]

= 0

3

Bit [11]

Bit [10...1] = 0

= [0] = 1

always FM/AM

none

Forced FM-Mono mode, i.e.

automatic switching is

disabled

24

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PRELIMINARY DATA SHEET

MSP 34x0D

6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values

6.5.1. Register ‘AD_CV’

Table 6–5: AD_CV Register (reset status: all bits are “0”)

AD_CV 00BB_hex

Set by Short-Programming

Bit

Meaning

Settings

AD_CV-FM

0

AD_CV-AM

0

AD_CV [0]

AD_CV [6...1]

not used

must be set to 0

Reference level in case of Auto-

matic Gain Control = on (see Table

6–6). Constant gain factor when

Automatic Gain Control = off

(see Table 6–7)

101000

100011

AD_CV [7]

AD_CV [8]

AD_CV [9]

Determination of Automatic Gain or 0 = constant gain

1

Constant Gain

1 = automatic gain

Selection of Sound IF source

0 = ANA_IN1+

1 = ANA_IN2+

not affected

1

not affected

0

MSP Carrier Mute Function

0 = off: no mute

1 = on: mute as de-

scribed in section 4.1.8.

on page 12

(Must be switched off in

High Deviation Mode)

AD_CV [15...10] not used

must be set to 0

000000

Table 6–6: Reference values for active AGC (AD_CV[7] = 1)

Application

Input Signal Contains

AD_CV [6...1]

Ref. Value

AD_CV [6...1]

(dec)

Range of Input Signal

at pin ANA_IN1+

and ANA_IN2+

Terrestrial TV

Dual-Carr. FM

NICAM/FM

1)

2 FM Carriers

101000

40

35

0.10 − 3 V_pp

1)

1 FM and 1 NICAM Carrier 101000

1 AM and 1 NICAM Carrier 100011

0.10 − 3 V_pp

NICAM/AM

0.10 − 1.4 V_pp

recommended:

0.10 − 0.8 V_pp

NICAM only

SAT

1 NICAM Carrier only

010100

100011

20

35

0.05 − 1.0 V_pp

1)

1 or more

0.10 − 3 V_pp

FM Carriers

ADR

FM a. ADR carriers

see DRP 3510A data sheet

¹⁾For signals above 1.4 V_pp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result.

Due to the robustness of the internal processing, the IC works up to and even more than 3 V_pp, if norm conditions

of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may

appear.

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MSP 34x0D

PRELIMINARY DATA SHEET

Table 6–7: AD_CV parameters for constant input gain (AD_CV[7]=0)

Step

AD_CV [6...1]

Constant Gain

Gain

Input Level at pin ANA_IN1+ and ANA_IN2+

maximum input level: 3 V_pp(FM) or 1 V_pp(NICAM)¹⁾

0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

3.00 dB

3.85 dB

4.70 dB

5.55 dB

6.40 dB

7.25 dB

8.10 dB

8.95 dB

9.80 dB

10.65 dB

11.50 dB

12.35 dB

13.20 dB

14.05 dB

14.90 dB

15.75 dB

16.60 dB

17.45 dB

18.30 dB

19.15 dB

20.00 dB

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

maximum input level: 0.14 V_pp

¹⁾For signals above 1.4 V_pp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result.

Due to the robustness of the internal processing, the IC works up to and even more than 3 V_pp, if norm conditions

of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may

appear.

26

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PRELIMINARY DATA SHEET

MSP 34x0D

6.5.2. Register ‘MODE_REG’

The register ‘MODE_REG’ contains the control bits

determining the operation mode of the MSP 34x0D;

Table 6–8 explains all bit positions.

Table 6–8: Control word ‘MODE_REG’; reset status: all bits are “0”

MODE_REG 0083_hex

Set by

Short-Programming

Bit

[0]

[1]

Function

not used

Comment

Definition

M1

0

M2

0

M3

0

0 : strongly recommended

DCTR_TRI

Digital control out

0/1 tri-state

0 : active

1 : tri-state

X

[2]

I2S_TRI

I²S outputs tri-state

(I2S_CL, I2S_WS,

I2S_DA_OUT)

0 : active

1 : tri-state

X

[3]

[4]

[5]

I²S Mode¹⁾

Master/Slave mode

of the I²S bus

0 : Master

1 : Slave

X

I2S_WS Mode

AUD_CL_OUT

WS due to the Sony or

Philips Format

0 : Sony

1 : Philips

Switch

0 : on

Audio_Clock_Output

to tri-state

1 : tri-state

[6]

NICAM¹⁾

Mode of MSP-Ch1

Mode of MSP Ch2

0 : FM

1 : Nicam

0

1

[7]

[8]

not used

FM AM

0 : strongly recommended

0

1

0 : FM

1 : AM

[9]

HDEV

High Deviation Mode

(channel matrix must be

sound A)

0 : normal

1 : high deviation mode

0

[11...10] not used

0 : strongly recommended

00

0

00

0

00

0

[12]

[13]

[14]

MSP Ch1 Gain

see also Table 6–11

0 : Gain = 6 dB

1 : Gain = 0 dB

FIR1 Filter Coeff. see also Table 6–11

Set

0 : use FIR1

1 : use FIR2

1

0

1

0

1

0

1

ADR

Mode of MSP Ch1/

ADR Interface

0 : normal mode/tri-state

1 : ADR mode/active

[15]

AM Gain

Gain for AM

Demodulation

0 : 0 dB (default. of MSPB)

1 : 12 dB (recommended)

1)

In case of NICAM operation, I²S slave mode is not possible.

X: not affected by

short-programming

In case of I²S slave mode, no synchronization to NICAM is allowed.

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MSP 34x0D

PRELIMINARY DATA SHEET

Table 6–9: Channel modes ‘MODE_REG [6, 8, 9]’

NICAM

Bit[6]

FM AM

Bit[8]

HDEV

Bit[9]

MSP Ch1

MSP Ch2

1

0

1

0

1

NICAM

FM2

FM1

AM

FM1

−:−

High-Deviation FM

6.5.3. FIR Parameter

Table 6–10: Loading sequence for FIR coefficients

The following data values (see Table 6–10) are to be

transferred 8 bits at a time embedded LSB-bound in

a 16-bit word.

FIR1 0001_hex(MSP Ch1: NICAM/FM2)

No.

1

Symbol Name

Bits

8

Value

NICAM/FM2_Coeff. (5)

NICAM/FM2_Coeff. (4)

NICAM/FM2_Coeff. (3)

NICAM/FM2_Coeff. (2)

NICAM/FM2_Coeff. (1)

NICAM/FM2_Coeff. (0)

The loading sequences must be obeyed. To change a

coefficient set, the complete block FIR1 or FIR2 must

be transmitted.

2

8

3

8

Note: For compatibility with MSP 3410B, IMREG1 and

IMREG2 have to be transmitted. The value for

IMREG1 and IMREG2 is 004. Due to the partitioning to

8-bit units, the values 04_hex, 40_hex, and 00_hexarise.

see Table 6–11

4

8

5

8

6

8

FIR2 0005_hex(MSP Ch2: FM1/AM )

No.

1

Symbol Name

IMREG1

Bits

8

Value

04_hex

40_hex

00_hex

2

IMREG1 / IMREG2

IMREG2

8

3

8

4

FM/AM_Coef (5)

FM/AM_Coef (4)

FM/AM_Coef (3)

FM/AM_Coef (2)

FM/AM_Coef (1)

FM/AM_Coef (0)

8

5

8

6

8

see Table 6–11

7

8

9

8

28

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

Table 6–11: 8-bit FIR coefficients (decimal integer) for MSP 34x0D (reset status: all coefficients are “0”)

Coefficients for FIR1 0001_hexand FIR2 0005_hex

FM Satellite

FIR filter corresponds to a

Terrestrial TV Standards

band-pass with a band-

B

width of B = 130 to 500 kHz

frequency

f_c

B/G-, D/K-

NICAM-FM

I-

L-

B/G-, D/K-,

M-Dual FM

130

kHz

180

kHz

200

kHz

280

kHz

380

kHz

500

kHz

Auto-

search

NICAM-FM

NICAM-AM

Coef(i)

FIR1 FIR2 FIR1 FIR2 FIR1 FIR2

FIR2

3

FIR2 FIR2 FIR2 FIR2 FIR2 FIR2

FIR2

−1

−8

2

0

1

2

3

4

5

−2

−8

3

18

27

48

66

72

2

4

3

18

27

48

66

72

−2

−8

−4

−12

−9

73

53

9

18

28

47

55

64

3

18

27

48

66

72

−8

4

−1

−9

−16

5

−1

−8

2

18

27

48

66

72

0

−10

10

−6

−4

40

94

−10

10

64

23

119

101

127

1

36

78

107

1

50

79

65

123

1

59

126

1

59

126

0

86

126

Mode-

REG[12]

0

1

Mode-

1

0

REG[13]

For compatibility, except for the FIR2 AM and the autosearch sets, the FIR filter programming as used for the MSP 3410B is also possible.

ADR coefficients are listed in the DRP data sheet.

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MSP 34x0D

PRELIMINARY DATA SHEET

6.5.4. DCO Registers

For a chosen TV standard, a corresponding set of

24-bit registers determining the mixing frequencies of

the quadrature mixers, has to be written into the IC. In

Table 6–12, some examples of DCO registers are

listed. It is necessary to divide them up into low part

and high part. The formula for the calculation of the

registers for any chosen IF frequency is as follows:

INCR_dec= int(f / fs 2²⁴)

with: int

= integer function

f

= IF frequency in MHz

f_S

= sampling frequency (18.432 MHz)

Conversion of INCR into hex format and separation of

the 12-bit low and high parts lead to the required regis-

ter values (DCO1_HI or _LO for MSP Ch1, DCO2_HI

or LO for MSP Ch2).

Table 6–12: DCO registers for the MSP 34x0D (reset status: DCO_HI/LO = “0000”)

DCO1_LO 0093_hex, DCO1_HI 009B_hex; DCO2_LO 00A3_hex, DCO2_HI 00AB_hex

Freq. [MHz] DCO_HI_hex

DCO_LO_hex

Freq. [MHz] DCO_HI_hex

DCO_LO_hex

4.5

03E8

0000

5.04

5.5

5.58

5.7421875

0460

04C6

04D8

04FC

0000

038E

0000

00AA

5.76

5.85

5.94

0500

0514

0528

0000

6.0

6.2

6.5

6.552

0535

0561

05A4

05B0

0555

0C71

071C

0000

6.6

6.65

6.8

05BA

05C5

05E7

0AAA

0C71

01C7

7.02

7.38

0618

0668

0000

7.2

0640

0690

0000

7.56

30

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PRELIMINARY DATA SHEET

MSP 34x0D

6.6. Demodulator Read Registers:

Functions and Values

All registers except C_AD_BITS are 8 bits wide. They

can be read out of the RAM of the MSP 34x0D.

All transmissions take place in 16-bit words. The valid

8 bit data are the 8 LSBs of the received data word.

To enable appropriate switching of the channel select

matrix of the baseband processing part, the NICAM or

FM identification parameters must be read and evalu-

ated by the CCU. The FM identification registers are

described in section 7.2. on page 39. To handle the

NICAM sound and to observe the NICAM quality, at

least the registers C_AD_BITS and ERROR_RATE

must be read and evaluated by the CCU. Additional

data bits and CIB bits, if supplied by the NICAM trans-

mitter, can be obtained by reading the registers

ADD_BITS and CIB_BITS.

Observing the presence and quality of NICAM can be

delegated to the MSP 3410D, if the automatic switch-

ing feature (AUTO_FM, section 6.6.1. on page 32) is

applied.

Table 6–13: Result of Autodetection

Result of Autodetect 007E_hex

Detected TV Sound Standard

Code

(Data) hex

Note: After detection, the detected standard is set automatically according to Table 6–3.

>07FF

0000

0002

0003

0008

autodetect still active

no TV sound standard was detected; select sound standard manually

M Dual FM, even if only FM1 is available

B/G Dual FM, even if only FM1 is available

B/G FM NICAM, only if NICAM is available

L_AM NICAM, whenever a 6.5-MHz carrier is detected, even if NICAM is not available.

If also D/K might be possible, a decision has to be made according to the video mode:

Video = SECAM_EAST

CAD_BITS[0] = 0

CAD_BITS[0] = 1

0009

Video = SECAM_L → no more activities

necessary

To be set by means of the

short programming mode:

D/K1 or D/K2

(see section 6.6.1.)

D/K-NICAM

(standard 00B_hex

)

000A

I-FM-NICAM, even if NICAM is not available

Note: Similar as for the Demodulator Short-Programming, the Autodetection does not affect most of the para-

meters of the DSP section (Audio Baseband Processing): The following exceptions are to be considered:

− identification mode: Autodetection resets and sets the corresponding identification mode

− Prescale FM/AM and FM matrix and Deemphasis FM are undefined after Autodetection

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MSP 34x0D

PRELIMINARY DATA SHEET

6.6.1. Autodetection of Terrestrial TV Audio Standards

Table 6–14: NICAM operation modes as defined by

the EBU NICAM 728 specification

By means of Autodetect, the MSP 34x0D offers a sim-

ple and fast (<0.5 s) facility to detect the actual TV

audio standard. The algorithm checks for the FM-

Mono and NICAM carriers of all common TV sound

standards. The following notes must be considered

when applying the Autodetect feature:

C4 C3 C2 C1 Operation Mode

0

1

0

1

0

Stereo sound (NICAM A/B),

independent mono sound (FM1)

Two independent mono signals

(NICAM A, FM1)

1. Since there is no way to distinguish between AM and

FM carrier, a carrier detected at 6.5 MHz is inter-

preted as an AM carrier. If video detection results in

SECAM East, the MSPD result “9” of Autodetect

Three independent mono

channels (NICAM A, NICAM B,

FM1)

must be reinterpreted as “B_hex

” in case of

CAD_BITS[0] = 1, or as “4” or “5” by using the

demodulator short programming mode. A simple

decision can be made between the two D/K FM ste-

reo standards by setting D/K1 and D/K2 using the

short programming mode and checking the identifi-

cation of both versions (see Table 6–13 on page 31).

0

1

0

1

0

1

0

Data transmission only; no audio

Stereo sound (NICAM A/B), FM1

carries same channel

1

0

1

0

One mono signal (NICAM A).

FM1 carries same channel as

NICAM A

2. During active Autodetect, no I²C transfers besides

reading the autodetect result are recommended.

Results exceeding 07FF_hexindicate an active auto-

detect.

Two independent mono channels

(NICAM A, NICAM B). FM1

carries same channel as

NICAM A

3. The results are to be understood as static informa-

tion, i.e. no evaluation of FM or NICAM identification

concerning the dynamic mode (stereo, bilingual, or

mono) are done.

1

x

0

1

x

1

x

Data transmission only; no audio

Unimplemented sound coding

option (not yet defined by EBU

NICAM 728 specification)

4. Before switching to Autodetect, the audio process-

ing part should be muted. Do not forget to demute

after having received the result.

AUTO_FM: monitor bit for the AUTO_FM Status:

0: NICAM source is NICAM

1: NICAM source is FM

6.6.2. C_AD_BITS

NICAM operation mode control bits and A[2...0] of the

additional data bits.

6.6.3. ADD_BITS [10...3] 0038_hex

Contains the remaining 8 of the 11 additional data bits.

The additional data bits are not yet defined by the

NICAM 728 system.

Format:

MSB

C_AD_BITS 0023

LSB

0

hex

11

...

7

6

5

4

3

2

1

Format:

Auto ... A[2] A[1] A[0] C4

_FM

C3

C2

C1

S

MSB

ADD_BITS 0038

LSB

0

hex

7

6

5

4

3

2

1

A[10] A[9]

A[8]

A[7]

A[6]

A[5]

A[4]

A[3]

Important: “S” = Bit[0] indicates correct NICAM syn-

chronization (S=1). If S=0, the MSP 3410D has not

yet synchronized correctly to frame and sequence, or

has lost synchronization. The remaining read registers

are therefore not valid. The MSP 3410D mutes the

NICAM output automatically and tries to synchronize

again as long as MODE_REG[6] is set.

6.6.4. CIB_BITS

Cib bits 1 and 2 (see NICAM 728 specifications).

Format:

The operation mode is coded by C4...C1 as shown in

Table 6–14.

MSB

CIB_BITS 003E

LSB

hex

7

x

6

x

5

x

4

x

3

x

2

x

1

0

CIB1 CIB2

32

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PRELIMINARY DATA SHEET

MSP 34x0D

6.6.5. ERROR_RATE 0057_hex

6.6.9. AGC_GAIN

Average error rate of the NICAM reception in a time

interval of 182 ms, which should be close to 0. The ini-

tial and maximum value of ERROR_RATE is 2047.

This value is also active, if the NICAM bit of

MODE_REG is not set. Since the value is achieved by

filtering, a certain transition time (appr. 0.5 sec) is

unavoidable. Acceptable audio may have error_rates

up to a value of 700_dec. Individual evaluation of this

value by the CCU and an appropriate threshold may

define the fallback mode from NICAM to FM/AM-Mono

in case of poor NICAM reception.

It is possible to read out the actual setting of

AGC_GAIN in Automatic Gain Mode. In standard

applications, this register is not of interest for the cus-

tomer.

AGC_GAIN

021E_hex

max. amplification

(20 dB)

0001 0100

14_hex

00_hex

min. amplification

(3 dB)

0000 0000

The bit error rate per second (BER) can be calculated

by means of the following formula:

BER = ERROR_RATE × 12.3 × 10⁻⁶/s

6.7. Sequences to Transmit Parameters

and to Start Processing

If the automatic switching feature is applied

(AUTO_FM; section 6.4.2. on page 24), reading of

ERROR_RATE can be omitted.

After having been switched on, the MSP has to be ini-

tialized by transmitting the parameters according to the

LOAD_SEQ_1/2 (see Table 6–15 on page 34). The

data are immediately active after transmission into the

MSP. It is no longer necessary to transmit

LOAD_REG_1/2 or LOAD_REG_1 as it was for

6.6.6. CONC_CT (for compatibility with MSP 3410B)

This register contains the actual number of bit errors of

the previous 728-bit data frame. Evaluation of

CONC_CT is no longer recommended.

MSP 34x0B.

Nevertheless,

transmission

of

LOAD_REG_1/2 or LOAD_REG_1 does no harm.

For NICAM operation, the following steps listed in

‘NICAM_WAIT, _READ, and _CHECK’ in Table 6–15

must be taken.

6.6.7. FAWCT_IST (for compatibility with MSP 3410B)

For compatibility with MSP 3410B this value equals 12

as long as NICAM quality is sufficient. It decreases to 0

if NICAM reception gets poor. Evaluation of

FAWCT_IST is no longer recommended.

For FM-Stereo operation, the evaluation of the identifi-

cation signal must be performed. For a positive identifi-

cation check, the MSP 3410D sound channels have to

be switched corresponding to the detected operation

mode.

6.6.8. PLL_CAPS

It is possible to read out the actual setting of the

PLL_CAPS. In standard applications, this register is

not of interest for the customer.

PLL_CAPS

021F_hex

minimum frequency

nominal frequency

0111 1111

7F_hex

56_hex

0101 0110

RESET

maximum frequency

0000 0000

00_hex

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PRELIMINARY DATA SHEET

Table 6–15: Sequences to initialize and start the MSP 34x0D

LOAD_SEQ_1/2: General Initialization

General Programming Mode

Demodulator Short Programming

Write into MSP 34x0D:

1. AD_CV

2. FIR1

3. FIR2

For example: Addr: 0020_hex, Data 0008_hex

Alternatively, for terrestrial reception, the Autodetect

feature can be applied.

4. MODE_REG

5. DCO1_LO

6. DCO1_HI

7. DCO2_LO

8. DCO2_HI

AUDIO PROCESSING INIT

Initialization of Audio Baseband Processing section, which may be customer-dependent

(see section 7. on page 37).

NICAM_WAIT: Automatic start of the NICAM Decoder if Bit[6] of MODE_REG is set to 1

1. Wait at least 0.25 s

NICAM_CHECK: Read NICAM specific information and check for presence, operation mode, and quality of

NICAM signal.

Read out of MSP 3410D:

1. C_AD_BITS

2. CONC_CT or ERROR_RATE; if AUTO_FM is active, reading of CONC_CT or ERROR_RATE can be omitted.

Evaluation of C_AD_BITS and CONC_CT or ERROR_RATE in the CCU (see section 6.6. on page 31).

If necessary, switch the corresponding sound channels within the audio baseband processing section.

FM_WAIT: Automatic start of the FM identification process if Bit[6] of MODE_REG is set to 0.

1. Ident Reset

2. Wait at least 0.5 s

FM_IDENT_CHECK: Read FM specific information and check for presence, operation mode, and quality of dual-

carrier FM.

Read out of MSP 34x0D:

1. Stereo detection register (DSP register 0018_hex, high part)

Evaluation of the stereo detection register (see section 7.6.1. on page 50).

If necessary, switch the corresponding sound channels within the audio baseband processing section.

LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2

Write into MSP 34x0D:

1. FIR1

(6 x 8 bit)

(12 bit)

2. MODE_REG

3. DCO1_LO

4. DCO1_HI

For example: Addr: 0020_hex, Data: 0003_hex

PAUSE: Duration of “Pause” determines the repetition rate of the NICAM or the FM_IDENT check.

Note: If downward-compatibility to the MSP 34x0B is required, the MSP 34x0D may be programmed

according to the MSP 34x0B data sheet.

34

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PRELIMINARY DATA SHEET

MSP 34x0D

6.8. Software Proposals for Multistandard TV Sets

6.8.3. Multistandard Including System B/G

with NICAM/FM-Mono and German DUAL-FM

To familiarize the reader with the programming

scheme of the MSP 34x0D demodulator part, three

examples in the shape of flow diagrams are shown in

the following sections.

Fig. 6–3 shows a flow diagram for the CCU software,

applied for the MSP 3410D in a TV set which supports

all standards according to system B/G. For the instruc-

tions used in the diagram, please refer to Table 6–15.

6.8.1. Multistandard Including System B/G

with NICAM/FM-Mono only

After having switched on the TV set and having initial-

ized the MSP 3410D (LOAD_SEQ_1/2), FM-Mono

sound is available.

Fig. 6–1 shows a flow diagram for the CCU software,

applied for the MSP 3410D in a TV set, which facili-

tates NICAM and FM-Mono sound. For the instruc-

tions, please refer to Table 6–15.

Fig. 6–3 shows that to check for any stereo or bilingual

audio information, the TV sound standards 0008_hex

(B/G-NICAM) and 0003_hexmust simply be set alter-

nately. If successful, the MSP 3410D must switch to

the desired audio mode.

If the program is changed, resulting in another pro-

gram within the Scandinavian System B/G, no param-

eters of the MSP 3410D need be modified. To facilitate

the check for NICAM, the CCU has only to continue at

the ’NICAM_WAIT’ instruction. During the NICAM

identification process, the MSP 3410D must be

switched to the FM-Mono sound.

6.8.4. Satellite Mode

Fig. 6–2 shows the simple flow diagram to be used for

the MSP 34x0D in a satellite receiver. For FM-Mono

operation, the corresponding FM carrier should prefer-

ably be processed at the MSP channel 2.

START

LOAD_SEQ_1/2

START

Set

Sound Standard

0008_hex

MSP-Channel 1

FM2-Parameter

MSP-Channel 2

FM1-Parameter

Audio Processing

Init

Audio Processing

Init

NICAM_WAIT

STOP

Fig. 6–2: CCU software flow diagram: SAT mode

Pause

NICAM_CHECK

6.8.5. Automatic Search Function for

FM Carrier Detection

Fig. 6–1: CCU software flow diagram: standard B/G

NICAM/FM-Mono only with Demodulator Short

Programming Mode

The AM demodulation ability of the MSP 34x0D offers

the possibility to calculate the “field strength” of the

momentarily selected FM carrier, which can be read

out by the CCU. In SAT receivers, this feature can be

used to make automatic FM carrier search possible.

6.8.2. Multistandard Including System I

with NICAM/FM-Mono only

Therefore, the MSPD has to be switched to AM mode

(MODE_REG[8]), FM prescale must be set to

7F_hex=+127_dec, and the FM DC notch must be

switched off. The sound IF frequency range must now

be “scanned” in the MSPD channel 2 by means of the

programmable quadrature mixer with an appropriate

incremental frequency (i.e. 10 kHz).

This case is identical to the afore-mentioned. The only

difference consists in selecting the UK TV sound stan-

dard, which is coded with 000A_hexof register 0020_hex

.

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PRELIMINARY DATA SHEET

After each incrementation, a field strength value is

available at the quasi-peak detector output (quasi-peak

detector source must be set to FM), which must be

examined for relative maxima by the CCU. This results

in either continuing search or switching the MSP 34x0D

back to FM demodulation mode.

START

LOAD_SEQ_1/2

Set

Sound Standard

0008_hex

During the search process, the FIR2 must be loaded

with the coefficient set “AUTOSEARCH”, which

enables small bandwidth, resulting in appropriate field

strength characteristics. The absolute field strength

value (can be read out of “quasi peak detector output

FM1”) also gives information on whether a main FM

carrier or a subcarrier was detected, and as a practical

consequence, the FM bandwidth (FIR1/2) and the

deemphasis (50 µs or adaptive) can be switched auto-

matically.

Audio Processing Init

NICAM_WAIT

Pause

Yes

Due to the fact that a constant demodulation frequency

offset of a few kHz, leads to a DC level in the demodu-

lated signal, further fine tuning of the found carrier can

be achieved by evaluating the “DC Level Readout

FM1”. Therefore, the FM DC Notch must be switched

on, and the demodulator part must be switched back to

FM demodulation mode.

NICAM_CHECK

NICAM

?

No

LOAD_SEQ_1

For a detailed description of the automatic search

function, please refer to the corresponding

MSP 34xxD Windows software.

Set

Sound Standard

0003_hex

Note: The automatic search is still possible by evaluat-

ing only the DC Level Readout FM1 (DC Notch On) as

it is described with the MSP 34x0B, but the above

mentioned method is faster. If this DC Level method is

applied with the MSP 34x0D, it is recommended to set

MODE_REG[15] to 1 (AM gain = 12 dB) and to use the

new Autosearch FIR2 coefficient set as given in

Table 6–11.

FM_WAIT

Pause

FM_

IDENT_CHECK

Stereo/Biling.

Mono

LOAD_SEQ_1

Set

Sound Standard

0008_hex

Fig. 6–3: CCU software flow diagram: standard B/G

with NICAM or FM-Stereo with Demodulator Short

Programming

36

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MSP 34x0D

7. Programming the DSP Section (Audio Baseband Processing)

7.1. DSP Write Registers: Table and Addresses

Table 7–1: DSP Write Registers; Subaddress: 12_hex; if necessary, these registers are readable as well.

DSP Write Register

Address High/ Adjustable Range, Operational Modes

Low

Reset Mode

Volume loudspeaker channel

Volume / Mode loudspeaker channel

Balance loudspeaker channel [L/R]

Balance Mode loudspeaker

0000_hex

H

L

[+12 dB ... −114 dB, MUTE]

MUTE

1/8 dB Steps, Reduce Volume / Tone Control

[0...100 / 100% and vv][−127 .. 0 / 0 dB and vv]

[Linear mode / logarithmic mode]

[+20 dB ... −12 dB]

00_hex

0001_hex

H

L

100% / 100%

linear mode

0 dB

Bass loudspeaker channel

0002_hex

0003_hex

0004_hex

H

L

Treble loudspeaker channel

[+15 dB ... −12 dB]

0 dB

Loudness loudspeaker channel

Loudness Filter Characteristic

[0 dB ... +17 dB]

0 dB

[NORMAL, SUPER_BASS]

NORMAL

OFF

Spatial effect strength loudspeaker ch. 0005_hex

Spatial effect mode/customize

H

L

[−100%...OFF...+100%]

[SBE, SBE+PSE]

SBE+PSE

MUTE

Volume headphone channel

Volume / Mode headphone channel

Volume / SCART1 channel

Volume / Mode SCART1 channel

Loudspeaker channel source

Loudspeaker channel matrix

Headphone channel source

Headphone channel matrix

SCART1 channel source

SCART1 channel matrix

I²S channel source

0006_hex

0007_hex

0008_hex

0009_hex

000A_hex

000B_hex

000C_hex

H

L

[+12 dB ... −114 dB, MUTE]

1/8 dB Steps, Reduce Volume / Tone Control

[00_hex... 7F_hex],[+12 dB ... −114 dB, MUTE]

[Linear mode / logarithmic mode]

[FM/AM, NICAM, SCART, I²S1, I²S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

[FM/AM, NICAM, SCART, I²S1, I²S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

[FM/AM, NICAM, SCART, I²S1, I²S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

[FM/AM, NICAM, SCART, I²S1, I²S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

[FM/AM, NICAM, SCART, I²S1, I²S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

00_hex

H

L

00_hex

linear mode

FM/AM

SOUNDA

FM/AM

SOUNDA

FM/AM

SOUNDA

FM/AM

SOUNDA

FM/AM

SOUNDA

00_hex

H

L

H

L

H

L

H

L

I²S channel matrix

Quasi-peak detector source

Quasi-peak detector matrix

Prescale SCART

H

L

000D_hex

000E_hex

H

L

[00_hex... 7F_hex

]

Prescale FM/AM

[00_hex... 7F_hex

00_hex

FM matrix

[NO_MAT, GSTEREO, KSTEREO]

[50 µs, 75 µs, J17, OFF]

[OFF, WP1]

NO_MAT

50 µs

Deemphasis FM

000F_hex

0010_hex

H

L

Adaptive Deemphasis FM

Prescale NICAM

OFF

H

[00_hex... 7F_hex

]

00_hex

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PRELIMINARY DATA SHEET

Table 7–1: DSP Write Registers; Subaddress: 12_hex; if necessary, these registers are readable as well., continued

DSP Write Register

Address High/ Adjustable Range, Operational Modes

Low

Reset Mode

Prescale I²S2

0012_hex

0013_hex

H

[00_hex... 7F_hex

]

10_hex

00_hex

ACB Register (SCART Switching

Facilities and Digital Control Output

Pins)

H/L

Bits [15...0]

Beeper

0014_hex

0015_hex

0016_hex

0017_hex

0020_hex

0021_hex

0022_hex

0023_hex

0024_hex

0025_hex

0029_hex

002C_hex

H/L

L

[00_hex... 7F_hex]/[00_hex... 7F_hex

[B/G, M]

]

0/0

Identification Mode

B/G

Prescale I²S1

H

L

[00_hex... 7F_hex

]

10_hex

FM DC Notch

[ON, OFF]

ON

Mode Tone Control

H

L

[BASS/TREBLE, EQUALIZER]

[+12 dB ... −12 dB]

BASS/TREB

0 dB

Equalizer loudspeaker ch. band 1

Equalizer loudspeaker ch. band 2

Equalizer loudspeaker ch. band 3

Equalizer loudspeaker ch. band 4

Equalizer loudspeaker ch. band 5

Automatic Volume Correction

Volume Subwoofer channel

[+12 dB ... −12 dB]

0 dB

[+12 dB ... −12 dB]

0 dB

[+12 dB ... −12 dB]

0 dB

[+12 dB ... −12 dB]

0 dB

[off, on, decay time]

off

[0 dB ... −30 dB, mute]

0 dB

Subwoofer Channel Corner Frequency 002D_hex

Subwoofer: Complementary High-pass

[50 Hz ... 400 Hz]

00_hex

[off, on]

off

Balance headphone channel [L/R]

Balance Mode headphone

Bass headphone channel

Treble headphone channel

Loudness headphone channel

Loudness filter characteristic

Volume SCART2 channel

Volume / Mode SCART2 channel

SCART2 channel source

0030_hex

H

L

[0...100 / 100% and vv][−127...0 / 0 dB and vv]

[Linear mode / logarithmic mode]

[+20 dB ... −12 dB]

100% /100%

linear mode

0 dB

0031_hex

0032_hex

0033_hex

H

L

[+15 dB ... −12 dB]

0 dB

[0 dB ... +17 dB]

0 dB

[NORMAL, SUPER_BASS]

[00_hex... 7F_hex],[+12 dB ... −114 dB, MUTE]

[Linear mode / logarithmic mode]

[FM, NICAM, SCART, I²S1, I²S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

NORMAL

00_hex

0040_hex

0041_hex

H

L

linear mode

FM

H

L

SCART2 channel matrix

SOUNDA

38

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PRELIMINARY DATA SHEET

MSP 34x0D

7.2. DSP Read Registers: Table and Addresses

Table 7–2: DSP Read Registers; Subaddress: 13_hex; these registers are not writable.

DSP Read Register

Address

0018_hex

0019_hex

001A_hex

001B_hex

001C_hex

001E_hex

High/Low Output Range

Stereo detection register

Quasi-peak readout left

Quasi-peak readout right

DC level readout FM1/Ch2-L

DC level readout FM2/Ch1-R

MSP hardware version code

MSP major revision code

MSP product code

H

[80_hex... 7F_hex

]

8 bit two’s complement

16 bit two’s complement

H&L

H

[0000_hex... 7FFF_hex

[8000_hex... 7FFF_hex

]

[00_hex... FF_hex

[00_hex... 0A_hex

[00_hex... FF_hex

]

L

001F_hex

H

MSP ROM version code

L

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PRELIMINARY DATA SHEET

7.3. DSP Write Registers: Functions and Values

With Fast Mute, volume is reduced to mute position by

digital volume only. Analog volume is not changed.

This reduces any audible DC plops. Going back from

Fast Mute should be done to the volume step which

was in existence before Fast Mute was activated.

Write registers are 16 bit wide, whereby the MSB is

denoted bit [15]. Transmissions via I²C bus have to

take place in 16-bit words. Some of the defined 16-bit

words are divided into low [7...0] and high [15...8] byte,

or in an other manner, thus holding two different con-

trol entities. All write registers are readable. Unused

parts of the 16-bit registers must be zero. Addresses

not given in this table must not be written at any time!

The Fast Mute facility is activated by the I2C com-

mand. After 75 ms (typically), the signal is completely

ramped down.

Clipping Mode

Loudspeaker

0000_hex

0006_hex

[3..0]

0_hex

7.3.1. Volume – Loudspeaker and

Headphone Channel

Clipping Mode

Headphone

Volume

Loudspeaker

0000_hex

0006_hex

[15...4]

Reduce Volume

0000

RESET

Volume

Headphone

Reduce Tone Control

Compromise Mode

0001

0010

1_hex

2_hex

+12 dB

0111 1111 0000¹⁾7F0_hex

+11.875 dB

+0.125 dB

0 dB

0111 1110 1110

0111 0011 0010

0111 0011 0000

0111 0010 1110

0000 0001 0010

0000 0001 0000

7EE_hex

732_hex

730_hex

72E_hex

012_hex

010_hex

000_hex

If the clipping mode is set to “Reduce Volume”, the fol-

lowing clipping procedure is used: To prevent severe

clipping effects with bass, treble, or equalizer boosts,

the internal volume is automatically limited to a level

where, in combination with either bass, treble, or

equalizer setting, the amplification does not exceed

12 dB.

−0.125 dB

−113.875 dB

−114 dB

Mute

If the clipping mode is “Reduce Tone Control”, the bass

or treble value is reduced if amplification exceeds

12 dB. If the equalizer is switched on, the gain of those

bands is reduced, where amplification together with

volume exceeds 12 dB.

0000 0000 0000

RESET

Fast Mute

1111 1111 1110

FFE_hex

¹⁾Bit[4] must always be set to 0

If the clipping mode is “Compromise Mode”, the bass

or treble value and volume are reduced half and half if

amplification exceeds 12 dB. If the equalizer is

switched on, the gain of those bands is reduced half

and half, where amplification together with volume

exceeds 12 dB.

The highest given positive 12-bit number (7F0hex)

yields in a maximum possible gain of 12 dB. Decreas-

ing the volume register by 2 LSBs decreases the vol-

ume by 0.125 dB. Volume settings lower than the

given minimum mute the output. With large scale input

signals, positive volume settings may lead to signal

clipping.

Example:

Vol.:

Bass:

+9 dB

Treble:

+5 dB

+6 dB

The MSPD loudspeaker and headphone volume func-

tion is divided up into a digital and an analog section.

Red. Volume

Red. Tone Con.

Compromise

3

9

5

6

4.5

7.5

40

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PRELIMINARY DATA SHEET

MSP 34x0D

7.3.2. Balance – Loudspeaker and

Logarithmic Mode

Headphone Channel

Balance Loudspeaker

Channel [L/R]

0001_hex

H

Positive balance settings reduce the left channel with-

out affecting the right channel; negative settings

reduce the right channel leaving the left channel unaf-

fected. In linear mode, a step by 1 LSB decreases or

increases the balance by about 0.8 % (exact figure:

100/127). In logarithmic mode, a step by 1 LSB

decreases or increases the balance by 1 dB.

Balance Headphone

Channel [L/R]

0030_hex

Left −127 dB, Right 0 dB 0111 1111

Left −126 dB, Right 0 dB 0111 1110

7F_hex

7E_hex

01_hex

00_hex

Left −1 dB, Right 0 dB

0000 0001

Balance Mode

Loudspeaker

0001_hex

0030_hex

[3..0]

0_hex

Left 0 dB, Right 0 dB

0000 0000

RESET

Balance Mode

Headphone

Left 0 dB, Right −1 dB

1111 1111

FF_hex

81_hex

80_hex

linear

0000

Left 0 dB, Right −127 dB 1000 0001

Left 0 dB, Right −128 dB 1000 0000

RESET

logarithmic

0001

1_hex

7.3.3. Bass – Loudspeaker and

Headphone Channel

Linear Mode

Balance Loudspeaker

Channel [L/R]

0001_hex

0030_hex

H

Bass Loudspeaker

Bass Headphone

+20 dB

0002_hex

H

0031_hex

H

Balance Headphone

Channel [L/R]

0111 1111

0111 1000

0111 0000

0110 1000

0110 0000

0101 1000

0000 1000

0000 0001

7F_hex

78_hex

70_hex

68_hex

60_hex

58_hex

08_hex

01_hex

00_hex

+18 dB

Left muted, Right 100 % 0111 1111

Left 0.8 %, Right 100 % 0111 1110

7F_hex

7E_hex

01_hex

00_hex

+16 dB

+14 dB

Left 99.2 %, Right 100 % 0000 0001

+12 dB

Left 100 %, Right 100 % 0000 0000

RESET

+11 dB

Left 100 %, Right 99.2 % 1111 1111

FF_hex

82_hex

81_hex

+1 dB

Left 100 %, Right 0.8 %

1000 0010

+1/8 dB

Left 100 %, Right muted 1000 0001

0 dB

0000 0000

RESET

−1/8 dB

−1 dB

1111 1111

1111 1000

1010 1000

1010 0000

FF_hex

F8_hex

A8_hex

A0_hex

−11 dB

−12 dB

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PRELIMINARY DATA SHEET

With positive bass settings, internal overflow may

occur even with overall volume less than 0 dB. This

will lead to a clipped output signal. Therefore, it is not

recommended to set bass to a value that, in conjunc-

tion with volume, would result in an overall positive

gain.

7.3.5. Loudness – Loudspeaker and

Headphone Channel

Loudness

Loudspeaker

0004_hex

0033_hex

H

Loudness

Loudspeaker channel: Bass and Equalizer cannot

work simultaneously (see section 7.3.22.: Mode Tone

Control). If Equalizer is used, Bass and Treble coeffi-

cients must be set to zero and vice versa.

Headphone

+17 dB

+16 dB

+1 dB

0 dB

0100 0100

0100 0000

0000 0100

44_hex

40_hex

04_hex

00_hex

7.3.4. Treble – Loudspeaker and

Headphone Channel

0000 0000

RESET

Treble Loudspeaker

Treble Headphone

+15 dB

0003_hex

H

0032_hex

H

0111 1000

0111 0000

0000 1000

0000 0001

78_hex

70_hex

08_hex

01_hex

00_hex

Mode Loudness

Loudspeaker

0004_hex

0033_hex

L

+14 dB

Mode Loudness

Headphone

L

+1 dB

+1/8 dB

Normal (constant

volume at 1 kHz)

0000 0000

RESET

00_hex

04_hex

0 dB

0000 0000

RESET

Super Bass (constant

volume at 2 kHz)

0000 0100

−1/8 dB

−1 dB

1111 1111

1111 1000

1010 1000

1010 0000

FF_hex

F8_hex

A8_hex

A0_hex

Loudness increases the volume of low and high fre-

quency signals, while keeping the amplitude of the

1 kHz reference frequency constant. The intended

loudness has to be set according to the actual volume

setting. Because loudness introduces gain, it is not

recommended to set loudness to a value that, in con-

junction with volume, would result in an overall positive

gain.

−11 dB

−12 dB

With positive treble settings, internal overflow may

occur even with overall volume less than 0 dB. This

will lead to a clipped output signal. Therefore, it is not

recommended to set treble to a value that, in conjunc-

tion with volume, would result in an overall positive

gain.

By means of ‘Mode Loudness’, the corner frequency

for bass amplification can be set to two different val-

ues. In Super Bass mode, the corner frequency is

shifted up. The point of constant volume is shifted from

1 kHz to 2 kHz.

Loudspeaker channel: Treble and Equalizer cannot

work simultaneously (see section 7.3.22.: Mode Tone

Control). If Equalizer is used, Bass and Treble coeffi-

cients must be set to zero and vice versa.

42

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MSP 34x0D

7.3.6. Spatial Effects – Loudspeaker Channel

There are several spatial effect modes available:

Mode A (low byte = 00_hex) is compatible to the formerly

used spatial effect. Here, the kind of spatial effect

depends on the source mode. If the incoming signal is

in mono mode, Pseudo Stereo Effect is active; for ste-

reo signals, Pseudo Stereo Effect and Stereo Base-

width Enlargement is active. The strength of the effect

is controllable by the upper byte. A negative value

reduces the stereo image. A rather strong spatial effect

is recommended for small TV sets where loudspeaker

spacing is rather close. For large screen TV sets, a

more moderate spatial effect is recommended. In

mode A, even in case of stereo input signals, Pseudo

Stereo Effect is active, which reduces the center

image.

Spatial Effect Strength 0005_hex

Loudspeaker

H

Enlargement 100%

Enlargement 50%

Enlargement 1.5%

Effect off

0111 1111

7F_hex

3F_hex

01_hex

00_hex

0011 1111

0000 0001

0000 0000

RESET

Reduction 1.5%

Reduction 50%

Reduction 100%

1111 1111

1100 0000

1000 0000

FF_hex

C0_hex

80_hex

In Mode B, only Stereo Basewidth Enlargement is

effective. For mono input signals, the Pseudo Stereo

Effect has to be switched on.

It is worth mentioning, that all spatial effects affect

amplitude and phase response. With the lower 4 bits,

the frequency response can be customized. A value of

0000_binyields a flat response for center signals (L = R)

but a high pass function of L or R only signals. A value

of 0110_binhas a flat response for L or R only signals

but a low-pass function for center signals. By using

1000_bin, the frequency response is automatically

adapted to the sound material by choosing an optimal

high-pass gain.

Spatial Effect Mode

Loudspeaker

0005_hex

[7...4]

Stereo Basewidth

0000

RESET

0_hex

Enlargement (SBE) and

Pseudo Stereo Effect

(PSE). (Mode A)

Stereo Basewidth

Enlargement (SBE) only.

(Mode B)

0010

2_hex

Spatial Effect

0005_hex

[3...0]

Customize Coefficient

Loudspeaker

max. high-pass gain

0000

0_hex

RESET

2/3 high-pass gain

1/3 high-pass gain

min. high-pass gain

automatic

0010

0100

0110

1000

2_hex

4_hex

6_hex

8_hex

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PRELIMINARY DATA SHEET

7.3.7. Volume – SCART1 and SCART2 Channel

7.3.8. Channel Source Modes

Volume Mode SCART1 0007_hex

Volume Mode SCART2 0040_hex

[3...0]

Loudspeaker Source

Headphone Source

SCART1 Source

SCART2 Source

I²S Source

0008_hex

0009_hex

000A_hex

0041_hex

000B_hex

000C_hex

H

[3...0]

linear

0000

0_hex

RESET

logarithmic

0001

1_hex

Quasi-Peak

Detector Source

Linear Mode

Volume SCART1

Volume SCART2

OFF

FM/AM

0000 0000

RESET

00_hex

0007_hex

0040_hex

H

NICAM

0000 0001

0000 0011

0000 0100

0000 0010

0000 0101

0000 0110

01_hex

03_hex

04_hex

02_hex

05_hex

06_hex

H

none _{(MSPB/C: SBUS12)}

0000 0000

RESET

00_hex

none _{(MSPB/C: SBUS34)}

0 dB gain

(digital full scale (FS) to

2 V_RMSoutput)

0100 0000

40_hex

SCART

I²S1

+6 dB gain (−6 dBFS to

2 V_RMSoutput)

0111 1111

7F_hex

I²S2

Logarithmic Mode

Volume SCART1

Volume SCART2

+12 dB

0007_hex

0040_hex

[15...4]

7F0_hex

7EE_hex

732_hex

730_hex

72E_hex

012_hex

010_hex

000_hex

0111 1111 0000

0111 1110 1110

0111 0011 0010

0111 0011 0000

0111 0010 1110

0000 0001 0010

0000 0001 0000

+11.875 dB

+0.125 dB

0 dB

−0.125 dB

−113.875 dB

−114 dB

Mute

0000 0000 0000

RESET

44

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PRELIMINARY DATA SHEET

MSP 34x0D

7.3.9. Channel Matrix Modes

7.3.10. SCART Prescale

Loudspeaker Matrix

Headphone Matrix

SCART1 Matrix

SCART2 Matrix

I²S Matrix

0008_hex

L

Volume Prescale

SCART

000D_hex

H

0009_hex

000A_hex

0041_hex

000B_hex

000C_hex

OFF

0000 0000

RESET

00_hex

19_hex

7F_hex

0 dB gain (2 V_RMSinput 0001 1001

to digital full scale)

+14 dB gain

(400 mV_RMSinput to

digital full scale)

0111 1111

Quasi-Peak

Detector Matrix

SOUNDA / LEFT /

MSP-IF-CHANNEL2

0000 0000

RESET

00_hex

10_hex

SOUNDB / RIGHT /

MSP-IF-CHANNEL1

0001 0000

STEREO

0010 0000

0011 0000

0100 0000

0101 0000

0110 0000

0111 0000

1000 0000

1001 0000

20_hex

30_hex

40_hex

50_hex

60_hex

70_hex

80_hex

90_hex

MONO

SUM / DIFF

AB_XCHANGE

PHASE_CHANGE_B

PHASE_CHANGE_A

A_ONLY

B_ONLY

The sum/difference mode can be used together with

the quasi-peak detector to determine the sound mate-

rial mode. If the difference signal on channel B (right)

is near to zero, and the sum signal on channel A (left)

is high, the incoming audio signal is mono. If there is a

significant level on the difference signal, the incoming

audio is stereo.

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45

MSP 34x0D

PRELIMINARY DATA SHEET

7.3.11. FM/AM Prescale

For the High Deviation Mode, the FM prescaling val-

ues can be used in the range from 14_hexto 30_hex

.

Please consider the internal reduction of 6 dB for this

mode. The FIR-bandwidth should be selected to

500 kHz.

Volume Prescale FM

(Normal FM Mode)

000E_hex

H

OFF

0000 0000

RESET

00_hex

7F_hex

¹⁾Given deviations will result in internal digital full-

scale signals. Appropriate clipping headroom has to be

set by the customer. This can be done by decreasing

the listed values by a specific factor.

Maximum Volume

(28 kHz deviation ¹⁾

recommended FIR-

bandwidth: 130 kHz)

0111 1111

²⁾In the mentioned SIF-level range, the AM-output

level remains stable and independent of the actual

SIF-level. In this case, only the AM degree of audio

signals above 40 Hz determines the AM-output level.

Deviation 50 kHz¹⁾

recommended FIR-

bandwidth: 200 kHz

0100 1000

0011 0000

48_hex

Deviation 75 kHz¹⁾

recommended FIR-

bandwidth: 200 or

280 kHz

30_hex

7.3.12. FM Matrix Modes (see also Table 4–1)

FM Matrix

000E_hex

L

Deviation 150 kHz¹⁾

recommended FIR-

bandwidth: 380 kHz

0001 1000

0001 0011

18_hex

NO MATRIX

0000 0000

RESET

00_hex

GSTEREO

KSTEREO

0000 0001

0000 0010

01_hex

02_hex

Maximum deviation

192 kHz¹⁾

13_hex

recommended FIR-

bandwidth: 380 kHz

NO_MATRIX is used for terrestrial mono or satellite

stereo sound. GSTEREO dematrixes [(L+R)/2, R] to

[L, R] and is used for German dual carrier stereo sys-

tem (Standard B/G). KSTEREO dematrixes [(L+R)/2,

(L−R)/2] to [L, R] and is used for the Korean dual car-

rier stereo system (Standard M).

Prescale for adaptive

deemphasis WP1

recommended FIR-

bandwidth: 130 kHz

0001 0000

10_hex

Volume Prescale FM

(High Deviation Mode)

000E_hex

H

7.3.13. FM Fixed Deemphasis

OFF

0000 0000

RESET

00_hex

30_hex

Deemphasis FM

000F_hex

H

Deviation 150 kHz¹⁾

recommended FIR-

bandwidth: 380 kHz

0011 0000

50 µs

0000 0000

RESET

00_hex

75 µs

J17

0000 0001

0000 0100

0011 1111

01_hex

04_hex

3F_hex

Maximum deviation

384 kHz¹⁾

recommended FIR-

bandwidth: 500 kHz

0001 0100

14_hex

OFF

Volume Prescale AM

000E_hex

H

7.3.14. FM Adaptive Deemphasis

OFF

0000 0000

RESET

00_hex

FM Adaptive

000F_hex

L

Deemphasis WP1

SIF input level:

1) 2)

OFF

WP1

0000 0000

RESET

00_hex

3F_hex

0.1 V_pp− 0.8 V_pp

0.8 V_pp− 1.4 V_pp

0111 1100

7C_hex

<7C_hex

1)

0011 1111

Note: For AM, the bit MODE_REG[15] must be 1

46

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

7.3.15. NICAM Prescale

Definition of SCART Switching Facilities

(see Fig. 4–3 on page 13)

Volume Prescale

NICAM

0010_hex

H

ACB Register

0013_hex

[13...0]

OFF

0000 0000

RESET

00_hex

DSP IN

Selection of Source:

* SC1_IN_L/R

MONO_IN

xx xx00 xx00 0000

xx xx01 xx00 0000

xx xx10 xx00 0000

xx xx11 xx00 0000

xx xx00 xx10 0000

xx xx11 xx10 0000

0 dB gain

0010 0000

0111 1111

20_hex

7F_hex

SC2_IN_L/R

SC3_IN_L/R

SC4_IN_L/R

Mute

+12 dB gain

7.3.16. NICAM Deemphasis

SC1_OUT_L/R

Selection of Source:

* SC3_IN_L/R

SC2_IN_L/R

A J17 Deemphasis is always applied to the NICAM

signal. It is not switchable.

xx 00xx x0x0 0000

xx 01xx x0x0 0000

xx 10xx x0x0 0000

xx 11xx x0x0 0000

xx 00xx x1x0 0000

xx 01xx x1x0 0000

xx 10xx x1x0 0000

xx 11xx x1x0 0000

MONO_IN

SCART1_L/R via D/A

SCART2_L/R via D/A

SC1_IN_L/R

SC4_IN_L/R

Mute

7.3.17. I²S1 and I²S2 Prescale

Prescale I²S1

Prescale I²S2

OFF

0016_hex

H

0012_hex

H

SC2_OUT_L/R

Selection of Source:

* SCART1_L/R via D/A

SC1_IN_L/R

0000 0000

00_hex

10_hex

00 xxxx 0xx0 0000

01 xxxx 0xx0 0000

10 xxxx 0xx0 0000

00 xxxx 1xx0 0000

01 xxxx 1xx0 0000

10 xxxx 1xx0 0000

11 xxxx 1xx0 0000

11 xxxx 0xx0 0000

0 dB gain

0001 0000

RESET

MONO_IN

SCART2_L/R via D/A

SC2_IN_L/R

SC3_IN_L/R

SC4_IN_L/R

+18 dB gain

0111 1111

7F_hex

7.3.18. ACB Register

Mute

* = RESET position, which becomes active at the

time of the first write transmission on the control bus

to the audio processing part (DSP). By writing to the

ACB register first, the RESET state can be rede-

fined.

Definition of Digital Control Output Pins

ACB Register

0013_hex

[15..14]

D_CTR_OUT0

low

high

(RESET)

x0

x1

Note: If “MONO_IN” is selected at the DSP_IN selec-

tion, the channel matrix mode of the corresponding

output channel(s) must be set to “sound A”.

D_CTR_OUT1

low

high

(RESET)

0x

1x

Micronas

47

MSP 34x0D

PRELIMINARY DATA SHEET

7.3.19. Beeper

7.3.21. FM DC Notch

The DC compensation filter (FM DC Notch) for FM

input can be switched off. This is used to speed up the

automatic search function (see section 6.8.5. on page

35). In normal FM mode, the FM DC Notch should be

switched on.

Beeper Volume

0014_hex

H

OFF

0000 0000

RESET

00_hex

Maximum Volume (full

digital scale FDS)

0111 1111

7F_hex

FM DC Notch

0017_hex

L

Beeper Frequency

16 Hz (lowest)

1 kHz

0014_hex

L

ON

0000 0000

Reset

00_hex

0000 0001

0100 0000

1111 1111

01_hex

40_hex

FF_hex

OFF

0011 1111

3F_hex

4 kHz (highest)

7.3.22. Mode Tone Control

A square wave beeper can be added to the loud-

speaker channel and the headphone channel. The

addition point is just before loudness and volume

adjustment.

Mode Tone Control

0020_hex

H

Bass and Treble

0000 0000

RESET

00_hex

Equalizer

1111 1111

FF_hex

7.3.20. Identification Mode

By means of ‘Mode Tone Control’, Bass/Treble or

Equalizer may be activated.

Identification Mode

0015_hex

L

Standard B/G

(German Stereo)

0000 0000

RESET

00_hex

7.3.23. Automatic Volume Correction (AVC)

Standard M

(Korean Stereo)

0000 0001

01_hex

3F_hex

AVC On/Off

0029_hex

[15...12]

Reset of Ident-Filter

0011 1111

AVC off and Reset

of int. variables

0000

RESET

0_hex

To shorten the response time of the identification algo-

rithm after a program change between two FM-Stereo

capable programs, the reset of the ident-filter can be

applied.

AVC on

1000

8_hex

AVC Decay Time

0029_hex

[11...8]

8 sec. (long)

1000

0100

0010

0001

8_hex

4_hex

2_hex

1_hex

Sequence:

4 sec. (middle)

2 sec. (short)

20 ms (very short)

1. Program change

2. Reset ident-filter

3. Set identification mode back to standard B/G or M

4. Read stereo detection register

Different sound sources (e.g. terrestrial channels, SAT

channels, or SCART) fairly often do not have the same

volume level. Advertisement during movies, as well,

usually has a different (higher) volume level than the

movie itself. The Automatic Volume Correction (AVC)

solves this problem and equalizes the volume levels.

48

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PRELIMINARY DATA SHEET

MSP 34x0D

The absolute value of the incoming signal is fed into a

filter with 16 ms attack time and selectable decay time.

The decay time must be adjusted as shown in the

table above. This attack/decay filter block works simi-

lar to a peak hold function. The volume correction

value with its quasi continuous step width is calculated

using the attack/decay filter output.

7.3.24. Subwoofer Channel

The subwoofer channel is created by combining the left

and right channels directly behind the tone control filter

block. A third order low-pass filter with programmable

corner frequency and volume adjustment according to

the main channel output is performed to the bass sig-

nal. Additionally, at the loudspeaker channels, a com-

plementary high-pass filter can be switched on.

The Automatic Volume Correction functions with an

internal reference level of −18 dBr. This means that

input signals with a volume level of −18 dBr will not be

affected by the AVC. If the input signals vary in a range

of −24 dB to 0 dB, the AVC maintains a fixed output

level of −18 dBr.

Subwoofer Channel

Volume Adjust

002C_hex

H

0 dB

0000 0000

RESET

00_hex

Fig. 7–1 shows the AVC output level versus its input

level. For prescale and volume registers set to 0 dB, a

level of 0 dBr corresponds to full scale input / output.

This is

−1 dB

−29 dB

−30 dB

Mute

1111 1111

1110 0011

1110 0010

1000 0000

002D_hex

FF_hex

E3_hex

E2_hex

80_hex

H

– SCART in-, output 0 dBr = 2.0 V_rms

– Loudspeaker and Aux output 0 dBr = 1.4 V_rms

output level

[dBr]

Subwoofer Channel

Corner Frequency

50 Hz ... 400 Hz

e.g. 50 Hz = 5_dec

400 Hz = 40_dec

RESET

0000 0101

0010 1000

00_hex

05_hex

28_hex

−12

−18

−24

Subwoofer: Comple-

mentary High-pass

002D_hex

L

HP off

0000 0000

RESET

00_hex

01_hex

−30

−24

−18

−12

−6

0

+6

input level

[dBr]

HP on

0000 0001

Fig. 7–1: Simplified AVC characteristics

To reset the internal variables, the AVC should be

switched off and on during any channel or source

change. For standard applications, the recommended

decay time is 4 sec.

Note: AVC should not be used in any Dolby Pro Logic

mode, except PANORAMA, where no other than the

loudspeaker output is active.

Micronas

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MSP 34x0D

PRELIMINARY DATA SHEET

7.3.25. Equalizer Loudspeaker Channel

7.5. Phase Relationship of Analog Outputs

The analog output signals: Loudspeaker, headphone,

and SCART2 all have the same phases. The user

does not need to change output phases when using

these analog outputs directly. The SCART1 output has

opposite phase.

Band 1 (below 120 Hz)

Band 2 (Center: 500 Hz)

0021_hex

0022_hex

H

Band 3 (Center: 1.5 kHz) 0023_hex

H

Using the I²S-outputs for other DSPs or D/A convert-

ers, care must be taken to adjust for the correct phase.

If the attached coprocessor is one of the MSP family,

the following schematics help to determine the phase

relationship.

Band 4 (Center: 5 kHz)

0024_hex

H

Band 5 (above 10 kHz)

0025_hex

H

+12 dB

+11 dB

+1 dB

0110 0000

0101 1000

0000 1000

0000 0001

60_hex

58_hex

08_hex

01_hex

00_hex

I2S_in I2S_out

+1/8 dB

0 dB

0000 0000

RESET

Loudspeaker

Headphone

Audio

Baseband

Processing

−1/8 dB

−1 dB

1111 1111

1111 1000

1010 1000

1010 0000

FF_hex

F8_hex

A8_hex

A0_hex

SCART2

SCART1

−11dB

−12 dB

Mono

SCART1…2

SCART1…3

With positive equalizer settings, internal overflow may

occur even with overall volume less than 0 dB. This

will lead to a clipped output signal. Therefore, it is not

recommended to set equalizer bands to a value that, in

conjunction with volume, would result in an overall

positive gain.

Fig. 7–2: Phase diagram of the MSP 34x0D

7.6. DSP Read Registers: Functions and Values

All readable registers are 16-bit wide. Transmissions

via I²C bus have to take place in 16-bit words. Single

data entries are 8 bit. Some of the defined 16-bit words

are divided into low and high byte, thus holding two dif-

ferent control entities.

Equalizer must not be used simultaneously with Bass

and Treble (Mode Tone Control must be set to FF to

use the Equalizer). If Bass and Treble are used, Equal-

izer coefficients must be set to zero.

These registers are not writable.

7.4. Exclusions for the Audio Baseband Features

In general, all functions can be switched independently

of the others. Exceptions:

7.6.1. Stereo Detection Register

1. NICAM cannot be processed simultaneously with

the FM2 channel.

Stereo Detection

Register

0018_hex

H

2. FM adaptive deemphasis WPI cannot be processed

simultaneously with the FM-identification.

Stereo Mode

Reading

(two’s complement)

MONO

near zero

STEREO

positive value (ideal

reception: 7F_hex

)

BILINGUAL

negative value (ideal

reception: 80_hex)

50

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

7.6.2. Quasi-Peak Detector

7.6.5. MSP Major Revision Code

Quasi-Peak

Readout Left

0019_hex

H+L

Major Revision

001E_hex

L

MSP 34x0D

04_hex

Quasi-Peak

001A_hex

Readout Right

The MSP 34x0D is the fourth generation of ICs in the

MSP family.

Quasi peak readout

[0000_hex... 7FFF_hex]

values are 16 bit two’s

complement

7.6.6. MSP Product Code

The quasi peak readout register can be used to read

out the quasi peak level of any input source, in order to

adjust all inputs to the same normal listening level. The

refresh rate is 32 kHz. The feature is based on the fil-

ter time constants:

Product

001F_hex

H

MSP 3400D

MSP 3410D

0000 0000

0000 1010

00_hex

0A_hex

attack time: 1.3 ms

decay time: 37 ms

By means of the MSP product code, the control pro-

cessor is able to decide whether or not NICAM-control-

ling should be accomplished.

7.6.3. DC Level Register

7.6.7. MSP ROM Version Code

DC Level Readout

FM1 (MSP-Ch2)

001B_hex

001C_hex

H+L

ROM Version

001F_hex

L

DC Level Readout

FM2 (MSP-Ch1)

Major software revision

MSP 34x0D − B4

[00_hex... FF_hex

]

DC Level

[8000_hex... 7FFF_hex]

values are 16 bit two’s

0010 0100

24_hex

complement

A change in the ROM version code defines internal

software optimizations, that may have influence on the

chip’s behavior, e.g. new features may have been

included. While a software change is intended to cre-

ate no compatibility problems, customers that would

like to use the new functions, can identify new

MSP 34x0D versions according to this number. To

avoid compatibility problems with MSP 34x0B, an off-

set of 20_hexis added to the ROM version code of the

chip’s imprint.

The DC level register measures the DC component of

the incoming FM signals (FM1 and FM2). This can be

used for seek functions in satellite receivers and for IF

FM frequencies fine tuning. A too low demodulation

frequency (DCO) results in a positive DC-level and

vice-versa. For further processing, the DC content of

the demodulated FM signals is suppressed. The time

constant τ, defining the transition time of the DC Level

Register, is approximately 28 ms.

7.6.4. MSP Hardware Version Code

Hardware Version

MSP 34x0D − B4

001E_hex

H

[00_hex... FF_hex

]

02_hex

A change in the hardware version code defines hard-

ware optimizations that may have influence on the

chip’s behavior. The readout of this register is identical

to the hardware version code in the chip’s imprint.

Micronas

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MSP 34x0D

PRELIMINARY DATA SHEET

8. Differences between MSP 3400C, MSP 3400D, MSP 3410B, and MSP 3410D

Feature

MSP 3400C

MSP 3400D−B4 MSP 3410B−F7

MSP 3410D−B4

Hardware

NICAM

No

Yes

S-Bus Output

S-Bus Input

Second I²S Data Input

ADR Interface

No

S_DA_OUT

S_DA_IN

No

S_DA_IN

I2S_DA_IN2

No

I2S_DA_IN2

ADR_CL,

ADR_WS,

ADR_DA

ADR_CL,

ADR_WS,

ADR_DA

No

ADR_CL,

ADR_WS,

ADR_DA

Second SCART D/A Converter

Demodulator

No

Yes

No

Yes

Demodulator Short Programming

Autodetection for terr. TV Sound Standards

No

Yes

No

Yes

Automatic switching from NICAM to FM and vv. No

Yes

ADCV[10]

Carrier Mute Level

Tri-state digital outputs

Carrier Mute

Level

not used

FIFO Watchdog

On/Off

not used

ADCV[11]

Carrier Mute

Level

not used

MODE_REG[1]:

MODE_REG[2]:

MODE_REG[6]:

MODE_REG[7]:

0: active

1: tri-state

0: active

1: tri-state

enable Pay-TV

0: active

1: tri-state

Tri-state digital outputs

I²S outputs

0: active

1: tri-state

0: active

1: tri-state

disable NICAM

Descrambler

0: active

1: tri-state

NICAM

no function

0: FM

1: NICAM

0: FM

1: NICAM

FM1FM2

0: NICAM

1: FM

no function

MODE_REG[10]: S-Bus Setting

MODE_REG[11]: S-Bus Mode

NICAM/FM on

S-Bus

Mode of internal

S-Bus

MODE_REG[12]: 6 dB gain in

MSP-Ch1

0: on

1: off

0: on

1: off

always on

always FIR1

No

0: on

1: off

MODE_REG[13]: FIR filter coeff. set for

MSP-Ch1

0: use FIR1

1: use FIR2

0: use FIR1

1: use FIR2

0: use FIR1

1: use FIR2

MODE_REG[14] Mode of ADR Interface

0: normal mode

1: ADR/SaRa

0: normal mode

1: ADR/SaRa

0: normal mode

1: ADR/SaRa

52

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PRELIMINARY DATA SHEET

MSP 34x0D

Feature

MSP 3400C

MSP 3400D−B4 MSP 3410B−F7

MSP 3410D−B4

Demodulator

MODE_REG[15]: Gain for AM-Demodulation 0: 0 dB¹⁾

1: 12 dB

0: 0 dB

1: 12 dB

No

0: 0 dB

1: 12 dB

FAWCT_SOLL

FAWCT_ER_TOL (DEMOD W Addr. 10F_hex

AUDIO_PLL (DEMOD W Addr. 2D7_hex

LOAD_REG_1/2 (DEMOD W Addr. 56_hex

LOAD_REG_1 (DEMOD W Addr. 60_hex

SEARCH_NICAM (DEMOD W Addr. 78_hex

(DEMOD W Addr. 107_hex

)

Not necessary

No

Not necessary

Yes

Not necessary

)

SELF_TEST

(DEMOD W Addr. 792_hex

)

No

not compatible,

not for customer

use,

values as

described in

Mubi-Software

not compatible,

not for customer

use,

FAWCT_IST

CONC_CT

(DEMOD R Addr. 25_hex

)

No

Yes

Yes, but not

necessary

(DEMOD R Addr. 58_hex

)

Yes, but not

recommended

ERROR_RATE

(DEMOD R Addr. 57_hex

No

Yes

Reading out RMS value of AGC

I²C Addr.

001E_hex

I²C Addr.

021E_hex

not possible

I²C Addr.

021E_hex

Reading out internal PLL capacitance switches I²C Addr.

001F_hex

I²C Addr.

021F_hex

not possible

I²C Addr.

021F_hex

Audio Baseband Processing

Improved oversampling filters for all

D/A converters

Yes

No

Yes

Mode Loudness Loudspeaker channel

00_hex: normal

04_hex: Super

Bass

00_hex: normal

04_hex: Super

Bass

00_hex: normal

04_hex: Super

Version ≥ F7

00_hex: normal

04_hex: Super

Bass

(DSP W Addr. 0004_hexL)

Spatial Effect Loudspeaker

(DSP W Addr. 05_hexL)

Mode/

Customize

Mode/

Customize

always 0

Mode/

Customize

Prescale I²S2

Prescale I²S1

(DSP W Addr. 0012_hexH)

(DSP W Addr. 0016_hexH)

Yes¹⁾

Yes

No

Yes

FM DC Notch switchable

(DSP W Addr. 0017_hex

)

Mode Tone Control Loudspeaker channel

(DSP W Addr. 0020_hexH)

00_hex: Bass/

Treble

FF_hex:Equalizer

00_hex: Bass/

Treble

FF_hex:Equalizer

always Bass/

Treble

00_hex: Bass/

Treble

FF_hex:Equalizer

5 Band Equalizer (DSP W Addr.

0021_hex− 0025_hex

[+12 ...−12 dB]

not implemented [+12 ...−12 dB]

)

Balance Headphone channel

(DSP W Addr. 0030_hexH)

Yes¹⁾

Yes

No

Yes

¹⁾This feature will be implemented in MSP 3400C from version C7 on.

Micronas

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MSP 34x0D

PRELIMINARY DATA SHEET

Feature

MSP 3400C

MSP 3400D−B4 MSP 3410B−F7

MSP 3410D−B4

Audio Baseband Processing

Bass for Loudspeaker and Headphone chan.

Yes¹⁾

Yes

No

Yes

(DSP W Addr. 0002/0031_hexH) [+20 ...−12 dB]

[+20 ...−12 dB]

Treble for Loudspeaker and Headphone chan.

Yes¹⁾

Yes

(DSP W Addr. 0003/0032_hexH) [+15 ...−12 dB]

[+15 ...−12 dB]

Loudness Headphone channel

Yes¹⁾

Yes

(DSP W Addr. 0033_hexH)

Mode Loudness Headphone channel

(DSP W Addr. 0033_hexL)

00_hex: normal

04_hex: Super

Bass¹⁾

00_hex: normal

04_hex: Super

Bass

00_hex: normal

04_hex: Super

Bass

SCART1/2 Volume in dB

Yes¹⁾

Yes

No

Yes

(DSP W Addr. 0007/0040_hexH) (SCART1)

Scart 2 Volume (DSP W Addr. 0040_hexH)

No

Yes

No

Yes

Scart 2 Source (DSP W Addr. 0041_hexH)

Scart 2 Matrix (DSP W Addr. 0041_hexL)

Full SCART I/O Matrix without restrictions

No

Balance of loudspeaker and headphone

channels in dB units

Yes¹⁾

(DSP W Addr. 0016/0012_hex

)

Subwoofer output

No

Yes

No

Yes

Automatic Volume Correction (AVC)

¹⁾This feature will be implemented in MSP 3400C from version C7 on.

54

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PRELIMINARY DATA SHEET

MSP 34x0D

9. Specifications

9.1. Outline Dimensions

±0.1

16 x 1.27

= 20.32

1.1 x 45 °

±0.1

1.27

1.2 x 45°

9

1

61

10

60

1.6

2

9

15

9

26

44

1.9

4.05

27

43

0.1

±0.1

24.22

± 0.125

25.125

±0.15

4.75

SPGS7004-3/5E

Fig. 9–1:

68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g

Dimensions in mm

SPGS0016-4/3E

SPGS0015-1/2E

64

1

33

32

52

27

26

1

±0.1

19.3

±0.1

15.6

±0.1

18

57.7

±0.1

47

14

±0.06

0.27

±0.06

0.27

0°...15°

±0.5

±0.1

20.1

1

±0.1

1

0.457

±0.1

0.457

±0.05

1.778

31 x 1.778 = 55.118

±0.05

1.778

±0.1

1.29

25 x 1.778 = 44.47

Fig. 9–2:

Fig. 9–3:

64-Pin Plastic Shrink Dual Inline Package

(PSDIP64)

52-Pin Plastic Shrink Dual Inline Package

(PSDIP52)

Weight approximately 9.0 g

Dimensions in mm

Weight approximately 5.5 g

Dimensions in mm

Micronas

55

MSP 34x0D

PRELIMINARY DATA SHEET

23 x 0.8 = 18.4

0.8

±0.03

0.17

64

41

40

65

8

1.8

10.3

9.8

5

16

25

80

1.28

1

24

2.70

23.2

20

0.1

±0.2

3

SPGS0025-1/1E

Fig. 9–4:

80-Pin Plastic Quad Flat Pack

(PQFP80)

Weight approximately 1.61 g

Dimensions in mm

15 x 0.5 = 7.5

0.5

0.145

48

33

49

64

32

17

1

16

1.4

1.75

12

10

0.1

1.5

D0025/2E

Fig. 9–5:

64-Pin Plastic Low-Profile Quad Flat Pack

(PLQFP64)

Weight approximately 0.35 g

Dimensions in mm

56

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

9.2. Pin Connections and Short Descriptions

NC = not connected (leave vacant for future compatibility reasons)

TP = Test Pin (leave vacant; pin is used for production test only)

LV = leave vacant

X = obligatory; connect as described in application circuit diagram

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

PQFP

80-pin

PLQFP

64-pin

1

16

−

14

−

9

8

ADR_WS

NC

OUT

LV

ADR word strobe

Not connected

ADR data output

I²S1 data input

I²S data output

I²S word strobe

I²S clock

2

−

3

15

14

13

12

11

10

9

13

12

11

10

9

8

7

ADR_DA

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

OUT

IN

4

7

6

5

6

5

OUT

6

5

4

IN/OUT LV

7

4

3

8

3

2

I2C_DA

IN/OUT

X

I²C data

9

7

2

1

I2C_CL

X

I²C clock

10

11

12

13

14

15

16

17

18

8

−

1

64

63

62

61

60

59

58

−

NC

LV

X

Not connected

Standby (low-active)

I²C Bus address select

Digital control output 0

Digital control output 1

Not connected

7

6

80

79

78

77

76

75

−

STANDBYQ

ADR_SEL

D_CTR_OUT0

D_CTR_OUT1

NC

IN

6

5

IN

X

5

4

OUT

LV

4

3

−

2

−

NC

−

NC

1

2

74

57

AUD_CL_OUT

OUT

Audio clock output

(18.432 MHz)

19

20

21

22

23

64

63

62

61

60

1

73

72

71

70

69

56

55

54

53

52

TP

LV

X

Test pin

52

51

50

49

XTAL_OUT

XTAL_IN

TESTEN

ANA_IN2+

OUT

IN

Crystal oscillator

Test pin

X

IN

X

IN

AVSS via

56 pF / LV

IF input 2

(can be left vacant only if

IF input1 is also not in use)

24

59

58

48

47

68

67

51

50

ANA_IN−

IN

AVSS via

56 pF / LV

IF common

(can be left vacant only if

IF input1 is also not in use)

25

ANA_IN1+

LV

IF input 1

Micronas

57

MSP 34x0D

PRELIMINARY DATA SHEET

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

PQFP

80-pin

PLQFP

64-pin

26

−

57

−

46

−

66

65

64

63

62

61

60

59

58

49

−

AVSUP

NC

X

Analog power supply 5V

Not connected

X

−

LV

X

−

NC

Not connected

27

−

56

−

45

−

48

−

AVSS

MONO_IN

NC

Analog ground

X

Analog ground

28

−

55

−

44

−

47

−

IN

LV

X

Mono input

Not connected

29

54

43

46

VREFTOP

Reference voltage

IF A/D converter

30

31

32

33

34

35

36

37

38

39

40

41

42

53

52

51

50

49

48

47

46

45

44

43

−

42

41

−

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

−

SC1_IN_R

SC1_IN_L

ASG1

IN

LV

SCART 1 input, right

SCART 1 input, left

Analog Shield Ground 1

SCART 2 input, right

SCART 2 input, left

Analog Shield Ground 2

SCART 3 input, right

SCART 3 input, left

Analog Shield Ground 4

SCART 4 input, right

SCART 4 input, left

LV

AHVSS

LV

40

39

−

SC2_IN_R

SC2_IN_L

ASG2

IN

LV

AHVSS

LV

38

37

−

SC3_IN_R

SC3_IN_L

ASG4

IN

LV

AHVSS

LV

−

SC4_IN_R

SC4_IN_L

NC

IN

−

LV

−

LV or AHVSS Not connected

42

36

34

AGNDC

X

Analog reference

voltage

43

−

41

−

35

−

44

43

42

41

40

39

38

37

33

−

AHVSS

NC

X

Analog ground

X

Analog ground

−

LV

X

Not connected

−

NC

Not connected

44

45

46

47

40

39

38

37

34

33

32

31

32

31

30

29

CAPL_M

AHVSUP

CAPL_A

SC1_OUT_L

Volume capacitor MAIN

Analog power supply 8V

Volume capacitor AUX

SCART 1 output, left

X

OUT

LV

58

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

PQFP

80-pin

PLQFP

64-pin

48

49

36

35

30

29

36

35

28

27

SC1_OUT_R

VREF1

OUT

LV

X

SCART 1 output, right

Reference ground 1

high voltage part

50

51

52

53

54

55

56

57

58

59

60

−

34

33

−

28

27

−

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

26

25

−

SC2_OUT_L

SC2_OUT_R

NC

OUT

LV

LV¹⁾

LV

X

SCART 2 output, left

SCART 2 output, right

Not connected

32

31

30

29

28

27

26

25

−

24

23

22

21

20

19

18

17

−

NC

Not connected

26

−

DACM_SUB

NC

Subwoofer output

Not connected

25

24

23

22

21

−

DACM_L

DACM_R

VREF2

DACA_L

DACA_R

NC

OUT

Loudspeaker out, left

Loudspeaker out, right

Reference ground 2

Headphone out, left

Headphone out, right

Not connected

OUT

LV

X

−

NC

Not connected

61

62

63

64

65

66

−

24

23

22

21

20

19

−

20

−

16

15

14

13

12

11

−

RESETQ

NC

IN

Power-on reset

LV

X

Not connected

−

NC

Not connected

19

18

17

−

NC

Not connected

I2S_DA_IN2

DVSS

I²S2 data input

Digital ground

DVSS

X

Digital ground

−

DVSS

X

Digital ground

67

−

18

−

16

−

10

−

DVSUP

ADR_CL

X

Digital power supply 5V

ADR clock

X

−

X

68

17

15

9

OUT

LV

¹⁾Due to compatibility with MSP 3410D-B4 and older versions, it is possible to connect with ground as well.

Micronas

59

MSP 34x0D

PRELIMINARY DATA SHEET

9.3. Pin Configurations

ADR_WS

NC

ADR_CL

DVSUP

DVSS

I2S_DA_IN2

NC

ADR_DA

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

I2C_DA

NC

I2C_CL

RESETQ

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

NC 10

STANDBYQ 11

ADR_SEL 12

D_CTR_OUT0 13

D_CTR_OUT1 14

NC 15

60 DACA_R

59 DACA_L

58 VREF2

57 DACM_R

56 DACM_L

55 NC

NC 16

54 DACM_SUB

53 NC

NC 17

AUD_CL_OUT 18

TP 19

52 NC

MSP 34x0D

51 SC2_OUT_R

50 SC2_OUT_L

49 VREF1

XTAL_OUT 20

XTAL_IN 21

TESTEN 22

ANA_IN2+ 23

ANA_IN− 24

ANA_IN1+ 25

AVSUP 26

48 SC1_OUT_R

47 SC1_OUT_L

46 CAPL_A

45 AHVSUP

44 CAPL_M

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

AVSS

AHVSS

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

SC2_IN_R

SC2_IN_L

AGNDC

NC

SC4_IN_L

SC4_IN_R

ASG4

SC3_IN_L

SC3_IN_R

ASG2

Fig. 9–6: 68-pin PLCC package

60

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

AUD_CL_OUT

NC

1

2

3

4

5

6

7

8

9

64 TP

TP

AUD_CL_OUT

D_CTR_OUT1

D_CTR_OUT0

ADR_SEL

1

2

3

4

5

6

7

8

9

52 XTAL_OUT

51 XTAL_IN

50 TESTEN

49 ANA_IN2+

48 ANA_IN−

47 ANA_IN1+

46 AVSUP

63 XTAL_OUT

62 XTAL_IN

61 TESTEN

60 ANA_IN2+

59 ANA_IN−

58 ANA_IN+

57 AVSUP

NC

D_CTR_OUT1

D_CTR_OUT0

ADR_SEL

STANDBYQ

NC

STANDBYQ

I2C_CL

I2C_DA

45 AVSS

I2C_CL

56 AVSS

I2S_CL

44 MONO_IN

43 VREFTOP

42 SC1_IN_R

41 SC1_IN_L

40 SC2_IN_R

39 SC2_IN_L

38 SC3_IN_R

37 SC3_IN_L

36 AGNDC

I2C_DA 10

I2S_CL 11

I2S_WS 12

I2S_DA_OUT 13

I2S_DA_IN1 14

ADR_DA 15

ADR_WS 16

ADR_CL 17

DVSUP 18

DVSS 19

55 MONO_IN

54 VREFTOP

53 SC1_IN_R

52 SC1_IN_L

51 ASG1

I2S_WS 10

I2S_DA_OUT 11

I2S_DA_IN1 12

ADR_DA 13

ADR_WS 14

ADR_CL 15

DVSUP 16

50 SC2_IN_R

49 SC2_IN_L

48 ASG2

DVSS 17

47 SC3_IN_R

46 SC3_IN_L

45 ASG4

I2S_DA_IN2 18

NC 19

35 AHVSS

34 CAPL_M

33 AHVSUP

32 CAPL_A

31 SC1_OUT_L

30 SC1_OUT_R

29 VREF1

I2S_DA_IN2 20

NC 21

RESETQ 20

DACA_R 21

DACA_L 22

VREF2 23

44 SC4_IN_R

43 SC4_IN_L

42 AGNDC

41 AHVSS

NC 22

NC 23

RESETQ 24

DACA_R 25

DACA_L 26

VREF2 27

DACM_R 28

DACM_L 29

NC 30

DACM_R 24

DACM_L 25

DACM_SUB 26

40 CAPL_M

39 AHVSUP

38 CAPL_A

37 SC1_OUT_L

36 SC1_OUT_R

35 VREF1

28 SC2_OUT_L

27 SC2_OUT_R

Fig. 9–8: 52-pin PSDIP package

DACM_SUB 31

NC 32

34 SC2_OUT_L

33 SC2_OUT_R

Fig. 9–7: 64-pin PSDIP package

Micronas

61

MSP 34x0D

PRELIMINARY DATA SHEET

SC2_IN_L

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

NC

ASG2

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

NC

MONO_IN

AVSS

AGNDC

AHVSS

NC

AVSS

NC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AVSUP 65

40 CAPL_M

39 AHVSUP

38 CAPL_A

37 SC1_OUT_L

36 SC1_OUT_R

35 VREF1

AVSUP 66

ANA_IN1+ 67

ANA_IN− 68

ANA_IN2+ 69

TESTEN 70

XTAL_IN 71

XTAL_OUT 72

TP 73

34 SC2_OUT_L

33 SC2_OUT_R

32 ASG3

MSP 34x0D

AUD_CL_OUT 74

NC 75

31 NC

30 DACM_SUB

29 NC

NC 76

D_CTR_OUT1 77

D_CTR_OUT0 78

ADR_SEL 79

STANDBYQ 80

28 DACM_L

27 DACM_R

26 VREF2

25 DACA_L

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

NC

DACA_R

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

DVSUP

NC

RESETQ

NC

I2S_DA_IN2

DVSS

DVSUP

Fig. 9–9: 80-pin PQFP package

62

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

SC2_IN_L

ASG2

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

AGNDC

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

AHVSS

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

AVSUP 49

ANA_IN1+ 50

ANA_IN- 51

ANA_IN2+ 52

TESTEN 53

XTAL_IN 54

XTAL_OUT 55

TP 56

32 CAPL_M

31 AHVSUP

30 CAPL_A

29 SC1_OUT_L

28 SC1_OUT_R

27 VREF1

26 SC2_OUT_L

25 SC2_OUT_R

24 NC

MSP 34x0D

AUD_CL_OUT 57

NC 58

23 DACM_SUB

22 NC

NC 59

D_CTR_OUT1 60

D_CTR_OUT0 61

ADR_SEL 62

STANDBYQ 63

NC 64

21 DACM_L

20 DACM_R

19 VREF2

18 DACA_L

17 DACA_R

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

I2C_CL

RESETQ

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

NC

I2S_DA_IN2

DVSS

DVSUP

ADR_CL

Fig. 9–10: 64-pin PLQFP package

Micronas

63

MSP 34x0D

PRELIMINARY DATA SHEET

9.4. Pin Circuits (pin numbers refer to PLCC68 package)

DVSUP

P

N

500 k

3−30 pF

GND

N

2.5 V

Fig. 9–11: Output Pins 1, 3, 5, 13, 14, and 68

(ADR_WS, ADR_CL, ADR_DA, I2S_DA_OUT,

D_CTR_OUT0/1)

Fig. 9–15: Output/Input Pins 18, 20, and 21

(AUD_CL_OUT, XTALIN/OUT)

N

GND

ANAIN1+

ANAIN2+

Fig. 9–12: Input/Output Pins 8 and 9

(I2C_DA, I2C_CL)

A

D

ANAIN−

VREFTOP

Fig. 9–16: Input Pins 23-25, and 29

(ANA_IN2+, ANA_IN-, ANA_IN1+, VREFTOP)

Fig. 9–13: Input Pins 4, 11, 12, 61, 62, and 65

(STANDBYQ, ADR_SEL, RESETQ, TESTEN,

I2S_DA_IN1, I2S_DA_IN2)

0...2 V

DVSUP

P

Fig. 9–17: Capacitor Pins 44 and 46

(CAPL_M, CAPL_A)

N

GND

Fig. 9–14: Input/Output Pins 6 and 7

(I2S_WS, I2S_CL)

24 k

≈ 3.75 V

Fig. 9–18: Input Pin 28 (MONO_IN)

64

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

40 k

≈ 3.75 V

Fig. 9–19: Input Pins 30, 31, 33, 34, 36, 37, 40, and 41

(SC1-4_IN_L/R)

AHVSUP

0...1.2 mA

3.3 k

Fig. 9–20: Output Pins 56, 57, 59, 60, and 54

(DACA_L/R, DACM_L/R, DACM_SUB)

125 k

≈ 3.75 V

Fig. 9–21: Pin 42 (AGNDC)

26 pF

120 k

300

≈ 3.75 V

Fig. 9–22: Output Pins 47, 48, 50, and 51

(SC_1/2_OUT_L/R)

Micronas

65

MSP 34x0D

PRELIMINARY DATA SHEET

9.5. Electrical Characteristics

9.5.1. Absolute Maximum Ratings

Symbol

T_A

Parameter

Pin Name

−

Min.

0

Max.

70¹⁾

125

9.0

Unit

°C

V

Ambient Operating Temperature

Storage Temperature

First Supply Voltage

Second Supply Voltage

Third Supply Voltage

T_S

−

−40

−0.3

−0.5

V_SUP1

V_SUP2

V_SUP3

dV_SUP23

AHVSUP

DVSUP

AVSUP

6.0

V

6.0

V

Voltage between AVSUP

and DVSUP

AVSUP,

DVSUP

0.5

V

P_TOT

Package Power Dissipation

PLCC68 without Heat Spreader

PSDIP64 without Heat Spreader

PSDIP52 without Heat Spreader

PQFP80 without Heat Spreader

PLQFP64 without Heat Spreader

1200

1300

1200

1000

960¹⁾

mW

V_Idig

I_Idig

Input Voltage, all Digital Inputs

Input Current, all Digital Pins

Input Voltage, all Analog Inputs

−0.3

−20

V_SUP2+0.3

+20

V

−

mA²⁾

V

V_Iana

SCn_IN_s,³⁾

MONO_IN

−0.3

V_SUP1+0.3

I_Iana

Input Current, all Analog Inputs

SCn_IN_s,³⁾

MONO_IN

−5

+5

mA²⁾

4) 5)

I_Oana

Output Current, all SCART Outputs SCn_OUT_s³⁾

,

4)

Output Current, all Analog Outputs

except SCART Outputs

DACp_s³⁾

I_Cana

Output Current, other pins

connected to capacitors

CAPL_p,³⁾

AGNDC

1)

PLQFP64: 65 °C

positive value means current flowing into the circuit

“n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”

The analog outputs are short circuit proof with respect to First Supply Voltage and ground.

Total chip power dissipation must not exceed absolute maximum rating.

2)

3)

4)

5)

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in

the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute

maximum ratings conditions for extended periods may affect device reliability.

66

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

9.5.2. Recommended Operating Conditions

(at T_A= 0 to 70 °C)

Symbol

V_SUP1

V_SUP2

V_SUP3

V_RLH

Parameter

Pin Name

AHVSUP

DVSUP

Min.

7.6

Typ.

8.0

Max.

8.7

Unit

First Supply Voltage

Second Supply Voltage

Third Supply Voltage

V

4.75

0.7

5.0

5.25

0.8

V

AVSUP

5.0

V

RESET Input Low-to-High

Transition Voltage

RESETQ

DVSUP

V_RHL

RESET Input High-to-Low

Transition Voltage

0.45

0.55

DVSUP

(see also Fig. 5–3 on page 20)

V_DIGIL

V_DIGIH

V_DIGIL

V_DIGIH

Digital Input Low Voltage

Digital Input High Voltage

Digital Input Low Voltage

ADR_SEL

0.2

V_SUP2

0.8

STANDBYQ

Digital Input High Voltage

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

0.8

0.5

V_SUP2

t_STBYQ1

STANDBYQ Setup Time before

Turn-off of Second Supply Voltage

STANDBYQ,

DVSUP

1

µs

I²C-Bus Recommendations

V_I2CIL

V_I2CIH

t_I2C5

I²C-BUS Input Low Voltage

I2C_CL,

I2C_DA

0.3

V_SUP2

ns

I²C-BUS Input High Voltage

0.6

55

I²C-Data Setup Time Before

Rising Edge of Clock

t_I2C6

I²C-Data Hold Time after Falling

Edge of Clock

55

ns

t_I2C1

t_I2C2

t_I2C3

t_I2C4

f_I2C

I²C START Condition Setup Time

I²C STOP Condition Setup Time

I²C-Clock Low Pulse Time

I²C-Clock High Pulse Time

I²C-BUS Frequency

120

500

ns

I2C_CL

ns

1.0

MHz

Micronas

67

MSP 34x0D

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

I²S-Bus Recommendations

V_I2SIH

I²S-Data Input High Voltage

I2S_DA_IN1/2

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

0.25

0.2

V_SUP2

V_I2SIL

I²S-Data Input Low Voltage

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

0.75

0.5

V_SUP2

t_I2S1

I²S-Data Input Setup Time

before Rising Edge of Clock

I2S_DA_IN1/2,

I2S_CL

20

ns

t_I2S2

I²S-Data Input Hold Time

after Falling Edge of Clock

0

ns

f_I2SCL

R_I2SCL

f_I2SWS

V_I2SIDL

I²S-Clock Input Frequency when

MSP in I²S-Slave-Mode

I2S_CL

1.024

32.0

MHz

I²S-Clock Input Ratio when

MSP in I²S-Slave-Mode

0.9

1.1

I²S-Word Strobe Input Frequency

when MSP in I²S-Slave-Mode

I2S_WS

kHz

I²S-Input Low Voltage when

MSP in I²S-Slave Mode

I2S_CL,

I2S_WS

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

0.25

0.2

V_SUP2

V_I2SIDH

I²S-Input High Voltage when

MSP in I²S-Slave Mode

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

0.75

0.5

V_SUP2

t_I2SWS1

I²S-Word Strobe Input Setup Time

before Rising Edge of Clock when

MSP in I²S-Slave-Mode

60

ns

t_I2SWS2

I²S-Word Strobe Input Hold Time

after Falling Edge of Clock when

MSP in I²S-Slave-Mode

0

ns

68

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

General Crystal Recommendations

f_P

Crystal Parallel Resonance Fre-

18.432

MHz

quency at 12 pF Load Capacitance

R_R

C₀

C_L

Crystal Series Resistance

8

25

Ω

Crystal Shunt (Parallel) Capacitance

External Load Capacitance¹⁾

6.2

7.0

pF

XTAL_IN,

XTAL_OUT

PSDIP

PLCC

P(L)QFP

1.5

3.3

pF

Crystal Recommendations for Master-Slave Applications

f_TOL

Accuracy of Adjustment

−20

+20

ppm

D_TEM

Frequency Variation

versus Temperature

C₁

Motional (Dynamic) Capacitance

19

24

fF

f_CL

Required Open Loop Clock

AUD_CL_OUT

18.431

18.433 MHz

Frequency (T_amb= 25°C)

Crystal Recommendations for FM / NICAM Applications (No Master-Slave Mode possible)

f_TOL

D_TEM

C₁

Accuracy of Adjustment

−30

+30

ppm

fF

Frequency Variation vs. Temp.

Motional (Dynamic) Capacitance

−30

15

18.4305

18.4335

f_CL

Required Open Loop Clock

AUD_CL_OUT

MHz

Frequency (T_amb= 25 °C)

Crystal Recommendations for FM Applications (No Master-Slave Mode possible)

f_TOL

Accuracy of Adjustment

−100

−50

+100

+50

ppm

D_TEM

Frequency Variation

versus Temperature

Amplitude Recommendation for Operation with External Clock Input (C_loadafter reset = 22 pF)

V_XCA

External Clock Amplitude

XTAL_IN

0.7

V_pp

1)

External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-

quency of the internal PLL and to stabilize the frequency in closed-loop operation.

Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The sug-

gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.

To define the capacitor size, reset the MSP without transmitting any further I²C telegrams. Measure the fre-

quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz

as closely as possible.The higher the capacity, the lower the resulting clock frequency.

Micronas

69

MSP 34x0D

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

AGNDC

Min.

Typ.

Max.

Unit

Analog Input and Output Recommendations

C_AGNDC

AGNDC Filter Capacitor

−20%

3.3

µF

nF

Ceramic Capacitor in Parallel

100

330

C_inSC

DC-Decoupling Capacitor

in front of SCART Inputs

SCn_IN_s¹⁾

+20%

V_inSC

SCART Input Level

2.0

V_RMS

kΩ

V_inMONO

R_LSC

Input Level, Mono Input

SCART Load Resistance

SCART Load Capacitance

Main/AUX Volume Capacitor

MONO_IN

SCn_OUT_s¹⁾

10

C_LSC

6.0

nF

C_VMA

CAPL_M,

CAPL_A

10

1

µF

C_FMA

Main/AUX Filter Capacitor

DACM_s,

DACA_s¹⁾

−10%

+10%

nF

Recommendations for Analog Sound IF Input Signal

C_VREFTOP

VREFTOP Filter Capacitor

VREFTOP

−20%

0

10

µF

Ceramic Capacitor in Parallel

Analog Input Frequency Range

Analog Input Range FM/NICAM

Analog Input Range AM/NICAM

Ratio: NICAM Carrier/FM Carrier

100

nF

F_{IF_FM}

V_{IF_FM}

V_{IF_AM}

R_FMNI

9

MHz

V_pp

0.1

0.8

3

0.1

0.45

0.8

(unmodulated carriers)

BG:

I:

−20

−23

−7

−10

0

dB

R_AMNI

Ratio: NICAM Carrier/AM Carrier

(unmodulated carriers)

−25

−11

0

dB

R_FM

Ratio: FM-Main/FM-Sub Satellite

7

dB

ANA_IN1+,

ANA_IN2+,

ANA_IN-

R_FM1/FM2

Ratio: FM1/FM2

German FM System

R_FC

R_FV

Ratio: Main FM Carrier/

Color Carrier

15

−

dB

Ratio: Main FM Carrier/

Luma Components

PR_IF

Pass-band Ripple

−

±2

dB

SUP_HF

Suppression of Spectrum

Above 9.0 MHz

15

−

FM_MAX

Maximum FM Deviation (approx.)

normal mode

±192

±360

kHz

high deviation mode

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”

70

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

9.5.3. Characteristics

at T_A= 0 to 70 °C, f_CLOCK= 18.432 MHz, V_SUP1= 7.6 to 8.7 V, V_SUP2= 4.75 to 5.25 V for min./max. values

at T_A= 60 °C, f_CLOCK= 18.432 MHz, V_SUP1= 8 V, V_SUP2= 5 V for typical values, T_J= Junction Temperature

MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

MHz

%

Test Conditions

f

Clock Input Frequency

Clock High to Low Ratio

XTAL_IN

18.432

CLOCK

D

45

55

50

CLOCK

JITTER

t

Clock Jitter (verification not

provided in production test)

ps

V

DC-Voltage Oscillator

2.5

0.4

V

xtalDC

t

I

Oscillator Start-up Time at

XTAL_IN,

XTAL_OUT

2

ms

Startup

V

Slew-rate of 1 V/1 µs

DD

First Supply Current (active)

AHVSUP

SUP1A

Analog Volume for Main and Aux at 0 dB

9.6

6.3

17.1

11.2

24.6

16.1

mA

Analog Volume for Main and Aux at −30 dB

I

First Supply Current

(standby mode) at T = 27 °C

3.5

5.6

7.7

mA

STANDBYQ = low

SUP1S

SUP2A

j

Second Supply Current (active)

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

DVSUP

86

50

95

70

110

85

mA

I

Third Supply Current (active)

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

AVSUP

SUP3A

15

20

25

35

45

mA

V

Audio Clock Output AC Voltage

Audio Clock Output DC Voltage

HF Output Resistance

AUD_CL_OUT

1.2

0.4

1.8

V

load = 40 pF

ACLKAC

pp

V

0.6

I

= 0.2 mA

max

ACLKDC

SUP3

r

140

0.5

Ω

outHF_ACL

a

Open Circuit Gain

AUD_CL_OUT,

XTAL_OUT

ACL

Digital Control Outputs

V

Digital Output Low Voltage

Digital Output High Voltage

D_CTR_OUT0,

D_CTR_OUT1

0.4

V

I

= 1 mA

DCTROL

DCTROH

DCTR

4.0

= −1 mA

2

I C-Bus

2

V

I C-Data Output Low Voltage

I2C_DA

0.4

1.0

V

I

= 3 mA

I2COL

I2COH

I2COL1

I2COL

2

I

t

I C-Data Output High Current

µA

ns

V

= 5 V

I2COH

2

I C-Data Output Hold Time

I2C_DA,

I2C_CL

15

after Falling Edge of Clock

2

t

I C-Data Output Setup Time

100

ns

f

= 1 MHz

I2C

I2COL2

before Rising Edge of Clock

2

I S-Bus

2

V

I S-Output Low Voltage

I2S_WS,

I2S_CL,

I2S_DA_OUT

0.4

1.1

V

I

= 1 mA

I2SOL

I2SOH

I2SOL

I2SOH

2

I S-Output High Voltage

4.0

0.9

V

= −1 mA

2

f

t

I S-Clock Output Frequency

I2S_CL

1024

32.0

1.0

kHz

NICAM-PLL closed

I2SCL

2

I S-Word Strobe Output Frequency I2S_WS

I2SWS

I2S1/I2S2

2

I S-Clock High/Low-Ratio

I2S_CL

Micronas

71

MSP 34x0D

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

C = 30 pF

2

t

I S-Data Setup Time

I2S_CL,

I2S_DA_OUT

200

ns

I2S3

I2S4

I2S5

I2S6

L

before Rising Edge of Clock

2

I S-Data Hold Time

180

C = 30 pF

L

after Falling Edge of Clock

2

I S-Word Strobe Setup Time

I2S_CL,

I2S_WS

200

C = 30 pF

L

before Rising Edge of Clock

2

I S-Word Strobe Hold Time

180

C = 30 pF

L

after Falling Edge of Clock

Analog Ground

V

AGNDC Open Circuit Voltage

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

AGNDC

R

≥10 MΩ

load

AGNDC0

3.63

3.67

3.73

3.77

3.83

3.87

V

R

AGNDC Output Resistance

70

125

180

kΩ

3 V ≤ V

≤ 4 V

outAGN

AGNDC

Analog Input Resistance

1)

R

SCART Input Resistance

SCn_IN_s

25

15

40

24

58

35

kΩ

f

= 1 kHz, I = 0.05 mA

= 1 kHz, I = 0.1 mA

inSC

signal

from T = 0 to 70 °C

A

MONO Input Resistance

MONO_IN

inMONO

signal

from T = 0 to 70 °C

A

Audio Analog-to-Digital-Converter

1)

V

Effective Analog Input Clipping

Level for Analog-to-Digital-

Conversion

SCn_IN_s,

MONO_IN

2.00

2.25

V

f

= 1 kHz

AICL

RMS

signal

SCART Outputs

1)

R

SCART Output Resistance

at T = 27 °C

SCn_OUT_s

f

= 1 kHz, I = 0.1 mA

outSC

200

330

460

500

Ω

j

from T = 0 to 70 °C

A

dV

Deviation of DC-Level at SCART

Output from AGNDC Voltage

−70

+70

mV

dB

OUTSC

1)

A

Gain from Analog Input

to SCART Output

SCn_IN_s

−1.0

−0.5

+0.5

f

= 1 kHz

SCtoSC

signal

MONO_IN

→

SCn_OUT_s

1)

f

Frequency Response from Analog

Input to SCART Output

bandwidth: 0 to 20000 Hz

with respect to 1 kHz

rSCtoSC

V

Effective Signal Level at

SCn_OUT_s

1.8

1.9

2.0

V

f

= 1 kHz

outSC

RMS

signal

SCART-Output during full-scale

digital input signal from DSP

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”

72

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Main and AUX Outputs

1

R

Main/AUX Output Resistance

at T = 27 °C

DACp_s )

f

= 1 kHz, I = 0.1 mA

signal

outMA

2.1

3.3

4.6

5.0

kΩ

j

from T = 0 to 70 °C

A

V

DC-Level at Main/AUX-Output

for Analog Volume at 0 dB

for Analog Volume at −30 dB

outDCMA

outMA

1.80

1.23

2.04

61

2.28

1.51

V

mV

V

Effective Signal Level at Main/

AUX-Output during full-scale digital

input signal from DSP for Analog

Volume at 0 dB

1.37

V

f

= 1 kHz

signal

RMS

Analog Performance

SNR

Signal-to-Noise Ratio

from Analog Input to DSP

MONO_IN,

SCn_IN_s

85

93

85

88

96

88

dB

Input Level = −20 dB with

resp. to V , f = 1 kHz,

1)

AICL sig

equally weighted

2)

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

Input Level = −20 dB,

1)

SCn_IN_s

→

f

= 1 kHz,

sig

equally weighted

20 Hz...20 kHz

1)

SCn_OUT_s

from DSP to SCART Output

SCn_OUT_s

Input Level = −20 dB,

f

= 1 kHz,

sig

equally weighted

3)

20 Hz...15 kHz

1)

from DSP to Main/AUX-Output

for Analog Volume at 0 dB

for Analog Volume at −30 dB

DACp_s

Input Level = −20 dB,

85

78

88

83

dB

f

= 1 kHz,

sig

equally weighted

3)

20 Hz...15 kHz

THD

Total Harmonic Distortion

from Analog Input to DSP

MONO_IN,

SCn_IN_s

0.01

0.03

%

Input Level = −3 dBr with

1)

resp. to V

, f = 1 kHz,

AICL sig

equally weighted

2)

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

SCn_IN_s

→

Input Level = −3 dBr,

f

= 1 kHz,

sig

equally weighted

20 Hz...20 kHz

1)

SCn_OUT_s

from DSP to SCART Output

SCn_OUT_s

Input Level = −3 dBr,

f

= 1 kHz,

sig

equally weighted

3)

20 Hz...16 kHz

from DSP to Main or AUX Output

DACA_s,

Input Level = −3 dBr,

1)

DACM_s

f

= 1 kHz,

sig

equally weighted

3)

20 Hz...16 kHz

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

2)

3)

2

DSP measured at I S-Output

2

DSP Input at I S-Input

Micronas

73

MSP 34x0D

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

XTALK

Crosstalk attenuation

− PLCC68

Input Level = −3 dB,

f

= 1 kHz, unused ana-

sig

− PSDIP64

log inputs connected to

ground by Z < 1 kΩ

between left and right channel within

SCART Input/Output pair (L→R, R→L)

equally weighted

20 Hz...20 kHz

1)

SCn_IN → SCn_OUT

PLCC68 80

PSDIP64 80

dB

2)

3)

SC1_IN or SC2_IN → DSP

SC3_IN → DSP

PLCC68 80

PSDIP64 80

dB

PLCC68 80

PSDIP64 80

dB

1)

DSP → SCn_OUT

PLCC68 80

PSDIP64 80

dB

between left and right channel within

Main or AUX Output pair

equally weighted

20 Hz...16 kHz

1)

3)

DSP → DACp

PLCC68 80

PSDIP64 75

dB

1)

between SCART Input/Output pairs

(equally weighted

20 Hz...20 kHz

D = disturbing program

O = observed program

same signal source on left

and right disturbing chan-

nel, effect on each

D: MONO/SCn_IN → SCn_OUT

O: MONO/SCn_IN → SCn_OUT

PLCC68 100

PSDIP64 100

dB

1)

observed output channel

2)

3)

D: MONO/SCn_IN → SCn_OUT or unsel.

O: MONO/SCn_IN → DSP

PLCC68 100

PSDIP64 95

dB

1)

D: MONO/SCn_IN → SCn_OUT

PLCC68 100

PSDIP64 100

dB

1)

O: DSP → SCn_OUT

D: MONO/SCn_IN → unselected

O: DSP → SC1_OUT

PLCC68 100

PSDIP64 100

dB

Crosstalk between Main and AUX Output pairs

(equally weighted

20 Hz...16 kHz)

3)

same signal source on left

and right disturbing chan-

nel, effect on each

1)

DSP → DACp

PLCC68 95

PSDIP64 90

dB

observed output channel

XTALK

Crosstalk from Main or AUX Output to SCART Output

and vice-versa

(equally weighted

20 Hz...20 kHz)

same signal source on left

and right disturbing chan-

nel, effect on each

D = disturbing program

O = observed program

observed output channel

D: MONO/SCn_IN/DSP → SCn_OUT

O: DSP → DACp

PLCC68 85

PSDIP64 80

dB

SCART output load resis-

tance 10 kΩ

1)

D: MONO/SCn_IN/DSP → SCn_OUT

O: DSP → DACp

PLCC68 90

PSDIP64 85

dB

SCART output load resis-

tance 30 kΩ

1)

3)

D: DSP → DACp

O: MONO/SCn_IN → SCn_OUT

PLCC68 100

PSDIP64 95

dB

1)

D: DSP → DACM

O: DSP → SCn_OUT

PLCC68 100

PSDIP64 95

dB

1)

“n” means “1”, “2”, “3”, or “4”; “p” means “M” or “A”

2)

3)

2

DSP measured at I S-Output

2

DSP Input at I S-Input

74

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

PSRR: rejection of noise on AHVSUP at 1 kHz

AGNDC

80

70

dB

From Analog Input to DSP

MONO_IN,

SCn_IN_s

1)

From Analog Input to

SCART Output

MONO_IN,

SCn_IN_s ,

SCn_OUT_s

70

dB

1)

From DSP to SCART Output

SCn_OUT_s

60

80

dB

1)

From DSP to MAIN/AUX Output

DACp_s

1)

S/N

FM Input to Main/AUX/SCART

Output

DACp_s ,

73

1 FM-carrier 5.5 MHz,

50 µs, 1 kHz, 40 kHz devi-

ation; RMS, unweighted 0

to 15 kHz (for S/N);

FM

1)

SCn_OUT_s

1)

THD

Total Harmonic Distortion + Noise

of FM demodulated signal on Main/ SCn_OUT_s

AUX/SCART output

DACp_s ,

0.1

%

FM

full input range,

FM-Prescale = 46 ,

h

Vol = 0 dB

→ Output Level 1 V

DACp_s ; SPM = 3

at

RMS

1)

S/N

Signal to Noise ratio of NICAM

baseband signal on Main/AUX/

SCART outputs

DACp_s ,

72

dB

%

NICAM: −6 dB, 1 kHz,

RMS unweighted

0 to 15 kHz, Vol = 9 dB

NICAM

1)

SCn_OUT_s

NIC_Presc = 7F

h

Output level 1 V

at

RMS

1)

DACp_s SPM = 8

;

1)

THD

BER

Total Harmonic Distortion + Noise

of NICAM baseband signal on

Main/AUX/SCART output

DACp_s ,

0.1

1

2.12 kHz, Modulator input

level = 0 dBref

SPM = 8

NICAM

NI

SCn_OUT_s

−7

NICAM: Bit Error Rate

−

10

FM+NICAM,

norm conditions

1)

S/N

Signal to Noise ratio of AM base-

band signal on Main/AUX/SCART

outputs

DACp_s ,

48

dB

%

SIF input range:

AM

1)

SCn_OUT_s

0.1−0.8 V ; AM = 70 %,

pp

1 kHz, RMS unweighted

(S/N); 0 to 15 kHz,

FM/AM-Prescale = 3C

1)

,

THD

Total Harmonic Distortion + Noise

DACp_s ,

0.3

hex

AM

Vol = 0 dB → Output level:

of AM demodulated signal on Main/ SCn_OUT_s

AUX/SCART output

1)

0.5 V

at DACp_s

RMS

FM+NICAM, norm condi-

tions; SPM = 9

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “Loudspeaker (Main)’’ or ‘‘Headphone (AUX)’’

SPM: Short Programming Mode

Micronas

75

MSP 34x0D

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

R

Input Impedance

ANA_IN1+,

ANA_IN2+,

ANA_IN−

1.5

6.8

2

9.1

2.5

11.4

kΩ

Gain AGC = 20 dB

Gain AGC = 3 dB

IFIN

DC

DC voltage at VREFTOP

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

VREFTOP

ANA_IN

2.4

2.56

2.6

2.66

2.7

2.76

V

DC voltage on IF inputs

ANA_IN1+,

ANA_IN2+,

ANA_IN−

1.3

1.5

1.7

V

XTALK

Crosstalk attenuation

3 dB Bandwidth

ANA_IN1+,

ANA_IN2+,

ANA_IN−

40

10

dB

f

= 1 MHz

IF

signal

Input Level = −2 dBr

BW

MHz

dB

IF

AGC

AGC Step Width

0.85

1)

dV

Tolerance of output voltage

of FM demodulated signal

DACp_s ,

−1.5

−1.0

+1.5

+1.0

dB

1 FM-carrier, 50 µs, 1 kHz,

40 kHz deviation; RMS

FMOUT

NICAMOUT

FM

1)

SCn_OUT_s

1)

dV

Tolerance of output voltage

of NICAM baseband signal

DACp_s ,

dB

2.12 kHz, Modulator input

level = 0 dBref

SCn_OUT_s

1)

fR

FM Frequency Response on Main/ DACp_s ,

1 FM-carrier 5.5 MHz,

50 µs, Modulator input

level = −14.6 dBref; RMS

AUX/SCART Outputs,

Bandwidth 20 to 15000 Hz

SCn_OUT_s

1)

fR

NICAM Frequency Response on

Main/AUX/SCART Outputs,

Bandwidth 20 to 15000 Hz

DACp_s ,

−1.0

+1.0

dB

Modulator input

level = −12 dB dBref; RMS

NICAM

1)

SCn_OUT_s

1)

SEP

FM Channel Separation (Stereo)

DACp_s ,

50

2 FM-carriers

FM

1)

SCn_OUT_s

5.5/5.74 MHz, 50 µs,

1 kHz, 40 kHz deviation;

RMS

1)

SEP

NICAM Channel Separation

(Stereo)

DACp_s ,

80

dB

NICAM

1)

SCn_OUT_s

1)

XTALK

FM Crosstalk Attenuation (Dual)

DACp_s ,

2 FM-carriers

FM

SCn_OUT_s

5.5/5.74 MHz, 50 µs,

1 kHz, 40 kHz deviation;

RMS

1)

XTALK

NICAM Crosstalk Attenuation

(Dual)

DACp_s ,

80

dB

NICAM

1)

SCn_OUT_s

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

76

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

10. Application Circuit

IF2 IN

Tuner 2

Tuner 1

if ANA_IN2+ not used

Signal GND

IF1 IN

C see section 9.5.2.

10

µF

100

nF

+8.0 V

-

+

3.3 100

µF nF

+

56 pF

10 µF 10 µF

1 µF

DACM_L (29) 56

28 (55) MONO_IN

31 (52) SC1_IN_L

330 nF

1 nF

DACM_R (28) 57

Loudspeaker

Headphones

330 nF

30 (53) SC1_IN_R

32 (51) ASG1

AHVSS

DACM_SUB (31) 54

34 (49) SC2_IN_L

330 nF

33 (50) SC2_IN_R

35 (48) ASG2

1 µF

DACA_L (26) 59

DACA_R (25) 60

37 (46) SC3_IN_L

36 (47) SC3_IN_R

330 nF

1 nF

AHVSS

38 (45) ASG4

40 (43) SC4_IN_L

39 (44) SC4_IN_R

330 nF

5 V

MSP 34x0D

100 Ω

22 µF

SC1_OUT_L (37) 47

SC1_OUT_R (36) 48

SC2_OUT_L (34) 50

11 (7) STANDBYQ

12 (6) ADR_SEL

+

5 V

DVSS

+

DVSS

8 (10) I2C_DA

9 (9) I2C_CL

22 µF

SC2_OUT_R (33) 51

1 (16) ADR_WS

68 (17) ADR_CL

3 (15) ADR_DA

+

D_CTR_OUT0 (5) 13

D_CTR_OUT1 (4) 14

6 (12) I2S_WS

7 (11) I2S_CL

4 (14) I2S_DA_IN1

65 (20) I2S_DA_IN2

AUD_CL_OUT (1) 18

TESTEN (61) 22

5 (13) I2S_DA_OUT

AVSS

Alternative circuit for

ANA_IN1/2+ for more

attenuation of video

components:

100

nF

100

nF

100

nF

100 p

56 p

ResetQ

*

ANA_IN1/2+

(from CCU,

see section.

5.3. )

5 V

8.0 V

1 kΩ

Micronas

77

MSP 34x0D

PRELIMINARY DATA SHEET

Note: Pin numbers refer to the PLCC68 package; numbers in brackets refer to the PSDIP64 package.

*Application Note:

All ground pins should be connected to one low-resis-

tive ground plane.

All supply pins should be connected separately with

short and low-resistive lines to the power supply.

Decoupling capacitors from DVSUP to DVSS, AVSUP

to AVSS, and AHVSUP to AHVSS are recommended

as closely as possible to these pins. Decoupling of

DVSUP and DVSS is most important. We recommend

using more than one capacitor. By choosing different

values, the frequency range of active decoupling can

be extended. In our application boards we use: 220 pF,

470 pF, 1.5 nF, and 10 µF. The capacitor with the low-

est value should be placed nearest to the DVSUP and

DVSS pins.

The ASG pins should be connected as closely as pos-

sible to the MSP to ground. If they are lead with the

SCART input lines as shielding line, they should NOT

be connected to ground at the SCART connector.

78

Micronas

PRELIMINARY DATA SHEET

MSP 34x0D

11. Appendix A: MSP 34x0D Version History

A1

First hardware release, which is completely compatible

to MSP 3410B.

A2

Hardware as A1 with additional features:

– Automatic NICAM-FM switching

– Demodulator Short Programming

– Automatic Standard Detection

B3

Hardware as A2 with additional features:

– Automatic Volume Correction (AVC)

– Subwoofer Output

– improved Automatic Standard Detection

– extended Short Programming Mode

– automatic reset and selection of identification for

Demodulator Short Programming

B4

Hardware and firmware as B3:

– Carrier Mute Function not recommended in High-

Deviation Mode

C5

– additional package PLQFP64

– digital input specification changed as of version C5

and later (see section 9.5. on page 66)

– max. analog high supply voltage AHVSUP 8.7 V

– supply currents changed as of version C5 and later

(see section 9.5.3. on page 71)

– Pin ASG3 no longer supported

Micronas

79

MSP 34x0D

PRELIMINARY DATA SHEET

12. Data Sheet History

1. Preliminary data sheet: “MSP 3400D, MSP 3410D

Multistandard Sound Processors, Nov. 30, 1998,

6251-482-1PD. First release of the preliminary data

sheet.

2. Preliminary data sheet: “MSP 3400D, MSP 3410D

Multistandard Sound Processors, May 14, 1999,

6251-482-2PD. Second release of the preliminary

data sheet. Major changes:

– specification for version C5 added

(see Appendix A: Version History)

– section 9.: specification for PLQFP64 package

added

All information and data contained in this data sheet are without any

commitment, are not to be considered as an offer for conclusion of a

contract, nor shall they be construed as to create any liability. Any new

issue of this data sheet invalidates previous issues. Product availability

and delivery are exclusively subject to our respective order confirmation

form; the same applies to orders based on development samples deliv-

ered. By this publication, Micronas GmbH does not assume responsibil-

ity for patent infringements or other rights of third parties which may

result from its use.

Further, Micronas GmbH reserves the right to revise this publication and

to make changes to its content, at any time, without obligation to notify

any person or entity of such revisions or changes.

No part of this publication may be reproduced, photocopied, stored on a

retrieval system, or transmitted without the express written consent of

Micronas GmbH.

Micronas GmbH

Hans-Bunte-Strasse 19

D-79108 Freiburg (Germany)

P.O. Box 840

D-79008 Freiburg (Germany)

Tel. +49-761-517-0

Fax +49-761-517-2174

E-mail: docservice@micronas.com

Internet: www.micronas.com

Printed in Germany

Order No. 6251-482-2PD

80

Micronas


型号：	MSP3410DPP
厂家：	TDK ELECTRONICS
描述：	Consumer Circuit, CMOS, PDIP64, SHRINK, PLASTIC, DIP-64 光电二极管
文件：	总83页 (文件大小：1228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP3410DPP [TDK]

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