MSP3427GPO [TDK]

Consumer Circuit, CMOS, PDIP52, SHRINK, PLASTIC, DIP-52;
MSP3427GPO
型号: MSP3427GPO
厂家: TDK ELECTRONICS    TDK ELECTRONICS
描述:

Consumer Circuit, CMOS, PDIP52, SHRINK, PLASTIC, DIP-52

光电二极管
文件: 总81页 (文件大小:1267K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PRELIMINARY DATA SHEET  
MSP 34x7G  
Multistandard  
Sound Processor Family  
Edition March 5, 2001  
6251-535-2PD  
MICRONAS  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Contents  
Page  
Section  
Title  
5
6
6
7
1.  
Introduction  
1.1.  
1.2.  
1.3.  
Features of the MSP 34x7G Family and Differences to MSPD  
MSP 34x7G Version List  
MSP 34x7G Versions and their Application Fields  
8
2.  
Functional Description  
9
2.1.  
Architecture of the MSP 34x7G Family  
Sound IF Processing  
9
2.2.  
9
2.2.1.  
2.2.2.  
2.2.3.  
2.2.4.  
2.2.5.  
2.3.  
Analog Sound IF Input  
9
Demodulator: Standards and Features  
Preprocessing of Demodulator Signals  
Automatic Sound Select  
10  
10  
10  
12  
12  
12  
12  
12  
13  
13  
13  
13  
13  
Manual Mode  
Preprocessing for SCART  
2.4.  
Source Selection and Output Channel Matrix  
Audio Baseband Processing  
Automatic Volume Correction (AVC)  
Quasi-Peak Detector  
2.5.  
2.5.1.  
2.5.2.  
2.6.  
SCART Signal Routing  
2.6.1.  
2.6.2.  
2.7.  
SCART DSP In and SCART Out Select  
Stand-by Mode  
Digital Control I/O Pins and Status Change Indication  
Clock PLL Oscillator and Crystal Specifications  
2.8.  
14  
14  
14  
15  
15  
16  
16  
16  
16  
16  
16  
16  
16  
18  
19  
19  
19  
21  
22  
23  
29  
30  
30  
3.  
Control Interface  
3.1.  
I2C Bus Interface  
3.1.1.  
3.1.2.  
3.1.3.  
3.1.4.  
3.1.4.1.  
3.1.4.2.  
3.1.4.3.  
3.1.4.4.  
3.2.  
Internal Hardware Error Handling  
Description of CONTROL Register  
Protocol Description  
Proposals for General MSP 34x7G I2C Telegrams  
Symbols  
Write Telegrams  
Read Telegrams  
Examples  
Start-Up Sequence: Power-Up and I2C-Controlling  
MSP 34x7G Programming Interface  
User Registers Overview  
3.3.  
3.3.1.  
3.3.2.  
3.3.2.1.  
3.3.2.2.  
3.3.2.3.  
3.3.2.4.  
3.3.2.5.  
3.3.2.6.  
3.3.2.7.  
3.4.  
Description of User Registers  
STANDARD SELECT Register  
Refresh of STANDARD SELECT Register  
STANDARD RESULT Register  
Write Registers on I2C Subaddress 10hex  
Read Registers on I2C Subaddress 11hex  
Write Registers on I2C Subaddress 12hex  
Read Registers on I2C Subaddress 13hex  
Programming Tips  
3.5.  
Examples of Minimum Initialization Codes  
2
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Contents, continued  
Page  
Section  
Title  
30  
30  
30  
31  
31  
31  
3.5.1.  
3.5.2.  
3.5.3.  
3.5.4.  
3.5.5.  
3.5.6.  
B/G-FM (A2 or NICAM)  
BTSC-Stereo  
BTSC-SAP with SAP at Loudspeaker Channel  
FM-Stereo Radio  
Automatic Standard Detection  
Software Flow for Interrupt driven STATUS Check  
33  
33  
34  
36  
38  
39  
41  
41  
42  
42  
42  
43  
44  
46  
46  
47  
48  
49  
50  
51  
51  
52  
53  
4.  
Specifications  
4.1.  
Outline Dimensions  
4.2.  
Pin Connections and Short Descriptions  
Pin Descriptions  
4.3.  
4.4.  
Pin Configurations  
4.5.  
Pin Circuits  
4.6.  
Electrical Characteristics  
4.6.1.  
4.6.2.  
4.6.2.1.  
4.6.2.2.  
4.6.2.3.  
4.6.2.4.  
4.6.3.  
4.6.3.1.  
4.6.3.2.  
4.6.3.3.  
4.6.3.4.  
4.6.3.5.  
4.6.3.6.  
4.6.3.7.  
4.6.3.8.  
4.6.3.9.  
Absolute Maximum Ratings  
Recommended Operating Conditions  
General Recommended Operating Conditions  
Analog Input and Output Recommendations  
Recommendations for Analog Sound IF Input Signal  
Crystal Recommendations  
Characteristics  
General Characteristics  
Digital Inputs, Digital Outputs  
Reset Input and Power-Up  
I2C Bus Characteristics  
Analog Baseband Inputs and Outputs, AGNDC  
Sound IF Input  
Power Supply Rejection  
Analog Performance  
Sound Standard Dependent Characteristics  
57  
57  
58  
59  
59  
60  
60  
5.  
Appendix A: Overview of TV Sound Standards  
NICAM 728  
5.1.  
5.2.  
5.3.  
5.4.  
5.5.  
5.6.  
A2 Systems  
BTSC-Sound System  
Japanese FM Stereo System (EIA-J)  
FM Satellite Sound  
FM-Stereo Radio  
61  
61  
62  
63  
63  
63  
63  
65  
65  
6.  
Appendix B: Manual/Compatibility Mode  
6.1.  
Demodulator Write and Read Registers for Manual/Compatibility Mode  
DSP Write and Read Registers for Manual/Compatibility Mode  
Manual/Compatibility Mode: Description of Demodulator Write Registers  
Automatic Switching between NICAM and Analog Sound  
Function in Automatic Sound Select Mode  
Function in Manual Mode  
6.2.  
6.3.  
6.3.1.  
6.3.1.1.  
6.3.1.2.  
6.3.2.  
6.3.3.  
A2 Threshold  
Carrier-Mute Threshold  
Micronas  
3
MSP 34x7G  
PRELIMINARY DATA SHEET  
Contents, continued  
Page  
Section  
Title  
66  
68  
69  
69  
71  
71  
71  
71  
72  
72  
72  
72  
73  
73  
73  
73  
73  
73  
74  
74  
74  
74  
74  
75  
75  
75  
75  
75  
6.3.4.  
6.3.5.  
6.3.6.  
6.3.7.  
6.4.  
Register AD_CV  
Register MODE_REG  
FIR-Parameter, Registers FIR1 and FIR2  
DCO-Registers  
Manual/Compatibility Mode: Description of Demodulator Read Registers  
NICAM Mode Control/Additional Data Bits Register  
Additional Data Bits Register  
6.4.1.  
6.4.2.  
6.4.3.  
6.4.4.  
6.4.5.  
6.4.6.  
6.4.7.  
6.5.  
CIB Bits Register  
NICAM Error Rate Register  
PLL_CAPS Readback Register  
AGC_GAIN Readback Register  
Automatic Search Function for FM-Carrier Detection in Satellite Mode  
Manual/Compatibility Mode: Description of DSP Write Registers  
Additional Channel Matrix Modes  
6.5.1.  
6.5.2.  
6.5.3.  
6.5.4.  
6.5.5.  
6.5.6.  
6.5.7.  
6.6.  
Volume Modes of SCART1 Output  
FM Fixed Deemphasis  
FM Adaptive Deemphasis  
NICAM Deemphasis  
Identification Mode for A2 Stereo Systems  
FM DC Notch  
Manual/Compatibility Mode: Description of DSP Read Registers  
Stereo Detection Register for A2 Stereo Systems  
DC Level Register  
6.6.1.  
6.6.2.  
6.7.  
Demodulator Source Channels in Manual Mode  
Terrestric Sound Standards  
6.7.1.  
6.7.2.  
6.8.  
SAT Sound Standards  
Exclusions of Audio Baseband Features  
Compatibility Restrictions to MSP 34x7D  
6.9.  
77  
77  
78  
7.  
Appendix D: Application Information  
Phase Relationship of Analog Outputs  
Application Circuit  
7.1.  
7.2.  
80  
80  
8.  
9.  
Appendix E: MSP 34x7G Version History  
Data Sheet History  
License Notice:  
“Dolby Pro Logic” is a trademark of Dolby Laboratories.  
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec-  
tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to  
use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.  
4
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Multistandard Sound Processor Family  
EIA-J. The MSP 34x7G has optimum stereo perfor-  
mance without any adjustments.  
Release Note: Revision bars indicate significant  
changes to the previous edition. The hardware and  
software description in this document is valid for  
the MSP 34x7G version B8 and following versions.  
All MSP 34xxG versions are pin compatible to the  
MSP 34xxD. Only minor modifications are necessary  
to adapt a MSP 34xxD controlling software to the  
MSP 34xxG. The MSP 34x7G further simplifies con-  
trolling software. Standard selection requires a single  
I2C transmission only.  
1. Introduction  
The MSP 34x7G family of single-chip Multistandard  
Sound Processors covers the sound processing of all  
analog TV standards worldwide, as well as the NICAM  
digital sound standards. The full TV sound processing,  
starting with analog sound IF signal-in, down to pro-  
cessed analog AF-out, is performed in a single chip.  
Figure 11 shows a simplified functional block diagram  
of the MSP 34x7G.  
Note: The MSP 34x7G version has reduced control  
registers and less functional pins. The remaining regis-  
ters are software-compatible to the MSP 34x0G. The  
pinning is compatible to the MSP 34x0G.  
The MSP 34x7G has built-in automatic functions: The  
IC is able to detect the actual sound standard automat-  
ically (Automatic Standard Detection). Furthermore,  
pilot levels and identification signals can be evaluated  
internally with subsequent switching between mono/  
stereo/bilingual; no I2C interaction is necessary (Auto-  
matic Sound Selection).  
These TV sound processing ICs include versions for  
processing the multichannel television sound (MTS)  
signal conforming to the standard recommended by  
the Broadcast Television Systems Committee (BTSC).  
The DBX noise reduction, or alternatively, Micronas  
Noise Reduction (MNR) is performed alignment free.  
The MSP 34x7G can handle very high FM deviations  
even in conjunction with NICAM processing. This is  
especially important for the introduction of NICAM in  
China.  
Other processed standards are the Japanese FM-FM  
multiplex standard (EIA-J) and the FM-Stereo-Radio  
standard.  
The ICs are produced in submicron CMOS technology.  
The MSP 34x7G is available in the following packages:  
PSDIP52 and PMQFP44.  
Current ICs have to perform adjustment procedures in  
order to achieve good stereo separation for BTSC and  
Loud-  
speaker  
Sound  
De-  
modulator  
Pre-  
processing  
Loud-  
speaker  
Sound IF1  
ADC  
DAC  
Processing  
SCART1  
DAC  
SCART  
DSP  
Input  
Select  
ADC  
Prescale  
SCART  
Output  
Select  
SCART1  
MONO  
Fig. 1–1: Simplified functional block diagram of MSP 34x7G  
Micronas  
5
MSP 34x7G  
PRELIMINARY DATA SHEET  
1.1. Features of the MSP 34x7G Family and Differences to MSPD  
Feature (Features not available for MSPD are shaded gray.)  
3407  
X
3417  
X
3427  
X
3447  
X
3457  
X
3467  
X
2
Standard Selection with single I C transmission  
Automatic Standard Detection of terrestrial TV standards  
Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS  
Automatic Carrier Mute function  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Interrupt output programmable (indicating status change)  
Loudspeaker channel with volume  
X
X
X
X
X
X
X
X
X
X
X
X
AVC: Automatic Volume Correction  
X
X
X
X
X
X
One Stereo SCART (line) input, one Mono input; one Stereo SCART output  
Complete SCART in/out switching matrix  
X
X
X
X
X
X
X
X
X
X
X
X
All analog Mono sound carriers including AM-SECAM L  
All analog FM-Stereo A2 and satellite standards  
X
X
X
X
X
X
X
X
X
All NICAM standards  
X
X
Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM  
Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)  
Demodulation of the BTSC multiplex signal and the SAP channel  
Alignment free digital DBX noise reduction for BTSC Stereo and SAP  
Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP  
BTSC stereo separation (MSP 3427/47G also EIA-J) significantly better than spec.  
SAP and stereo detection for BTSC system  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Korean FM-Stereo A2 standard  
X
X
Alignment-free Japanese standard EIA-J  
Demodulation of the FM-Radio multiplex signal  
1.2. MSP 34x7G Version List  
Version  
Status  
Description  
MSP 3407G  
MSP 3417G  
MSP 3427G  
MSP 3447G  
MSP 3457G  
MSP 3467G  
available  
available  
FM Stereo (A2) Version  
NICAM and FM Stereo (A2) Version  
not confirmed NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system)  
not confirmed NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system)  
not confirmed Global Stereo Version (all sound standards)  
not confirmed Global Mono Version (all sound standards)  
6
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
1.3. MSP 34x7G Versions and their Application Fields  
Table 11 provides an overview of TV sound standards  
that can be processed by the MSP 34x7G family. In  
addition, the MSP 34x7G is able to handle the FM-  
Radio standard. With the MSP 34x7G, a complete  
multimedia receiver covering all TV sound standards  
together with terrestrial/cable and satellite radio sound  
can be built.  
Table 11: TV Stereo Sound Standards covered by the MSP 34x7G IC Family (details see Appendix A)  
MSP Version  
TV-  
System  
Position of Sound  
Carrier /MHz  
Sound  
Modulation  
Color  
System  
Broadcast e.g. in:  
5.5/5.7421875  
5.5/5.85  
FM-Stereo (A2)  
PAL  
Germany  
B/G  
FM-Mono/NICAM  
AM-Mono/NICAM  
FM-Mono/NICAM  
FM-Stereo (A2, D/K1)  
FM-Stereo (A2, D/K2)  
FM-Stereo (A2, D/K3)  
PAL  
Scandinavia, Spain  
France  
L
I
6.5/5.85  
SECAM-L  
PAL  
6.0/6.552  
UK, Hong Kong  
Slovak. Rep.  
currently no broadcast  
Poland  
6.5/6.2578125  
6.5/6.7421875  
6.5/5.7421875  
6.5/5.85  
SECAM-East  
PAL  
D/K  
SECAM-East  
FM-Mono/NICAM (D/K, NICAM) PAL  
China, Hungary  
6.5  
FM-Mono  
7.02/7.2  
7.38/7.56  
etc.  
FM-Stereo  
PAL  
Europe Sat.  
ASTRA  
Satellite  
4.5/4.724212  
FM-Stereo (A2)  
FM-FM (EIA-J)  
NTSC  
Korea  
M/N  
4.5  
NTSC  
Japan  
4.5  
BTSC-Stereo + SAP  
FM-Stereo Radio  
NTSC, PAL  
USA, Argentina  
USA, Europe  
FM-Radio  
10.7  
3467  
All standards as above, but Mono demodulation only.  
33 34 39 MHz  
4.5 9 MHz  
SAW Filter  
Sound  
Tuner  
IF  
Mixer  
Loudspeaker  
1
Mono  
Vision  
Demo-  
dulator  
MSP 34x7G  
2
2
SCART  
Input  
SCART1  
SCART1  
SCART Output  
Composite  
Video  
Fig. 12: Typical MSP 34x7G application  
Micronas  
7
Automatic  
Standard Selection  
Sound Select  
Deemphasis:  
50/75 s,  
J17  
DACM_L  
DACM_R  
Loud-  
speaker  
Channel  
Matrix  
FM/AM  
AGC  
Volume  
D
A
FM/AM  
Stereo or A/B  
Stereo or A  
Stereo or B  
µ
0
1
3
4
AVC  
ANA_IN1+  
Σ
DEMODULATOR  
(incl. Carrier Mute)  
DBX/MNR  
Panda1  
A
D
Prescale  
(0E  
)
(08  
)
(29  
)
(00  
)
hex  
hex  
hex  
hex  
Decoded  
Standards:  
NICAM  
Deemphasis  
J17  
NICAM  
A2  
AM  
BTSC  
EIA-J  
SAT  
Beeper  
(14  
)
hex  
Prescale  
(10  
)
hex  
I2C  
Read  
Register  
Standard  
and Sound  
Detection  
FM-Radio  
I2C  
Read  
Register  
Quasi-Peak  
Channel  
Matrix  
Quasi-Peak  
Detector  
(19  
)
hex  
(1A  
)
hex  
(0C  
)
hex  
Volume  
SCART  
D
A
SCART1  
Channel  
Matrix  
SCART1_L/R  
2
A
D
Prescale  
(0A  
)
(07  
)
hex  
(0D  
)
hex  
hex  
SC1_OUT_L  
SC1_OUT_R  
(13  
)
hex  
SC1_IN_L  
SC1_IN_R  
MONO_IN  
(13  
)
hex  
Fig. 21: Signal flow block diagram of the MSP 34x7G (input and output names correspond to pin names).  
PRELIMINARY DATA SHEET  
MSP 34x7G  
2.1. Architecture of the MSP 34x7G Family  
BTSC-Mono + SAP: Detection and FM demodulation  
of the aural carrier resulting in the MTS/MPX signal.  
Detection and evaluation of the pilot carrier, detection  
and FM demodulation of the SAP-subcarrier. Process-  
ing of the DBX noise reduction or Micronas Noise  
Reduction (MNR).  
Fig. 21 on page 8 shows a simplified block diagram of  
the IC. The block diagram contains all features of the  
MSP 3457G. Other members of the MSP 34x7G family  
do not have the complete set of features: The demodu-  
lator handles only a subset of the standards presented  
in the demodulator block; NICAM processing is only  
possible in the MSP 3417G and MSP 3457G (see  
dashed block in Fig. 21).  
Japan Stereo: Detection and FM demodulation of the  
aural carrier resulting in the MPX signal. Demodulation  
and evaluation of the identification signal and FM  
demodulation of the (L-R)-carrier.  
2.2. Sound IF Processing  
FM-Satellite Sound: Demodulation of one or two FM  
carriers. Processing of high-deviation mono or narrow  
bandwidth mono, stereo, or bilingual satellite sound  
according to the ASTRA specification.  
2.2.1. Analog Sound IF Input  
The input pins ANA_IN1+ and ANA_INoffer the pos-  
sibility to connect sound IF (SIF) sources to the  
MSP 34x7G. The analog-to-digital conversion of the  
sound IF signal is done by an A/D-converter. An ana-  
log automatic gain circuit (AGC) allows a wide range of  
input levels. The high-pass filter formed by the cou-  
pling capacitor at pin ANA_IN1+ (see Section 7.  
Appendix D: Application Informationon page 77) is  
sufficient in most cases to suppress video compo-  
nents. Some combinations of SAW filters and sound IF  
mixer ICs, however, show large picture components on  
their outputs. In this case, further filtering is recom-  
mended.  
FM-Stereo-Radio: Detection and FM demodulation of  
the aural carrier resulting in the MPX signal. Detection  
and evaluation of the pilot carrier and AM demodula-  
tion of the (L-R)-carrier.  
The demodulator blocks of all MSP 34x7G versions  
have identical user interfaces. Even completely differ-  
ent systems like the BTSC and NICAM systems are  
controlled the same way. Standards are selected by  
means of MSP Standard Codes. Automatic processes  
handle standard detection and identification without  
controller interaction. The key features of the  
MSP 34x7G demodulator blocks are  
2.2.2. Demodulator: Standards and Features  
Standard Selection: The controlling of the demodula-  
tor is minimized: All parameters, such as tuning fre-  
quencies or filter bandwidth, are adjusted automati-  
cally by transmitting one single value to the  
STANDARD SELECT register. For all standards, spe-  
cific MSP standard codes are defined.  
The MSP 34x7G is able to demodulate all TV sound  
standards worldwide including the digital NICAM sys-  
tem. Depending on the MSP 34x7G version, the fol-  
lowing demodulation modes can be performed:  
A2-Systems: Detection and demodulation of two sep-  
arate FM carriers (FM1 and FM2), demodulation and  
evaluation of the identification signal of carrier FM2.  
Automatic Standard Detection: If the TV sound stan-  
dard is unknown, the MSP 34x7G can automatically  
detect the actual standard, switch to that standard, and  
respond the actual MSP standard code.  
NICAM-Systems: Demodulation and decoding of the  
NICAM carrier, detection and demodulation of the ana-  
log (FM or AM) carrier. For D/K-NICAM, the FM carrier  
may have a maximum deviation of 384 kHz.  
Automatic Carrier Mute: To prevent noise effects or  
FM identification problems in the absence of an FM  
carrier, the MSP 34x7G offers a configurable carrier  
mute feature, which is activated automatically if the TV  
sound standard is selected by means of the STAN-  
DARD SELECT register. If no FM carrier is detected at  
one of the two MSP demodulator channels, the corre-  
sponding demodulator output is muted. This is indi-  
cated in the STATUS register.  
Very high deviation FM-Mono: Detection and robust  
demodulation of one FM carrier with a maximum devi-  
ation of 540 kHz.  
BTSC-Stereo: Detection and FM demodulation of the  
aural carrier resulting in the MTS/MPX signal. Detec-  
tion and evaluation of the pilot carrier, AM demodula-  
tion of the (L-R)-carrier and detection of the SAP sub-  
carrier. Processing of the DBX noise reduction or  
Micronas Noise Reduction (MNR).  
Micronas  
9
MSP 34x7G  
PRELIMINARY DATA SHEET  
2.2.3. Preprocessing of Demodulator Signals  
Stereo or Achannel: Analog or digital mono  
sound, stereo if available. In case of bilingual broad-  
cast, it contains language A (on left and right).  
The NICAM signals must be processed by a deempha-  
sis filter and adjusted in level. The analog demodu-  
lated signals must be processed by a deemphasis fil-  
ter, adjusted in level, and dematrixed. The correct  
deemphasis filters are already selected by setting the  
standard in the STANDARD SELECT register. The  
level adjustment has to be done by means of the FM/  
AM and NICAM prescale registers. The necessary  
dematrix function depends on the selected sound  
standard and the actual broadcasted sound mode  
(mono, stereo, or bilingual). It can be manually set by  
the FM Matrix Mode register or automatically by the  
Automatic Sound Selection.  
Stereo or Bchannel: Analog or digital mono  
sound, stereo if available. In case of bilingual broad-  
cast, it contains language B (on left and right).  
Fig. 22 and Table 22 show the source channel  
assignment of the demodulated signals in case of  
Automatic Sound Select mode for all sound standards.  
Note: The analog primary input channel contains the  
signal of the mono FM/AM carrier or the L+R signal of  
the MPX carrier. The secondary input channel con-  
tains the signal of the 2nd FM carrier, the L-R signal of  
the MPX carrier, or the SAP signal.  
2.2.4. Automatic Sound Select  
LS Ch.  
Matrix  
In the Automatic Sound Select mode, the dematrix  
function is automatically selected based on the identifi-  
cation information in the STATUS register. No I2C inter-  
action is necessary when the broadcasted sound  
mode changes (e.g. from mono to stereo).  
primary  
channel  
FM/AM  
0
1
FM/AM  
secondary  
channel  
Prescale  
Stereo or A/B  
Automatic  
Sound  
Select  
Output-Ch.  
matrices  
must be set  
once to  
NICAM  
NICAM A  
NICAM B  
Stereo or A  
Stereo or B  
3
4
stereo.  
The demodulator supports the identification check by  
switching between mono-compatible standards (stan-  
dards that have the same FM-Mono carrier) automati-  
cally and non-audible. If B/G-FM or B/G-NICAM is  
selected, the MSP will switch between these stan-  
dards. The same action is performed for the standards:  
D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM.  
Switching is only done in the absence of any stereo or  
bilingual identification. If identification is found, the  
MSP keeps the detected standard.  
Prescale  
Fig. 22: Source channel assignment of demodulated  
signals in Automatic Sound Select Mode  
2.2.5. Manual Mode  
Fig. 23 shows the source channel assignment of  
demodulated signals in case of manual mode. If man-  
ual mode is required, more information can be found in  
Section 6.7. Demodulator Source Channels in Manual  
Modeon page 75.  
In case of high bit-error rates, the MSP 34x7G auto-  
matically falls back from digital NICAM sound to ana-  
log FM or AM mono.  
Table 21 summarizes all actions that take place when  
Automatic Sound Select is switched on.  
LS Ch.  
Matrix  
primary  
channel  
FM/AM  
FM/AM  
0
1
FM-Matrix  
To provide more flexibility, the Automatic Sound Select  
block prepares four different source channels of  
demodulated sound (Fig. 22). By choosing one of the  
four demodulator channels, the preferred sound mode  
can be selected for each of the output channels (loud-  
speaker, headphone, etc.). This is done by means of  
the Source Select registers.  
secondary  
channel  
Prescale  
Output-Ch.  
matrices  
must be set  
according to  
the standard.  
NICAM  
NICAM A  
NICAM B  
NICAM  
(Stereo or A/B)  
Prescale  
Fig. 23: Source channel assignment of demodulated  
signals in Manual Mode  
The following source channels of demodulated sound  
are defined:  
FM/AMchannel: Analog mono sound, stereo if  
available. In case of NICAM, analog mono only  
(FM or AM mono).  
Stereo or A/Bchannel: Analog or digital mono  
sound, stereo if available. In case of bilingual broad-  
cast, it contains both languages A (left) and B  
(right).  
10  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Table 21: Performed actions of the Automatic Sound Selection  
Selected TV Sound Standard  
Performed Actions  
B/G-FM, D/K-FM, M-Korea,  
and M-Japan  
Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four  
demodulator source channels according to Table 22.  
B/G-NICAM, L-NICAM, I-NICAM,  
D/K-NICAM  
Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four  
demodulator source channels according to Table 22.  
In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches  
back to NICAM if possible. A hysteresis prevents periodical switching.  
B/G-FM, B/G-NICAM  
or  
Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and non-  
audible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound  
carrier.  
Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the  
absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP  
keeps the corresponding standard.  
D/K1-FM, D/K2-FM, D/K3-FM,  
and D/K-NICAM  
BTSC-STEREO, FM Radio  
M-BTSC-SAP  
Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator  
source channels according to Table 22. Detection of the SAP carrier.  
In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP  
switches automatically to SAP (see Table 22).  
Table 22: Sound modes for the demodulator source channels with Automatic Sound Select  
Source Channels in Automatic Sound Select Mode  
Broadcasted Selected  
Broadcasted  
Sound Mode  
FM/AM  
(source select: 0)  
Stereo or A/B  
(source select: 1)  
Stereo or A  
(source select: 3)  
Stereo or B  
(source select: 4)  
Sound  
MSP Standard  
Standard  
Code3)  
M-Korea  
B/G-FM  
D/K-FM  
M-Japan  
02  
MONO  
Mono  
Mono  
Mono  
Stereo  
A
Mono  
Stereo  
B
03, 081)  
04, 05, 07, 0B1)  
30  
STEREO  
Stereo  
Stereo  
BILINGUAL:  
Left = A  
Languages A and B  
Right = B  
Right = B  
B/G-NICAM  
L-NICAM  
08, 032)  
09  
NICAM not available or analog Mono  
error rate too high  
analog Mono  
analog Mono  
analog Mono  
I-NICAM  
0A  
0B, 042), 052)  
0C, 0D  
MONO  
analog Mono  
analog Mono  
analog Mono  
NICAM Mono  
NICAM Stereo  
NICAM Mono  
NICAM Stereo  
NICAM A  
NICAM Mono  
NICAM Stereo  
NICAM B  
D/K-NICAM  
D/K-NICAM  
(with high  
STEREO  
deviation FM)  
BILINGUAL:  
Languages A and B  
Left = NICAM A  
Right = NICAM B  
20, 21  
20  
MONO  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Mono  
Stereo  
Mono  
Stereo  
SAP  
STEREO  
MONO + SAP  
STEREO + SAP  
MONO + SAP  
BTSC  
21  
Left = Mono  
Right = SAP  
Left = Mono  
Right = SAP  
STEREO + SAP  
Left = Mono  
Right = SAP  
Left = Mono  
Right = SAP  
Mono  
SAP  
FM Radio  
40  
MONO  
Mono  
Mono  
Mono  
Mono  
STEREO  
Stereo  
Stereo  
Stereo  
Stereo  
1)  
The Automatic Sound Select process will automatically switch to the mono compatible analog standard.  
The Automatic Sound Select process will automatically switch to the mono compatible digital standard.  
The MSP Standard Codes are defined in Table 37 on page 18.  
2)  
3)  
Micronas  
11  
MSP 34x7G  
PRELIMINARY DATA SHEET  
2.3. Preprocessing for SCART  
2.5. Audio Baseband Processing  
The SCART input need only be adjusted in level by  
means of the SCART prescale register.  
2.5.1. Automatic Volume Correction (AVC)  
Different sound sources (e.g. terrestrial channels, SAT  
channels, or SCART) fairly often do not have the same  
volume level. Advertisements during movies usually  
have a higher volume level than the movie itself. This  
results in annoying volume changes. The AVC solves  
this problem by equalizing the volume level.  
2.4. Source Selection and Output Channel Matrix  
The Source Selector makes it possible to distribute all  
source signals (one of the demodulator source chan-  
nels or SCART) to the desired output channels (loud-  
speaker, etc.). All input and output signals can be pro-  
cessed simultaneously. Each source channel is  
identified by a unique source address.  
To prevent clipping, the AVCs gain decreases quickly  
in dynamic boost conditions. To suppress oscillation  
effects, the gain increases rather slowly for low level  
inputs. The decay time is programmable by means of  
the AVC register (see page 27).  
For each output channel, the sound mode can be set  
to sound A, sound B, stereo, or mono by means of the  
output channel matrix.  
For input signals ranging from 24 dBr to 0 dBr, the  
AVC maintains a fixed output level of 18 dBr. Fig. 24  
shows the AVC output level versus its input level. For  
prescale and volume registers set to 0 dB, a level of  
0 dBr corresponds to full scale input/output. This is  
If Automatic Sound Select is on, the output channel  
matrix can stay fixed to stereo (transparent) for demod-  
ulated signals.  
SCART input/output 0 dBr = 2.0 Vrms  
Loudspeaker output 0 dBr = 1.4 Vrms  
output level  
[dBr]  
18  
24  
input level  
[dBr]  
30  
24  
18  
12  
6  
0
Fig. 24: Simplified AVC characteristics  
2.5.2. Quasi-Peak Detector  
The quasi-peak readout register can be used to read  
out the quasi-peak level of any input source. The fea-  
ture is based on following filter time constants:  
attack time: 1.3 ms  
decay time: 37 ms  
12  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
2.6. SCART Signal Routing  
2.7. Digital Control I/O Pins and  
Status Change Indication  
2.6.1. SCART DSP In and SCART Out Select  
The static level of the digital input/output pins  
D_CTR_I/O_0/1 is switchable between HIGH and  
LOW via the I2C-bus by means of the ACB register  
(see page 28). This enables the controlling of external  
hardware switches or other devices via I2C-bus.  
The SCART DSP Input Select and SCART Output  
Select blocks include switching facilities. The switches  
are controlled by the ACB user register (see page 28).  
2.6.2. Stand-by Mode  
The digital input/output pins can be set to high imped-  
ance by means of the MODUS register (see page 21).  
In this mode, the pins can be used as input. The cur-  
rent state can be read out of the STATUS register (see  
page 22).  
If the MSP 34x7G is switched off by first pulling  
STANDBYQ low and then (after >1 µs delay) switching  
off DVSUP and AVSUP, but keeping AHVSUP  
(Stand-by-mode), the SCART switches maintain  
their position and function. This allows the copying  
from SCART-input to SCART-output in the TV sets  
stand-by mode.  
Optionally, the pin D_CTR_I/O_1 can be used as an  
interrupt request signal to the controller, indicating any  
changes in the read register STATUS. This makes poll-  
ing unnecessary; I2C-bus interactions are reduced to a  
minimum (see STATUS register on page 22 and  
MODUS register on page 21).  
In case of power on or starting from stand-by (switch-  
ing on the DVSUP and AVSUP, RESETQ going high  
2 ms later), all internal registers except the ACB regis-  
ter (page 28) are reset to the default configuration (see  
Table 35 on page 17). The reset position of the ACB  
register becomes active after the first I2C transmission  
into the Baseband Processing part. By transmitting the  
ACB register first, the reset state can be redefined.  
2.8. Clock PLL Oscillator and  
Crystal Specifications  
The MSP 34x7G derives all internal system clocks  
from the 18.432-MHz oscillator. In NICAM mode, the  
clock is phase-locked to the corresponding source.  
For proper performance, the MSP clock oscillator  
requires a 18.432-MHz crystal. Note, that for the  
phase-locked mode (NICAM), crystals with tighter tol-  
erance are required.  
Micronas  
13  
MSP 34x7G  
PRELIMINARY DATA SHEET  
3. Control Interface  
response time is about 0.3 ms. If the MSP cannot  
accept another byte of data (e.g. while servicing an  
internal interrupt), it holds the clock line I2C_CL low to  
force the transmitter into a wait state. The I2C Bus  
Master must read back the clock line to detect when  
the MSP is ready to receive the next I2C transmission.  
The positions within a transmission where this may  
happen are indicated by Waitin Section 3.1.3. The  
maximum wait period of the MSP during normal opera-  
tion mode is less than 1 ms.  
3.1. I2C Bus Interface  
The MSP 34x7G is controlled via the I2C bus slave  
interface.  
The IC is selected by transmitting one of the  
MSP 34x7G device addresses. In order to allow up to  
three MSP ICs to be connected to a single bus, an  
address select pin (ADR_SEL) has been implemented.  
With ADR_SEL pulled to high, low, or left open, the  
MSP 34x7G responds to different device addresses. A  
device address pair is defined as a write address and a  
read address (see Table 31).  
3.1.1. Internal Hardware Error Handling  
In case of any hardware problems (e.g. interruption of  
the power supply of the MSP), the MSPs wait period is  
extended to 1.8 ms. After this time period elapses, the  
MSP releases data and clock lines.  
Writing is done by sending the write device address,  
followed by the subaddress byte, two address bytes,  
and two data bytes.  
Reading is done by sending the write device address,  
followed by the subaddress byte and two address  
bytes. Without sending a stop condition, reading of the  
addressed data is completed by sending the device  
read address and reading two bytes of data.  
Indication and solving the error status:  
To indicate the error status, the remaining acknowl-  
edge bits of the actual I2C-protocol will be left high.  
Additionally, bit[14] of CONTROL is set to one. The  
MSP can then be reset via the I2C bus by transmitting  
the RESET condition to CONTROL.  
Refer to Section 3.1.3. for the I2C bus protocol and to  
Section 3.4. Programming Tipson page 30 for pro-  
posals of MSP 34x7G I2C telegrams. See Table 32  
for a list of available subaddresses.  
Indication of reset:  
Besides the possibility of hardware reset, the MSP can  
also be reset by means of the RESET bit in the CON-  
TROL register by the controller via I2C bus.  
Any reset, even caused by an unstable reset line etc.,  
is indicated in bit[15] of CONTROL.  
A general timing diagram of the I2C bus is shown in  
Due to the architecture of the MSP 34x7G, the IC can-  
not react immediately to an I2C request. The typical  
Fig. 421 on page 49.  
Table 31: I2C Bus Device Addresses  
ADR_SEL  
Low  
High  
Left Open  
(connected to DVSS)  
(connected to DVSUP)  
Mode  
Write  
80hex  
Read  
Write  
84hex  
Read  
Write  
Read  
89hex  
MSP device address  
81hex  
85hex  
88hex  
Table 32: I2C Bus Subaddresses  
Name  
Binary Value  
Hex Value  
Mode  
Function  
CONTROL  
0000 0000  
00  
Read/Write  
Write: Software reset of MSP (see Table 33)  
Read: Hardware error status of MSP  
WR_DEM  
RD_DEM  
WR_DSP  
RD_DSP  
0001 0000  
0001 0001  
0001 0010  
0001 0011  
10  
11  
12  
13  
Write  
Write  
Write  
Write  
write address demodulator  
read address demodulator  
write address DSP  
read address DSP  
14  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
3.1.2. Description of CONTROL Register  
Table 33: CONTROL as a Write Register  
Name  
Subaddress  
Bit[15] (MSB)  
Bits[14:0]  
CONTROL 00hex  
1 : RESET  
0 : normal  
0
Table 34: CONTROL as a Read Register  
Name  
Subaddress  
%LW>ꢀꢁ@ꢂꢃ06%ꢄ  
Bit>ꢀꢅ@ꢂ  
BitV>ꢀꢆꢇꢈ@ꢂ  
CONTROL 00hex  
RESET status after last reading of  
CONTROL:  
Internal hardware status:  
0 : no error occured  
not of interest  
1 : internal error occured  
0 : no reset occured  
1 : reset occured  
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be  
read once to be reset.  
3.1.3. Protocol Description  
Write to DSP or Demodulator  
S
write  
device  
address  
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK  
high low high low  
P
Read from DSP or Demodulator  
S
write  
device  
address  
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK  
high low  
S
P
read  
device  
address  
Wait ACK data-byte- ACK data-byte NAK  
high low  
P
Write to Control Register  
S
write  
device  
address  
Wait ACK sub-addr ACK data-byte ACK data-byte ACK  
high low  
Read from Control Register  
S
write  
device  
address  
Wait ACK  
00hex  
ACK  
S
read  
device  
address  
Wait ACK data-byte- ACK data-byte NAK  
high low  
P
Note: S =  
I2C-Bus Start Condition from master  
I2C-Bus Stop Condition from master  
P =  
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)  
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate End of Read’  
or from MSP indicating internal error state  
Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.  
This waiting time is max. 1 ms  
Micronas  
15  
MSP 34x7G  
PRELIMINARY DATA SHEET  
1
0
I2C_DA  
S
P
I2C_CL  
Fig. 31: I2C bus protocol (MSB first; data must be stable while clock is high)  
3.1.4. Proposals for General MSP 34x7G  
I2C Telegrams  
3.2. Start-Up Sequence:  
Power-Up and I2C-Controlling  
3.1.4.1. Symbols  
After POWER-ON or RESET (see Fig. 420), the IC is  
in an inactive state. All registers are in the Reset posi-  
tion (see Table 35 and Table 36), the analog outputs  
are muted. The controller has to initialize all registers  
for which a non-default setting is necessary.  
daw  
dar  
<
write device address (80hex, 84hex or 88hex)  
read device address (81hex, 85hex or 89hex  
Start Condition  
)
>
Stop Condition  
aa  
dd  
Address Byte  
Data Byte  
3.3. MSP 34x7G Programming Interface  
3.3.1. User Registers Overview  
3.1.4.2. Write Telegrams  
The MSP 34x7G is controlled by means of user regis-  
ters. The complete list of all user registers are given in  
Table 35 and Table 36. The registers are partitioned  
into the Demodulator section (Subaddress 10hex for  
writing, 11hex for reading) and the Baseband Process-  
ing sections (Subaddress 12hex for writing, 13hex for  
reading).  
<daw 00 d0 00>  
write to CONTROL register  
write data into demodulator  
write data into DSP  
<daw 10 aa aa dd dd>  
<daw 12 aa aa dd dd>  
3.1.4.3. Read Telegrams  
<daw 00 <dar dd dd>  
read data from  
CONTROL register  
Write and read registers are 16 bit wide, whereby the  
MSB is denoted bit[15]. Transmissions via I2C bus  
have to take place in 16-bit words (two byte transfers, with  
the most significant byte transferred first). All write regis-  
ters, except the demodulator write registers are readable.  
<daw 11 aa aa <dar dd dd> read data from demodulator  
<daw 13 aa aa <dar dd dd> read data from DSP  
3.1.4.4. Examples  
Unused parts of the 16-bit write registers must be zero.  
Addresses not given in this table must not be  
accessed.  
<80 00 80 00>  
RESET MSP statically  
Clear RESET  
<80 00 00 00>  
<80 10 00 20 00 03>  
Set demodulator to stand. 03hex  
For reasons of software compatibility to the  
MSP 34xxD, a Manual/Compatibility Mode is available.  
More read and write registers together with a detailed  
description can be found in Appendix B: Manual/Com-  
patibility Modeon page 61.  
<80 11 02 00 <81 dd dd> Read STATUS  
<80 12 00 08 01 20> Set loudspeaker channel  
source to NICAM and  
Matrix to STEREO  
More examples of typical application protocols are  
listed in Section 3.4. Programming Tipson page 30.  
16  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
.
Table 35: List of MSP 34x7G Write Registers  
Write Register  
Address Bits  
(hex)  
Description and Adjustable Range  
Reset  
See  
Page  
2
I C Sub-Address = 10  
; Registers are not readable  
hex  
STANDARD SELECT  
MODUS  
00 20  
00 30  
[15:0]  
[15:0]  
Initial Programming of the Demodulator  
00 00  
00 00  
19  
21  
Demodulator, Automatic options  
2
2
I C Sub-Address = 12  
; Registers are all readable by using I C Sub-Address = 13  
hex  
hex  
Volume loudspeaker channel  
00 00  
[15:8]  
[7:0]  
[+12 dB ... 114 dB, MUTE]  
MUTE  
26  
Volume / Mode loudspeaker channel  
1/8 dB Steps,  
00  
hex  
Reduce Volume / Tone Control / Compromise /  
Dynamic  
Volume SCART1 output channel  
Loudspeaker source select  
Loudspeaker channel matrix  
SCART1 source select  
SCART1 channel matrix  
Quasi-peak detector source select  
Quasi-peak detector matrix  
Prescale SCART input  
Prescale FM/AM  
00 07  
00 08  
[15:8]  
[15:8]  
[7:0]  
[+12 dB ... 114 dB, MUTE]  
MUTE  
27  
25  
25  
25  
25  
25  
25  
24  
23  
24  
24  
28  
28  
27  
2
2
[FM/AM, NICAM, SCART, I S1, I S2]  
FM/AM  
[SOUNDA, SOUNDB, STEREO, MONO...]  
SOUNDA  
FM/AM  
2
2
00 0A  
00 0C  
[15:8]  
[7:0]  
[FM/AM, NICAM, SCART, I S1, I S2]  
[SOUNDA, SOUNDB, STEREO, MONO...]  
SOUNDA  
FM/AM  
SOUNDA  
2
2
[15:8]  
[7:0]  
[FM/AM, NICAM, SCART, I S1, I S2]  
[SOUNDA, SOUNDB, STEREO, MONO...]  
00 0D  
00 0E  
[15:8]  
[15:8]  
[7:0]  
[00  
[00  
... 7F  
... 7F  
]
]
00  
00  
hex  
hex  
hex  
hex  
hex  
hex  
FM matrix  
[NO_MAT, GSTERERO, KSTEREO]  
[00 ... 7F ] (MSP 3417G, MSP 3457G only)  
NO_MAT  
Prescale NICAM  
00 10  
[15:8]  
[15:0]  
[15:0]  
[15:8]  
00  
00  
hex  
hex  
hex  
hex  
ACB : SCART Switches a. D_CTR_I/O 00 13  
Bits[15:0]  
[00 ... 7F ]/[00  
Beeper  
00 14  
00 29  
... 7F ]  
hex  
0/0  
off  
hex  
hex  
hex  
Automatic Volume Correction  
[off, on, decay time]  
Table 36: List of MSP 34x7G Read Registers  
Read Register  
Address Bits  
(hex)  
Description and Adjustable Range  
See  
Page  
2
I C Sub-Address = 11  
; Registers are not writable  
hex  
STANDARD RESULT  
STATUS  
00 7E  
02 00  
[15:0]  
[15:0]  
Result of Automatic Standard Detection (see Table 38)  
22  
22  
Monitoring of internal settings e.g. Stereo, Mono, Mute etc.  
2
I C Sub-Address = 13  
; Registers are not writable  
hex  
Quasi-peak readout left  
Quasi-peak readout right  
MSP hardware version code  
MSP major revision code  
MSP product code  
00 19  
00 1A  
00 1E  
[15:0]  
[00 ... 7FFF  
]
16 bit twos complement  
] 16 bit twos complement  
hex  
29  
29  
29  
29  
29  
29  
hex  
hex  
[15:0]  
[15:8]  
[7:0]  
[00 ... 7FFF  
hex  
[00 ... FF  
]
]
]
]
hex  
hex  
hex  
hex  
hex  
[00 ... FF  
hex  
00 1F  
[15:8]  
[7:0]  
[00 ... FF  
hex  
MSP ROM version code  
[00 ... FF  
hex  
Micronas  
17  
MSP 34x7G  
PRELIMINARY DATA SHEET  
3.3.2. Description of User Registers  
Table 37: Standard Codes for STANDARD SELECT register  
MSP Standard Code TV Sound Standard  
(Data in hex)  
Sound Carrier  
Frequencies in MHz  
MSP 34x7G Version  
Automatic Standard Detection  
Starts Automatic Standard Detection and  
00 01  
all  
sets detected standard  
Standard Selection  
00 02  
00 03  
00 04  
00 05  
00 06  
M-Dual FM-Stereo  
4.5/4.724212  
5.5/5.7421875  
6.5/6.2578125  
6.5/6.7421875  
6.5  
3407, -17, -27, -47, -57  
3407, -17, -57  
1)  
B/G-Dual FM-Stereo  
2)  
D/K1-Dual FM-Stereo  
D/K2-Dual FM-Stereo  
2)  
3)  
D/K -FM-Mono with HDEV3 , not detectable by  
Automatic Standard Detection, for China  
3)  
HDEV3 SAT-Mono (i.e. Eutelsat, s. Table 618)  
00 07  
00 08  
00 09  
00 0A  
00 0B  
00 0C  
D/K3-Dual FM-Stereo  
6.5/5.7421875  
5.5/5.85  
1)  
B/G-NICAM-FM  
3417, -57  
L-NICAM-AM  
I-NICAM-FM  
6.5/5.85  
6.0/6.552  
6.5/5.85  
2)  
D/K-NICAM-FM  
4)  
D/K-NICAM-FM with HDEV2 , not detectable by  
6.5/5.85  
Automatic Standard Detection, for China  
3)  
00 0D  
D/K-NICAM-FM with HDEV3 , not detectable by  
6.5/5.85  
4.5  
Automatic Standard Detection, for China  
00 20  
00 21  
00 30  
00 40  
00 50  
BTSC-Stereo  
3427, -47, -57  
BTSC-Mono + SAP  
M-EIA-J Japan Stereo  
4.5  
3427, -47, -57  
3427, -47, -57  
3407, -17, -57  
FM-Stereo Radio with 75 µs Deemphasis  
SAT-Mono (see Table 618)  
SAT-Stereo (see Table 618)  
10.7  
6.5  
00 51  
7.02/7.20  
1)  
In case of Automatic Sound Select, the B/G-codes 3  
and 8  
are equivalent.  
hex  
hex  
2)  
3)  
4)  
In case of Automatic Sound Select, the D/K-codes 4 , 5 , 7 , and B  
are equivalent.  
hex hex hex  
hex  
HDEV3: Max. FM deviation must not exceed 540 kHz  
HDEV2: Max. FM deviation must not exceed 360 kHz  
18  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
3.3.2.1. STANDARD SELECT Register  
3.3.2.2. Refresh of STANDARD SELECT Register  
The TV sound standard of the MSP 34x7G demodula-  
tor is determined by the STANDARD SELECT register.  
There are two ways to use the STANDARD SELECT  
register:  
A general refresh of the STANDARD SELECT register  
is not allowed. However, the following method  
enables watching the MSP 34x7G alivestatus and  
detection of accidental resets (only versions B6 and  
later):  
Setting up the demodulator for a TV sound standard  
by sending the corresponding standard code with a  
single I2C bus transmission.  
After Power-on, bit[15] of CONTROL will be set; it  
must be read once to enable the reset-detection  
feature.  
Starting the Automatic Standard Detection for ter-  
restrial TV standards. This is the most comfortable  
way to set up the demodulator. Within 0.5 s, the  
detection and setup of the actual TV sound standard  
is performed. The detected standard can be read  
out of the STANDARD RESULT register by the con-  
trol processor. This feature is recommended for the  
primary setup of a TV set. Outputs should be muted  
during Automatic Standard Detection.  
Reading of the CONTROL register and checking  
the reset indicator bit[15] .  
If bit[15] is 0, any refresh of the STANDARD  
SELECT register is not allowed.  
If bit[15] is 1, indicating a reset, a refresh of the  
STANDARD SELECT register and all other MSPG  
registers is required.  
The Standard Codes are listed in Table 37.  
3.3.2.3. STANDARD RESULT Register  
Selecting a TV sound standard via the STANDARD  
SELECT register initializes the demodulator. This  
includes: AGC-settings and carrier mute, tuning fre-  
quencies, FIR-filter settings, demodulation mode (FM,  
AM, NICAM), deemphasis and identification mode.  
If Automatic Standard Detection is selected in the  
STANDARD SELECT register, status and result of the  
Automatic Standard Detection process can be read out  
of the STANDARD RESULT register. The possible  
results are based on the mentioned Standard Code  
and are listed in Table 38.  
TV stereo sound standards that are unavailable for a  
specific MSP version are processed in analog mono  
sound of the standard. In that case, stereo or bilingual  
processing will not be possible.  
In cases where no sound standard has been detected  
(no standard present, too much noise, strong interfer-  
ers, etc.) the STANDARD RESULT register contains  
00 00hex. In that case, the controller has to start further  
actions (for example set the standard according to a  
preference list or by manual input).  
For a complete setup of the TV sound processing from  
analog IF input to the source selection, the transmis-  
sions as shown in Section 3.5. are necessary.  
For reasons of software compatibility to the  
MSP 34x7D, a Manual/Compatibility mode is avail-  
able. A detailed description of this mode can be found  
on page 61.  
As long as the STANDARD RESULT register contains  
a value greater than 07 FFhex, the Automatic Standard  
Detection is still active. During this period, the MODUS  
and STANDARD SELECT register must not be written.  
The STATUS register will be updated when the Auto-  
matic Standard Detection has finished.  
If a present sound standard is unavailable for a spe-  
cific MSP-version, it detects and switches to the ana-  
log mono sound of this standard.  
Example:  
The MSPs 3427G and 3447G will detect a B/G-NICAM  
signal as standard 3 and will switch to the analog FM-  
Mono sound.  
Micronas  
19  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 38: Results of the Automatic Standard  
Detection  
Broadcasted Sound  
Standard  
STANDARD RESULT Register  
Read 007Ehex  
Automatic Standard  
Detection could not  
find a sound standard  
0000hex  
B/G-FM  
B/G-NICAM  
I
0003hex  
0008hex  
000Ahex  
FM-Radio  
0040hex  
M-Korea  
M-Japan  
M-BTSC  
0002hex (if MODUS[14,13]=00)  
0020hex (if MODUS[14,13]=01)  
0030hex (if MODUS[14,13]=10)  
0009hex (if MODUS[12]=0)  
0004hex (if MODUS[12]=1)  
L-AM  
D/K1  
D/K2  
D/K3  
L-NICAM  
D/K-NICAM  
0009hex (if MODUS[12]=0)  
000Bhex (if MODUS[12]=1)  
>07FFhex  
Automatic Standard  
Detection still active  
20  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
3.3.2.4. Write Registers on I2C Subaddress 10hex  
Table 39: Write registers on I2C subaddress 10hex  
Register  
Address  
Function  
Name  
00 20hex  
STANDARD SELECTION Register  
STANDARD_SEL  
Defines TV-Sound or FM-Radio Standard  
bit[15:0] 00 01hex start Automatic Standard Detection  
00 02hex MSP Standard Codes (see Table 37)  
...  
00 51hex  
00 30hex  
MODUS Register  
MODUS  
Preference in Automatic Standard Detection:  
bit[15]  
0
undefined, must be 0  
bit[14:13]  
detected 4.5 MHz carrier is interpreted as:1)  
standard M (Korea)  
standard M (BTSC)  
standard M (Japan)  
chroma carrier (M/N standards are ignored)  
0
1
2
3
bit[12]  
detected 6.5 MHz carrier is interpreted as:1)  
standard L (SECAM)  
standard D/K1, D/K2, D/K3, or D/K NICAM  
0
1
General MSP 34x7G Options  
bit[11:4]  
bit[3]  
0
undefined, must be 0  
state of digital output pins D_CTR_I/O_0 and _1  
active: D_CTR_I/O_0 and _1 are output pins  
(can be set by means of the ACB register.  
see also: MODUS[1])  
0
1
tristate: D_CTR_I/O_0 and _1 are input pins  
(level can be read out of STATUS[4,3])  
bit[2]  
bit[1]  
0
undefined, must be 0  
0/1  
disable/enable STATUS change indication by means of  
the digital I/O pin D_CTR_I/O_1  
Necessary condition: MODUS[3] = 0 (active)  
bit[0]  
0/1  
off/on: Automatic Sound Select  
1) Valid at the next start of Automatic Standard Detection.  
Micronas  
21  
MSP 34x7G  
PRELIMINARY DATA SHEET  
3.3.2.5. Read Registers on I2C Subaddress 11hex  
Table 310: Read Registers on I2C Subaddress 11hex  
Register  
Address  
Function  
Name  
00 7Ehex  
STANDARD RESULT Register  
STANDARD_RES  
Readback of the detected TV sound or FM-Radio Standard  
bit[15:0] 00 00hex Automatic Standard Detection could not find  
a sound standard  
00 02hex MSP Standard Codes (see Table 38)  
...  
00 40hex  
>07 FFhex Automatic Standard Detection still active  
02 00hex  
STATUS Register  
STATUS  
Contains all user relevant internal information about the status of the MSP  
bit[15:10]  
bit[8]  
undefined  
0/1  
1indicates bilingual sound mode or SAP present  
(internally evaluated from received analog or digital iden-  
tification signals)  
bit[7]  
bit[6]  
0/1  
0/1  
1indicates independent mono sound (only for  
NICAM)  
mono/stereo indication  
(internally evaluated from received analog or digital iden-  
tification signals)  
bit[5,9]  
00  
01  
10  
11  
analog sound standard (FM or AM) active  
this pattern will not occur  
digital sound (NICAM) available  
bad reception condition of digital sound (NICAM) due to:  
a. high error rate  
b. unimplemented sound code  
c. data transmission only  
bit[4]  
bit[3]  
bit[2]  
0/1  
0/1  
low/high level of digital I/O pin D_CTR_I/O_1  
low/high level of digital I/O pin D_CTR_I/O_0  
0
1
detected secondary carrier (2nd A2 or SAP sub-carrier)  
no secondary carrier detected  
bit[1]  
bit[0]  
0
1
detected primary carrier (Mono or MPX carrier)  
no primary carrier detected  
undefined  
If STATUS change indication is activated by means of MODUS[1]: Each  
change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high  
level. Reading the STATUS register resets D_CTR_I/O_1.  
22  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
3.3.2.6. Write Registers on I2C Subaddress 12hex  
Table 311: Write Registers on I2C Subaddress 12hex  
Register  
Address  
Function  
Name  
PREPROCESSING  
00 0Ehex FM/AM Prescale  
PRE_FM  
bit[15:8] 00hex  
Defines the input prescale gain for the demodulated  
FM or AM signal  
...  
7Fhex  
00hex  
off (RESET condition)  
For all FM modes except satellite FM and AM-mode, the combinations of pres-  
cale value and FM deviation listed below lead to internal full scale.  
FM mode  
bit[15:8] 7Fhex  
48hex  
28 kHz FM deviation  
50 kHz FM deviation  
75 kHz FM deviation  
100 kHz FM deviation  
150 kHz FM deviation  
180 kHz FM deviation (limit)  
30hex  
24hex  
18hex  
13hex  
FM high deviation mode (HDEV2, MSP Standard Code = Chex  
)
bit[15:8] 30hex  
14hex  
150 kHz FM deviation  
360 kHz FM deviation (limit)  
FM very high deviation mode (HDEV3, MSP Standard Code = 6hex and Dhex  
)
bit[15:8] 20hex  
1Ahex  
450 kHz FM deviation  
540 kHz FM deviation (limit)  
Satellite FM with adaptive deemphasis  
bit[15:8] 10hex recommendation  
AM mode (MSP Standard Code = 9hex  
)
bit[15:8] 7Chex  
recommendation for SIF input levels from  
0.1 Vpp to 0.8 Vpp  
(Due to the AGC being switched on, the AM-output level  
remains stable and independent of the actual SIF-level in  
the mentioned input range)  
Micronas  
23  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 311: Write Registers on I2C Subaddress 12hex, continued  
Register  
Address  
Function  
Name  
(continued)  
FM Matrix Modes  
FM_MATRIX  
00 0Ehex  
Defines the dematrix function for the demodulated FM signal  
bit[7:0]  
00hex  
01hex  
02hex  
03hex  
no matrix (used for bilingual and unmatrixed stereo sound)  
German stereo (Standard B/G)  
Korean stereo (also used for BTSC, EIA-J and FM Radio)  
sound A mono (left and right channel contain the mono  
sound of the FM/AM mono carrier)  
04hex  
sound B mono  
In case of Automatic Sound Select = on, the FM Matrix Mode is set automati-  
cally. Writing to the FM/AM prescale register (00 0Ehex high part) is still allowed.  
In order not to disturb the automatic process, the low part of any I2C transmis-  
sion to this register is ignored. Therefore, any FM-Matrix readback values may  
differ from data written previously.  
In case of Automatic Sound Select = off, the FM Matrix Mode must be set as  
shown in Table 617 of Appendix B.  
To enable a Forced Mono Mode set A2 THRESHOLD as described in  
Section 6.3.2.on page 65  
00 10hex  
NICAM Prescale  
PRE_NICAM  
Defines the input prescale value for the digital NICAM signal  
bit[15:8] 00hex ... 7Fhex prescale gain  
examples:  
00hex  
20hex  
5Ahex  
7Fhex  
off  
0 dB gain  
9 dB gain (recommendation)  
+12 dB gain (maximum gain)  
00 0Dhex  
SCART Input Prescale  
PRE_SCART  
Defines the input prescale value for the analog SCART input signal  
bit[15:8] 00hex ... 7Fhex prescale gain  
examples:  
00hex  
19hex  
7Fhex  
off (RESET condition)  
0 dB gain (2 VRMS input leads to digital full scale)  
+14 dB gain (400 mVRMS input leads to digital full scale)  
24  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Table 311: Write Registers on I2C Subaddress 12hex, continued  
Register  
Address  
Function  
Name  
SOURCE SELECT AND OUTPUT CHANNEL MATRIX  
Source for:  
00 08hex  
00 0Ahex  
00 0Chex  
Loudspeaker Output  
SCART1 DA Output  
Quasi-Peak Detector  
SRC_MAIN  
SRC_SCART1  
SRC_QPEAK  
bit[15:8]  
0
1
FM/AM: demodulated FM or AM mono signal  
Stereo or A/B: demodulator Stereo or A/B signal  
(in manual mode, this source is identical to the NICAM  
source in the MSP 3417D)  
3
4
2
Stereo or A: demodulator Stereo Sound or  
Language A (only defined for Automatic Sound Select)  
Stereo or B: demodulator Stereo Sound or  
Language B (only defined for Automatic Sound Select)  
SCART input  
For demodulator sources, see Table 22.  
Matrix Mode for:  
00 08hex  
00 0Ahex  
00 0Chex  
Loudspeaker Output  
SCART1 DA Output  
Quasi-Peak Detector  
MAT_MAIN  
MAT_SCART1  
MAT_QPEAK  
bit[7:0]  
00hex  
10hex  
20hex  
30hex  
Sound A Mono (or Left Mono) (RESET condition)  
Sound B Mono (or Right Mono)  
Stereo (transparent mode)  
Mono (sum of left and right inputs divided by 2)  
special modes are available (see Section 6.5.1. on page 73)  
In Automatic Sound Select mode, the demodulator source channels are set  
according to Table 22. Therefore, the matrix modes of the corresponding out-  
put channels should be set to Stereo(transparent).  
Micronas  
25  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 311: Write Registers on I2C Subaddress 12hex, continued  
Register  
Address  
Function  
Name  
LOUDSPEAKER PROCESSING  
00 00hex  
Volume Loudspeaker  
VOL_MAIN  
bit[15:8] volume table with 1 dB step size  
7Fhex  
7Ehex  
...  
+12 dB (maximum volume)  
+11 dB  
74hex  
73hex  
72hex  
...  
+1 dB  
0 dB  
1 dB  
02hex  
01hex  
00hex  
FFhex  
113 dB  
114 dB  
Mute (RESET condition)  
Fast Mute (needs about 75 ms until the signal is com-  
pletely ramped down)  
bit[7:5]  
higher resolution volume table  
0
+0 dB  
1
+0.125 dB increase in addition to the volume table  
...  
7
+0.875 dB increase in addition to the volume table  
bit[4]  
0
must be set to 0  
bit[3:0]  
clipping mode  
0
1
2
3
reduce volume  
reduce tone control  
compromise  
dynamic  
With large scale input signals, positive volume settings may lead to signal clip-  
ping.  
The MSP 34x7G loudspeaker and headphone volume function is divided into a  
digital and an analog section. With Fast Mute, volume is reduced to mute posi-  
tion by digital volume only. Analog volume is not changed. This reduces any  
audible DC plops. To turn volume on again, the volume step that has been used  
before Fast Mute was activated must be transmitted.  
If the clipping mode is set to reduce volume, the following rule is used: To  
prevent severe clipping effects with bass, treble, or equalizer boosts, the inter-  
nal volume is automatically limited to a level where, in combination with either  
bass, treble, or equalizer setting, the amplification does not exceed 12 dB.  
If the clipping mode is reduce tone control, the bass or treble value is  
reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain  
of those bands is reduced, where amplification together with volume exceeds  
12 dB.  
If the clipping mode is compromise, the bass or treble value and volume are  
reduced half and half if amplification exceeds 12 dB. If the equalizer is switched  
on, the gain of those bands is reduced half and half, where amplification  
together with volume exceeds 12 dB.  
If the clipping mode is dynamic, volume is reduced automatically if the signal  
amplitudes would exceed 2 dBFS within the IC.  
26  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Table 311: Write Registers on I2C Subaddress 12hex, continued  
Register  
Address  
Function  
Name  
00 29hex  
Automatic Volume Correction (AVC) Loudspeaker Channel  
bit[15:12] 00hex  
08hex  
AVC off (and reset internal variables)  
AVC on  
AVC  
bit[11:8] 08hex  
04hex  
8 sec decay time  
4 sec decay time (recommended)  
2 sec decay time  
AVC_DECAY  
02hex  
01hex  
20 ms decay time (should be used for approx. 100 ms  
after channel change)  
SCART OUTPUT CHANNEL  
00 07hex Volume SCART1 Output Channel  
VOL_SCART1  
bit[15:8] volume table with 1 dB step size  
7Fhex  
7Ehex  
...  
+12 dB (maximum volume)  
+11 dB  
74hex  
73hex  
72hex  
...  
+1 dB  
0 dB  
1 dB  
02hex  
01hex  
00hex  
113 dB  
114 dB  
Mute (RESET condition)  
bit[7:5]  
bit[4:0]  
higher resolution volume table  
0
+0 dB  
1
+0.125 dB increase in addition to the volume table  
...  
7
+0.875 dB increase in addition to the volume table  
01hex  
this must be 01hex  
Micronas  
27  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 311: Write Registers on I2C Subaddress 12hex, continued  
Register  
Address  
Function  
Name  
SCART SWITCHES AND DIGITAL I/O PINS  
00 13hex  
ACB Register  
Defines the level of the digital output pins and the position of the SCART switches  
ACB_REG  
bit[15]  
0/1  
low/high of digital output pin D_CTR_I/O_1  
(MODUS[3]=0)  
bit[14]  
0/1  
low/high of digital output pin D_CTR_I/O_0  
(MODUS[3]=0)  
bit[13:5] SCART DSP Input Select  
xxxx00xx0 SCART1 to DSP input (RESET position)  
xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in  
the channel matrix mode for the corresponding output  
channels)  
xxxx11xx1 mute DSP input  
bit[13:5] SCART1 Output Select  
xx00xxx0x undefined (RESET position)  
xx10xxx0x MONO input to SCART1 output  
xx11xxx0x SCART1 DA to SCART1 output  
xx01xxx1x SCART1 input to SCART1 output  
xx11xxx1x mute SCART1 output  
The RESET position becomes active at the time of the first write transmission  
on the control bus to the audio processing part. By writing to the ACB register  
first, the RESET state can be redefined.  
BEEPER  
00 14hex  
Beeper Volume and Frequency  
BEEPER  
bit[15:8] Beeper Volume  
00hex  
7Fhex  
off  
maximum volume  
bit[7:0]  
Beeper Frequency  
01hex  
40hex  
FFhex  
16 Hz (lowest)  
1 kHz  
4 kHz  
28  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
3.3.2.7. Read Registers on I2C Subaddress 13hex  
Table 312: Read Registers on I2C Subaddress 13hex  
Register  
Address  
Function  
Name  
QUASI-PEAK DETECTOR READOUT  
00 19hex  
00 1Ahex  
Quasi-Peak Detector Readout Left  
Quasi-Peak Detector Readout Right  
QPEAK_L  
QPEAK_R  
bit[15:0] 0hex ... 7FFFhex values are 16 bit twos complement (only positive)  
MSP 34x7G VERSION READOUT REGISTERS  
00 1Ehex MSP Hardware Version Code  
MSP_HARD  
bit[15:8] 02hex  
MSP 34x7G - B8  
A change in the hardware version code defines hardware optimizations that  
may have influence on the chips behavior. The readout of this register is iden-  
tical to the hardware version code in the chips imprint.  
MSP Major Revision Code  
MSP_REVISION  
MSP_PRODUCT  
bit[7:0]  
07hex  
MSP 34x7G - B8  
00 1Fhex  
MSP Product Code  
bit[15:8] 07hex  
11hex  
MSP 3407G - B8  
MSP 3417G - B8  
MSP 3427G - B8  
MSP 3447G - B8  
MSP 3457G - B8  
MSP 3467G - B8  
1Bhex  
2Fhex  
39hex  
43hex  
By means of the MSP product code, the control processor is able to decide  
which TV sound standards have to be considered.  
MSP ROM Version Code  
MSP_ROM  
bit[7:0]  
46hex  
48hex  
MSP 34x7G - B6  
MSP 34x7G - B8  
A change in the ROM version code defines internal software optimizations,  
that may have influence on the chips behavior, e.g. new features may have  
been included. While a software change is intended to create no compatibility  
problems, customers that want to use the new functions can identify new  
MSP 34x7G versions according to this number.  
To avoid compatibility problems with MSP 3410B and MSP 34x7D, an offset of  
40hex is added to the ROM version code of the chips imprint.  
Micronas  
29  
MSP 34x7G  
PRELIMINARY DATA SHEET  
3.4. Programming Tips  
3.5. Examples of Minimum Initialization Codes  
This section describes the preferred method for  
initializing the MSP 34x7G. The initialization is  
grouped into three sections:  
Initialization of the MSP 34x7G according to these list-  
ings reproduces sound of the selected standard on the  
loudspeaker output. All numbers are hexadecimal. The  
examples have the following structure:  
SCART Signal Path (analog signal path)  
Demodulator  
1. Perform an I2C controlled reset of the IC.  
2. Write MODUS register  
Output Channels  
(with Automatic Sound Select).  
See Fig. 21 on page 8 for a complete signal flow.  
3. Set Source Selection for loudspeaker channel  
(with matrix set to STEREO).  
4. Set Prescale  
SCART Signal Path  
(FM and/or NICAM and dummy FM matrix).  
1. Select analog input for the SCART baseband pro-  
cessing (SCART DSP Input Select) by means of the  
ACB register.  
5. Write STANDARD SELECT register.  
6. Set Volume loudspeaker channel to 0 dB.  
2. Set preferred prescale for SCART.  
3. Select the source for the analog SCART output by  
means of the ACB register.  
3.5.1. B/G-FM (A2 or NICAM)  
<80 00 80 00>  
<80 00 00 00>  
// Softreset  
<80 10 00 30 20 03> // MODUS-Register: Automatic = on  
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St  
Demodulator  
<80 12 00 0E 24 03> // FM/AM-Prescale = 24  
,
hex  
For a complete setup of the TV sound processing from  
analog IF input to the source selection, the following  
steps must be performed:  
FM-Matrix = MONO/SOUNDA  
<80 12 00 10 5A 00> // NICAM-Prescale = 5A  
hex  
<80 10 00 20 00 03> // Standard Select: A2 B/G or NICAM B/G  
1. Set MODUS register to the preferred mode and  
Sound IF input.  
or  
<80 10 00 20 00 08>  
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB  
2. Set preferred prescale (FM and NICAM) values.  
3. Write STANDARD SELECT register.  
3.5.2. BTSC-Stereo  
4. If Automatic Sound Select is not active:  
Choose FM matrix repeatedly according to the  
sound mode indicated in the STATUS register.  
<80 00 80 00>  
<80 00 00 00>  
// Softreset  
<80 10 00 30 20 03> // MODUS-Register: Automatic = on  
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St  
Output Channels  
<80 12 00 0E 24 03> // FM/AM-Prescale = 24  
,
hex  
FM-Matrix = Sound A Mono  
<80 10 00 20 00 20> // Standard Select: BTSC-STEREO  
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB  
1. Select the source channel and matrix for each out-  
put channel.  
2. Select volume for each output channel.  
3.5.3. BTSC-SAP with SAP at Loudspeaker Channel  
<80 00 80 00>  
<80 00 00 00>  
// Softreset  
<80 10 00 30 20 03> // MODUS-Register: Automatic = on  
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St  
<80 12 00 0E 24 03> // FM/AM-Prescale = 24  
,
hex  
FM-Matrix = Sound A Mono  
<80 10 00 20 00 21> // Standard Select: BTSC-SAP  
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB  
30  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
3.5.4. FM-Stereo Radio  
<80 00 80 00>  
<80 00 00 00>  
// Softreset  
<80 10 00 30 20 03> // MODUS-Register: Automatic = on  
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St  
<80 12 00 0E 24 03> // FM/AM-Prescale = 24  
,
hex  
FM-Matrix = Sound A Mono  
<80 10 00 20 00 40> // Standard Select: FM-STEREO-RADIO  
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB  
3.5.5. Automatic Standard Detection  
A detailed software flow diagram is shown in Fig. 32  
on page 32.  
<80 00 80 00>  
<80 00 00 00>  
// Softreset  
<80 10 00 30 20 03> // MODUS-Register: Automatic = on  
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St  
<80 12 00 0E 24 03> // FM/AM-Prescale = 24  
,
hex  
FM-Matrix = Sound A Mono  
<80 12 00 10 5A 00> // NICAM-Prescale = 5A  
hex  
<80 10 00 20 00 01> // Standard Select:  
Automatic Standard Detection  
// Wait till STANDARD RESULT contains a value 07FF  
// IF STANDARD RESULT contains 0000  
// do some error handling  
// ELSE  
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB  
3.5.6. Software Flow for Interrupt driven STATUS  
Check  
A detailed software flow diagram is shown in Fig. 32  
on page 32.  
If the D_CTR_I/O_1 pin of the MSP 34x7G is con-  
nected to an interrupt input pin of the controller, the fol-  
lowing interrupt handler can be applied to be automati-  
cally called with each status change of the  
MSP 34x7G. The interrupt handler may adjust the TV  
display according to the new status information.  
Interrupt Handler:  
<80 11 02 00 <81 dd dd> // Read STATUS  
// adjust TV-display with given status information  
// Return from Interrupt  
Micronas  
31  
MSP 34x7G  
PRELIMINARY DATA SHEET  
:ULWHꢂ02'86ꢂ5HJLVWHU  
:
for the essential bits:  
[1] = 1  
[8] = 0  
Enable interrupt if STATUS changes  
ANA_IN1+ is selected  
Define Preference for Automatic Standard  
Detection:  
[12] = 0  
If 6.5 MHz, set SECAM-L  
[14:13] = 3 Ignore 4.5 MHz carrier  
:ULWHꢂ6285&(ꢂ6(/(&7ꢂ6HWWLQJV  
set loudspeaker Source Select to "Stereo or A"  
set headphone Source Select to "Stereo or B"  
set SCART_Out Source Select to "Stereo or A/B"  
set Channel Matrix mode for all outputs to "Stereo"  
Write FM/AM-Prescale  
Write NICAM-Prescale  
:ULWHꢂꢈꢀꢂLQWR  
67$1'$5'ꢂ6(/(&7ꢂ5HJLVWHU  
(Start Automatic Standard Detection)  
set previous standard or  
set standard manually according  
picture information  
Result = 0  
yes  
?
no  
expecting interrupt from MSP  
,QꢂFDVHꢂRIꢂLQWHUUXSWꢂIURP  
063ꢂWRꢂFRQWUROOHUꢇ  
Read STATUS  
Adjust TV-Display  
If bilingual, adjust Source Select setting if required  
Fig. 32: Software flow diagram for a minimum demodulator setup for a European multistandard set applying the  
Automatic Sound Select feature  
32  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4. Specifications  
4.1. Outline Dimensions  
SPGS703000-1(P52)/1E  
52  
27  
26  
1
±0.1  
15.6  
±0.1  
47.0  
±0.1  
14  
±0.06  
0.28  
±1  
±0.05  
16.3  
1
±0.06  
0.48  
1.778  
25 x 1.778 = 44.4  
±0.1  
Fig. 41:  
52-Pin Plastic Shrink Dual Inline Package  
(PSDIP52)  
Weight approximately 5.5 g  
Dimensions in mm  
± 0.1  
10 x 0.8 = 8  
0.8  
± 0.06  
0.17  
33  
23  
34  
22  
12  
44  
1
11  
± 0.1  
2.0  
± 0.2  
± 0.1  
10  
13.2  
0.1  
± 0.2  
2.15  
SPGS706000-5(P44)/1E  
Fig. 42:  
44-Pin Plastic Metric Quad Flat Pack  
(PMQFP44)  
Weight approximately 0.4 g  
Dimensions in mm  
Micronas  
33  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.2. Pin Connections and Short Descriptions  
NC = not connected; leave vacant  
LV = if not used, leave vacant  
DVSS: if not used, connect to DVSS  
X = obligatory; connect as described in circuit diagram  
AHVSS: connect to AHVSS  
Pin No.  
Pin Name  
Type  
Connection  
(if not used)  
Short Description  
PSDIP  
PMQFP  
44-pin  
52-pin  
1
7
TP  
LV  
LV  
LV  
LV  
X
Test pin  
2
NC  
Not connected  
D_CTR_I/O_1  
D_CTR_I/O_0  
I2C Bus address select  
Standby (low-active)  
I2C clock  
3
8
D_CTR_I/O_1  
D_CTR_I/O_0  
ADR_SEL  
STANDBYQ  
I2C_CL  
I2C_DA  
TP  
IN/OUT  
IN/OUT  
IN  
4
9
5
10  
11  
12  
13  
14  
15  
16  
17  
6
IN  
X
7
IN/OUT  
IN/OUT  
X
8
X
I2C data  
9
LV  
LV  
LV  
LV  
LV  
LV  
LV  
X
Test pin  
10  
11  
12  
13  
14  
15  
16  
17  
TP  
Test pin  
TP  
Test pin  
TP  
Test pin  
TP  
Test pin  
TP  
Test pin  
18  
19  
TP_CO  
DVSUP  
DVSS  
DVSS  
TP  
OUT  
Test pin1)  
Digital power supply +5 V  
Digital ground  
Digital ground  
Test pin  
X
20  
21  
X
18  
19  
20  
21  
22  
23  
24  
LV  
LV  
X
NC  
Not connected  
Power-on-reset  
Not connected  
Not connected  
Reference ground 2 high-voltage part  
Loudspeaker out, right  
22  
23  
24  
25  
26  
RESETQ  
NC  
IN  
LV  
LV  
X
NC  
VREF2  
DACM_R  
OUT  
LV  
1) Use this pin to define the capacitor size at the crystal oscillator (see Section 4.6.2.4. on page 44).  
34  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Pin No.  
Pin Name  
Type  
Connection  
(if not used)  
Short Description  
PSDIP  
PMQFP  
44-pin  
52-pin  
25  
27  
DACM_L  
NC  
OUT  
LV  
LV  
LV  
LV  
X
Loudspeaker out, left  
Not connected  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
NC  
Not connected  
28  
29  
30  
31  
32  
33  
34  
35  
36  
NC  
Not connected  
VREF1  
SC1_OUT_R  
SC1_OUT_L  
NC  
Reference ground 1 high-voltage part  
SCART 1 output, right  
SCART 1 output, left  
Not connected  
OUT  
OUT  
LV  
LV  
LV  
X
AHVSUP  
CAPL_M  
AHVSS  
AGNDC  
Analog power supply +8.0 V  
Volume capacitor MAIN  
Analog ground  
X
X
X
Analog reference voltage high-volt-  
age part  
37  
38  
39  
40  
NC  
LV  
LV  
LV  
LV  
LV  
LV  
LV  
X
Not connected  
NC  
Not connected  
37  
38  
39  
40  
41  
42  
NC  
Not connected  
NC  
Not connected  
NC  
Not connected  
41  
42  
43  
SC1_IN_L  
SC1_IN_R  
VREFTOP  
IN  
IN  
SCART 1 input, left  
SCART 1 input, right  
Reference voltage IF  
A/D converter  
44  
45  
46  
47  
48  
49  
50  
51  
52  
43  
44  
1
MONO_IN  
AVSS  
IN  
LV  
X
Mono input  
Analog ground  
Analog power supply +5 V  
IF input 1  
AVSUP  
X
2
ANA_IN1+  
ANA_IN−  
NC  
IN  
IN  
LV  
LV  
LV  
X
3
IF common  
Not connected  
Test pin  
4
TESTEN  
XTAL_IN  
XTAL_OUT  
IN  
5
IN  
X
Crystal oscillator  
Crystal oscillator  
6
OUT  
X
Micronas  
35  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.3. Pin Descriptions  
CAPLM Volume Capacitor Loudspeakers (Fig. 418)  
A 10µF capacitor to AHVSUP must be connected to  
this pin. It serves as smoothing filter for volume  
changes in order to suppress audible plops. The value  
of the capacitor can be lowered to 1µF if faster  
response is required. The area encircled by the trace  
lines should be minimized, keep traces as short as  
possible. This input is sensitive for magnetic induction.  
NC Pin not connected  
I2C_CL I2C Clock Input/Output (Fig. 412)  
Via this pin the I2C bus clock signal has to be supplied.  
The signal can be pulled down by the MSP in case of  
wait conditions.  
I2C_DA I2C Data Input/Output (Fig. 412)  
Via this pin the I2C bus data is written to or read from  
the MSP.  
AHVSS* Ground for Analog Power Supply High Volt-  
age  
Ground connection for the analog circuitry of the MSP  
(except IF input).  
TP_CO Clock Output  
Output of clock signal used in order to define capaci-  
tors at the crystal oscillator (see Section 4.6.2.4. on  
page 44).  
AGNDC Internal Analog Reference Voltage  
This pin serves as the internal ground connection for  
the analog circuitry (except IF input). It must be con-  
nected to the VREF pins with a 3.3 µF and a 100 nF  
capacitor in parallel. This pins shows a DC level of typ-  
ically 3.73 V.  
DVSUP* Digital Supply Voltage  
Power supply for the digital circuitry of the MSP. Must  
be connected to a power supply.  
SC1_IN_L/R SCART1 Inputs (Fig. 48)  
DVSS* Digital Ground  
Ground connection for the digital circuitry of the MSP  
The analog input signal for SCART1 is fed to this pin.  
Analog input connection must be AC coupled.  
RESETQ Reset Input (Fig. 45)  
In the steady state, high level is required. A low level  
resets the MSP 34x7G.  
VREFTOP Reference Voltage IF AD Converter  
(Fig. 410)  
Via this pin, the reference voltage for the IF AD con-  
verter is decoupled. It must be connected to AVSS  
pins with a 10µF and a 100nF capacitor in parallel.  
Traces must be kept short.  
VREF2 Reference Ground 2  
Reference analog ground. This pin must be connected  
separately to ground (AHVSS). VREF2 serves as a  
clean ground and should be used as the reference for  
analog connections to the loudspeaker outputs.  
MONO_IN Mono Input (Fig. 48)  
The analog mono input signal is fed to this pin. Analog  
input connection must be AC coupled.  
DACM_R/L Loudspeaker Outputs (Fig. 415)  
Output of the loudspeaker signal. A 1nF capacitor to  
AHVSS must be connected to these pins. The DC off-  
set on these pins depends on the selected volume.  
AVSS* Ground for Analog Power Supply Voltage  
Ground connection for the analog IF input circuitry of  
the MSP.  
VREF1 Reference Ground 1  
AVSUP* Analog Power Supply Voltage  
Power is supplied via this pin for the analog IF input cir-  
cuitry of the MSP. This pin must be connected to the  
+5 V supply.  
Reference analog ground. This pin must be connected  
separately to ground (AHVSS). VREF1 serves as a  
clean ground and should be used as the reference for  
analog connections to the SCART output.  
ANA_IN1+ IF Input 1 (Fig. 410)  
SC1_OUT_R/L SCART1 Outputs (Fig. 416)  
Output of the SCART1 signal. Connections to these  
pins must use a 100 ohm series resistor and are  
intended to be AC coupled.  
The analog sound if signal is supplied to this pin.  
Inputs must be AC coupled. This pin is designed as  
symmetrical input: ANA_IN1+ is internally connected  
to one input of a symmetrical op amp, ANA_INto the  
other.  
AHVSUP* Analog Power Supply High Voltage  
Power is supplied via this pin for the analog circuitry of  
the MSP (except IF input). This pin must be connected  
to the +8 V supply.  
ANA_INIF Common (Fig. 410)  
This pin serves as a common reference for ANA_IN1+  
input.  
TESTEN Test Enable Pin (Fig. 46)  
This pin enables factory test modes. For normal opera-  
tion it must be connected to ground.  
36  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
XTAL_IN, XTAL_OUT Crystal Input and Output Pins  
(Fig. 414)  
These pins are connected to an 18.432 MHz crystal  
oscillator which is digitally tuned by integrated shunt  
capacitances. An external clock can be fed into  
XTAL_IN. External capacitors at each crystal pin to  
ground (AVSS) are required. It should be verified by  
layout, that no supply current for the digital circuitry is  
flowing through the ground connection point. To adjust  
capacitors see Crystal Recommendations on page 44.  
D_CTR_I/O_1/0 Digital Control Input/Output Pins  
(Fig. 413)  
General purpose input/output pins. Pin D_CTR_I/O_1  
can be used as an interrupt request pin to the control-  
ler.  
ADR_SEL I2C Bus Address Select (Fig. 411)  
This pin selects the device address for the MSP (see  
Table 31 on page 14).  
STANDBYQ Standby  
In normal operation, this pin must be high. If the  
MSP 34x7G is switched to (Standby-mode), the  
SCART switches maintain their position and function  
(see Section 2.6.2.on page 13).  
* Application Note:  
All ground pins should be connected to one low-resis-  
tive ground plane. All supply pins should be connected  
separately with short and low-resistive lines to the  
power supply. Decoupling capacitors from DVSUP to  
DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are  
recommended as closely as possible to these pins.  
Decoupling of DVSUP and DVSS is most important.  
We recommend using more than one capacitor. By  
choosing different values, the frequency range of  
active decoupling can be extended. In our application  
boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF. The  
capacitor with the lowest value should be placed near-  
est to the DVSUP and DVSS pins.  
Micronas  
37  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.4. Pin Configurations  
NC  
TP  
NC  
1
2
3
4
5
6
7
8
9
52 XTAL_OUT  
51 XTAL_IN  
50 TESTEN  
49 NC  
VREF1  
SC1_OUT_R  
SC1_OUT_L  
NC  
DACM_L  
DACM_R  
VREF2  
NC  
D_CTR_I/O_1  
D_CTR_I/O_0  
ADR_SEL  
STANDBYQ  
I2C_CL  
48 ANA_IN−  
47 ANA_IN1+  
46 AVSUP  
45 AVSS  
AHVSUP  
NC  
33 32 31 30 29 28 27 26 25 24 23  
I2C_DA  
CAPL_M 34  
AHVSS 35  
AGNDC 36  
NC 37  
22 RESETQ  
21 TP  
TP  
44 MONO_IN  
43 VREFTOP  
42 SC1_IN_R  
41 SC1_IN_L  
40 NC  
TP 10  
TP 11  
20 DVSS  
19 DVSUP  
18 TP_CO  
17 TP  
TP 12  
NC 38  
TP 13  
NC 39  
MSP 34x7G  
TP 14  
39 NC  
SC1_IN_L 40  
SC1_IN_R 41  
VREFTOP 42  
MONO_IN 43  
AVSS 44  
16 TP  
TP_CO 15  
DVSUP 16  
DVSS 17  
TP 18  
38 NC  
15 TP  
37 NC  
14 TP  
36 AGNDC  
35 AHVSS  
34 CAPL_M  
33 AHVSUP  
32 NC  
13 I2C_DA  
12 I2C_CL  
NC 19  
1
2
3
4
5
6
7
8
9
10 11  
RESETQ 20  
NC 21  
AVSUP  
STANDBYQ  
NC 22  
31 SC1_OUT_L  
30 SC1_OUT_R  
29 VREF1  
28 NC  
ANA_IN1+  
ANA_IN−  
TESTEN  
XTAL_IN  
ADR_SEL  
D_CTR_I/O0  
D_CTR_I/O1  
VERF2 23  
DACM_R 24  
DACM_L 25  
NC 26  
TP  
27 NC  
XTAL_OUT  
Fig. 43: PSDIP52 package  
Fig. 44: PMQFP44 package  
38  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4.5. Pin Circuits  
ANA_IN1+  
>300 k  
A
D
DVSS  
ANA_IN1−  
Fig. 45: Input Pin: RESETQ  
VREFTOP  
Fig. 410: Input Pins:  
VREFTOP, ANA_IN1+, ANA_IN−  
AVSUP  
200 k  
DVSUP  
Fig. 46: Input Pin TESTEN  
23 k  
23 k  
24 k  
3.75 V  
GND  
ADR_SEL  
Fig. 411: Input Pin: ADR_SEL  
Fig. 47: Input Pin: MONO_IN  
40 k  
3.75 V  
Fig. 48: Input Pins: SC1_IN_L/R  
Fig. 49: Input Pin: STANDBYQ  
Micronas  
39  
MSP 34x7G  
PRELIMINARY DATA SHEET  
AHVSUP  
0...1.2 mA  
N
GND  
Fig. 412: Input/Output Pins: I2C_CL, I2C_DA  
3.3 k  
Fig. 415: Output Pins: DACM_R/L  
DVSUP  
P
26 pF  
120 k  
N
GND  
Fig. 413: Input/Output Pins:  
D_CTR_I/O_1, D_CTR_I/O_0  
300  
3.75 V  
Fig. 416: Output Pins: SC1_OUT_R/L  
P
500 k  
DVSUP  
P
330 pF  
N
N
330 pF  
GND  
Fig. 414: Output/Input Pins: XTAL_IN, XTAL_OUT  
Fig. 417: Output Pin: TP_CO  
0...2 V  
Fig. 418: Capacitor Pin: CAPL_M  
125 k  
3.75 V  
Fig. 419: AGNDC  
40  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4.6. Electrical Characteristics  
4.6.1. Absolute Maximum Ratings  
Symbol  
TA  
Parameter  
Pin Name  
Min.  
0
Max.  
Unit  
°C  
°C  
V
Ambient Operating Temperature  
Storage Temperature  
First Supply Voltage  
Second Supply Voltage  
Third Supply Voltage  
70  
TS  
40  
0.3  
0.3  
0.3  
0.5  
125  
9.0  
6.0  
6.0  
0.5  
VSUP1  
VSUP2  
VSUP3  
dVSUP23  
AHVSUP  
DVSUP  
AVSUP  
V
V
Voltage between AVSUP  
and DVSUP  
AVSUP,  
DVSUP  
V
PTOT  
Package Power Dissipation  
PSDIP52  
PMQFP44  
AHVSUP,  
DVSUP,  
AVSUP  
1200  
960  
mW  
mW  
VIdig  
IIdig  
Input Voltage, all Digital Inputs  
Input Current, all Digital Pins  
Input Voltage, all Analog Inputs  
0.3  
20  
VSUP2+0.3  
+20  
V
mA1)  
V
VIana  
SC1_IN_s,2)  
MONO_IN  
0.3  
VSUP1+0.3  
IIana  
Input Current, all Analog Inputs  
SC1_IN_s,2)  
MONO_IN  
5  
+5  
mA1)  
3) 4)  
3) 4)  
IOana  
IOana  
Output Current, all SCART Outputs SC1_OUT_s2)  
,
,
3)  
3)  
3)  
3)  
Output Current, all Analog Outputs  
except SCART Outputs  
DACM_s2)  
ICana  
Output Current, other pins  
connected to capacitors  
CAPL_M,  
AGNDC  
1)  
positive value means current flowing into the circuit  
smeans Lor R”  
The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground.  
Total chip power dissipation must not exceed absolute maximum rating.  
2)  
3)  
4)  
Stresses beyond those listed in the Absolute Maximum Ratingsmay cause permanent damage to the device. This  
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in  
the Recommended Operating Conditions/Characteristicsof this specification is not implied. Exposure to absolute  
maximum ratings conditions for extended periods may affect device reliability.  
Micronas  
41  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.6.2. Recommended Operating Conditions  
at TA = 0 to 70 °C  
4.6.2.1. General Recommended Operating Conditions  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
VSUP1  
First Supply Voltage  
(AHVSUP = 8 V)  
AHVSUP  
7.6  
8.0  
8.7  
V
First Supply Voltage  
(AHVSUP = 5V)  
4.75  
5.0  
5.25  
V
VSUP2  
VSUP3  
tSTBYQ1  
Second Supply Voltage  
Third Supply Voltage  
DVSUP  
AVSUP  
4.75  
4.75  
1
5.0  
5.0  
5.25  
5.25  
V
V
STANDBYQ Setup Time before  
Turn-off of Second Supply Voltage  
STANDBYQ,  
DVSUP  
µs  
4.6.2.2. Analog Input and Output Recommendations  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
3.3  
Max.  
Unit  
µF  
CAGNDC  
AGNDC-Filter-Capacitor  
Ceramic Capacitor in Parallel  
AGNDC  
20%  
20%  
20%  
100  
330  
nF  
CinSC  
DC-Decoupling Capacitor in front of SC1_IN_s1)  
SCART Inputs  
nF  
VinSC  
VinMONO  
RLSC  
SCART Input Level  
2.0  
2.0  
VRMS  
VRMS  
kΩ  
Input Level, Mono Input  
SCART Load Resistance  
SCART Load Capacitance  
Main Volume Capacitor  
Main Filter Capacitor  
MONO_IN  
SC1_OUT_s1)  
10  
CLSC  
6.0  
nF  
CVMA  
CAPL_M  
10  
1
µF  
CFMA  
DACM_s1)  
10%  
+10%  
nF  
1)  
smeans Lor R”  
42  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4.6.2.3. Recommendations for Analog Sound IF Input Signal  
Symbol  
Parameter  
Pin Name  
Min.  
20%  
20%  
0
Typ.  
10  
Max.  
Unit  
µF  
CVREFTOP  
VREFTOP-Filter-Capacitor  
Ceramic Capacitor in Parallel  
VREFTOP  
100  
nF  
FIF_FMTV  
Analog Input Frequency Range  
for TV applications  
ANA_IN1+,  
ANA_IN−  
9
MHz  
FIF_FMRADIO  
Analog Input Frequency for  
FM-Radio Applications  
10.7  
MHz  
VIF_FM  
VIF_AM  
RFMNI  
Analog Input Range FM/NICAM  
Analog Input Range AM/NICAM  
0.1  
0.1  
0.8  
3
Vpp  
Vpp  
0.45  
0.8  
Ratio: NICAM Carrier/FM Carrier  
(unmodulated carriers)  
BG:  
I:  
20  
23  
7  
10  
0
0
dB  
dB  
RAMNI  
Ratio: NICAM Carrier/AM Carrier  
(unmodulated carriers)  
25  
11  
0
dB  
RFM  
Ratio: FM-Main/FM-Sub Satellite  
7
7
dB  
dB  
RFM1/FM2  
Ratio: FM1/FM2  
German FM-System  
RFC  
RFV  
Ratio: Main FM Carrier/  
Color Carrier  
15  
15  
dB  
dB  
Ratio: Main FM Carrier/  
Luma Components  
PRIF  
Passband Ripple  
±2  
dB  
dB  
SUPHF  
Suppression of Spectrum  
15  
above 9.0 MHz (not for FM Radio)  
FMMAX  
Maximum FM-Deviation (approx.)  
normal mode  
±180  
±360  
±540  
kHz  
kHz  
kHz  
HDEV2: high deviation mode  
HDEV3: very high deviation mode  
Micronas  
43  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.6.2.4. Crystal Recommendations  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
General Crystal Recommendations  
fP  
Crystal Parallel Resonance Fre-  
18.432  
MHz  
quency at 12 pF Load Capacitance  
RR  
C0  
CL  
Crystal Series Resistance  
8
25  
Crystal Shunt (Parallel) Capacitance  
External Load Capacitance1)  
6.2  
7.0  
pF  
XTAL_IN,  
XTAL_OUT  
PSDIP  
PMQFP  
approx. 1.5  
approx. 3.3  
pF  
pF  
Crystal Recommendations for FM / NICAM Applications  
fTOL  
Accuracy of Adjustment  
30  
30  
+30  
+30  
ppm  
ppm  
DTEM  
Frequency Variation  
versus Temperature  
C1  
Motional (Dynamic) Capacitance  
15  
fF  
18.4305  
18.4335  
fCL  
Required Open Loop Clock  
MHz  
Frequency (Tamb = 25 °C)  
1) External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-  
quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the  
accurate capacitor value should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are  
figures based on experience and should serve as start value.  
To adjust the capacitor value, reset the MSP and transfer only the following I2C-protocol:  
<80 10 00 20 00 60>.  
Measure the frequency at pin TP_CO. Measurement at XTAL_IN/OUT pins is not possible. Change the capaci-  
tor value until the frequency matches 18.432/3 = 6.144 MHz as closely as possible. The higher the capacity, the  
lower the resulting clock frequency.  
Note: To minimize adjustment tolerances for all MSP-generations, it is strongly recommended to use the so-  
called MSP-XTAL-REF ICs (available in all packages) for the capacitor adjustment. Since all MSP-XTAL-REF ICs  
do have an AUD_CL_OUT-pin with the 18.432 MHz signal, this pin should be used for the capacitor adjustment  
instead of the TP_CO-pin. After the reset, no I2C-protocol should be transmitted. The AUD_CL_OUT-signal is  
available at the following pins:  
PLCC68  
PSDIP64  
PSDIP52  
PQFP80  
PLQFP64  
PMQFP442)  
pin 18  
pin 1  
pin 2  
pin 74  
pin 57  
pin 8  
2) For the MSP-XTAL-REF IC, the PMQFP44 pin functionality of the D_CTR_I/O1-pin has been changed to  
the Audio_Clock_Out signal. If D_CTR_I/O1 is used in the customer application, this pin must be left open for  
the adjustment procedure.  
44  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Crystal Recommendations for all analog FM/AM Applications  
fTOL  
Accuracy of Adjustment  
100  
50  
+100  
+50  
ppm  
ppm  
DTEM  
Frequency Variation  
versus Temperature  
fCL  
Required Open Loop Clock  
18.429  
18.435 MHz  
Frequency (Tamb = 25 °C)  
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF)  
VXCA  
External Clock Amplitude  
XTAL_IN  
0.7  
Vpp  
Micronas  
45  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.6.3. Characteristics  
at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values  
at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values,  
TJ = Junction Temperature  
MAIN (M) = Loudspeaker Channel  
4.6.3.1. General Characteristics  
Symbol  
Supply  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
I
First Supply Current (active)  
(AHVSUP = 8 V)  
AHVSUP  
14  
10  
22  
16  
mA  
mA  
Volume Main = 0 dB  
Volume Main = 30 dB  
SUP1A  
First Supply Current (active)  
(AHVSUP = 5 V)  
11  
8
16  
11  
mA  
mA  
Volume Main = 0 dB  
Volume Main = 30 dB  
I
I
I
Second Supply Current (active)  
Third Supply Current (active)  
DVSUP  
AVSUP  
AHVSUP  
55  
30  
5.6  
70  
38  
7.7  
mA  
mA  
mA  
SUP2A  
SUP3A  
SUP1S  
First Supply Current  
(AHVSUP = 8 V)  
STANDBYQ = low  
STANDBYQ = low  
First Supply Current  
(AHVSUP = 5 V)  
3.7  
5.1  
mA  
Clock  
f
Clock Input Frequency  
Clock High to Low Ratio  
XTAL_IN  
18.432  
MHz  
%
CLOCK  
D
45  
55  
50  
CLOCK  
JITTER  
t
Clock Jitter (verification not  
provided in production test)  
ps  
V
DC-Voltage Oscillator  
2.5  
0.4  
V
xtalDC  
t
Oscillator Startup Time at  
XTAL_IN,  
2
ms  
Startup  
VDD Slew-rate of 1 V/1 µs  
XTAL_OUT  
46  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4.6.3.2. Digital Inputs, Digital Outputs  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
Digital Input Levels  
V
V
Digital Input Low Voltage  
Digital Input High Voltage  
Input Impedance  
STANDBYQ  
0.2  
V
V
DIGIL  
DIGIH  
DIGI  
SUP2  
0.5  
SUP2  
Z
5
1
pF  
I
Digital Input Leakage Current  
1  
µA  
0 V < U  
< DVSUP  
INPUT  
DLEAK  
D_CTR_I/O_0/1: tri-state  
V
V
Digital Input Low Voltage  
ADR_SEL  
0.2  
V
V
DIGIL  
SUP2  
Digital Input High Voltage  
Input Current Address Select Pin  
0.8  
DIGIH  
SUP2  
I
500  
220  
µA  
µA  
pF  
µA  
U
U
= DVSS  
ADRSEL  
ADR_SEL  
220  
500  
5
= DVSUP  
ADR_SEL  
Z
Input Capacitance  
Input Low Current  
TESTEN  
TESTEN  
I
30  
U
= AVSS  
TESTEN  
TESTEN  
Digital Output Levels  
V
Digital Output Low Voltage  
Digital Output High Voltage  
D_CTR_I/O_0  
D_CTR_I/O_1  
0.4  
V
V
IDDCTR = 1 mA  
DCTROL  
DCTROH  
V
V
IDDCTR = 1 mA  
SUP2  
0.3  
Micronas  
47  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.6.3.3. Reset Input and Power-Up  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
RESETQ Input Levels  
V
V
Reset High-Low Transition Voltage RESETQ  
Reset Low-High Transition Voltage  
Input Capacitance  
0.3  
0.4  
0.55  
5
V
V
RHL  
RLH  
RES  
RES  
SUP2  
0.45  
SUP2  
Z
pF  
I
Input High Current  
20  
µA  
U
= DVSUP  
RESETQ  
DVSUP  
AVSUP  
4.5 V  
t/ms  
RESETQ  
Note: The reset should  
not reach high level  
before the oscillator has  
started. This requires a  
reset delay of >2 ms  
Low-to-High  
Threshold  
0.45×DVSUP  
High-to-Low  
Threshold  
0.3...0.4×DVSUP  
0.45 x DVSUP means  
2.25 Volt with  
DVSUP = 5.0 V  
t/ms  
Reset Delay  
>2 ms  
Internal  
Reset  
High  
Low  
t/ms  
Fig. 420: Power-up sequence  
48  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4.6.3.4. I2C Bus Characteristics  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
2
V
V
I C-Bus Input Low Voltage  
I2C_CL,  
I2C_DA  
0.3  
V
I2CIL  
I2CIH  
I2C1  
SUP2  
SUP2  
2
I C-Bus Input High Voltage  
0.6  
120  
120  
55  
V
2
t
t
t
I C Start Condition Setup Time  
ns  
ns  
ns  
2
I C Stop Condition Setup Time  
I2C2  
2
I C-Data Setup Time  
I2C5  
before Rising Edge of Clock  
2
t
I C-Data Hold Time  
55  
ns  
I2C6  
after Falling Edge of Clock  
2
t
t
f
I C-Clock Low Pulse Time  
I2C_CL  
500  
500  
ns  
I2C3  
I2C4  
I2C  
2
I C-Clock High Pulse Time  
ns  
2
I C-BUS Frequency  
1.0  
0.4  
1.0  
MHz  
V
2
V
I C-Data Output Low Voltage  
I2C_CL,  
I2C_DA  
I
= 3 mA  
I2COL  
I2COL  
2
I
t
t
I C-Data Output  
µA  
V
= 5 V  
I2COH  
I2COH  
High Leakage Current  
2
I C-Data Output Hold Time  
15  
ns  
ns  
I2COL1  
I2COL2  
after Falling Edge of Clock  
2
I C-Data Output Setup Time  
100  
f
= 1 MHz  
I2C  
before Rising Edge of Clock  
1/FI2C  
TI2C4  
TI2C3  
I2C_CL  
TI2C1  
TI2C5  
TI2C6  
TI2C2  
I2C_DA as input  
I2C_DA as output  
TI2COL2  
TI2COL1  
Fig. 421: I2C bus timing diagram  
Micronas  
49  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.6.3.5. Analog Baseband Inputs and Outputs, AGNDC  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
Analog Ground  
V
AGNDC Open Circuit Voltage  
(AHVSUP = 8 V)  
AGNDC  
3.77  
2.51  
125  
83  
V
R
10 MΩ  
load  
AGNDC0  
AGNDC Open Circuit Voltage  
(AHVSUP = 5 V)  
V
R
AGNDC Output Resistance  
(AHVSUP = 8 V)  
70  
47  
180  
120  
kΩ  
kΩ  
3 V V  
4 V  
outAGN  
AGNDC  
AGNDC Output Resistance  
(AHVSUP = 5 V)  
Analog Input Resistance  
1)  
R
R
SCART Input Resistance  
SC1_IN_s  
25  
15  
40  
24  
58  
35  
kΩ  
kΩ  
f
f
= 1 kHz, I = 0.05 mA  
= 1 kHz, I = 0.1 mA  
inSC  
signal  
from T = 0 to 70 °C  
A
MONO Input Resistance  
MONO_IN  
inMONO  
signal  
from T = 0 to 70 °C  
A
Audio Analog-to-Digital-Converter  
1)  
V
Analog Input Clipping Level for  
Analog-to-Digital-Conversion  
(AHVSUP = 8 V)  
SC1_IN_s,  
MONO_IN  
2.00  
1.13  
2.25  
1.51  
V
V
f = 1 kHz  
signal  
AICL  
RMS  
RMS  
Analog Input Clipping Level for  
Analog-to-Digital-Conversion  
(AHVSUP = 5 V)  
SCART Output  
1)  
R
SCART Output Resistance  
SC1_OUT_s  
f
= 1 kHz, I = 0.1 mA  
outSC  
signal  
200  
200  
330  
460  
500  
T = 27 °C  
j
T = 0 to 70 °C  
A
dV  
Deviation of DC-Level at SCART  
Output from AGNDC Voltage  
70  
1.0  
0.5  
1.8  
+70  
+0.5  
+0.5  
2.0  
mV  
dB  
dB  
OUTSC  
1)  
A
Gain from Analog Input  
to SCART Output  
SCn_IN_s,  
MONO_IN  
f
= 1 kHz  
SCtoSC  
signal  
1)  
1)  
SC1_OUT_s  
f
Frequency Response from Analog  
Input to SCART Output  
with resp. to 1 kHz  
Bandwidth: 0 to 20000 Hz  
rSCtoSC  
V
Signal Level at SCART Output  
(AHVSUP = 8 V)  
SC1_OUT_s  
1.9  
V
V
f
= 1 kHz  
outSC  
RMS  
RMS  
signal  
Volume 0 dB  
Full Scale input from I S  
2
Signal Level at SCART Output  
(AHVSUP = 5V)  
1.17  
1.27  
1.37  
1)  
smeans Lor R”  
50  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
Main Output  
1
R
Main Output Resistance  
DACM_s )  
f
= 1 kHz, I = 0.1 mA,  
signal  
outMA  
2.1  
2.1  
3.3  
4.6  
5.0  
kΩ  
kΩ  
T = 27 °C  
j
T
= 0 to 70 °C  
A
V
DC-Level at Main-Output  
(AHVSUP = 8 V)  
1.80  
1.12  
1.23  
0.76  
2.04  
61  
2.28  
1.60  
1.51  
1.04  
V
mV  
Volume Main = 0 dB  
Volume Main = 30 dB  
outDCMA  
DC-Level at Main-Output  
(AHVSUP = 5 V)  
1.36  
40  
V
mV  
Volume Main = 0 dB  
Volume Main = 30 dB  
V
Signal Level at Main-Output  
(AHVSUP = 8 V)  
1.37  
0.90  
V
V
f
= 1 kHz, full scale,  
signal  
outMA  
RMS  
RMS  
Volume Main = 0 dB  
Signal Level at Main-Output  
(AHVSUP = 5 V)  
1)  
smeans Lor R”  
4.6.3.6. Sound IF Input  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
R
Input Impedance  
ANA_IN1+,  
ANA_IN−  
1.5  
6.8  
2
9.1  
2.5  
11.4  
kΩ  
kΩ  
Gain AGC = 20 dB  
Gain AGC = 3 dB  
IFIN  
DC  
DC  
DC Voltage at VREFTOP  
DC Voltage on IF Inputs  
VREFTOP  
2.4  
1.3  
2.65  
1.5  
2.75  
1.7  
V
V
VREFTOP  
ANA_IN  
ANA_IN1+,  
ANA_IN−  
XTALK  
Crosstalk Attenuation  
3 dB Bandwidth  
ANA_IN1+,  
ANA_IN−  
40  
10  
dB  
IF  
f
= 1 MHz  
signal  
BW  
MHz  
dB  
IF  
Input Level = 2 dBr  
AGC  
AGC Step Width  
0.85  
4.6.3.7. Power Supply Rejection  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
PSRR: Rejection of Noise on AHVSUP at 1 kHz  
PSRR  
AGNDC  
AGNDC  
80  
70  
dB  
dB  
From Analog Input to  
SCART Output  
MONO_IN,  
SC1_IN_s  
SC1_OUT_s  
1)  
1)  
1)  
smeans Lor R”  
Micronas  
51  
MSP 34x7G  
PRELIMINARY DATA SHEET  
4.6.3.8. Analog Performance  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
Specifications for AHVSUP = 8 V  
SNR  
THD  
Signal-to-Noise Ratio  
from Analog Input to  
SCART Output  
MONO_IN,  
SC1_IN_s  
93  
96  
dB  
%
Input Level = 20 dB,  
1)  
f
= 1 kHz,  
sig  
unweighted  
20 Hz...20 kHz  
1)  
SC1_OUT_s  
Total Harmonic Distortion  
from Analog Input to  
SCART Output  
MONO_IN,  
SC1_IN_s  
0.01  
0.03  
Input Level = 3 dBr,  
f
= 1 kHz,  
sig  
unweighted  
20 Hz...20 kHz  
1)  
SC1_OUT_s  
Specifications for AHVSUP = 5 V  
SNR  
Signal-to-Noise Ratio  
from Analog Input to  
SCART Output  
MONO_IN,  
SC1_IN_s  
90  
93  
dB  
%
Input Level = 20 dB,  
1)  
f
= 1 kHz,  
sig  
unweighted  
20 Hz...20 kHz  
1)  
SC1_OUT_s  
THD  
Total Harmonic Distortion  
from Analog Input to  
SCART Output  
MONO_IN,  
SC1_IN_s  
0.1  
Input Level = 3 dBr,  
f
= 1 kHz,  
sig  
unweighted  
20 Hz...20 kHz  
1)  
SC1_OUT_s  
CROSSTALK Specifications for AHVSUP = 8 V and 5 V  
XTALK  
Crosstalk Attenuation  
Input Level = 3 dB,  
f
= 1 kHz, unused  
sig  
analog inputs connected to  
ground by Z < 1 kΩ  
between left and right channel within  
unweighted  
SCART Input/Output pair (LR, RL)  
20 Hz...20 kHz  
SC1_IN SC1_OUT  
80  
95  
dB  
dB  
between MONO Input and SCART Input  
unweighted  
20 Hz...20 kHz  
1)  
smeans Lor R”  
52  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
4.6.3.9. Sound Standard Dependent Characteristics  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
NICAM Characteristics (MSP Standard Code = 8)  
dV  
Tolerance of Output Voltage  
of NICAM Baseband Signal  
DACM_s,  
SC1_OUT_s  
1.5  
+1.5  
dB  
dB  
2.12 kHz, Modulator input  
level = 0 dBref  
NICAMOUT  
1)  
S/N  
S/N of NICAM Baseband Signal  
72  
NICAM: 6 dB, 1 kHz, RMS  
unweighted  
NICAM  
0 to 15 kHz, Vol = 9 dB  
NIC_Presc = 7F  
Output level 1 V  
DACM_s  
hex  
at  
RMS  
THD  
BER  
Total Harmonic Distortion + Noise  
of NICAM Baseband Signal  
0.1  
%
2.12 kHz, Modulator input  
level = 0 dBref  
NICAM  
NICAM  
7  
NICAM: Bit Error Rate  
1
10  
FM+NICAM, norm conditions  
fR  
NICAM Frequency Response,  
20...15000 Hz  
1.0  
+1.0  
dB  
Modulator input  
level = 12 dB dBref; RMS  
NICAM  
XTALK  
NICAM Crosstalk Attenuation (Dual)  
NICAM Channel Separation (Stereo)  
80  
80  
dB  
dB  
NICAM  
SEP  
NICAM  
FM Characteristics (MSP Standard Code = 3)  
dV  
Tolerance of Output Voltage  
of FM Demodulated Signal  
DACM_s,  
SC1_OUT_s  
1.5  
+1.5  
dB  
1 FM-carrier, 50 µs, 1 kHz,  
40 kHz deviation; RMS  
FMOUT  
1)  
S/N  
S/N of FM Demodulated Signal  
73  
dB  
%
1 FM-carrier 5.5 MHz, 50 µs,  
1 kHz, 40 kHz deviation;  
RMS, unweighted  
0 to 15 kHz (for S/N);  
full input range, FM-Pres-  
FM  
THD  
Total Harmonic Distortion + Noise  
of FM Demodulated Signal  
0.1  
FM  
cale = 46 , Vol = 0 dB  
hex  
Output Level 1 V  
at  
RMS  
DACM_s  
fR  
FM Frequency Responses,  
20...15000 Hz  
1.0  
80  
+1.0  
dB  
dB  
dB  
1 FM-carrier 5.5 MHz,  
50 µs, Modulator input  
level = 14.6 dBref; RMS  
FM  
XTALK  
FM Crosstalk Attenuation (Dual)  
FM Channel Separation (Stereo)  
2 FM-carriers 5.5/5.74 MHz,  
50 µs, 1 kHz, 40 kHz  
deviation; Bandpass 1 kHz  
FM  
SEP  
50  
2 FM-carriers 5.5/5.74 MHz,  
50 µs, 1 kHz, 40 kHz  
deviation; RMS  
FM  
AM Characteristics (MSP Standard Code = 9)  
S/N  
S/N  
S/N of AM Demodulated Signal  
measurement condition: RMS/Flat  
DACM_s,  
SC1_OUT_s  
55  
45  
dB  
dB  
%
SIF level: 0.10.8 V  
pp  
AM(1)  
AM(2)  
1)  
AM-carrier 54% at 6.5 MHz  
Vol = 0 dB, FM/AM  
prescaler set for  
S/N of AM Demodulated Signal  
measurement condition: QP/CCIR  
output = 0.5 V  
at  
RMS  
Loudspeaker out;  
Standard Code = 09  
no video/chroma  
components  
THD  
Total Harmonic Distortion + Noise  
of AM Demodulated Signal  
0.6  
hex  
AM  
fR  
AM Frequency Response  
50...12000 Hz  
2.5  
+1.0  
dB  
AM  
1) smeans Lor R”  
Micronas  
53  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
BTSC Characteristics (MSP Standard Code = 20 , 21  
)
hex  
hex  
S/N  
S/N of BTSC Stereo Signal  
S/N of BTSC-SAP Signal  
DACM_s,  
SC1_OUT_s  
68  
57  
dB  
dB  
1 kHz L or R or SAP, 100%  
modulation, 75 µs deempha-  
sis, RMS unweighted 0 to 15  
kHz  
BTSC  
1)  
THD  
THD+N of BTSC Stereo Signal  
THD+N of BTSC SAP Signal  
0.1  
0.5  
%
%
1 kHz L or R or SAP, 100%  
75 µs EIM , DBX NR or  
MNR, RMS unweighted  
0 to 15 kHz  
BTSC  
2)  
fR  
Frequency Response of BTSC Ste-  
reo, 50 Hz...12 kHz  
1.0  
1.0  
1.0  
1.0  
dB  
dB  
L or R or SAP,  
1%...66% EIM , DBX NR  
DBX  
2)  
Frequency Response of BTSC-  
SAP, 50 Hz...9 kHz  
2)  
fR  
Frequency Response of BTSC Ste-  
reo, 50 Hz...12 kHz  
2.0  
2.0  
2.0  
2.0  
dB  
dB  
L or R 5%...66% EIM , MNR  
MNR  
Frequency Response of BTSC-  
SAP, 50 Hz...9 kHz  
SAP, white noise, 10% Modu-  
lation, MNR  
XTALK  
Stereo SAP  
SAP Stereo  
76  
80  
dB  
dB  
1 kHz L or R or SAP, 100%  
modulation, 75 µs deempha-  
sis, Bandpass 1 kHz  
BTSC  
2)  
SEP  
SEP  
Stereo Separation DBX NR  
50 Hz...10 kHz  
50 Hz...12 kHz  
L or R 1%...66% EIM , DBX  
NR  
DBX  
35  
30  
dB  
dB  
Stereo Separation MNR  
30  
dB  
L = 300 Hz, R = 3.1 kHz  
14% Modulation, MNR  
MNR  
FM  
Pilot deviation threshold  
Stereo off on  
ANA_IN1+  
4.5 MHz carrier modulated  
pil  
with f = 15.734 kHz  
h
3.2  
1.2  
3.5  
1.5  
kHz  
kHz  
SIF level = 100 mV  
pp  
indication: STATUS Bit[6]  
Stereo on off  
f
Pilot Frequency Range  
15.563  
15.843 kHz  
standard BTSC stereo signal,  
sound carrier only  
Pilot  
1)  
2)  
smeans Lor R”  
EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,  
when the DBX encoding process is replaced by a 75-µs preemphasis network.  
54  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Symbol  
Parameter  
Pin Name  
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
BTSC Characteristics (MSP Standard Code = 20 , 21  
)
hex  
hex  
with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components)  
S/N  
S/N of BTSC Stereo Signal  
S/N of BTSC-SAP Signal  
DACM_s,  
SC1_OUT_s  
64  
55  
dB  
dB  
1 kHz L or R or SAP, 100%  
modulation, 75 µs deempha-  
sis, RMS unweighted 0 to 15  
kHz  
BTSC  
1)  
THD  
THD+N of BTSC Stereo Signal  
THD+N of BTSC SAP Signal  
0.15  
0.8  
%
%
1 kHz L or R or SAP, 100%  
75 µs EIM , DBX NR or  
MNR, RMS unweighted  
0 to 15 kHz  
BTSC  
2)  
fR  
fR  
Frequency Response of BTSC Ste-  
reo, 50 Hz...12 kHz  
1.0  
1.0  
1.0  
1.0  
dB  
dB  
L or R or SAP,  
1%...66% EIM , DBX NR  
DBX  
2)  
Frequency Response of BTSC-  
SAP, 50 Hz...9 kHz  
2)  
Frequency Response of BTSC Ste-  
reo, 50 Hz...12 kHz  
2.0  
2.0  
2.0  
2.0  
dB  
dB  
L or R 5%...66% EIM , MNR  
MNR  
Frequency Response of BTSC-  
SAP, 50 Hz...9 kHz  
SAP, white noise, 10% Modu-  
lation, MNR  
XTALK  
Stereo SAP  
SAP Stereo  
75  
75  
dB  
dB  
1 kHz L or R or SAP, 100%  
modulation, 75 µs deempha-  
sis, Bandpass 1 kHz  
BTSC  
2)  
SEP  
Stereo Separation DBX NR  
50 Hz...10 kHz  
50 Hz...12 kHz  
L or R 1%...66% EIM , DBX  
NR  
DBX  
35  
30  
dB  
dB  
SEP  
Stereo Separation MNR  
30  
dB  
L = 300 Hz, R = 3.1 kHz  
14% Modulation, MNR  
MNR  
1)  
smeans Lor R”  
2)  
EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,  
when the DBX encoding process is replaced by a 75-µs preemphasis network.  
Micronas  
55  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Symbol  
Parameter  
Pin Name  
)
Min.  
Typ.  
Max.  
Unit  
Test Conditions  
EIA-J Characteristics (MSP Standard Code = 30  
hex  
S/N  
S/N of EIA-J Stereo Signal  
S/N of EIA-J Sub-Channel  
DACM_s,  
SC1_OUT_s  
60  
60  
dB  
dB  
1 kHz L or R,  
EIAJ  
1)  
100% modulation,  
75 µs deemphasis,  
RMS unweighted  
0 to 15 kHz  
THD  
THD+N of EIA-J Stereo Signal  
THD+N of EIA-J Sub-Channel  
0.2  
0.3  
%
%
EIAJ  
fR  
Frequency Response of EIA-J  
Stereo, 50 Hz...12 kHz  
1.0  
1.0  
1.0  
1.0  
dB  
dB  
100% modulation,  
75 µs deemphasis  
EIAJ  
Frequency Response of EIA-J  
Sub-Channel, 50 Hz...12 kHz  
XTALK  
Main SUB  
Sub MAIN  
66  
80  
dB  
dB  
1 kHz L or R, 100%  
modulation, 75 µs  
deemphasis,  
EIAJ  
Bandpass 1 kHz  
SEP  
Stereo Separation  
50 Hz...5 kHz  
50 Hz...10 kHz  
EIA-J Stereo Signal, L or R  
100% modulation  
EIAJ  
35  
28  
dB  
dB  
FM-Radio Characteristics (MSP Standard Code = 40  
)
hex  
S/N  
S/N of FM-Radio Stereo Signal  
DACM_s,  
SC1_OUT_s  
68  
dB  
%
1 kHz L or R, 100%  
modulation, 75 µs  
deemphasis, RMS  
unweighted  
UKW  
1)  
THD  
THD+N of FM-Radio Stereo Signal  
0.1  
UKW  
0 to 15 kHz  
fR  
Frequency Response of  
FM-Radio Stereo  
50 Hz...15 kHz  
L or R, 1%...100%  
modulation, 75 µs  
deemphasis  
UKW  
1.0  
45  
+1.0  
dB  
dB  
SEP  
Stereo Separation 50 Hz...15 kHz  
Pilot Frequency Range  
UKW  
f
ANA_IN1+  
18.844  
19.125 kHz  
standard FM radio  
stereo signal  
Pilot  
1)  
smeans Lor R”  
56  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
5. Appendix A: Overview of TV Sound Standards  
5.1. NICAM 728  
Table 51: Summary of NICAM 728 sound modulation parameters  
Specification  
I
B/G  
L
D/K  
5.85 MHz  
Carrier frequency of  
digital sound  
6.552 MHz  
5.85 MHz  
5.85 MHz  
Transmission rate  
Type of modulation  
728 kbit/s  
Differentially encoded quadrature phase shift keying (DQPSK)  
by means of Roll-off filters  
Spectrum shaping  
Roll-off factor  
1.0  
0.4  
0.4  
6.5 MHz AM mono  
0.4  
Carrier frequency of  
analog sound component  
6.0 MHz  
5.5 MHz  
6.5 MHz  
FM mono  
FM mono  
FM mono  
terrestrial  
10 dB  
cable  
Power ratio between  
vision carrier and  
analog sound carrier  
10 dB  
10 dB  
13 dB  
7 dB  
16 dB  
13 dB  
Power ratio between  
analog and modulated  
digital sound carrier  
17 dB  
11 dB  
China/  
Hungary  
Poland  
7 dB  
12 dB  
Table 52: Summary of NICAM 728 sound coding characteristics  
Characteristics  
Values  
32 kHz  
2
Audio sampling frequency  
Number of channels  
Initial resolution  
14 bit/sample  
Companding characteristics  
Coding for compressed samples  
Preemphasis  
near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks  
2s complement  
CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz)  
+12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)  
Audio overload level  
Micronas  
57  
MSP 34x7G  
PRELIMINARY DATA SHEET  
5.2. A2 Systems  
Table 53: Key parameters for A2 Systems of Standards B/G, D/K, and M  
Characteristics  
Sound Carrier FM1  
Sound Carrier FM2  
TV-Sound Standard  
Carrier frequency in MHz  
B/G  
D/K  
M
B/G  
D/K  
M
5.5  
6.5  
4.5  
5.7421875 6.2578125 4.724212  
6.7421875  
5.7421875  
Vision/sound power difference  
Sound bandwidth  
13 dB  
20 dB  
40 Hz to 15 kHz  
Preemphasis  
50 µs  
±2750 kHz  
75 µs  
50 µs  
75 µs  
Frequency deviation (nom/max)  
Transmission Modes  
±1725 kHz  
±2750 kHz  
±1525 kHz  
Mono transmission  
mono  
mono  
Stereo transmission  
(L+R)/2  
language A  
(L+R)/2  
R
(LR)/2  
Dual sound transmission  
Identification of Transmission Mode  
Pilot carrier frequency  
language B  
54.6875 kHz  
±2.5 kHz  
55.0699 kHz  
Max. deviation portion  
Type of modulation / modulation depth  
Modulation frequency  
AM / 50%  
mono: unmodulated  
stereo: 117.5 Hz  
dual: 274.1 Hz  
149.9 Hz  
276.0 Hz  
58  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
5.3. BTSC-Sound System  
Table 54: Key parameters for BTSC-Sound Systems  
Aural  
BTSC-MPX-Components  
Carrier  
(L+R)  
Pilot  
(LR)  
SAP  
Prof. Ch.  
Carrier frequency  
4.5 MHz  
Baseband  
fh  
2 fh  
5 fh  
6.5 fh  
(fhNTSC = 15.734 kHz)  
(fhPAL = 15.625 kHz)  
Sound bandwidth in kHz  
Preemphasis  
0.05 - 15  
75 µs  
0.05 - 15  
DBX  
0.05 - 12  
DBX  
0.05 - 3.4  
150 µs  
3 kHz  
Max. deviation to Aural Carrier  
73 kHz  
(total)  
25 kHz1)  
5 kHz  
50 kHz1)  
15 kHz  
Max. Freq. Deviation of Subcarrier  
Modulation Type  
10 kHz  
FM  
3 kHz  
FM  
AM  
1) Sum does not exceed 50 kHz due to interleaving effects  
5.4. Japanese FM Stereo System (EIA-J)  
Table 55: Key parameters for Japanese FM-Stereo Sound System EIA-J  
Aural  
Carrier  
FM  
EIA-J-MPX-Components  
(L+R)  
(LR)  
Identification  
Carrier frequency (fh = 15.734 kHz)  
Sound bandwidth  
4.5 MHz  
Baseband  
0.05 - 15 kHz  
75 µs  
2 fh  
3.5 fh  
0.05 - 15 kHz  
75 µs  
Preemphasis  
none  
2 kHz  
Max. deviation portion to Aural Carrier  
47 kHz  
25 kHz  
20 kHz  
Max. Freq. Deviation of Subcarrier  
Modulation Type  
10 kHz  
FM  
60%  
AM  
Transmitter-sided delay  
Mono transmission  
20 µs  
0 µs  
0 µs  
L+R  
unmodulated  
982.5 Hz  
922.5 Hz  
Stereo transmission  
Bilingual transmission  
L+R  
LR  
Language A  
Language B  
Micronas  
59  
MSP 34x7G  
PRELIMINARY DATA SHEET  
5.5. FM Satellite Sound  
Table 56: Key parameters for FM Satellite Sound  
Carrier Frequency  
Maximum  
FM Deviation  
Sound Mode  
Bandwidth  
Deemphasis  
6.5 MHz  
85 kHz  
50 kHz  
50 kHz  
50 kHz  
Mono  
15 kHz  
15 kHz  
15 kHz  
15 kHz  
50 µs  
7.02/7.20 MHz  
7.38/7.56 MHz  
7.74/7.92 MHz  
Mono/Stereo/Bilingual  
Mono/Stereo/Bilingual  
Mono/Stereo/Bilingual  
adaptive  
adaptive  
adaptive  
5.6. FM-Stereo Radio  
Table 57: Key parameters for FM-Stereo Radio Systems  
Aural  
FM-Radio-MPX-Components  
Carrier  
(L+R)  
Pilot  
(LR)  
2 fp  
RDS/ARI  
Carrier frequency (fp = 19 kHz)  
Sound bandwidth in kHz  
10.7 MHz  
Baseband  
0.05 - 15  
fp  
3 fh  
0.05 - 15  
Preemphasis:  
USA  
Europe  
75 µs  
50 µs  
75 µs  
50 µs  
Max. deviation to Aural Carrier  
75 kHz  
(100%)  
90%1)  
10%  
90%1)  
5%  
1) Sum does not exceed 90% due to interleaving effects.  
60  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
6. Appendix B: Manual/Compatibility Mode  
To adapt the modes of the STANDARD SELECT regis-  
ter to individual requirements and for reasons of com-  
patibility to the MSP 34x7D, the MSP 34x7G offers  
an Manual/Compatibility Mode, which provides sophis-  
ticated programming of the MSP 34x7G.  
Using the STANDARD SELECT register generally pro-  
vides  
a
more economic way to program the  
MSP 34x7G and will result in optimal behavior. There-  
fore, it is not recommend to use the Manual/Com-  
patibility mode. In those cases, where the  
MSP 34x7D is to be substituted by the MSP 34x7G,  
the tips given in Section 6.9. on page 75 have to be  
obeyed by the controller software.  
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode  
Table 61: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!  
Demodulator  
Write Registers  
Address MSP-  
Description  
Reset  
Mode  
Page  
(hex)  
Version  
AUTO_FM/AM  
00 21  
3417,  
3457  
1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of 00 00  
Automatic Switching between NICAM and FM/AM in case of bad NICAM  
reception  
63  
2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic  
Switching between NICAM and FM/AM in case of bad NICAM reception  
A2_Threshold  
CM_Threshold  
AD_CV  
00 22  
00 24  
00 BB  
00 83  
all  
all  
all  
A2 Stereo Identification Threshold  
00 19  
65  
65  
66  
68  
hex  
Carrier-Mute Threshold  
00 2A  
00 00  
hex  
SIF-input selection, configuration of AGC, and Carrier-Mute Function  
MODE_REG  
3417,  
3457  
Controlling of MSP-Demodulator and Interface options. As soon as this 00 00  
register is applied, the MSP 34x7G works in the MSP 34x7D compatibility  
mode.  
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only  
MSP 34x7D features are available; the use of MODUS and STATUS register  
is not allowed.  
The MSP 34x7G is reset to the normal mode by first programming the  
MODUS register followed by transmitting a valid standard code to the  
STANDARD SELECTION register.  
FIR1  
FIR2  
00 01  
00 05  
FIR1-filter coefficients channel 1 (6 8 bit)  
FIR2-filter coefficients channel 2 (6 8 bit), + 3 8 bit offset (total 72 bit)  
00 00  
00 00  
69  
69  
DCO1_LO  
DCO1_HI  
00 93  
00 9B  
Increment channel 1 Low Part  
Increment channel 1 High Part  
DCO2_LO  
DCO2_HI  
00 A3  
00 AB  
Increment channel 2 Low Part  
Increment channel 2 High Part  
Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are  
automatically updated when Automatic Sound Select (MODUS[0]=1) is on.  
Micronas  
61  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 62: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!  
Demodulator  
Address MSP-  
Description  
Page  
Read Registers  
(hex)  
00 23  
00 38  
00 3E  
00 57  
02 1F  
02 1E  
Version  
C_AD_BITS  
ADD_BITS  
CIB_BITS  
3417,  
3457  
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits  
NICAM: bit [10:3] of additional data bits  
NICAM: CIB1 and CIB2 control bits  
NICAM error rate, updated with 182 ms  
Not for customer use.  
71  
71  
71  
72  
72  
72  
ERROR_RATE  
PLL_CAPS  
AGC_GAIN  
Not for customer use.  
6.2. DSP Write and Read Registers for Manual/Compatibility Mode  
Table 63: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well  
Write Register  
Address Bits  
(hex)  
Operational Modes and Adjustable Range  
Reset  
Mode  
Page  
Volume SCART1 channel: Ctrl. mode  
FM Fixed Deemphasis  
FM Adaptive Deemphasis  
Identification Mode  
00 07  
00 0F  
[7:0]  
[15:8]  
[7:0]  
[7:0]  
[7:0]  
[Linear mode / logarithmic mode]  
[50 µs, 75 µs, J17, OFF]  
[OFF, WP1]  
00  
73  
73  
73  
74  
74  
hex  
50 µs  
OFF  
B/G  
00 15  
00 17  
[B/G, M]  
FM DC Notch  
[ON, OFF]  
ON  
Table 64: DSP Read Registers; Subaddress: 13hex, all registers are not writable  
Additional Read  
Registers  
Address Bits  
(hex)  
Output Range  
Page  
Stereo detection register for  
A2 Stereo Systems  
00 18  
[15:8]  
[80 ... 7F  
]
8 bit twos complement  
74  
hex  
hex  
DC level readout FM1/Ch2-L  
DC level readout FM2/Ch1-R  
00 1B  
00 1C  
[15:0]  
[15:0]  
[8000 ... 7FFF  
]
16 bit twos complement  
16 bit twos complement  
74  
74  
hex  
hex  
[8000 ... 7FFF  
]
hex  
hex  
62  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
6.3. Manual/Compatibility Mode:  
6.3.1.1. Function in Automatic Sound Select Mode  
Description of Demodulator Write Registers  
The Automatic Sound Select feature (MODUS[0]=1)  
includes the procedure mentioned above. By default, the  
internal ERROR_RATE threshold is set to 700dec. i.e.:  
6.3.1. Automatic Switching between NICAM and  
Analog Sound  
NICAM analog Sound if ERROR_RATE > 700  
analog Sound NICAM if ERROR_RATE < 700/2  
In case of bad NICAM reception or loss of the  
NICAM-carrier, the MSP 34x7G offers an Automatic  
Switching (fall back) to the analog sound (FM/AM-  
mono), without the necessity for the controller of reading  
and evaluating any parameters. If a proper NICAM sig-  
nal returns, switching back to this source is performed  
automatically as well. The feature evaluates the NICAM  
ERROR_RATE and switches, if necessary, all output  
channels which are assigned to the NICAM-source, to  
the analog source, and vice versa.  
The ERROR_RATE value of 700 corresponds to a  
BER of approximately 5.46*10-3 /s.  
Individual configuration of the threshold can be done  
using Table 65. We recommend to use the internal  
setting used by the standard selection.  
The optimum NICAM sound can be assigned to the  
MSP output channels by selecting one of the Stereo  
or A/B, Stereo or A, or Stereo or Bsource chan-  
nels  
An appropriate hysteresis algorithm avoids oscillating  
effects (see Fig. 61). STATUS[9] and C_AD_BITS[11]  
(Addr: 0023 hex) provide information about the actual  
NICAM-FM/AM-status.  
6.3.1.2. Function in Manual Mode  
Selected Sound  
NICAM  
If the manual mode (MODUS[0]=0) is required, the  
activation and configuration of the Automatic Switching  
feature has to be done as described in Table 66.  
Note, that the channel matrix of the corresponding out-  
put-channels must be set according to the  
NICAM-mode and need not to be changed in the FM/  
AM-fallback case.  
analog  
sound  
ERROR_RATE  
threshold/2  
threshold  
Example:  
Fig. 61: Hysteresis for Automatic Switching  
Required threshold = 500: bits[10:1] = 00 1111 1010  
Table 65: Coding of Automatic NICAM/Analog Sound Switching;  
Automatic Sound Select is on (MODUS[0] = 1)  
Mode  
Description  
AUTO_FM [11:0]  
ERROR_RATE- Source Select:  
Threshold/dec  
Addr. = 00 21  
Input at NICAM Path1)  
hex  
1
Automatic Switching with  
internal threshold  
bit[11:0] = 0  
700  
NICAM or FM/AM,  
depending on  
Default  
ERROR_RATE  
2
Automatic Switching with  
external threshold  
(Customizing of Automatic  
Sound Select)  
bit[11]  
bit[10:1] = 25...1000  
= threshold/2  
= 0  
set by customer;  
recommended  
range: 50...2000  
bit[0]  
= 1  
3
Forced Analog Mono  
bit[11]  
bit[10:1] = ignored  
bit[0] = 1  
= 1  
always FM/AM  
1)  
The NICAM path may be assigned to Stereo or A/B, Stereo or A, or Stereo or Bsource channels  
(see Table 22 on page 11).  
Micronas  
63  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 66: Coding of Automatic NICAM/Analog Sound Switching;  
Automatic Sound Select is off (MODUS[0] = 0)  
Mode  
Description  
AUTO_FM [11:0]  
ERROR_RATE- Source Select:  
Addr. = 00 21  
Threshold/dec  
Input at NICAM Path  
hex  
0
Forced NICAM  
(Automatic Switching disabled)  
bit[11]  
bit[10:1] = 0  
bit[0]  
= 0  
none  
always NICAM; Mute in  
case of no NICAM available  
reset  
status  
= 0  
= 0  
1
2
3
Automatic Switching with  
internal threshold  
(Default, if Automatic Sound  
bit[11]  
bit[10:1] = 0  
bit[0]  
700  
NICAM or FM/AM,  
depending on  
ERROR_RATE  
= 1  
Select is on)  
Automatic Switching with  
external threshold  
(Customizing of Automatic  
bit[11]  
bit[10:1] = 25...1000  
= threshold/2  
= 0  
set by customer;  
recommended  
range: 50...2000  
Sound Select)  
bit[0]  
= 1  
Forced Analog Mono  
bit[11]  
= 1  
none  
always FM/AM  
(Automatic Switching disabled)  
bit[10:1] = 0  
bit[0] = 1  
64  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
6.3.2. A2 Threshold  
The threshold between Stereo/Bilingual and Mono  
Identification for the A2 Standard has been made pro-  
grammable according to the users preferences. An  
internal hysteresis ensures robustness and stability.  
Table 67: Write Register on I2C Subaddress 10hex : A2 Threshold  
Register  
Address  
Function  
Name  
THRESHOLDS  
00 22hex (write)  
A2 THRESHOLD Register  
A2_THRESH  
Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual  
detection  
bit[15:0] 07F0hex force Mono Identification  
...  
0190hex default setting after reset  
...  
00A0hex  
minimum Threshold for stable detection  
recommended range : 00A0hex...03C0hex  
6.3.3. Carrier-Mute Threshold  
The Carrier-Mute threshold has been made program-  
mable according to the users preferences. An internal  
hysteresis ensures stable behavior.  
Table 68: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold  
Register  
Address  
Function  
Name  
THRESHOLDS  
00 24hex (write)  
Carrier-Mute THRESHOLD Register  
CM_THRESH  
Defines threshold for the carrier mute feature  
bit[15:0] 0000hex Carrier-Mute always ON (both channels muted)  
...  
002Ahex default setting after reset  
...  
07FFhex Carrier-Mute always OFF  
(both channels forced on)  
recommended range : 0014hex...0050hex  
Micronas  
65  
MSP 34x7G  
PRELIMINARY DATA SHEET  
6.3.4. Register AD_CV  
The use of this register is no longer recommended.  
Use it only in cases where compatibility to the  
MSP 34x7D is required. Using the STANDARD  
SELECTION register together with the MODUS regis-  
ter provides a more economic way to program the  
MSP 34x7G  
Table 69: AD_CV Register; reset status: all bits are 0”  
AD_CV  
(00 BBhex  
Automatic setting by  
STANDARD SELECT Register  
)
Bit  
[0]  
Function  
Settings  
2-8, 0A-51hex  
9
not used  
must be set to 0  
0
0
[1:6]  
Reference level in case of Automatic Gain  
Control = on (see Table 610). Constant gain  
factor when Automatic Gain Control = off  
(see Table 611).  
101000  
100011  
[7]  
Determination of Automatic Gain or  
Constant Gain  
0 = constant gain  
1 = automatic gain  
1
1
[8]  
[9]  
not used  
must be set to 0  
0
1
0
1
MSP-Carrier-Mute Feature  
0 = off: no mute  
1 = on: mute as de-  
scribed in Section 2.2.2.  
[10:15]  
not used  
must be set to 0  
0
0
X: not affected while choosing the TV sound standard by means of the STANDARD SELECT Register  
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Automatic  
Sound Select (MODUS[0]=1) is on.  
Table 610: Reference values for active AGC (AD_CV[7] = 1)  
Application  
Input Signal Contains  
AD_CV [6:1]  
Ref. Value  
AD_CV [6:1]  
in decimal  
Range of Input Signal  
at pin ANA_IN1+  
Terrestrial TV  
1)  
Dual Carrier FM  
NICAM/FM  
NICAM/AM  
2 FM Carriers  
101000  
101000  
100011  
40  
40  
35  
0.10 3 Vpp  
1)  
1 FM and 1 NICAM Carrier  
1 AM and 1 NICAM Carrier  
0.10 3 Vpp  
0.10 1.4 Vpp  
(recommended: 0.10 0.8 Vpp  
)
NICAM only  
1 NICAM Carrier only  
1 or more FM Carriers  
010100  
100011  
20  
35  
0.05 1.0 Vpp  
1)  
SAT  
0.10 3 Vpp  
1)  
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the  
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or  
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear.  
66  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Table 611: AD_CV parameters for constant input gain (AD_CV[7]=0)  
Step  
AD_CV [6:1]  
Constant Gain  
Gain  
Input Level at pin ANA_IN1+ and ANA_IN2+  
maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1)  
0
000000  
000001  
000010  
000011  
000100  
000101  
000110  
000111  
001000  
001001  
001010  
001011  
001100  
001101  
001110  
001111  
010000  
010001  
010010  
010011  
010100  
3.00 dB  
1
2
3
4
5
6
7
8
3.85 dB  
4.70 dB  
5.55 dB  
6.40 dB  
7.25 dB  
8.10 dB  
8.95 dB  
9.80 dB  
10.65 dB  
11.50 dB  
12.35 dB  
13.20 dB  
14.05 dB  
14.90 dB  
15.75 dB  
16.60 dB  
17.45 dB  
18.30 dB  
19.15 dB  
20.00dB  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
maximum input level: 0.14 Vpp  
1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the  
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or  
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear.  
Micronas  
67  
MSP 34x7G  
PRELIMINARY DATA SHEET  
6.3.5. Register MODE_REG  
disabled. Only MSP 34x7D features are available; the  
use of MODUS and STATUS register is not allowed.  
The MSP 34x7G is reset to the normal mode by first  
programming the MODUS register, followed by trans-  
mitting a valid standard code to the STANDARD  
SELECTION register.  
Note: The use of this register is no longer recom-  
mended. It should be used only in cases where soft-  
ware compatibility to the MSP 34x7D is required.  
Using the STANDARD SELECTION register together  
with the MODUS register provides a more economic  
way to program the MSP 34x7G.  
The register MODE_REGcontains the control bits  
determining the operation mode of the MSP 34x7G in  
the MSP 34x7D Manual/Compatibility Mode; Table 6–  
12 explains all bit positions.  
As soon as this register is applied, the MSP 34x7G  
works in the MSP 34x7D Manual/Compatibility  
Mode. In this mode, BTSC, EIA-J, and FM-Radio are  
Table 612: Control word MODE_REG; reset status: all bits are 0”  
MODE_REG 00 83hex  
Automatic setting by  
STANDARD SELECT Register  
Bit  
[0]  
[1]  
Function  
not used  
Comment  
Definition  
2 - 5  
0
8,A,B  
9
0
X
0 : must be used  
0
DCTR_TRI  
Digital control out  
0/1 tri-state  
0 : active  
1 : tri-state  
X
X
[2]  
[3]  
[4]  
[5]  
[6]  
not used  
not used  
not used  
not used  
NICAM  
1 : recommended  
0 : must be used  
0 : must be used  
1 : recommended  
X
X
X
X
0
X
X
X
X
1
X
X
X
X
1
Mode of MSP-Ch1  
Mode of MSP-Ch2  
0 : FM  
1 : Nicam  
[7]  
[8]  
not used  
FM AM  
0 : must be used  
0
0
0
0
0
1
0 : FM  
1 : AM  
[9]  
HDEV  
High Deviation Mode  
(channel matrix must be  
sound A)  
0 : normal  
1 : high deviation mode  
0
0
0
[11:10]  
[12]  
not used  
0 : must be used  
0
0
0
0
0
0
MSP-Ch1 Gain  
see also Table 614  
see also Table 614  
0 : Gain = 6 dB  
1 : Gain = 0 dB  
[13]  
FIR1-Filter  
Coeff. Set  
0 : use FIR1  
1 : use FIR2  
1
0
0
[14]  
[15]  
not used  
AM-Gain  
0 : recommended  
0
1
0
1
0
1
Gain for AM  
Demodulation  
0 : 0 dB (default. of MSPB)  
1 : 12 dB (recommended)  
X: not affected by  
STANDARD SELECT Register  
68  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Table 613: Loading sequence for FIR-coefficients  
The loading sequences must be obeyed. To change a  
coefficient set, the complete block FIR1 or FIR2 must  
be transmitted.  
FIR1 00 01hex (MSP-Ch1: NICAM/FM2)  
Note: For compatibility with MSP 3410B, IMREG1 and  
IMREG2 have to be transmitted. The value for  
IMREG1 and IMREG2 is 004. Due to the partitioning to  
8-bit units, the values 04hex, 40hex, and 00hex arise.  
No.  
1
Symbol Name  
Bits  
8
Value  
NICAM/FM2_Coeff. (5)  
NICAM/FM2_Coeff. (4)  
NICAM/FM2_Coeff. (3)  
NICAM/FM2_Coeff. (2)  
NICAM/FM2_Coeff. (1)  
NICAM/FM2_Coeff. (0)  
2
8
3
8
6.3.7. DCO-Registers  
see Table 614  
4
8
Note: The use of this register is no longer recom-  
mended. It should be used only in cases where soft-  
ware compatibility to the MSP 34x7D is required.  
Using the STANDARD SELECTION register together  
with the MODUS register provides a more economic  
way to program the MSP 34x7G.  
5
8
6
8
FIR2 00 05hex (MSP-Ch2: FM1/AM)  
No.  
1
Symbol Name  
IMREG1  
Bits  
8
Value  
04hex  
40hex  
00hex  
When selecting a TV-sound standard by means of the  
STANDARD SELECT register, all frequency tuning is  
performed automatically.  
2
IMREG1 / IMREG2  
IMREG2  
8
IF manual setting of the tuning frequency is required, a  
set of 24-bit registers determining the mixing frequen-  
cies of the quadrature mixers can be written manually  
into the IC. In Table 615, some examples of DCO reg-  
isters are listed. It is necessary to divide them up into  
low part and high part. The formula for the calculation  
of the registers for any chosen IF-Frequency is as fol-  
lows:  
3
8
4
FM/AM_Coef (5)  
FM/AM_Coef (4)  
FM/AM_Coef (3)  
FM/AM_Coef (2)  
FM/AM_Coef (1)  
FM/AM_Coef (0)  
8
5
8
6
8
see Table 614  
7
8
8
8
INCRdec = int(f/fs 224)  
9
8
with: int = integer function  
f
= IF-frequency in MHz  
fS = sampling frequency (18.432 MHz)  
6.3.6. FIR-Parameter, Registers FIR1 and FIR2  
Conversion of INCR into hex-format and separation of  
the 12-bit low and high parts lead to the required regis-  
ter values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI  
or LO for MSP-Ch2).  
Note: The use of this register is no longer recom-  
mended. Use it only in cases where software compati-  
bility to the MSP 34x7D is required. Using the STAN-  
DARD SELECTION register together with the MODUS  
register provides a more economic way to program the  
MSP 34x7G.  
Data shaping and/or FM/AM bandwidth limitation is  
performed by a pair of linear phase Finite Impulse  
Response filters (FIR-filter). The filter coefficients are  
programmable and either are configured automatically  
by the STANDARD SELECT register or written manu-  
ally by the control processor via the control bus. Two  
not necessarily different sets of coefficients are  
required: one for MSP-Ch1 (NICAM or FM2) and one  
for MSP-Ch2 (FM1 = FM-mono). In Table 614 several  
coefficient sets are proposed.  
To load the FIR-filters, the following data values are to  
be transferred  
8
bits at  
a
time embedded  
LSB-bound in a 16-bit word.  
Micronas  
69  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 614: 8-bit FIR-coefficients (decimal integer); reset status: all coefficients are 0”  
Coefficients for FIR1 00 01hex and FIR2 00 05hex  
Terrestrial TV Standards  
FM - Satellite  
FIR filter corresponds to a  
band-pass with a band-  
width of B = 130 to 500 kHz  
B
fc  
frequency  
B/G-, D/K-  
NICAM-FM  
I-  
L-  
B/G-, D/K-,  
M-Dual FM  
130  
kHz  
180  
kHz  
200  
kHz  
280  
kHz  
380  
kHz  
500  
kHz  
Auto-  
search  
NICAM-FM  
NICAM-AM  
FIR1  
2  
FIR2  
FIR1  
FIR2  
FIR1  
2  
FIR2  
4  
FIR2  
3
FIR2  
73  
FIR2  
FIR2  
FIR2  
8  
8  
4
FIR2  
1  
FIR2  
1  
1  
8  
2
FIR2  
1  
1  
8  
2
Coef(i)  
3
2
3
9
3
0
1
2
3
4
5
8  
18  
27  
48  
66  
72  
4
6  
4  
40  
94  
18  
27  
48  
66  
72  
8  
12  
9  
18  
27  
48  
66  
72  
0
53  
18  
28  
47  
55  
64  
1
18  
27  
48  
66  
72  
1
9  
10  
10  
10  
10  
64  
16  
5
23  
119  
101  
127  
1
36  
78  
107  
1
50  
50  
79  
65  
59  
126  
1
59  
126  
0
86  
86  
126  
123  
1
0
0
0
0
0
0
Mode-  
REG[12]  
1
1
1
1
1
1
1
0
Mode-  
REG[13]  
For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3410B is also possible.  
Table 615: DCO registers for the MSP 34x7G; reset status: DCO_HI/LO = 0000”  
DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex  
Freq. MHz  
DCO_HI/hex  
DCO_LO/hex  
Freq. MHz  
DCO_HI/hex  
DCO_LO/hex  
4.5  
03E8  
0000  
5.04  
5.5  
5.58  
5.7421875  
0460  
04C6  
04D8  
04FC  
0000  
038E  
0000  
00AA  
5.76  
5.85  
5.94  
0500  
0514  
0528  
0000  
0000  
0000  
6.0  
6.2  
6.5  
6.552  
0535  
0561  
05A4  
05B0  
0555  
0C71  
071C  
0000  
6.6  
6.65  
6.8  
05BA  
05C5  
05E7  
0AAA  
0C71  
01C7  
7.02  
7.38  
0618  
0668  
0000  
0000  
7.2  
0640  
0690  
0000  
0000  
7.56  
70  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
6.4. Manual/Compatibility Mode:  
Table 616: NICAM operation modes as defined by  
Description of Demodulator Read Registers  
the EBU NICAM 728 specification  
Note: The use of these register is no longer recom-  
mended. It should be used only in cases where soft-  
ware compatibility to the MSP 34x7D is required.  
Using the STANDARD SELECTION register together  
with the STATUS register provides a more economic  
way to program the MSP 34x7G and to retrieve infor-  
mation from the IC.  
C4 C3 C2 C1 Operation Mode  
0
0
0
0
0
0
0
0
1
0
1
0
Stereo sound (NICAMA/B),  
independent mono sound (FM1)  
Two independent mono signals  
(NICAMA, FM1)  
Three independent mono channels  
(NICAMA, NICAMB, FM1)  
All registers except C_AD_BITs are 8 bit wide. They  
can be read out of the RAM of the MSP 34x7G if the  
MSP 34x7D compatibility mode is required.  
0
1
0
0
1
0
1
0
Data transmission only; no audio  
Stereo sound (NICAMA/B), FM1  
carries same channel  
All transmissions take place in 16-bit words. The valid  
8-bit data are the 8 LSBs of the received data word.  
1
1
0
0
0
1
1
0
One mono signal (NICAMA). FM1  
carries same channel as NICAMA  
If the Automatic Sound Select feature is not used, the  
NICAM or FM-identification parameters must be read  
and evaluated by the controller in order to enable  
appropriate switching of the channel select matrix of  
the baseband processing part. The FM-identification  
registers are described in Section 6.6.1. To handle the  
NICAM-sound and to observe the NICAM-quality, at  
least the registers C_AD_BITS and ERROR_RATE  
must be read and evaluated by the controller. Addi-  
tional data bits and CIB bits, if supplied by the NICAM  
transmitter, can be obtained by reading the registers  
ADD_BITS and CIB_BITS.  
Two independent mono channels  
(NICAMA, NICAMB). FM1 carries  
same channel as NICAMA  
1
x
0
1
1
x
1
x
Data transmission only; no audio  
Unimplemented sound coding  
option (not yet defined by EBU  
NICAM 728 specification)  
AUTO_FM: monitor bit for the AUTO_FM Status:  
0: NICAM source is NICAM  
1: NICAM source is FM  
Note: It is no longer necessary to read out and evalu-  
ate the C_AD_BITS. All evaluation is performed in the  
MSP and indicated in the STATUS register.  
6.4.1. NICAM Mode Control/Additional Data Bits  
Register  
NICAM operation mode control bits and A[2:0] of the  
additional data bits.  
6.4.2. Additional Data Bits Register  
Format:  
Contains the remaining 8 of the 11 additional data bits.  
The additional data bits are not yet defined by the  
NICAM 728 system.  
MSB  
C_AD_BITS 00 23hex  
LSB  
11  
...  
...  
7
6
5
4
3
2
1
0
Auto  
_FM  
A[2] A[1] A[0]  
C4  
C3  
C2  
C1  
S
Format:  
MSB  
7
ADD_BITS 00 38hex  
LSB  
0
6
5
4
3
2
1
Important: S= bit[0] indicates correct NICAM-syn-  
chronization (S = 1). If S = 0, the MSP 3417/3457G  
has not yet synchronized correctly to frame and  
sequence, or has lost synchronization. The remaining  
read registers are therefore not valid. The MSP mutes  
the NICAM output automatically and tries to synchro-  
nize again as long as MODE_REG[6] is set.  
A[10]  
A[9]  
A[8]  
A[7]  
A[6]  
A[5]  
A[4]  
A[3]  
6.4.3. CIB Bits Register  
Cib bits 1 and 2 (see NICAM 728 specifications).  
Format:  
The operation mode is coded by C4-C1 as shown in  
Table 616.  
MSB  
CIB_BITS 00 3Ehex  
LSB  
0
7
x
6
x
5
x
4
x
3
x
2
x
1
CIB1  
CIB2  
Micronas  
71  
MSP 34x7G  
PRELIMINARY DATA SHEET  
6.4.4. NICAM Error Rate Register  
6.4.7. Automatic Search Function for FM-Carrier  
Detection in Satellite Mode  
ERROR_RATE  
Error free  
00 57hex  
0000hex  
07FFhex  
The AM demodulation ability of the MSP 3417G and  
MSP 3457G offers the possibility to calculate the field  
strengthof the momentarily selected FM carrier,  
which can be read out by the controller. In SAT receiv-  
ers, this feature can be used to make automatic FM  
carrier search possible.  
maximum error rate  
Average error rate of the NICAM reception in a time  
interval of 182 ms, which should be close to 0. The ini-  
tial and maximum value of ERROR_RATE is 2047.  
This value is also active if the NICAM bit of  
MODE_REG is not set. Since the value is achieved by  
filtering, a certain transition time (approx. 0.5 sec) is  
unavoidable. Acceptable audio may have error rates  
up to a value of 700 int. Individual evaluation of this  
value by the controller and an appropriate threshold  
may define the fallback mode from NICAM to FM/  
AM-mono in case of poor NICAM reception.  
For this, the MSP has to be switched to AM-mode  
(MODE_REG[8]), FM-Prescale must be set to  
7Fhex= +127dec  
,
and the FM DC notch (see  
Section 6.5.7.) must be switched off. The sound-IF fre-  
quency range must now be scannedin the  
MSP-channel 2 by means of the programmable  
quadrature mixer with an appropriate incremental fre-  
quency (i.e. 10 kHz). After each incrementation, a field  
strength value is available at the quasi-peak detector  
output (quasi-peak detector source must be set to  
FM), which must be examined for relative maxima by  
the controller. This results in either continuing search  
or switching the MSP back to FM demodulation mode.  
The bit error rate per second (BER) can be calculated  
by means of the following formula:  
BER= ERROR_RATE * 12.3*106 /s  
During the search process, the FIR2 must be loaded  
with the coefficient set AUTOSEARCH, which  
enables small bandwidth, resulting in appropriate field  
strength characteristics. The absolute field strength  
value (can be read out of quasi peak detector output  
FM1) also gives information on whether a main FM  
carrier or a subcarrier was detected; and as a practical  
consequence, the FM bandwidth (FIR1/2) and the  
deemphasis (50 µs or adaptive) can be switched  
accordingly.  
6.4.5. PLL_CAPS Readback Register  
It is possible to read out the actual setting of the  
PLL_CAPS. In standard applications, this register is  
not of interest for the customer.  
PLL_CAPS  
02 1Fhex L  
minimum frequency  
nominal frequency  
1111 1111  
FFhex  
56hex  
Due to the fact that a constant demodulation frequency  
offset of a few kHz, leads to a DC level in the demodu-  
lated signal, further fine tuning of the found carrier can  
be achieved by evaluating the DC Level Readout  
FM1. Therefore, the FM DC Notch must be switched  
on, and the demodulator part must be switched back to  
FM-demodulation mode.  
0101 0110  
RESET  
maximum frequency  
PLL_CAPS  
0000 0000  
00hex  
02 1Fhex  
H
PLL open  
xxxx xxx0  
xxxx xxx1  
For a detailed description of the automatic search  
function, please refer to the corresponding MSP Win-  
dows software.  
PLL closed  
6.4.6. AGC_GAIN Readback Register  
It is possible to read out the actual setting of  
AGC_GAIN in Automatic Gain Mode. In standard  
applications, this register is not of interest for the cus-  
tomer  
.
AGC_GAIN  
02 1Ehex  
max. amplification  
(20 dB)  
0001 0100  
14hex  
00hex  
min. amplification  
(3 dB)  
0000 0000  
72  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
6.5. Manual/Compatibility Mode:  
Description of DSP Write Registers  
6.5.2. Volume Modes of SCART1 Output  
Volume Mode SCART1  
00 07hex  
[3:0]  
6.5.1. Additional Channel Matrix Modes  
linear  
0000  
RESET  
0hex  
Loudspeaker Matrix  
SCART1 Matrix  
00 08hex  
00 0Ahex  
00 0Chex  
L
L
L
logarithmic  
0001  
1hex  
Quasi-Peak  
Linear Mode  
Volume SCART1  
OFF  
Detector Matrix  
00 07hex  
H
SUM/DIFF  
0100 0000  
0101 0000  
0110 0000  
0111 0000  
1000 0000  
1001 0000  
40hex  
50hex  
60hex  
70hex  
80hex  
90hex  
0000 0000  
RESET  
00hex  
AB_XCHANGE  
PHASE_CHANGE_B  
PHASE_CHANGE_A  
A_ONLY  
0 dB gain (digital full scale  
to 2 VRMS output)  
0100 0000  
40hex  
7Fhex  
+6 dB gain (6 dBFS to  
2 VRMS output)  
0111 1111  
B_ONLY  
6.5.3. FM Fixed Deemphasis  
This table shows more modes for the channel matrix  
registers.  
FM Deemphasis  
00 0Fhex  
H
The sum/difference mode can be used together with  
the quasi-peak detector to determine the sound mate-  
rial mode. If the difference signal on channel B (right)  
is near to zero, and the sum signal on channel A (left)  
is high, the incoming audio signal is mono. If there is a  
significant level on the difference signal, the incoming  
audio is stereo.  
50 µs  
0000 0000  
RESET  
00hex  
75 µs  
J17  
0000 0001  
0000 0100  
0011 1111  
01hex  
04hex  
3Fhex  
OFF  
Note: This register is initialized during STANDARD  
SELECTION and is automatically updated when Auto-  
matic Sound Select (MODUS[0]=1) is on.  
6.5.4. FM Adaptive Deemphasis  
FM Adaptive  
00 0Fhex  
L
Deemphasis WP1  
OFF  
WP1  
0000 0000  
RESET  
00hex  
3Fhex  
0011 1111  
Note: This register is initialized during STANDARD  
SELECTION and is automatically updated when Auto-  
matic Sound Select (MODUS[0]=1) is on.  
6.5.5. NICAM Deemphasis  
A J17 Deemphasis is always applied to the NICAM sig-  
nal. It is not switchable.  
Micronas  
73  
MSP 34x7G  
PRELIMINARY DATA SHEET  
6.5.6. Identification Mode for A2 Stereo Systems  
6.6. Manual/Compatibility Mode:  
Description of DSP Read Registers  
Identification Mode  
00 15hex  
L
All readable registers are 16-bit wide. Transmissions  
via I2C bus have to take place in 16-bit words. Some of  
the defined 16-bit words are divided into low and high  
byte, thus holding two different control entities.  
Standard B/G  
(German Stereo)  
0000 0000  
RESET  
00hex  
Standard M  
(Korean Stereo)  
0000 0001  
0011 1111  
01hex  
3Fhex  
These registers are not writable.  
Reset of Ident-Filter  
6.6.1. Stereo Detection Register  
for A2 Stereo Systems  
To shorten the response time of the identification algo-  
rithm after a program change between two FM-Stereo  
capable programs, the reset of the ident-filter can be  
applied.  
Stereo Detection  
Register  
00 18hex  
H
MONO  
near zero  
Sequence:  
STEREO  
positive value (ideal  
reception: 7Fhex  
1. Program change  
)
2. Reset ident-filter  
BILINGUAL  
negative value (ideal  
reception: 80hex)  
3. Set identification mode back to standard B/G or M  
4. Wait approx. 500 ms  
Note: It is no longer necessary to read out and evalu-  
ate the A2 identification level. All evaluation is per-  
formed in the MSP and indicated in the STATUS regis-  
ter.  
5. Read stereo detection register  
Note: This register is initialized during STANDARD  
SELECTION and is automatically updated when Auto-  
matic Sound Select (MODUS[0]=1) is on.  
6.6.2. DC Level Register  
6.5.7. FM DC Notch  
DC Level Readout  
FM1 (MSP-Ch2)  
00 1Bhex  
00 1Chex  
H+L  
H+L  
The DC compensation filter (FM DC Notch) for FM  
input can be switched off. This is used to speed up the  
automatic search function (see Section 6.4.7.). In nor-  
mal FM-mode, the FM DC Notch should be switched  
on.  
DC Level Readout  
FM2 (MSP-Ch1)  
DC Level  
[8000hex ... 7FFFhex]  
values are 16 bit twos  
complement  
FM DC Notch  
00 17hex  
L
ON  
0000 0000  
Reset  
00hex  
The DC level register measures the DC component of  
the incoming FM signals (FM1 and FM2). This can be  
used for seek functions in satellite receivers and for IF  
FM frequencies fine tuning. A too low demodulation  
frequency (DCO) results in a positive DC-Level and  
vice versa. For further processing, the DC content of  
the demodulated FM signals is suppressed. The time  
constant τ, defining the transition time of the DC Level  
Register, is approximately 28 ms.  
OFF  
0011 1111  
3Fhex  
74  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
6.7. Demodulator Source Channels in Manual Mode  
6.7.1. Terrestric Sound Standards  
6.8. Exclusions of Audio Baseband Features  
In general, all functions can be switched independently.  
Two exceptions exist:  
Table 617 shows the source channel assignment of  
the demodulated signals in case of manual mode for  
all terrestric sound standards. See Table 22 for the  
assignment in the Automatic Sound Select mode. In  
manual mode for terrestric sound standards, only two  
demodulator sources are defined.  
1. NICAM cannot be processed simultaneously with  
the FM2 channel.  
2. FM adaptive deemphasis cannot be processed  
simultaneously with FM-identification.  
6.9. Compatibility Restrictions to MSP 34x7D  
6.7.2. SAT Sound Standards  
The MSP 34x7G is fully hardware compatible to the  
MSP 34x7D. However, to substitute a MSP 34x7D by  
the corresponding MSP 34x7G, the controller software  
has to be adapted slightly:  
Table 618 shows the source channel assignment of  
the demodulated signals for SAT sound standards.  
1. The register FM-Matrix (00 0Ehex low part) must be  
changed from no matrix (00hex)to sound A mono  
(03hex)during mono transmission of all TV-sound  
standards (see also Table 617).  
2. With the MSP 34x7G, the STANDARD SELECTION  
initializes the FM-deemphasis, which is not the case  
for the MSP 34x7D. So, if STANDARD SELECTION  
is applied, this I2C instruction can be omitted.  
Micronas  
75  
MSP 34x7G  
PRELIMINARY DATA SHEET  
Table 617: Manual Sound Select Mode for Terrestric Sound Standards  
Source Channels of Sound Select Block  
Broadcasted  
Sound  
Standard  
Selected MSP Broadcasted  
FM Matrix  
FM/AM  
Stereo or A/B  
Standard  
Sound Mode  
(use 0 for channel select) (use 1 for channel select)  
Code  
B/G-FM  
D/K-FM  
M-Korea  
M-Japan  
03  
04, 05  
02  
30  
MONO  
Sound A Mono  
Mono  
Mono  
STEREO  
German Stereo  
Korean Stereo  
Stereo  
Stereo  
BILINGUAL,  
No Matrix  
Left = A  
Left = A  
Languages A and B  
Right = B  
Right = B  
B/G-NICAM  
L-NICAM  
I-NICAM  
D/K-NICAM  
D/K-NICAM  
(with high  
08  
09  
0A  
0B  
0C  
0D  
NICAM not available Sound A Mono1) analog Mono  
or NICAM error rate  
too high  
no sound  
with AUTO_FM:  
analog Mono  
MONO  
Sound A Mono1) analog Mono  
Sound A Mono1) analog Mono  
Sound A Mono1) analog Mono  
NICAM Mono  
NICAM Stereo  
deviation FM)  
STEREO  
BILINGUAL,  
Left = NICAM A  
Right = NICAM B  
Languages A and B  
MONO  
Sound A Mono  
Korean Stereo  
Sound A Mono  
Korean Stereo  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Stereo  
Mono  
Stereo  
STEREO  
20  
MONO + SAP  
STEREO + SAP  
MONO  
BTSC  
Sound A Mono  
No Matrix  
Mono  
Mono  
STEREO  
21  
40  
MONO + SAP  
STEREO + SAP  
MONO  
Left = Mono  
Right = SAP  
Left = Mono  
Right = SAP  
Sound A Mono  
Korean Stereo  
Mono  
Mono  
FM-Radio  
STEREO  
Stereo  
Stereo  
1) Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!  
Table 618: Manual Sound Select Modes for SAT-Standards  
Source Channels of Sound Select Block for SAT-Modes  
Broadcasted Selected  
Broadcasted  
FM Matrix  
FM/AM  
Stereo or A/B  
Stereo or A  
Stereo or B  
Sound  
Standard  
MSP Standard Sound Mode  
Code  
(source select: 0)  
(source select: 1)  
(source select: 3) (source select: 4)  
6, 50  
MONO  
Sound A Mono Mono  
Mono  
Mono  
Mono  
hex  
51  
STEREO  
BILINGUAL  
No Matrix  
No Matrix  
Stereo  
Stereo  
Stereo  
A (FM1)  
Stereo  
B (FM2)  
hex  
FM SAT  
Left = A (FM1)  
Left = A (FM1)  
Right = B (FM2) Right = B (FM2)  
76  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
7. Appendix D: Application Information  
7.1. Phase Relationship of Analog Outputs  
The user does not need to correct output phases when  
using the loudspeaker output directly. The SCART1  
output has opposite phase.  
The following schematics shows the phase relation-  
ship of all analog inputs and outputs.  
Loudspeaker  
SCART1-Ch.  
Audio  
Baseband  
Processing  
SCART1  
SCART1  
SCART  
DSP  
Input  
Select  
MONO  
SCART  
Output Select  
MONO, SCART1  
Fig. 71: Phase diagram of the MSP 34x7G  
Micronas  
77  
MSP 34x7G  
PRELIMINARY DATA SHEET  
7.2. Application Circuit  
Signal GND  
C s. section 4.6.2.  
10  
µF  
100  
nF  
8 V (5 V)  
-
100 p  
56 p  
SIF 1 IN  
Tuner  
+
ANA_IN1+  
18.432  
MHz  
3.3 100  
µF nF  
Alternative circuit for  
+
1 kΩ  
SIF-input for more  
attenuation of video  
components:  
+
10 µF  
56 pF  
56 pF  
1 µF  
DACM_L  
DACM_R  
MONO_IN  
330 nF  
Loudspeaker  
1 µF  
1 nF  
1 nF  
SC1_IN_L  
SC1_IN_R  
330 nF  
330 nF  
MSP 34x7G  
100Ω  
100Ω  
22 µF  
5 V  
SC1_OUT_L  
SC1_OUT_R  
+
+
STANDBYQ  
ADR_SEL  
22 µF  
5 V  
DVSS  
DVSS  
I2C_DA  
I2C_CL  
D_CTR_I/O_0  
D_CTR_I/O_1  
TESTEN  
AHVSS  
220  
pF  
470  
pF  
1.5  
nF  
470  
pF  
1.5  
nF  
10  
µF  
470  
pF  
1.5  
nF  
10  
µF  
RESETQ  
(from Controller, see section 4.6.3.3.)  
10  
µF  
5 V  
5 V  
8 V  
(5 V)  
78  
Micronas  
PRELIMINARY DATA SHEET  
MSP 34x7G  
Micronas  
79  
MSP 34x7G  
PRELIMINARY DATA SHEET  
8. Appendix E: MSP 34x7G Version History  
9. Data Sheet History  
1. Preliminary data sheet: MSP 34x7G Multistandard  
Sound Processor Family, Edition Sept. 7, 2000,  
6251-535-1PD. First release of the preliminary data  
sheet.  
MSP 34x7G-B6  
improved AM-performance (see page 53)  
new D/K standard for Poland  
(see Table 37 on page 18)  
improved I2C hardware problem handling  
2. Preliminary data sheet: MSP 34x7G Multistandard  
Sound Processor Family, March 5, 2001,  
6251-535-2PD. Second release of the preliminary data  
sheet. Major changes:  
(see Section 3.1.1. on page 14)  
I2C-bus description changed  
faster system-D/K-loop for stereo detection  
ACB register: documentation for bit allocation  
extended features in the CONTROL register  
D_CTR_I/O changed  
(see Section 3.1.2. on page 15)  
MSP 34x7G-B8  
fine-tuning of A2-identification and carrier mute  
EIA-J identification: faster transition time stereo/  
bilingual to mono  
J17 FM-deemphasis implemented  
input specification for RESETQ and TESTEN  
changed  
All information and data contained in this data sheet are without any  
commitment, are not to be considered as an offer for conclusion of a  
contract, nor shall they be construed as to create any liability. Any new  
issue of this data sheet invalidates previous issues. Product availability  
and delivery are exclusively subject to our respective order confirmation  
form; the same applies to orders based on development samples deliv-  
ered. By this publication, Micronas GmbH does not assume responsibil-  
ity for patent infringements or other rights of third parties which may  
result from its use.  
Further, Micronas GmbH reserves the right to revise this publication  
and to make changes to its content, at any time, without obligation to  
notify any person or entity of such revisions or changes.  
No part of this publication may be reproduced, photocopied, stored on a  
retrieval system, or transmitted without the express written consent of  
Micronas GmbH.  
Micronas GmbH  
Hans-Bunte-Strasse 19  
D-79108 Freiburg (Germany)  
P.O. Box 840  
D-79008 Freiburg (Germany)  
Tel. +49-761-517-0  
Fax +49-761-517-2174  
E-mail: docservice@micronas.com  
Internet: www.micronas.com  
Printed in Germany  
Order No. 6251-535-2PD  
80  
Micronas  
MSP 34xxG  
Preliminary Data Sheet Supplement  
Subject:  
MSP 34xxG Version History  
All MSP 34xxG Data Sheets  
Data Sheet Concerned:  
Supplement:  
Edition:  
No. 2/ 6251-525-2PDS  
Oct. 11, 2000  
Version Changes within the MSP 34xxG Family:  
For a detailed description of the below-mentioned items, see the corresponding data sheets. For quick reference,  
check the version history in the data sheet appendices.  
MSP 34x0G  
MSP 34x1G  
MSP 34x2G  
MSP 34x5G  
MSP 34x7G  
A4  
B4  
A1  
B5  
B6  
A2  
B8  
B8  
A1  
A4  
B5  
B6  
B8  
B8  
B6  
technology  
0.8 µ  
0.5 µ  
0.5 µ  
0.5 µ  
0.45 µ  
740 mW 640 mW 640 mW 640 mW 600 mW  
690 mW  
power dissipation (typical) at 8 V operation  
MSP 34x0/x1/x5/x7  
MSP 34x2  
digital input specification change  
x
x
x
specification of max. analog high voltage (AHVSUP)  
programmable A2 and carrier mute thresholds  
8.4 V  
8.4 V  
8.7 V  
8.7 V  
8.7 V  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
new Standard Select Mode 0Dhex: D/K-NICAM together with HDEV3 FM mode  
additional preference “color” for 4.5 MHz carrier in Automatic Standard Detection  
improved AM-performance (better SNR and THD)  
new Standard Select Mode 07hex: D/K3 for Poland  
faster system D/K loop for stereo detection (standards 4, 5, 7, B with ASS = on)  
improved I2C hardware problem handling  
extended features in the CONTROL register (readout hardware / reset status)  
Micronas Dynamic Bass (MDB)  
MSP 34x0/x1/x2  
MSP 34x0/x1/x2  
Micronas Dynamic Bass (improved MDB)  
faster identification for all standards, major speedup of  
identification for EIA-J standard  
faster carrier mute  
J17 deemphasis  
x
x
Micronas  
page 1 of 1  

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