IMSR-67025V-45 [TEMIC]
Dual-Port SRAM, 8KX16, 45ns, CMOS, PQCC84, PLASTIC, LCC-84;型号: | IMSR-67025V-45 |
厂家: | TEMIC SEMICONDUCTORS |
描述: | Dual-Port SRAM, 8KX16, 45ns, CMOS, PQCC84, PLASTIC, LCC-84 静态存储器 内存集成电路 |
文件: | 总23页 (文件大小:257K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MATRA MHS
M 67025
8 K × 16 CMOS Dual Port RAM
Introduction
The M 67025 is a very low power CMOS dual port static Using an array of eigh transistors (8T) memory cell and
RAM organised as 8192 × 16. The M 67025 is designed fabricated with the state of the art 0.65 µ lithography
to be used as a stand-alone 16 bit dual port RAM or as a named SCMOS, the M 67025 combines an extremely low
combination MASTER/SLAVE dual port for 32 bit or standby supply current (typ = 1.0 µA) with a fast access
more
width
systems.
The
MATRA-MHS time at 20 ns over the full temperature range. All versions
MASTER/SLAVE dual port approach in memory system offer battery backup data retention capability with a
applications results in full speed, error free operation typical power consumption at less than 5 µW.
without the need of an additional discrete logic.
For military/space applications that demand superior
Master and slave devices provide two independant ports
with separate control, address and I/O pins that permit
independant, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the on-chip circuitry of
each port in order to enter a very low stand by power
mode.
levels of performance and reliability the M 67025 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D Fast access time : 20/25/30/35/45/55 ns
D Wide temperature range :
D Versatile pin select for master or slave :
– M/S = H for busy output flag on master
– M/S = L for busy input flag on slave
–55 °C to +125 °C
D 67025 L low power
D INT flag for port to port communication
D Full hardware support of semaphore signaling between ports
D Fully asynchronous operation from either port
D Battery back-up operation : 2 V data retention
D TTL compatible
67025 V very low power
D Separate upper byte and lower byte control for multiplexed
bus compatibility
D Expandable data bus to 32 bits or more using master/slave
chip select when using more than one device
D On chip arbitration logic
D Single 5 V ± 10 % power supply
D For 3.3 V version, please consult sales
Rev. D (29/09/95)
1
M 67025
MATRA MHS
Interface
Block Diagram
Note :
1. (MASTER) : BUSY is output. (SLAVE) : BUSY is input.
2. LB = Lower Byte UB = Upper Byte
Pin Names
LEFT PORT
RIGHT PORT
NAMES
CS
L
CS
R
Chip select
R/W
R/W
Read/Write Enable
Output Enable
Address
L
R
OE
OE
R
L
A
A
0R – 12R
0L – 12L
I/O
I/O
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
0L – 15L
0R – 15R
SEM
SEM
R
L
UB
UB
R
L
LB
LB
R
L
INT
INT
R
L
BUSY
BUSY
R
L
M/S
Vcc
Master or Slave Select
Power
GND
Ground
2
Rev. D (29/09/95)
MATRA MHS
M 67025
Functional Description
Pin Configuration
Top View
Rev. D (29/09/95)
3
M 67025
MATRA MHS
Pin Configuration
INDEX
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
I/O
I/O
A
A
A
A
A
A
A
A
1
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
8L
7L
6L
5L
4L
3L
2L
1L
0L
2
3
9L
I/O
10L
I/O
I/O
4
11L
5
12L
13L
I/O
6
GND
7
I/O
8
14L
15L
I/O
INT
L
9
67025
F-84-2
Vcc
BUSY
GND
M/S
10
11
12
13
14
15
16
17
18
19
20
21
L
GND
84-PIN MQFPF
FLATPACK
TOP VIEW
I/O
0R
I/O
1R
BUSY
R
I/O
2R
INT
R
Vcc
A
0R
I/O
3R
A
1R
I/O
4R
A
2R
I/O
5R
A
3R
I/O
6R
A
4R
I/O
7R
A
5R
I/O
8R
A
6R
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
INDEX
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
N/C
N/C
N/C
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N/C
N/C
N/C
2
3
4
5
6
7
8
9
I/O
10L
A
5L
I/O
A
11L
12L
13L
4L
I/O
I/O
A
3L
A
2L
GND
A
1L
I/O
A
10
14L
15L
0L
I/O
INT
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
L
67025
Vcc
BUSY
GND
M/S
L
GND
100-PIN TQFP
TOP VIEW
I/O
0R
I/O
1R
BUSY
R
I/O
2R
INT
R
Vcc
A
0R
I/O
3R
A
1R
I/O
4R
A
2R
I/O
5R
A
3R
I/O
6R
A
4R
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4
Rev. D (29/09/95)
MATRA MHS
M 67025
Functional Description
The M 67025 has two ports with separate control, address if the CSs are low before an address match, on-chip
and I/0 pins that permit independent read/write access to control logic arbitrates between the left and right
any memory location. These devices have an automatic addresses for access (refer to table 4). The inhibited port’s
power-down feature controlled by CS.CS controls BUSY flag is set and will reset when the port granted
on-chip power-down circuitry which causes the port access completes its operation in both arbitration modes.
concerned to go into stand-by mode when not selected
(CS high). When a port is selected access to the full
memory array is permitted. Each port has its own Output
Data Bus Width Expansion
Enable control (OE). In read mode, the port’s OE turns the
Master/Slave Description
Output drivers on when set LOW. Non-conflicting
Expanding the data bus width to 32 or more bits in a
READ/WRITE conditions are illustrated in table 1.
dual-port RAM system means that several chips may be
The interrupt flag (INT) allows communication between
active simultaneously. If every chips has a hardware
ports or systems. If the user chooses to use the interrupt
arbitrator, and the addresses for each arrive at the same
function, a memory location (mail box or message center)
time one chip may activate in L BUSY signal while
is assigned to each port. The left port interrupt flag (INT )
L
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading
address location 1FFE. Similarly, the right port interrupt
To overcome this “Busy Lock-Out” problem, MHS has
developped a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to the
MASTER with no external components, giving a speed
advantage over other systems.
flag (INT ) is set when the left port writes to memory
R
location 1FFF (HEX), and the right port must read
memory location 1FFF in order to clear the interrupt flag
(INT ). The 16 bit message at 1FFE or 1FFF is
R
user-defined. If the interrupt function is not used, address
locations 1FFE and 1FFF are not reserved for mail boxes
but become part of the RAM. See table 3 for the interrupt
function.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until after
the BUSY input has settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation.
Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the
conflict is resolved. This timing is inherent in all
dual-port memory systems where more than one chip is
active at the same time.
Arbitration Logic
Functional Description
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns determine
which port has access. In all cases, an active BUSY flag
will be set for the inhibited port.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
The BUSY flags are required when both ports attempt to
access the same location simultaneously. Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the Semaphore Logic
inhibited port. BUSY is set at speeds that allow the
Functional Description
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
The M 67025 is an extremely fast dual-port 4k × 16
CMOS static RAM with an additional locations dedicated
to binary semaphore flags. These flags allow either of the
A conflict will occur when both left and right ports are processors on the left or right side of the dual-port RAM
active and the two addresses coincide. The on-chip to claim priority over the other for functions defined by
arbitration determines access in these circumstances. the system software. For example, the semaphore flag can
Two modes of arbitration are provided : (1) if the be used by oner processor to inhibit the other from
addresses match and are valid before CS on-chip control accessing a portion of the dual-port RAM or any other
logic arbitrates between CS and CS for access ; or (2) shared resource.
L
R
Rev. D (29/09/95)
5
M 67025
MATRA MHS
The dual-port RAM has a fast access time, and the two reading it. If the latch has been set the processor assumes
ports are completely independent of each another. This control over the shared resource. If the latch has not been
means that the activity on the left port cannot slow the set, the left processor has established that the right
access time of the right port. The ports are identical in processor had set the latch first, has the token and is using
function to standard CMOS static RAMs and can be read the shared resource. The left processor may then either
from, or written to, at the same time with the only possible repeatedly query the status of the semaphore, or abandon
conflict arising from simultaneous writing to, or a its request for the token and perform another operation
simultaneous READ/WRITE operation on,
a
whilst occasionally attempting to gain control of the
non-semaphore location. Semaphores are protected token through a set and test operation. Once the right side
against such ambiguous situations and may be used by the has relinquished the token the left side will be able to take
system program to prevent conflicts in the control of the shared resource.
non-semaphore segment of the dual-port RAM. The
devices have an automatic power-down feature
by writing a zero to a semaphore latch, and is relinquished
controlled by CS, the dual-port RAM select and SEM, the
again when the same side writes a one to the latch.
The semaphore flags are active low. A token is requested
semaphore enable. The CS and SEM pins control
The eight semaphore flags are located in a separate
on-chip-power-down circuitry that permits the port
memory space from the dual-port RAM in the M 67025.
concerned to go into stand-by mode when not selected.
The address space is accessed by placing a low input on
This conditions is shown in table 1 where CS and SEM
the SEM pin (which acts as a chip select for the
are both high.
semaphore flags) and using the other control pins
Systems best able to exploit the M 67025 are based
around multiple processors or controllers and are
typically very high-speed, software controlled or
software-intensive systems. These systems can benefit
from the performance enhancement offered by the
M 67025 hardware semaphores, which provide a lock-out
mechanism without the need for complex programming.
(address, OE and R/W) as normally used in accessing a
standard static RAM. Each of the flags has a unique
address accessed by either side through address pins
A0-A2. None of the other address pins has any effect
when accessing the semaphores. Only data pin D is used
0
when writing to a semaphore. If a low level is written to
an unused semaphore location, the flag will be set to zero
on that side and to one on the other side (see table 5). The
semaphore can now only be modified by the side showing
the zero. Once a one is writen to this location from the
same side, the flag will be set to one for both sides (unless
a request is pending from the other side) and the
semaphore can then be written to by either side.
Software handshaking between processors offers the
maximum level of system flexibility by permitting shared
resources to be allocated in varying configurations. The
M 67025 does not use its semaphore flags to control any
resources through hardware, thus allowing the system
designer total flexibility in system architecture.
The effect the side writing a zero to a semaphore location
has of locking out the other side is the reason for the use
of semaphore logic in interprocessor communication. (A
thorough discussion of the use of this feature follows
below). A zero written to the semaphore location from the
locked-out side will be stored in the semaphore request
latch for that side until the semaphore is relinquished by
the side having control. When a semaphore flag is read its
An advantage of using semaphores rather than the more
usual methods of hardware arbitration is that neither
processor ever incurs wait states. This can prove to be a
considerable advantage in very high speed systems.
How The Semaphore Flags Work
The semaphore logic is a set of eight latches independent value is distributed to all data bits so that a flag set at one
of the dual-port RAM. These latches can be used to pass reads as one in all data bits and a flag set at zero reads as
a flag or token, from one port to the other to indicate that all zeros. The read value is latched into the output register
a shared resource is in use. The semaphore provide the of one side when its semaphore select (SEM) and output
hardware context for the “Token Passing Allocation” enable (OE) signals go active. This prevents the
method of use assignment. This method uses the state of semaphore changing state in the middle of a read cycle as
a semaphore latch as a token indicating that a shared a result of a write issued by the other side. Because of this
resource is in use. If the left processor needs to use a latch, a repeated read of a semaphore flag in a test loop
resource, it requests the token by setting the latch. The must cause either signal (SEM or OE) to go inactive,
processor then verifies that the latch has been set by otherwise the output will never change.
6
Rev. D (29/09/95)
MATRA MHS
M 67025
The semaphore must use a WRITE/READ sequence in Semaphore initialization is not automatic and must
order to ensure that no system level conflict will occur. A therefore be incorporated in the power up initialization
processor requests access to shared resources by procedures. Since any semaphore flag containing a zero
attempting to write a zero to a semaphore location. If the must be reset to one, initialization should write a one to
semaphore is already in use, the semaphore request latch all request flags from both sides to ensure that they will
will contain a zero, yet the semaphore flag will appear as be available when required.
a one, and the processor will detect this status in the
subsequent read (see table 5). For example, assume a
Using Semaphores - Some Examples
processor writes a zero to the left port at a free semaphore
location. On a subsequent read, the processor will verify
that it has written successfully to that location and will
assume control over the resource concerned. If a
processor on the right side then attempts to write a zero
to the same semaphore flag it will fail, as will be verified
by a subsequent read returning a one from the semaphore
location on the right side has a READ/WRITE sequence
been used instead, system conflict problems could have
occurred during the interval between the read and write
cycles.
Perhaps the simplest application of semaphores is their
use as resource markers for the M 67025’s dual-port
RAM. If it is necessary to split the 8 k × 16 RAM into two
4 K × 16 blocks which are to be dedicated to serving either
the left or right port at any one time. Semaphore 0 can be
used to indicate which side is controlling the lower
segment of memory and semaphore 1 can be defined as
indicating the upper segment of memory.
To take control of a resource, in this case the lower 4 k of
It must be noted that a failed semaphore request needs to a dual-port RAM, the left port processor would then write
be followed by either repeated reads or by writing a one a zero into semaphore flag 0 and then read it back. If
to the same location. The simple logic diagram for the successful in taking the token (reading back a zero rather
semaphore flag in figure 2 illusrates the reason for this than a one), the left processor could then take control of
quite clearly. Two semaphore request latches feed into a the lower 4 k of RAM. If the right processor attempts to
semaphore flag. The first latch to send a zero to the perform the same function to take control of the resource
semaphore flag will force its side of the semaphore flag after the left processor has already done so, it will read
low and other side high. This status will be maintained back a one in response to the attempted write of a zero into
until a one is written to the same semaphore request latch. semaphore 0. At this point the software may choose to
Sould a zero be written to the other side’s semaphore attempt to gain control of the second 4 k segment of RAM
request latch in the meantime, the semaphore flag will flip by writing and then reading a zero in semaphore 1. If
over to this second side as soon as a one is written to the successful, it will lock out the left processor.
first side’s request latch. The second side’s flag will now
Once the left side has completed its task it will write a one
stay low until its semaphore request latch is changed to a
to semaphore 0 and may then attempt to access
one. Thus, clearly, if a semaphore flag is requested and the
semaphore 1. If semaphore 1 is still occupied by the right
processor requesting it no longer requires access to the
side, the left side may abandon its semaphore request and
resource, the entire system can hang up until a one is
perform other operations until it is able to write and then
written to the semaphore request latch concerned.
read a zero in semaphore 1. If the right processor
Semaphore timing becomes critical when both sides
request the same token by attempting to write a zero to it
at the same time. Semaphore logic is specially conceived
to resolve this problem. The logic ensures that only one
side will receive the token if simultaneous requests are
made. The first side to make a request will receive the
token where request do not arrive at the same time. Where
they do arrive at the same time, the logic will assign the
token arbitrarily to one of the ports. It should be noted,
however, that semaphores alone do not guarantee that
access to a resource is secure. As with any powerful
programming technique, errors can be introduced if
performs the same operation with semaphore 0, this
protocol would then allow the two processes to swap 4 k
blocks of dual-port RAM between one another.
The blocks do not have to be any particular size, and may
even be of variable size depending on the complexity of
the software using the semaphore flags. All eight
semaphores could be used to divide the dual-port RAM or
other shared resources into eight parts. Semaphores can
even be assigned different meanings on each side, rather
than having a common meaning as is described in the
above example.
semaphores are misused or misinterpreted. Code integrity Semaphores are a useful form of arbitration in systems
is of the utmost performance when semaphores are being such as disk interfaces where the CPU must be locked out
used instead of slower, more restrictive hardware-intensive of a segment of memory during a data transfer operation,
systems.
and the I/0 device cannot tolerate any wait states. If
Rev. D (29/09/95)
7
M 67025
MATRA MHS
semaphores are used, both the CPU and the I/0 device can a data structure whilst the other processor reads and
access assigned memory segments, without the need for interprets it. A major error condition may be created if the
wait states, once the two devices have determined which interpreting processor reads an incomplete data structure.
memory area is barred to the CPU.
Some sort of arbitration between the two different
processors is therefore necessary. The building processor
requests access to the block, locks it and is then able to
enter the block to update the data structure. Once the
update is completed the data structure may be released.
Semaphores are also useful in applications where no
memory WAIT state is available on one or both sides. On
a semaphore handshake has been performed, both
processors can access their assigned RAM segments at
full speed.
This allows the interpreting processor, to return to read
the complete data structure, thus ensuring a consistent
data structure.
Another application is in complex data structures. Block
arbitration is very important in this case, since one
processor may be responsible for building and updating
Truth Table
Table 1 : Non Contention Read/Write Control.
INPUTS (1)
OUTPUTS
MODE
CS
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
L
IO8–IO15
I/O0–I/O7
Hi–Z
H
Hi–Z
Hi–Z
Deselected : Power Down
Deselected : Power Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
X
Hi–Z
L
L
DATA
Hi–Z
IN
L
L
H
L
Hi–Z
DATA
DATA
IN
IN
L
L
L
DATA
IN
L
H
L
H
L
DATA
Hi–Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
OUT
L
H
L
H
L
Hi–Z
DATA
OUT
OUT
L
H
L
L
DATA
DATA
OUT
X
X
H
L
X
X
H
X
H
L
X
X
H
X
H
X
L
Hi–Z
Hi–Z
Outputs Disabled
H
H
DATA
DATA
DATA
DATA
Read Data in Sema. Flag
Read Data in Sema. Flag
OUT
OUT
OUT
OUT
X
H
L
L
H
X
X
X
X
L
DATA
DATA
Write D
into Sema. Flag
into Sema. Flag
IN
IN
IN
IN
IN0
IN0
X
L
L
DATA
DATA
Write D
X
X
L
–
–
–
–
Not Allowed
Not Allowed
L
X
L
Note :
1.
A
– A
≠ A – A
.
0L
12L
0R
12R
Table 2 : Arbitration Options.
INPUTS
OUTPUTS
OPTIONS
CS
UB
X
L
LB
L
M/S
SEM
H
BUSY
Output
Signal
Input
Signal
–
INT
Busy Logic Master
Busy Logic Slave
Interrupt Logic
–
L
L
L
L
L
L
H
H
H
H
L
X
L
H
X
L
H
–
–
X
L
L
H
X
L
X
X
H
L
H
Output
Signal
–
X
X
X
H
Semaphore Logic*
X
X
L
H
L
Hi–Z
* Inputs Signals are for Semaphore Flags set and test (Write and Read) operations.
8
Rev. D (29/09/95)
MATRA MHS
M 67025
(1, 4)
Table 3 : Interrupt Flag
.
LEFT PORT
RIGHT PORT
FUNCTION
R/WL CSL
OEL
X
AOL–A12L
INTL R/WR CSR
OER
X
AOR–A12R
INTR
(2)
L
X
X
X
L
X
X
L
1FFF
X
X
X
X
X
L
X
L
L
X
X
L
Set Right INT Flag
R
(3)
X
L
1FFF
1FFE
X
H
Reset Right INT Flag
R
(3)
X
X
L
X
X
X
Set Left INT Flag
L
(2)
L
1FFE
H
X
X
Reset Left INT Flag
L
Notes :
1. Assumes BUSY = BUSY = H.
L R
2. If BUSY = L, then NC.
L
3. If BUSY = L, then NC.
R
4. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
(2)
Table 4 : Arbitration
LEFT PORT
RIGHT PORT
FLAGS (1)
FUNCTION
CSL
H
A0L – A12L
CSR
A0R – A12R
BUSYL
BUSYR
X
Any
X
H
H
L
L
X
X
H
H
H
H
H
H
H
H
No Contention
L
No Contention
No Contention
No Contention
H
Any
L
≠ A – A
≠ A – A
0L 12L
0R
12R
ADDRESS ARBITRATION WITH CS LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
H
L
L
H
L
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
H
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
= A – A
LL5R
RL5L
LW5R
LW5R
= A – A
H
L
H
L
L
H
L
L–Port Wins
0R
12R
12R
0L
12L
= A – A
= A
R–Port Wins
0R
0L – A12L
= A
= A – A
Arbitration Resolved
Arbitration Resolved
0R – A12R
0L
12L
= A – A
= A – A
H
0R
12R
0L
12L
Notes :
1. INT Flags Don’t Care.
2. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid ≥ 5 ns before right address.
RV5L = Right Address Valid ≥ 5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW ≥ 5 ns before Right CS.
RL5L = Right CS = LOW ≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
Rev. D (29/09/95)
9
M 67025
MATRA MHS
Table 5 : Example Semaphore Procurement Sequence.
FUNCTION
D0 – D15 LEFT
D0 – D15 RIGHT
STATUS
No Action
1
0
0
1
1
1
Semaphore free
Left Port Writes ”0” to Semaphore
Right Port Writes ”0” to Semaphore
Left Port has semaphore token
No change. Right side has no write
access to semaphore
Left Port Writes ”1” to Semaphore
Left Port Writes ”0” to Semaphore
1
1
0
0
Right port obtains semaphore token
No change. Left port has no write access
to semaphore
Right Port Writes ”1” to Semaphore
Left Port Writes ”1” to Semaphore
Right Port Writes ”0” to Semaphore
Right Port Writes ”1” to Semaphore
Left Port Writes ”0” to Semaphore
Left Port Writes ”1” to Semaphore
0
1
1
1
0
1
1
1
0
1
1
1
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left Port has semaphore token
Semaphore free
Note :
1. This table denotes a sequence of events for only one of the 8 semaphores on the M 67025.
Figure 1. M 67025 – Semaphore Logic.
10
Rev. D (29/09/95)
MATRA MHS
M 67025
Electrical Characteristics
* Notice
Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extented periods may affect reliability.
Supply voltage (VCC-GND) : . . . . . . . . . . . . . . . . . . . -0.3 V to 7.0 V
Input or output voltage applied : . . . . . . . . . . . . . . . (GND – 0.3 V) to
(VCC + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . –65 °C to +150 °C
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
– 55 °C to + 125 °C
Military
Industrial
V
V
V
= 5 V ± 10 %
= 5 V ± 10 %
= 5 V ± 10 %
CC
CC
CC
– 40 °C to + 85 °C
Commercial
0 °C to + 70 °C
DC Parameters
67025–20
67025–25
67025–30
67025–35
Parameter
Description
Version
UNIT VALUE
IND
MIL
IND
MIL
IND
MIL
COM only COM
COM
COM
I
Standby supply current (Both
ports TTL level inputs)
V
L
V
L
V
L
V
L
10
40
10
40
10
50
10
40
10
50
10
40
10
mA
mA
µA
Max
Max
Max
Max
Max
Max
Max
Max
CCSB (1)
CCSB1 (2)
CCOP (3)
CCOP1 (4)
50
I
I
I
Standby supply current (Both
ports CMOS level inputs)
400
4000
320
340
220
220
400
500
400
500
400
500
4000 5000 4000 5000 4000 5000
µA
Operating supply current (Both
ports active)
310
330
210
210
350
370
210
210
280
300
200
200
320
340
200
200
270
290
190
190
300
320
190
190
mA
mA
mA
mA
Operating supply current (One
port active – One port standby)
DC Parameters (Continued)
67025–45
67025–55
Parameter
Description
Version
UNIT
VALUE
IND
MIL
IND
MIL
COM
COM
I
I
I
I
Standby supply current
(Both ports TTL level inputs)
V
L
V
L
V
L
V
L
10
40
10
10
40
10
mA
mA
µA
Max
Max
Max
Max
Max
Max
Max
Max
CCSB (1)
50
50
Standby supply current
(Both ports CMOS level inputs)
400
4000
260
260
180
180
500
5000
260
280
180
180
400
4000
230
230
160
160
500
5000
230
260
160
160
CCSB1 (2)
CCOP (3)
CCOP1 (4)
µA
Operating supply current
(Both ports active)
mA
mA
mA
mA
Operating supply current
(One port active – One port standby)
Notes :
1. CS = CS ≥ 2.2 V.
L R
2. CS = CS ≥ VCC – 0.2 V.
L
R
3. Both ports active – Maximum frequency – Outputs open – OE = VIH.
4. One port active (f = fMAX) – Output open – One port stand-by TTL or CMOS Level Inputs – CS = CS ≥ 2.2 V.
L
R
Rev. D (29/09/95)
11
M 67025
MATRA MHS
67025–20/–25/–30/
–35/–45/–55
PARAMETER
DESCRIPTION
UNIT
VALUE
IL I/O
VIL
(5)
(6)
Input/Output leakage current
Input low voltage
± 10
0.8
2.2
0.4
2.4
5
µA
V
Max
Max
Min
Max
Min
Max
Max
VIH
(6)
Input high voltage
V
VOL
VOH
C IN
C OUT
(7)
(7)
Output low voltage (I/O –I/O
)
15
V
0
Output high voltage
Input capacitance
Output capacitance
V
pF
pF
7
Notes :
5. Vcc = 5.5 V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
6. VIH max = Vcc + 0.3 V, VIL min = –0.3 V or –1 V pulse width 50 ns.
7. Vcc min, IOL = 4 mA, IOH = –4 mA.
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in 2 – CS must be kept between V – 0.2 V and 70 % of V
CC
CC
mind. Data retention voltage and supply current are during the power up and power down transitions.
guaranteed over temperature. The following rules insure
data retention :
3 – The RAM can begin operation > tRC after V
reaches the minimum operating voltage (4.5 volts).
CC
1 – Chip select (CS) must be held high during data
retention ; within V to V – 0.2 V.
CC
CC
Timing
VERSION
UNIT
PARAMETER (max)
TEST CONDITIONS (9)
V
L
UNIT
µA
ICC
ICC
@ VCC = 2 V
Com
20
200
400
DR
DR
@ VCC = 2 V
Ind, Mil
200
µA
DR
DR
Notes :
8. CS = V , Vin = Gnd to V
.
CC
CC
9.
t
RC
= Read cycle time.
12
Rev. D (29/09/95)
MATRA MHS
M 67025
Test Conditions (8)
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
: GND to 3.0 V
: 5 ns
: 1.5 V
Output Reference Levels : 1.5 V
Output Load : see figures 2, 3
Figure 2. Output Load.
Figure 3. Output Load (for t , t , t , and t ).
HZ LZ WZ OW
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
M
M
M
M
M
M
READ CYCLE
Symbol Symbol
67025–20 67025–25 67025–30 67025–35 67025–45 67025–55
UNI
T
PARAMETER
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
(4)
(5)
TAVAVR
TAVQV
TELQV
t
t
t
Read cycle time
20
–
–
25
–
–
30
–
–
35
–
–
45
–
–
55
–
–
ns
ns
ns
RC
Address access time
20
20
25
25
30
30
35
35
45
45
55
55
AA
Chip Select access
time (3)
–
–
–
–
–
–
ACS
TBLQV
TGLQV
TAVQX
TELQZ
TEHQZ
TPU
t
t
t
t
t
t
t
t
Byte enable access
time (3)
–
–
20
11
–
–
–
25
13
–
–
–
30
15
–
–
–
35
20
–
–
–
45
25
–
–
–
55
30
–
ns
ns
ns
ns
ns
ns
ns
ns
ABE
AOE
OH
LZ
Output enable access
time
Output hold from
address change
3
3
3
3
3
3
Output low Z time (1,
2)
3
–
3
–
3
–
3
–
5
–
5
–
Output high Z time (1,
2)
–
15
–
–
15
–
–
15
–
–
15
–
–
20
–
–
25
–
HZ
Chip Select to power
up time (2)
0
0
0
0
0
0
PU
TPD
Chip disable to power
down time (2)
–
50
–
–
50
–
–
50
–
–
50
–
–
50
–
–
50
–
PD
TSOP
SEM flag update pulse
(OE or SEM)
12
12
15
15
15
15
SOP
Notes : 1. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 2 and 3).
2. This parameters is guaranteed but not tested.
3. To access RAM CS = V , UB or LB = V , SEM = V . To access semaphore CS = V , SEM = V . Refer to table 1.
IL
IL
IH
IH
IL
4. STD symbol.
5. ALT symbol.
Rev. D (29/09/95)
13
M 67025
MATRA MHS
Timing Waveform of Read Cycle n° 1, Either Side (1, 2, 4)
Timing Waveform of Read Cycle n° 2, Either Side (1, 3, 5)
Timing Waveform of Read Cycle n° 3, Either Side (1, 3, 4, 5)
Notes : 1. R/W is high for read cycles.
2. Device is continuously enabled, CS = V , UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
3. Addresses valid prior to or coincident with CS transition low.
4. OE = V
.
IL
5. To access RAM, CS = V , UB or LB = V , SEM = V . To access semaphore, CS = V , SEM = V . Refer to table 1.
IL
IL
IH
IH
IL
14
Rev. D (29/09/95)
MATRA MHS
M 67025
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
M
M
M
M
M
M
WRITE CYCLE
67025–20 67025–25 67025–30 67025–35 67025–45 67025–55
UNI
T
PARAMETER
Symbol Symbol
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
(4)
(5)
TAVAVW
t
t
t
Write cycle time
20
15
15
–
–
–
25
20
20
–
–
–
30
25
25
–
–
–
35
30
30
–
45
40
40
–
–
–
55
45
45
–
–
–
ns
ns
ns
WC
Chip select to end of
write (3)
TELWH
TAVWH
SW
AW
Address valid to end
of write
TAVWL
TWLWH
TWHAX
TDVWH
t
t
t
t
Address Set–up Time
Write Pulse Width
0
15
0
–
–
–
–
0
20
0
–
–
–
–
0
25
0
–
–
–
–
0
30
0
0
35
0
–
–
–
–
0
40
0
–
–
–
–
ns
ns
ns
ns
AS
–
–
–
WP
WR
DW
Write Recovery Time
Data Valid to end of
write
13
15
20
25
25
30
TGHQZ
t
HZ
Output high Z time (1,
2)
–
15
–
15
–
15
–
15
–
20
–
25
ns
TWHDX
TWLQZ
t
t
Data hold time (4)
0
–
–
0
–
–
0
–
–
0
–
–
0
–
–
0
–
–
ns
ns
DH
Write enable to output
in high Z (1, 2)
15
15
15
15
20
25
WZ
TWHQX
TSWRD
TSPS
t
t
t
Output active from
end of write (1, 2, 4)
0
–
–
–
0
–
–
–
0
–
–
–
0
–
–
–
0
–
–
–
0
–
–
–
ns
ns
ns
OW
SEM flag write to
read time
10
10
10
10
10
10
10
10
10
10
10
10
SWRD
SPS
SEM flag contention
window
Notes : 1. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 2 and 3).
2. This parameters is guaranteed but not tested.
3. To access RAM CS = V , UB or LB = V , SEM = V . To access semaphore CS = V , SEM = V . This condition must be valid
IL
IL
IH
IH
IL
for entire t time.
SW
4. The specification for t must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
DH
and t
values will vary over voltage and temperature, the actual t will always be smaller than the actual t
.
OW
DH
OW
5. STD symbol.
6. ALT symbol.
Rev. D (29/09/95)
15
M 67025
MATRA MHS
Timing Waveform of Write Cycle n° 1, R/W Controlled Timing (1, 2, 3, 7)
Timing Waveform of Write Cycle n° 2, CS Controlled Timing (1, 2, 3, 5)
Notes :
1. R/W must be high during all address transitions.
2. A write occurs during the overlap (t or t ) of a low CS or SEM and a low R/W.
SW
WP
3.
t
is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle.
WR
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high imped-
ance state.
6. Transition is measured ± 500 mV from steady state with a 5pF load (including scope and jig).This parameter is sampled and not
100 % tested.
7. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t or (t
+ t ) to allow the I/O
DW
WP
WZ
drivers to turn off and data to be placed on the bus for the required t . If OE is high during an R/W controlled write cycle, this
DW
requirement does not apply and the write pulse can be as short as the specified t
.
WP
8. To access RAM, CS = V . SEM = V
.
IL
IH
9. To access upper byte CS = V , UB = V , SEM = V .
IL
IL
IH
To access lower byte CS = V , LB = V , SEM = V .
IL
IL
IH
16
Rev. D (29/09/95)
MATRA MHS
M 67025
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
M
M
M
M
M
M
WRITE
CYCLE
67025–20
67025–25
67025–30
67025–35
67025–45
67025–55
PARAMETER
UNIT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
BUSY TIMING (For Master 67025 only)
t
t
t
t
t
t
t
t
BUSY Access time
to address
–
–
–
–
–
–
5
–
20
15
–
–
–
–
–
–
5
–
25
20
–
–
–
–
–
–
5
–
30
25
–
–
–
–
–
–
5
–
35
30
–
–
–
–
–
–
5
–
35
30
–
–
–
–
–
–
5
–
45
40
ns
ns
ns
ns
ns
ns
ns
ns
BAA
BDA
BAC
BDC
WDD
DDD
APS
BUSY Disable time
to address
BUSY Access time
to Chip Select
15
20
25
30
30
40
BUSY Disable time
to Chip Select
13
17
20
25
25
35
Write Pulse to data Delay
(1)
45
50
55
60
70
80
Write data valid to read
data delay (1)
35
35
40
45
55
65
Arbitration priority
set–up time (2)
–
–
–
–
–
–
BUSY disable to valid
data
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
BDD
BUSY TIMING (For Slave 67025 only)
t
Write to BUSY input (4)
0
–
–
0
–
–
0
–
–
0
–
–
0
–
–
0
–
–
ns
ns
WB
WH
t
Write hold after BUSY
(5)
15
17
20
25
25
25
t
t
Write pulse to data delay
(6)
–
–
45
35
–
–
50
35
–
–
55
40
–
–
60
45
–
–
70
55
–
–
80
65
ns
ns
WDD
DDD
Write data valid to read
data delay (6)
Notes : 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For
Master 67025 only).
2. To ensure that the earlier of the two ports wins.
3.
t
is a calculated parameter and is the greater of 0, t
– t (actual) ot t
WP
– t
DW
(actual).
BDD
WDD
DDD
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)”.
Rev. D (29/09/95)
17
M 67025
MATRA MHS
Timing Waveform of Read with BUSY (2, 3, 4) (For Master 67025)
Notes :
1. To ensure that the earlier of the two port wins.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE = L for the reading port.
Timing Waveform of Write with Port-to-Port (1, 2, 3) (For Slave 67025 Only)
Notes :
1. Assume BUSY = H for the writing port, and OE = L for the reading port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
18
Rev. D (29/09/95)
MATRA MHS
M 67025
Timing Waveform of Write with BUSY (For Slave 67025)
Timing Waveform of Contention Cycle n° 1, CS Arbitration
(For Master 67025 only)
Rev. D (29/09/95)
19
M 67025
MATRA MHS
Timing Waveform of Contention Cycle n° 2, Address Valid Arbitration
(For Master 67025 only) (1)
Left Address Valid First :
Right Address Valid First :
Note :
1. CS = CS = V
L R IL
AC Parameters
INTERRUPT
TIMING
67025–20
67025–25
67025–30
67025–35
67025–45
67025–55
UNIT
PARAMETER
SYMBOL
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
t
t
t
Address set–up time
Write recovery time
Interrupt set time
0
0
–
–
–
–
0
0
–
–
–
–
0
0
–
–
–
–
0
0
–
–
–
–
0
0
–
–
–
–
0
0
–
–
–
–
ns
ns
ns
ns
AS
WR
INS
INR
17
17
20
20
25
25
30
30
35
35
40
40
Interrupt reset time
20
Rev. D (29/09/95)
MATRA MHS
M 67025
Waveform of Interrupt Timing (1)
Notes :
1. All timing is the same for left and right ports. Port “A” may bei either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
32-bit Master/Slave Dual-Port Memory Systems
Notes :
1. No arbitration in M 67025 (SLAVE). BUSY-IN inhibits write in M 67025 SLAVE.
Rev. D (29/09/95)
21
M 67025
MATRA MHS
Timing Waveform of Semaphore Read after Write Timing, Either Side (1)
Note :
1. CS = V for the duration of the above timing (both write and read cycle).
IH
Timing Waveform of Semaphore Contention (1, 3, 4)
Notes :
1.
2. Either side “A” = left and side “B” = right, or side “A” = right and side “B” = left.
3. This parameter is measured from the point where R/W or SEM goes high until R/W or SEM goes high.
D
= D = V , CS = CS = V , semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
OR OL IL R L IH
A
A
B
B
4. If t
is violated, the semaphore will fall positively to one side or the other, but there is no guaranted which side will obtain the
SPS
flag.
22
Rev. D (29/09/95)
MATRA MHS
M 67025
Ordering Information
TEMPERATURE RANGE PACKAGE
DEVICE SPEED
FLOW
C
M
RT
67025V
25
M = 5 V version
L = 3.3 V version
blank
/883
= MHS standards
= MIL-STD 883 Class B or S
20 ns
25 ns
30 ns
35 ns
45 ns
55 ns
QR = 84 pins J CERQUAD
8R = 84 pins PIN GRID ARRAY
SR = 84 pins PLCC
42 = 84 pins LCC
K2 = 84 pins MQFPF*
RT = 100 pins VQFP
8K × 16 Dual Port RAM
C = Commercial
I = Industrial
M = Military
S = Space
0° to +70°C
–40° to +85°C
–55° to +125°C
–55° to +125°C
L
V
EL
EV
= Low power
= Very low power
= Low power and rad tolerant
= Very low power and rad tolerant
* 50 mils pitch
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication
and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. D (29/09/95)
23
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