T5750-6AQJ [ATMEL]
UHF ASK/FSK Transmitter; 超高频ASK / FSK发射器
| 型号： | T5750-6AQJ |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK/FSK Transmitter |
| 文件： | 总13页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Integrated PLL Loop Filter
• ESD Protection also at ANT1/ANT2
(4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM)
• High Output Power (5.5 dBm) with Low Supply Current (8.5 mA)
• Modulation Scheme ASK/FSK
– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the
XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller
• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
• Single Li-cell for Power Supply
• Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C/+125°C
• Package TSSOP8L
UHF ASK/FSK
Transmitter
• Single-ended Antenna Output with High Efficient Power Amplifier
• CLK Output for Clocking the Microcontroller
• One-chip Solution with Minimum External Circuitry
• 125°C Operation for Tire Pressure Systems
T5750
1. Description
The T5750 is a PLL transmitter IC which has been developed for the demands of RF
low-cost transmission systems at data rates up to 32 kBaud. The transmitting
frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK
systems.
Figure 1-1. System Block Diagram
UHF ASK/FSK
UHF ASK/FSK
Remote control transmitter
Remote control receiver
1 Li cell
T5750
T5760/
T5761
1 to 3 Micro-
controller
Demod
Control
Encoder
ATARx9x
PLL
Keys
Antenna Antenna
XTO
VCO
LNA
PLL
XTO
LNA
VCO
4546E–RKE–02/07
2. Pin Configuration
Figure 2-1. Pinning TSSOP8L
CLK
PA_ENABLE
ANT2
1
2
3
4
8
7
6
5
ENABLE
GND
VS
ANT1
XTAL
Table 2-1.
Pin
Pin Description
Symbol
Function
Configuration
VS
Clock output signal for micro con roller
The clock output frequency is set by the
crystal to fXTAL/4
100Ω
100Ω
CLK
1
CLK
50 kΩ
PA_ENABLE
UREF = 1.1V
Switches on power amplifier, used for
ASK modulation
2
PA_ENABLE
20 µA
ANT1
ANT2
3
4
ANT2
ANT1
Emitter of antenna output stage
Open collector antenna output
2
T5750
4546E–RKE–02/07
T5750
Table 2-1.
Pin
Pin Description (Continued)
Symbol
Function
Configuration
VS
VS
1.5 kΩ
1.2 kΩ
5
XTAL
Connection for crystal
XTAL
182 µA
6
7
VS
Supply voltage
Ground
See ESD protection circuitry (see Figure 4-5 on page 9)
See ESD protection circuitry (see Figure 4-5 on page 9)
GND
200 kΩ
ENABLE
8
ENABLE
Enable input
Figure 2-2. Block Diagram
T5750
Power up/down
f
CLK
PA_ENABLE
ANT2
ENABLE
4
1
8
7
f
64
GND
2
PDF
CP
VS
3
4
6
5
LF
ANT1
PA
VCO
XTO
XTAL
PLL
3
4546E–RKE–02/07
3. General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmit-
ters to be assembled. The VCO is locked to 64 × fXTAL hence a 13.5672 MHz crystal is needed
for a 868.3 MHz transmitter and a 14.2969 MHz crystal for a 915 MHz transmitter. All other PLL
and VCO peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal con-
nected in series to GND are needed as external elements.
The crystal oscillator together with the PLL needs typically < 1 ms until the PLL is locked and the
CLK output is stable. There is a wait time of ≥ 4 ms must be used until the CLK is used for the
microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly inde-
pendent from the load impedance. The delivered output power is hence controllable via the
connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high
power efficiency of η= Pout/(IS,PA × VS) of 24% for the power amplifier at 868.3 MHz results when
an optimized load impedance of ZLoad = (166 + j226)Ω is used at 3V supply voltage.
4. Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very
small amount of current, so that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L
only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The
VCO locks to 64 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are
on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform
the ASK modulation.
4.1
4.2
ASK Transmission
The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK
signal can be taken to clock the microcontroller and the output power can be modulated by
means of pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the microcon-
troller switches back to internal clocking. The T5750 is switched back to standby mode with
ENABLE = L.
FSK Transmission
The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK
signal can be taken to clock the microcontroller and the power amplifier is switched on with
PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to
switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain
output port, thus changing the reference frequency of the PLL. If the switch is closed, the output
frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L
and the microcontroller switches back to internal clocking. The T5750 is switched back to
standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol-
lowing tolerances are considered.
4
T5750
4546E–RKE–02/07
T5750
Figure 4-1. Tolerances of Frequency Modulation
VS
CStray1
CStray2
LM
C4
XTAL
CM
RS
C0
C5
CSwitch
Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capaci-
tances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the
crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21.5 kHz
typical with worst case tolerances of ±16.8 kHz to ±28.0 kHz results.
4.3
CLK Output
An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS
compatible if the load capacitance is lower than 10 pF.
4.3.1
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel®’s
ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the
T5750 with ENABLE = H, and after 4 ms to assume the clock signal of the transmission IC, so
that the message can be sent with crystal accuracy.
4.3.2
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of ZLoad,opt = (166 + j226)Ω at 868.3 MHz. There must be a low
resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 7.7 mA and the maximum output power is
delivered to a resistive load of 475Ω if the 0.53 pF output capacitance of the power amplifier is
compensated by the load impedance.
An optimum load impedance of:
Z
Load = 475Ω || j/(2 × p × f × 0.53 pF) = (166 + j226)Ω thus results for the maximum output
power of 5.5 dBm.
The load impedance is defined as the impedance seen from the T5750’s ANT1, ANT2 into the
matching network. Do not confuse this large signal load impedance with a small signal input
impedance delivered as input characteristic of RF amplifiers and measured from the application
into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 475Ωwhere the parallel imag-
inary part should be kept constant.
Output power measurement can be done with the circuit of Figure 4-2 on page 6. Note that the
component values must be changed to compensate the individual board parasitics until the
T5750 has the right load impedance ZLoad,opt = (166 + j226)Ω at 868.3 MHz. Also the damping of
the cable used to measure the output power must be calibrated out.
5
4546E–RKE–02/07
Figure 4-2. Output Power Measurement
VS
C1
1 nF
L1 10 nH
Power
meter
Z = 50Ω
C2
ANT1
1.5 pF
C3
ZLopt
Rin
50Ω
2.7 pF
ANT2
4.4
Application Circuit
For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended (see Figure
4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the
power amplifier where C1 typically is 3.9 pF/NP0 and C2 is 1 pF/NP0; for C2 two capacitors in
series should be used to achieve a better tolerance value and to have the possibility to realize
the ZLoad,opt by using standard valued capacitors.
C1 forms together with the pins of T5750 and the PCB board wires a series resonance loop that
suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the
best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and
ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop
antenna is too high.
L1 (≈ 50 nH to 100 nH) can be printed on PCB. C4 should be selected so that the XTO runs on
the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF
load-capacitance crystal.
6
T5750
4546E–RKE–02/07
T5750
Figure 4-3. ASK Application Circuit
S1
VDD
VSS
BPXY
BPXY
BPXY
OSC1
ATARx9x
VS
1
S2
20
BPXY
7
T5750
Power up/down
CLK
ENABLE
f
4
1
2
8
7
f
64
PA_ENABLE
GND
PDF
CP
C3
C2
ANT2
VS
3
4
6
5
VS
Loop
Antenna
LF
C1
ANT1
XTAL
XTAL
PA
VCO
XTO
PLL
L1
C4
VS
7
4546E–RKE–02/07
Figure 4-4. FSK Application Circuit
S1
VDD
BPXY
BPXY
BPXY
OSC1
ATARx9x
VS
1
20
18
S2
VSS
BP42/T2O
BPXY
7
T5750
Power up/down
CLK
ENABLE
f
4
1
2
8
7
f
64
PA_ENABLE
GND
PDF
CP
C3
C2
ANT2
VS
3
4
6
5
Loop
Antenna
LF
VS
C1
C5
XTAL
ANT1
XTAL
PA
VCO
XTO
PLL
L1
C4
VS
8
T5750
4546E–RKE–02/07
T5750
Figure 4-5. ESD Protection Circuit
VS
ANT1
ANT2
CLK
PA_ENABLE
XTAL
ENABLE
GND
5. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Minimum
Maximum
Unit
V
Supply voltage
VS
5
100
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
Input voltage
Ptot
mW
°C
°C
°C
V
Tj
Tstg
150
–55
–55
–0.3
125
Tamb
125
(VS + 0.3)(1)
VmaxPA_ENABLE
Note:
1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.
6. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
170
K/W
7. Electrical Characteristics
VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Power down,
V
ENABLE < 0.25V, –40°C to 85°C
350
7
nA
µA
nA
Supply current
VPA_ENABLE < 0.25V, –85°C to +125°C
VPA_ENABLE < 0.25V, 25°C
IS_Off
<10
(100% correlation tested)
Power up, PA off, VS = 3V,
VENABLE > 1.7V, VPA_ENABLE < 0.25V
IS
3.6
8.5
5.5
4.6
11
8
mA
mA
Supply current
Output power
Power up, VS = 3.0,
VENABLE > 1.7V, VPA_ENABLE > 1.7V
IS_Transmit
PRef
VS = 3.0V, Tamb = 25°C,
f = 868.3 MHz, ZLoad = (166 + j226)Ω
3.5
dBm
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
9
4546E–RKE–02/07
7. Electrical Characteristics (Continued)
VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Tamb = –40°C to +85°C,
VS = 3.0V
VS = 2.0V
Output power variation for the full
temperature range
∆PRef
∆PRef
–1.5
–4.0
dB
dB
Tamb = –40°C to +125°C,
Output power variation for the full VS = 3.0V
∆PRef
∆PRef
–2.0
–4.5
dB
dB
temperature range
VS = 2.0V,
POut = PRef + ∆PRef
Achievable output-power range
Selectable by load impedance
POut_typ
–3
+5.5
dBm
fCLK = f0/128
Load capacitance at pin CLK = 10 pF
fO ±1 × fCLK
fO ±4 × fCLK
Spurious emission
–52
–52
dBc
dBc
other spurious are lower
f
XTO = f0/32
fXTAL = resonant frequency of the XTAL,
CM ≤ 10 fF, load capacitance selected
Oscillator frequency XTO
(= phase comparator frequency)
fXTO
accordingly
Tamb = –40°C to +85°C,
Tamb = –40°C to +125°C
–30
–40
fXTAL
+30
+40
ppm
ppm
PLL loop bandwidth
250
–116
–80
kHz
Referred to fPC = fXT0,
25 kHz distance to carrier
Phase noise of phase comparator
In loop phase noise PLL
Phase noise VCO
–110
–74
dBc/Hz
25 kHz distance to carrier
dBc/Hz
at 1 MHz
at 36 MHz
–89
–120
–86
–117
dBc/Hz
dBc/Hz
Frequency range of VCO
fVCO
868
928
MHz
Clock output frequency (CMOS
microcontroller compatible)
f0/256
MHz
V0h
V0l
VS × 0.8
V
V
Voltage swing at pin CLK
CLoad ≤ 10 pF
VS × 0.2
110
7
Series resonance R of the crystal
Capacitive load at pin XT0
Rs
Ω
pF
FSK modulation frequency rate
ASK modulation frequency rate
Duty cycle of the modulation signal = 50%
Duty cycle of the modulation signal = 50%
0
0
32
kHz
kHz
32
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
V
V
µA
ENABLE input
1.7
1.7
20
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
V
V
µA
(1)
PA_ENABLE input
VS
5
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
10
T5750
4546E–RKE–02/07
T5750
8. Ordering Information
Extended Type Number
Package
Remarks
T5750-6AQJ
TSSOP8L
Taped and reeled, Marking: T570, Pb-free
9. Package Information
Package: TSSOP 8L
Dimensions in mm
3±0.1
3±0.1
+0.06
3.8±0.3
4.9±0.1
0.31-0.07
0.65 nom.
3 x 0.65 = 1.95 nom.
8
5
4
technical drawings
according to DIN
specifications
1
Drawing-No.: 6.543-5083.01-4
Issue: 2; 15.03.04
11
4546E–RKE–02/07
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
• Pb-free logo on page 1 deleted
4546E-RKE-02/07
• Pb-free logo on page 1 added
4546D-RKE-09/05
4546C-RKE-05/05
• Ordering Information on page 11 changed
• Put datasheet in a new template
• Rename M4xCx9x in ATARx9x
• Table “Absolute Maximum Ratings” on page 9: New heading rows added
• Table “Absolute Maximum Ratings” on page 9: row “Input voltage” added
• Table “Absolute Maximum Ratings” on page 9: table note 1 added
• Table “Electrical Characteristics” on pages 9 to 10: row “PA_ENABLE input”
changed
4546B-RKE-07/04
• Table “Electrical Characteristics” on pages 9 to 10: table note 1 added
• Table “Ordering Informations” on page 11: Remarks changed
12
T5750
4546E–RKE–02/07
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4546E–RKE–02/07
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