U4256BM-NFSG3 [TEMIC]
PLL Frequency Synthesizer, BICMOS, PDSO20, SSOP-20;
| 型号： | U4256BM-NFSG3 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | PLL Frequency Synthesizer, BICMOS, PDSO20, SSOP-20 ATM 异步传输模式 信息通信管理 光电二极管 |
| 文件： | 总14页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U4256BM
Frequency Synthesizer for Radio Tuning
Description
The U4256BM is a synthesizer IC for FM receiver and an recommended also for RDS (Radio Data System)
AM up-convertion system in BICMOS technology. applications. It is controlled by 3-wire bus and contains also
Together with the AM/FM IC U4255BM, it performs a switches and Digital to Analog Converters (DACs) for soft-
complete AM/FM car radio front end, which is ware controlled alignment of the AM/FM tuner.
FD eRaetfuerreencse oscillator up to 15 MHz (tuned)
D Four programmable switching outputs (open drain)
D Three DACs for software controlled tuner alignment
D Low power consumption
D Oscillator buffer output (for AM up/down conversion)
D Two programmable 16-bit dividers
D Fine-tuning steps possible
D High S/N ratio
D Fast response time due to integrated loop push-pull stage
D 3-wire bus (enable, clock and data; 3 V and 5 V micro- D Integrated band gap * only one supply voltage
controllers acceptable)
necessary
Block Diagram
SWO1 SWO2 SWO3 SWO4
7
8
9
10
Tuning
13
OSCIN
Oscillator
Switching outputs
12
DAC3
3–bit
OSCOUT
5
DAC3
V
15
Ref
OSC
buffer
MX2LO
DAC2
DAC1
4
3
DAC2
DAC1
17
16
18
CLK
DATA
EN
3W–
bus
interface
R–
divider
DAC
AM/FM
V
Ref
1
2
19
FM–
preamp
N–
divider
Phase
Current
sources
FMOSCIN
PDO
PD
detector
Band-gap
6
20
14
11
GNDan
V5
GND
VS
Figure 1. Block diagram
Ordering Information
Extended Type Number
U4256BM-NFS
Package
SSO20
SSO20
Remarks
Tube
Taped and reeled
U4256BM-NFSG3
Rev. A5, 06-Oct-00
1 (14)
Preliminary Information
U4256BM
Pin Description
Pin
1
Symbol
PDO
Function
1
20
19
18
17
16
15
GNDan
FMOSCIN
EN
PDO
Phase detector output
Pulsed current output
Digital-to-analog converter 1
Digital-to-analog converter 2
Digital-to-analog converter 3
Supply voltage analog part
Switching output 1
2
PD
2
3
DAC1
DAC2
DAC3
VS
PD
4
5
3
4
DAC1
DAC2
DAC3
VS
6
7
SWO1
SWO2
SWO3
SWO4
GND
CLK
8
Switching output 2
9
Switching output 3
5
6
DATA
MX2LO
10
11
12
13
14
15
16
17
18
19
20
Switching output 4
U4256BM
Ground, digital part
OSCOUT Reference oscillator output
OSCIN
V5
Reference oscillator input
Capacitor band gap
14
13
12
11
7
SWO1
SWO2
SWO3
V5
MX2LO Oscillator buffer output
8
OSCIN
DATA
CLK
EN
Data input
Clock
9
Enable
OSCOUT
GND
FMOSCIN FM-oscillator input
GNDan Ground, analog part
10
SWO4
Figure 2. Pinning
If this oscillator tuning feature is not used, the internal
capacities have to be switched off and the oscillator has
to be operated with high-quality external capacities to
ensure that the operational frequency is exactly
10.250 MHz.
Functional Description
For a tuned FM – broadcast receiver, the following parts
are needed:
– voltage-controlled oscillator (VCO)
– antenna amplifier tuned circuit
– RF amplifier tuned circuit
When dimensioning the oscillator circuit, it is important
that the additional capacities enable the oscillator to
Typical modern receivers with electronic tuning are tuned operate through its complete tracking range. The oscillat-
to the desired FM frequency by the frequency synthesizer
IC U4256BM. The special design allows to build
software-controlled tuner alignment systems. Two pro-
grammable DACs (Digital-to-Analog Converter) support
the computer-controlled alignment. The output of the
PLL is a tuning voltage which is connected to the VCO
of the receiver IC. The output of the VCO is equal to the
desired station frequency plus the IF (10.7 MHz). The RF
and the oscillator signal (VCO) are both input to the mixer
that translates the desired FM channel signal to the fixed
IF signal. For FM, the double-conversion system of the
receiver requires exactly 10.7 MHz for the first IF
ing ability depends very strongly on the used crystal
oscillator. Initializing the oscillator should be established
without switching any additional capacities to guarantee
that the oscillator starts to operate properly. Due to the
lower quality of the integrated capacities compared to
discrete capacities, the amount of the switched integrated
capacities should always be minimized. (if necessary re-
duce tracking range or use another crystal oscillator)
The U4256BM has a very fast response time of maximum
800 ms (at 2 mA, fref = 100 kHz, measured on MPX
signal). It performs a high signal to noise ratio.
frequency, which determines the center frequency of the Only one supply voltage is necessary, due to a
software-controlled integrated second IF filter. integrated band gap.
2 (14)
Rev. A5, 06-Oct-00
Preliminary Information
U4256BM
Absolute Maximum Ratings
All voltages are referred to GND (Pin 11)
Parameters
Symbol
Value
Unit
V
Analog supply voltage
Input voltage BUS
Pin 6
V
S
8 to 15
–0.3 to +12
–1 to +5
Pins 16, 17 and 18
Pins 7, 8, 9 and 10
V
I
V
Output current switches
(see figure 10)
I
mA
O
Drain voltage switches
Ambient temperature range
Storage temperature range
Junction temperature
Pins 7, 8, 9 and 10
V
15
–40 to +85
–40 to +125
125
V
°C
°C
°C
V
OD
T
amb
T
stg
T
j
Electrostatic handling
V
ESD
t.b.d.
Thermal Resistance
Parameters
Symbol
Value
140
Unit
K/W
Junction ambient
when soldered to PCB
R
thJA
Operating Range
All voltages are referred to GND (Pin 11)
Parameter
Symbol
Min.
8
Typ.
8.5
Max.
14
Unit
Supply voltage range
Pin 6
V
S
V
°C
Ambient temperature
Tamb
–40
70
+85
160
65535
15
Input frequency FMOSCIN
Programmable N, R divider
Crystal reference oscillator
Pin 19
f
MHz
in
SF
2
Pins 12 and 13
fXTAL
0.1
MHz
Electrical Characteristics
Test conditions (unless otherwise specified): V = +8.5 V, T
= +25°C
S
amb
Parameters
Supply voltage
Test Conditions / Pins
Symbol
Min.
Typ.
8.5
10
Max.
12
Unit
V
Pin 6
Analog supply voltage
Supply current
Analog supply current
OSCIN
V
S
8
Pin 20
I
4.5
100
20
mA
S
Pin 13
f = 0.1 to 15 MHz
Pin 15
Input voltage
OSC
mV
rms
OSC buffer (MX2LO)
Output AC voltage
Output DC voltage
FMOSCIN
At Pin15: 47 pF and 1 kW
v
80
120
1.9
200
2.1
mV
V
MX2LO
pp
V
MX2LO
1.6
Pin 19
Input voltage
f = 70 to 120 MHz
f = 120 to 160 MHz
FMOSC
FMOSC
40
150
mV
mV
rms
rms
Rev. A5, 06-Oct-00
3 (14)
Preliminary Information
U4256BM
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): V = +8.5 V, T
= +25°C
S
amb
Parameters
Pulsed current output PD
Output current Bit 71, 70 = ‘00’
Output current Bit 71, 70 = ‘001’
Output current Bit 71, 70 = ‘10’
Output current Bit 71, 70 = ‘11’
Leakage current
Test Conditions / Pins
Pin 2
PD = 2.5 V
Symbol
Min.
Typ.
Max.
Unit
± IPD
20
80
25
100
500
2000
30
120
600
2400
20
µA
µA
µA
µA
nA
400
1600
PD = 2.5 V
Pin 1
± IPDL
PDO
Saturation voltage HIGH
LOW
I = 15 mA
V
V
V – 0.5
V
V
PDOH
S
0.1
0.2
0.4
PDOL
SWO1, SWO2, SWO3, SWO4 (open drain) Pins 7, 8, 9 and 10
Output leakage current
HIGH
LOW
V7,8,9,10 = 8.5 V
I
100
400
nA
SWOH
Output voltage
DAC1, DAC2
Output current
Output voltage
I = 1 mA
V
100
mV
SWOL
Pins 3 and 4
I
± 1
mA
V
DAC1, 2
V
DAC1, 2
0.3
0.6
V – 0.5
S
Gain range (resolution 256 steps)
Offset range (resolution 24 steps)
DAC 3
2.3
0.7
–0.6
V
Pin 5
Output current
I
± 1
mA
V
DAC3
Output voltage (resolution 16 steps)
V
0.25
6
DAC3
3-Wire Bus Description
16-bit command
EN
DATA
CLK
LSB
BYTE 1
MSB LSB
BYTE 2
MSB
24-bit command
EN
DATA
CLK
LSB
MSB
LSB
BYTE 1
BYTE 2
MSB LSB
BYTE 3
MSB
e.g., Divider
IPD
25
27 28
26
R–Divider
211
21
24
29 210
212
0
20
22 23
213 214 215
0
0
1
2
OSCB
P–2 P–2 P–2
DAC3
Status 0
Addr.
Figure 3. Pulse diagram
4 (14)
Rev. A5, 06-Oct-00
Preliminary Information
U4256BM
Data Transfer
A
MSB
Byte 3
STATUS 0
LSB MSB
BYTE 2
LSB MSB
BYTE 1
LSB
ADDR
DAC3
1
R – DIVIDER
2
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
IPD
OSCB
P–2 P–2 P–2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0 = on,
1 = off
B71 B70
B69
B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50
B
MSB
Byte 3
LSB MSB
BYTE 2
LSB MSB
BYTE 1
LSB
ADDR
STATUS 1
N – DIVIDER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AM=1 SWO4 SWO3 SWO2 SWO1
0
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
FM=0 1=off,
1=off,
0=on
1=off,
0=on
1=off,
0=on
DAC
0=on
B35 B34
B33
B32
B31
B30 B29 B28 B27 B25 B24 B23 B22 B22 B21 B20 B19 B18 B17 B16 B15 B14
C
MSB
BYTE 2
LSB MSB
BYTE 1
LSB
ADDR
DAC1 OFFSET
DAC1 GAIN
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
O–2
O–2
O–2
O–2
B46
O–2
O–2
G–2
G–2
G–2
G–2
B40
G–2
B39
G–2
G–2
G–2
B49
B48
B47
B45
B44
B43
B42
B41
B38
B37
B36
D
MSB
BYTE 2
LSB MSB
BYTE 1
DAC2 GAIN
LSB
ADDR
DAC2 OFFSET
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
O–2
O–2
O–2
O–2
B10
O–2
O–2
B8
G–2
B7
G–2
B6
G–2
B5
G–2
B4
G–2
B3
G–2
B2
G–2
B1
G–2
B13
B12
B11
B9
B0
E
MSB
BYTE 2
LSB MSB
BYTE 1
Not used
LSB
X
ADDR
Oscillator tuning function
8pF 32pF 16pF 8pF 4pF
B85 B84 B83 B82 B81 B80
1
0
2pF
1pF 0.5pF
B79 B78
X
X
X
X
X
B77 B76 B75 B74 B73 B72
Rev. A5, 06-Oct-00
5 (14)
Preliminary Information
U4256BM
Timing Information
Parameters
Test Conditions / Pins
Symbol
Min.
2.0
Typ.
Max.
Unit
3-wire bus, ENABLE, DATA, CLOCK
Pins 16, 17, 18
Input voltage
HIGH
LOW
V
BUSH
V
V
MHz
V
BUSL
1.0
1.0
Clock frequency
Period of CLK
HIGH
LOW
t
250
250
ns
ns
ns
H
t
L
Rise time EN, DATA, CLK
Fall time EN, DATA, CLK
Set-up time
t
400
100
r
f
s
t
ns
ns
ns
ns
t
100
250
0
Hold time EN
t
HEN
HDA
Hold time DATA
t
Bus Timing
t
R
t
F
Enable
Data
t
t
HEN
S
t
F
t
R
tHDA
t
S
t
R
t
F
Clock
t
H
t
L
Figure 4. Bus timing
6 (14)
Rev. A5, 06-Oct-00
Preliminary Information
U4256BM
Bus Control
The charge-pump current can be choosen by setting the The gains of DAC1 and DAC2 have a range of
0.7 x V(PDO) to 2.15 x V(PDO). V(PDO) is the PLL
tuning voltage output. This range is divided into 256
Bits 71 and 70 as following:
IPD (µA)
25
B71
0
B70
0
steps.
So
one
step
is
approximately
(2.15–0.7)/256 = 5.664 m. The gain can be controlled by
0
7
100
0
1
the Bits 36 to 43 (G–2 to G–2 ) as following:
500
1
0
Gain DAC1
Approx.
Gain DAC2
Approx.
B43 B42 B41 B40 B39 B38 B37 B36
B7 B6 B5 B4 B3 B2 B1 B0
2000
1
1
0.7
0.70566
0.71133
0.71699
...
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
The oscillator buffer output can be switched by the OSCB
Bit as following (Bit 69):
0
...
0
0
...
0
0
...
1
0
...
1
0
...
0
0
...
1
1
...
0
1
...
1
MX2LO AC Voltage
B69
0
ON
1.00019
...
2.1386
2.14434
2.15
OFF
1
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
1
1
1
1
1
1
1
0
The DAC3 output voltage can be controlled by the
1
1
1
1
1
1
1
1
0
2
Bits P-2 to P-2 (Bits 66 to 68) as following:
The offset of DAC1 has a range of 0.5 V to –0.6 V. This
range is divided into 64 steps. So one step is approxi-
mately 1.1V/63 = 17.2 m. The offset can be controlled by
DAC3 Offset Approx.
B68
0
B67
0
B66
0
0.5 V
1.1 V
1.8 V
2.4 V
3.1 V
3.7 V
4.4 V
5.0 V
0
0
1
0
5
the Bits 44 to 49 (O–2 to O–2 ) as following:
0
1
0
Offset DAC1 B49 B48 B47 B46 B45
Approx. [V]
B44
B8
0
1
1
Offset DAC2 B13 B12 B11 B10
Approx. [V]
B9
1
0
0
1
0
1
0.5
0.4828
0.4656
0.4484
...
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
...
0
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
0
...
1
The switching output SWO1 to SWO4 can be controlled
as following (Bits 30 to 33):
–0.0156
...
0.5656
–0.5828
–0.6
Switch Output
B29 + X
0
1
1
1
1
1
0
SWOx = ON
(switch to GND)
SWOx = OFF
1
1
1
1
1
1
1
The tuning capacity for the crystal oscillator has a range
of 0.5 pF to 71.5 pF. The values are coded binary. The
tuning can be controlled by the Bits 78 to 85 as following:
The DAC mode can be controlled by setting the Bit 34 as
following:
B85=0 B85=1 B84 B83 B82 B81 B80 B79 B78
pF
pF
DAC Mode
FM
B34
0
0
8.0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0.5
1.0
1.5
...
63.0
63.5
8.5
9.0
AM
1
19.5
...
71.0
71.5
1
1
1
1
1
0
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
0
0
0
0
0
0
0
Rev. A5, 06-Oct-00
7 (14)
Preliminary Information
U4256BM
The gain of DAC2 has a range of 0.7 x V(PDO) to The offset of DAC2 has a range of 0.5 to –0.6. This range
2.15 x V(PDO). V(PDO) is the PLL tuning voltage is divided into 64 steps. So one step is approximately
output. This range is divided into 256 steps. So one step 1.1V/63 = 17.2 m. The offset can be controlled by the
0
5
is approximately (2.15–0.7)/256 = 5.664 m. The gain can Bits 8 to 13 (O–2 to O–2 ) as following:
0
7
be controlled by the bits 0 to 7 (G–2 to G–2 ) as
following:
Offset DAC2 B13 B12 B11 B10
Approx.
B9
B8
0.5
0.4828
0.4656
0.4484
...
0
0
0
0
0
0
0
0
0
0
0
1
Gain
DAC2
Approx.
B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
1
0
0.7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0.70566
0.71133
0.71699
...
...
0
...
1
...
1
...
1
...
1
...
0
0
0
0
0
0
0
1
0
–0.0156
...
0
0
0
0
0
0
1
1
...
1
...
1
...
1
...
1
...
0
...
1
...
0
...
0
...
1
...
1
...
0
...
1
...
0
...
1
0.5656
–0.5828
–0.6
1.00019
...
1
1
1
1
1
0
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
1
1
1
1
1
1
2.1386
2.14434
2.15 m
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Input / Output Interface Circuits
PDO
PD
PD is the current charge pump output of the PLL. The
current can be controlled by setting the Bits. The loop
filter has to be designed corresponding to the choosen
pump current and the internal reference frequency. A
recommendation can be found in the application circuit.
PDO is the loop amplifier output of the PLL. The bipolar
output stage is a rail-to-rail amplifier.
V5
C
PDO
PD
Figure 5.
8 (14)
Rev. A5, 06-Oct-00
Preliminary Information
U4256BM
FMOSCIN
FMOSCIN is the preamplifier input for the FM oscillator signal.
V
S
FMOSCIN
Figure 6.
MX2LO
EN, DATA, CLK
MX2LO is the buffered output of the crystal oscillator.
This signal can be used as a reference frequency for
U4255BM.
All functions can be controlled via a 3-wire bus consisting
of ENABLE, DATA and CLOCK. The bus is designed for
microcontrollers which operate with 3 V supply voltage.
Details of the data transfer protocol are shown in the table
‘Data Transfer’.
V5
V5
VS
EN
DATA
CLK
OSCIN
MX2LO
Figure 9.
Figure 7.
SWO1, 2, 3 and 4
DAC 1, 2 and 3
DAC 1 to 3 are the outputs for automatic tuner alignment.
VS
All switching outputs are ‘open drain’ and can be set and
reset by software control. Details are described in the data
transfer protocol.
SWO1
I
SWO2
SWO3
SWO4
DAC1
Figure 8.
Figure 10.
Rev. A5, 06-Oct-00
9 (14)
Preliminary Information
U4256BM
OSCIN, OSCOUT
A crystal resonator (up to 15 MHz) is connected between
OSCIN and OSCOUT in order to generate the reference
frequency. By using the U4256BM in connection with
U4255BM the crystal frequency must be 10.25 MHz. The
complete application circuit is shown in figure 15. If a
reference is available, it can be applied at OSCIN. The
minimum voltage should be 100mVrms. In this case, pin
OSCOUT has to be open.
VS
OSCIN
VS
OSCOUT
Figure 11.
Application Information
Function of DAC1, 2 in FM Mode
Function of DAC1, 2 in AM Mode
If Bit 94 = 1, the DAC1, 2 can be used as standard DAC
converters. The resolution of 8 bit is controlled via the
gain bits in a range of approximately 0.5 V to 7 V,
depending on the offset value.
For automatic tuner alignment, the DAC1 and 2 of the
U4256BM can be controlled by setting gain of VPDO and
offset values. The following figure shows the principle of
the operation. The gain is in the range of 0.7 to 2.15. The
offset range is +0.5 V to –0.6 V. For alignment, DAC1
and 2 are connected to the varicaps of the preselection
filters. For alignment, offset and gain is set for having the
best tuner tracking.
FMOSCIN Sensitivity
Vi (mV on 50 W)
rms
150
Bit 34
100
50
PDO (FM)
DAC1,2
Gain
+/–
Vref (AM)
Offset
0
0
20
40
60
80
100
120 140
160
Frequency (MHz)
Figure 12.
Figure 13.
10 (14)
Rev. A5, 06-Oct-00
Preliminary Information
U4256BM
Oscillator Tuning Function Schematic
Cx1
Cx2
INV
32p
16p
0.5p
0.5p
16p
32p
B78
B84
B85
Figure 14.
DATA
Application Circuit
EN
CLK
GND
C12
100 nF
C9
*)
R5
*)
5.1 k Ω
*) depends on
crystal
C8
47 pF
10.25 MHz
12
20
19
18
17
16
15
14
13
11
C1
R2
BUS
OSC
600 Ω
10 pF
LOGIC
f
OSC
FM
VCO
DAC’s
4
Switches
1
2
3
5
6
7
8
9
10
V
tune
C16
C5
C6
330 pF
C7
R4
C 15
C4
10 k Ω
10 nF
100 nF
10 nF
C14
10 nF
100 µF
R3
10 nF
100 Ω
DAC1 DAC2
DAC3
VS
8 ... 12 V
SWO1 SWO2 SWO3 SWO4
Figure 15. Application circuit
Rev. A5, 06-Oct-00
11 (14)
Preliminary Information
U4256BM
Application Board Schematic
Figure 16. Application board schematic
12 (14)
Rev. A5, 06-Oct-00
Preliminary Information
U4256BM
Package Information
Package SSO20
Dimensions in mm
5.7
5.3
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
13007
1
10
Rev. A5, 06-Oct-00
13 (14)
Preliminary Information
U4256BM
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
1.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
14 (14)
Rev. A5, 06-Oct-00
Preliminary Information
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