2N7001TDCKR [TI]
1 位双电源缓冲电压信号转换器 | DCK | 5 | -40 to 125;
| 型号： | 2N7001TDCKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1 位双电源缓冲电压信号转换器 | DCK | 5 | -40 to 125 光电二极管 接口集成电路 转换器 |
| 文件： | 总26页 (文件大小：1179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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2N7001T
ZHCSI88A –MAY 2018–REVISED JUNE 2018
2N7001T 单位双电源缓冲电压信号转换器
1 特性
3 说明
1
•
•
•
•
•
在 1.65V 至 3.6V 范围内进行上行和下行电平转换
2N7001T 是一款采用两个独立可配置电源轨的单比特
位缓冲电压信号转换器，可对单向信号进行上行或下行
工作温度：–40°C 至 +125°C
电平转换。该器件通过 1.65V 至 3.60V 的 VCCA 和
最大静态电流 (ICCA + ICCB) 14µA（最高 125°C）
在整个电源范围内支持高达 100Mbps 的速率
VCCB 电源供电。VCCA 定义了 A 输入端的输入阈值电
压。VCCB 定义了 B 输出端的输出驱动电压。
VCC 隔离特性
–
如果任何一个 VCC 输入低于 100mV，则输出处
于高阻抗状态
该器件完全 适用于 使用 Ioff 电流的局部掉电应用。当
器件掉电时，Ioff 保护电路可确保不从输入/输出或偏置
到特定电压的快速 I/O 获取或向其提供多余电流。
•
•
•
Ioff 支持局部关断模式运行
闩锁性能超出 JESD 78 II 类规范要求的 100mA
V
CC 隔离功能确保当 VCCA 或 VCCB 低于 100mV 时，
静电放电 (ESD) 保护性能超过 JESD 22 规范的要
求
输出端口 (B) 进入高阻抗状态。
–
–
2000V 人体放电模型
1000V 充电器件模型
器件信息(1)
器件型号
2N7001TDCK
2N7001TDPW
封装
封装尺寸（标称值）
2.00mm × 1.25mm
0.80mm × 0.80mm
SC70 (5)
X2SON (5)
2 应用
•
•
•
MCU/FPGA/处理器 GPIO 转换
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
通信模块至处理器转换
推挽式 I/O 缓冲
方框图和引脚配置
VCCA
VCCB
DPW Package
DCK Package
2N7001T
5
4
VCCA
B
1
2
VCCA
B
VCCB
GND
5
1
2
A
A
B
3
GND
ESD
ESD
VCCB
A
3
4
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES888
2N7001T
ZHCSI88A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 11
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 6
6.7 Operating Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
7.1 Load Circuit and Voltage Waveforms ....................... 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
9
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 器件和文档支持 ..................................................... 14
12.1 文档支持 ............................................................... 14
12.2 接收文档更新通知 ................................................. 14
12.3 社区资源................................................................ 14
12.4 商标....................................................................... 14
12.5 静电放电警告......................................................... 14
12.6 术语表 ................................................................... 14
13 机械、封装和可订购信息....................................... 14
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (May 2018) to Revision A
Page
•
已更改 从“预告信息”更改为“生产数据”.................................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
2N7001T
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ZHCSI88A –MAY 2018–REVISED JUNE 2018
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
DPW Package
5-Pin X2SON
Transparent Top View
VCCA
B
VCCB
GND
5
1
2
VCCA
B
A
GND
VCCB
A
3
4
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
A
DCK
DPW
4
1
5
2
3
1
4
5
2
3
I
Data Input. This pin is referenced to VCCA
.
B
O
Data Output. This pin is referenced to VCCB.
VCCA
VCCB
GND
—
—
—
Input Supply voltage. 1.65V ≤ VCCA ≤ 3.6 V.
Output Supply voltage. 1.65V ≤ VCCB ≤ 3.6 V.
Ground
Copyright © 2018, Texas Instruments Incorporated
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ZHCSI88A –MAY 2018–REVISED JUNE 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.2
UNIT
VCCA
VCCB
VI
Supply voltage, A Port
V
V
V
V
Supply voltage, B Port
Input voltage(2)
Voltage applied to the output in the high-impedance or power-off state(2)
Voltage applied to the output in the high or low state(2)(3)
4.2
4.2
VO
VO
IIK
4.2
VCCB + 0.2
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
mA
°C
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCCB or GND
Continuous current through VCCA
Operating junction temperature
Storage temperature
–50
–50
–10
–40
–65
50
IO
50
IO
10
TJ
150
Tstg
150
°C
(1) Stresses beyond those listed under the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current ratings are observed.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2018, Texas Instruments Incorporated
2N7001T
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ZHCSI88A –MAY 2018–REVISED JUNE 2018
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
MAX
3.6
UNIT
V
VCCA Supply voltage, VCCA
VCCB Supply voltage, VCCB
VCCA = 1.65 V - 1.95 V
1.65
3.6
V
VCCA × 0.65
1.60
VIH
High-level input voltage
VCCA = 2.30 V - 2.70 V
VCCA = 3.00 V - 3.60 V
VCCA = 1.65 V - 1.95 V
VCCA = 2.30 V - 2.70 V
VCCA = 3.00 V - 3.60 V
V
V
2.00
VCCA × 0.65
0.70
VIL
Low-level input voltage
0.80
VI
Input voltage
0
0
0
3.6
V
V
Active state
Tri-state
VCCB
3.6
VO
Output voltage
Δt/Δv Input transition rise or fall rate
TA Operating free-air temperature
100
ns/V
°C
–40
125
6.4 Thermal Information
2N7001T
THERMAL METRIC(1)
DCK (SC70)
5 PINS
253.5
DPW (X2SON)
5 PINS
462.7
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
162.6
227.7
140.6
326.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
69.8
33.8
ψJB
139.7
325.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –8 mA
IOH = –9 mA
IOH = –12 mA
IOL = 100 µA
IOL = 8 mA
VCCA
1.65 V - 3.6 V
1.65 V
VCCB
1.65 V - 3.6 V
1.65 V
MIN
VCCB - 0.1
1.2
TYP(1)
MAX UNIT
High-level
output voltage
VOH
VI = VIH
V
2.3 V
2.3 V
1.75
3 V
3 V
2.3
1.65 V - 3.6 V
1.65 V
1.65 V - 3.6 V
1.65 V
0.1
0.45
V
0.55
Low-level
output voltage
VOL
VI = VIL
IOL = 9 mA
2.3 V
2.3 V
IOL = 12 mA
3 V
3 V
0.7
VI or VO = 0 V - 3.6 V
VI or VO = 0 V - 3.6 V
0 V
0 V - 3.6 V
0 V
–8
–8
8
Partial power
down current
Ioff
µA
8
0 V - 3.6 V
1.65 V - 3.6 V
0 V
1.65 V - 3.6 V
3.6 V
8
VCCA supply
current
ICCA
VI = VCCA or GND, IO = 0 mA
–8
µA
3.6 V
0 V
8
1.65 V - 3.6 V
0 V
1.65 V - 3.6 V
3.6 V
8
VCCB supply
current
ICCB
VI = VCCI or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
8
µA
3.6 V
0 V
–8
ICCA
ICCB
+
Combined
supply current
1.65 V - 3.6 V
3.3 V
1.65 V - 3.6 V
0 V
14
µA
pF
pF
Input
capacitance
VI = 1.65 V DC + 1MHz -16 dBm sine
wave
CI
2
4
Output
capacitance
VI = 1.65 V DC + 1MHz -16 dBm sine
wave
CO
0 V
3.3 V
(1) All typical values are for TA = 25°C
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
20
17
14
18
15
12
16
13
10
UNIT
VCCB = 1.80 ± 0.15 V
VCCA= 1.80 ± 0.15 V
VCCA= 2.50 ± 0.20 V
VCCA = 3.30 ± 0.30 V
VCCB = 2.50 ± 0.20 V
VCCB = 3.30 ± 0.30 V
VCCB = 1.80 ± 0.15 V
VCCB = 2.50 ± 0.20 V
VCCB = 3.30 ± 0.30 V
VCCB = 1.80 ± 0.15 V
VCCB = 2.50 ± 0.20 V
VCCB = 3.30 ± 0.30 V
tpd
Propagation Delay
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
IO = 0 mA
TEST CONDITIONS
VCCA = VCCB = 1.8 V
MIN
TYP
MAX
UNIT
1
Power dissipation
capacitance - Port A
CL = 0 pF,
f = 1 MHz,
tr = tf = 1 ns
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
1.3
1.8
12
15
18
CpdA
pF
IO = 0 mA
CL = 0 pF,
f = 1 MHz,
tr = tf = 1 ns
Power dissipation
capacitance - B Port
CpdB
pF
6
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ZHCSI88A –MAY 2018–REVISED JUNE 2018
6.8 Typical Characteristics
Output High Voltage (VOH) vs. Output High Current (IOH
CCA = VCCB = 1.8 V, TA = 25èC
)
Output Low Voltage (VOL) vs. Output Low Current (IOL
)
)
)
V
V
CCA = VCCB = 1.8V, TA = 25èC
1.85
1.8
0.4
0.35
0.3
1.75
1.7
0.25
0.2
1.65
1.6
0.15
0.1
1.55
1.5
0.05
0
1.45
-8
-7
-6
-5
-4
-3
-2
-1
0
0
0
0
1
2
3
4
5
6
7
8
Output High Current (IOH) [mA]
Output Low Current (IOL) [mA]
VOH1
VOL1
图 1. VOH vs IOH, 1.8 V
图 2. VOL vs IOL, 1.8 V
Output High Voltage (VOH) vs. Output High Current (IOH
CCA = VCCB = 2.5V, TA = 25èC
)
Output Low Voltage (VOL) vs. Output Low Current (IOL
V
VCCA = VCCB = 2.5V, TA = 25èC
2.55
2.5
0.4
0.35
0.3
2.45
2.4
0.25
0.2
2.35
2.3
0.15
0.1
2.25
2.2
0.05
0
2.15
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
Output High Current (IOH) [mA]
Output Low Current (IOL) [mA]
VOH2
VOL2
图 3. VOH vs IOH, 2.5 V
图 4. VOL vs IOL, 2.5 V
Output High Voltage (VOH) vs. Output High Current (IOH
)
Output Low Voltage (VOL) vs. Output Low Current (IOL
VCCA = VCCB = 3.3V, TA = 25èC
VCCA = VCCB = 3.3V, TA = 25èC
3.35
3.3
0.5
0.45
0.4
3.25
3.2
0.35
0.3
3.15
3.1
0.25
0.2
3.05
3
0.15
0.1
2.95
2.9
0.05
0
2.85
-12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1
Output High Current (IOH) [mA]
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Low Current (IOL) [mA]
VOH3
VOL3
图 5. VOH vs IOH, 3.3 V
图 6. VOL vs IOL, 3.3 V
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2N7001T
ZHCSI88A –MAY 2018–REVISED JUNE 2018
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
•
•
•
f = 1 MHz
ZO = 50 Ω
dv/dt ≤ 1 ns/V
Measurement Point
Output Pin
Under Test
(1)
CL
RL
(1) CL includes probe and jig capacitance.
图 7. Load Circuit
表 1. Load Circuit Conditions
Parameter
VCC
RL
CL
tpd
Propagation (delay) time
1.65 V – 3.6 V
2 kΩ
15 pF
VCCA
VCCA / 2
VCCA / 2
Input A
0 V
VOH
tpd
tpd
(2)
Output B
VCCB / 2
VCCB / 2
(2)
VOL
(1) VCCI is the supply pin associated with the input port.
(2) VOH and VOL are typical output voltage levels that occur with specified RL and CL.
图 8. Propagation Delay
8
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8 Detailed Description
8.1 Overview
The 2N7001T is a single-bit dual-supply buffered voltage signal converter that can be used to up or down-
translate a single unidirectional signal. The device is operational with both VCCA and VCCB supplies down to 1.65
V and up to 3.60 V. VCCA defines the input threshold voltage on the A input while VCCB defines the output voltage
on the B output.
8.2 Functional Block Diagram
VCCA
VCCB
2N7001T
A
B
ESD
ESD
GND
8.3 Feature Description
8.3.1 Up-Translation or Down-Translation from 1.65 V to 3.60 V
The VCCA and VCCB pins can both be supplied by a voltage range from 1.65 V to 3.6 V. This voltage range makes
the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, and 3.3 V).
8.3.2 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined the in the Absolute Maximum Raings must be followed at all
times.
8.3.3 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance shown in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, shown in the Absolute Maximum Ratings, and the maximum input leakage current, shown in the
Electrical Characteristics, using Ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
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Feature Description (接下页)
8.3.4 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in 图 9.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
图 9. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.5 Partial Power Down (Ioff
)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input pin or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.6 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the input supply voltage (VCCA), as long as they remain below
the maximum input voltage value specified in the Recommended Operating Conditions.
8.4 Device Functional Modes
表 2 lists the functional modes of the 2N7001T device.
表 2. Function Table
INPUT
OUTPUT
L (Referenced to VCCA
)
L (Referenced to VCCB)
H (Referenced to VCCA
)
H (Referenced to VCCB)
10
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The 2N7001T device can be used in level-translation applications for interfacing between devices or systems that
are operating at different interface voltages.
9.2 Typical Applications
9.2.1 Processor Error Up Translation
图 10 shows an example of the 2N7001T being used in a unidirectional logic level-shifting application.
1.8 V
3.3 V
2N7001T
VCCA
VCCB
System
Controller
A
PROC
ERR
B
PROC
ERR
Processor
ESD
ESD
GND
图 10. Processor Error Up Translation Application
9.2.1.1 Design Requirements
For this design example, use the parameters shown in 表 3.
表 3. Design Parameters
DESIGN PARAMETER
Input voltage supply
Output voltage supply
EXAMPLE VALUE
1.8 V
3.3 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range
–
The supply voltage of the upstream device (device that is driving input pin A) will determine the
appropriate input voltage range. For a valid logic-high, the value must exceed the high-level input voltage
(VIH) of the input port. For a valid logic low the value must be less than the low-level input voltage (VIL) of
the input port.
•
Output voltage range
–
The supply voltage of the downstream device (device that output pin B is driving) will determine the
appropriate output voltage range.
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9.2.1.3 Application Curve
A Data Input = 1.8V
B Data Output = 3.3V
图 11. Up Translation (1.8 V to 3.3 V) at 1 MHz
9.2.2 Discrete FET Translation Replacement
The 2N7001T device is an excellent option for replacing discrete translators, as shown in 图 12, and has the
following benefits regarding discrete translation implementations:
•
•
•
•
•
•
•
A single device vs a four component solution
Minimized implementation size
Lower power consumption
VCC isolation feature
Higher data rates
Integrated ESD protection
Improved glitch performance
Discrete Translator: Four Component,
Push-Pull Translation w/o ESD Protection
2N7001T: Single Small Footprint Device,
Low Power Translation with ESD Protection
DPW Package
A
VCCB
VCCA
B
GND
0603
Res.
SOT23
FET
Solution Size: 0.64mm2
DCK Package
SOT23
FET
VCCA
SOT23
FET
B
VCCB
GND
1
2
3
5
4
A
Solution Size: ~ 60mm2 Solution Size: 4.2mm2
图 12. Discrete Translation vs. 2N7001T Solution
12
版权 © 2018, Texas Instruments Incorporated
2N7001T
www.ti.com.cn
ZHCSI88A –MAY 2018–REVISED JUNE 2018
10 Power Supply Recommendations
The 2N7001T device uses two separate configurable power-supply rails, VCCA and VCCB. The VCCA and VCCB
power-supply rails accept any supply voltage that range from 1.65 V to 3.6 V. The A input and B output are
referenced to VCCA and VCCB respectively allowing up or down translation among the 1.8-V, 2.5-V, and 3.3-V
voltage nodes. A 0.1 µF bypass capacitor is recommended on all VCC pins.
Always apply a ground reference to the GND pin first. However, there are no additional requirement for power
supply sequencing.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, follow the common printed-circuit board layout guidelines listed below:
•
•
Use bypass capacitors on power supplies.
Use short trace lengths to avoid excessive loading.
An example layout is given in 图 13 for the DPW (X2SON-5) package. This example layout includes two 0402
(metric) capacitors, and uses the measurements that are in the package outline drawing appended to the end of
this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or the via can be left out of the layout.
11.2 Layout Example
0402
0.1 …F
Bypass
Capacitor
VCCA
8 mil
8 mil
A
8 mil
8 mil
VCCB
B
SOLDER MASK
0402
OPENING, TYP
0.1 …F
Bypass
Capacitor
METAL UNDER
SOLDER MASK,
TYP
图 13. Example Layout for the DPW (X2SON-5) Package
版权 © 2018, Texas Instruments Incorporated
13
2N7001T
ZHCSI88A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，《慢速或浮点 CMOS 输入的影响》应用报告
德州仪器 (TI)，借助 TI 的 X2SON 封装应用报告设计和制造
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
14
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
2N7001TDCKR
2N7001TDPWR
ACTIVE
ACTIVE
SC70
DCK
5
5
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
(DQ, DQL)
DP
Samples
Samples
X2SON
DPW
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2023
OTHER QUALIFIED VERSIONS OF 2N7001T :
Automotive : 2N7001T-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
2N7001TDCKR
2N7001TDPWR
SC70
DCK
5
5
3000
3000
178.0
178.0
9.0
8.4
2.4
2.5
1.2
0.5
4.0
2.0
8.0
8.0
Q3
Q3
X2SON
DPW
0.91
0.91
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
2N7001TDCKR
2N7001TDPWR
SC70
DCK
5
5
3000
3000
180.0
205.0
180.0
200.0
18.0
33.0
X2SON
DPW
Pack Materials-Page 2
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.324)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
3
2X (0.26)
0.48
0.27
0.17
4X
0.239
0.139
0.1
C A B
C
0.288
0.188
3X
0.05
4223102/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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