5962-1722001VXC [TI]
耐辐射 QMLV、1.5V 至 7V 输入、6A 负载开关/电子保险丝 | HKR | 16 | -55 to 125;
| 型号： | 5962-1722001VXC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射 QMLV、1.5V 至 7V 输入、6A 负载开关/电子保险丝 | HKR | 16 | -55 to 125 电子 开关 |
| 文件： | 总40页 (文件大小：1804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
TPS7H2201-SP 耐辐射 1.5V 至 7V、6A 负载开关
1 特性
3 说明
1
•
辐射性能：
TPS7H2201-SP 是一款单通道负载开关，可提供用于
最大限度地降低浪涌电流的可配置上升时间和反向电流
保护。此器件包括一个 P 沟道 MOSFET，可在 1.5V
至 7V 的输入电压范围内运行并可支持 6A 的最大持续
电流。此开关由一个开关输入 (EN) 控制，该输入能够
直接连接至低电压控制信号。
–
–
抗辐射加固保障 (RHA) 高达 100krad (Si) TID
单粒子锁定 (SEL)、单粒子烧毁 (SEB) 和单粒
子栅穿 (SEGR) 对于 LET 的抗扰度 = 75MeV-
cm2/mg
–
SEFI/SET 对于
LET 的额定值 = 75MeV-cm2/mg
TPS7H2201-SP 采用具有集成式散热垫的陶瓷封装，
从而支持高功率耗散。该器件在自然通风环境下的额定
运行温度范围为 –55°C 至 125°C。
•
•
•
集成型单通道负载开关
输入电压范围：1.5V 至 7V
低导通电阻 (RON)，在温度为 25°C 和输入电压为
5V 时具有 35mΩ 的最大值
器件信息(1)
•
•
6A 最大持续开关电流
器件型号
等级
封装
低控制输入阈值支持使用
1.2V、1.8V、2.5V 和 3.3V 逻辑器件
可配置上升时间（软启动）
反向电流保护
耐辐射等级 RHA
100krad(Si)
16 引脚 CDFP
11.00 × 9.60mm
5962R1722001VXC
5962-1722001VXC
TPS7H2201HKR/EM
耐辐射等级 QMLV 重量：
工程样片(2)
•
•
•
1.56g(3)
TPS7H2201EVM-CVAL 陶瓷评估板
EVM
可编程和内部电流限制
（快速跳变）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
可编程故障计时器（电流限制和
重试模式）
(2) 这些部件仅适用于工程评估。部件按照不合规的流程进行加工
处理。这些部件不适用于质检、生产、辐射测试或飞行。这些
零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围内或
运行寿命中保证其性能。
•
•
热关断
带散热垫的陶瓷封装
(3) 重量误差在 ±10% 以内。
2 应用
•
•
•
航天卫星电源管理和配电
耐辐射电源树 应用
支持军用（–55°C 至 125°C）温度范围
简化原理图
VIN
VOUT
CSS
SS
CS
ON
TPS7H2201-SP
EN
RTIMER
OFF
CRTIMER
ILTIMER
IL
OVP
GND
CILTIMER
RIL
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDO0
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 17
8.4 Device Functional Modes ....................................... 25
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Applications ................................................ 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 8
6.5 Electrical Characteristics........................................... 8
6.6 Switching Characteristics........................................ 10
6.7 Quality Conformance Inspection............................. 10
6.8 Typical Characteristics............................................ 11
Parameter Measurement Information ................ 14
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
9
10 Power Supply Recommendations ..................... 31
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 器件和文档支持 ..................................................... 32
12.1 文档支持................................................................ 32
12.2 接收文档更新通知 ................................................. 32
12.3 社区资源................................................................ 32
12.4 商标....................................................................... 32
12.5 静电放电警告......................................................... 32
12.6 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 33
7
8
4 修订历史记录
Changes from Revision A (January 2019) to Revision B
Page
•
•
•
•
Added Bare Die Information table in Pin Configuration and Functions section ..................................................................... 4
Added Bond Pad Coordinates in Microns table in Pin Configuration and Functions section................................................. 5
Added after TID specification for ISD VIN................................................................................................................................ 8
已添加 Quality Conformance Inspection table to Specifications section.............................................................................. 10
Changes from Original (September 2018) to Revision A
Page
•
已更改 将器件状态从高级信息 更改为生产数据...................................................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
5 Pin Configuration and Functions
HKR Package
16-Pin CFP With Thermal Pad
Top View
VIN
VIN
VIN
VIN
CS
1
16
15
14
13
12
11
10
9
VOUT
VOUT
VOUT
VOUT
SS
2
3
4
5
6
7
8
Thermal
Pad
EN
ILTIMER
IL
OVP
GND
RTIMER
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
2
VIN
I
Switch input. Input bypass capacitor recommended for minimizing VIN dip.
3
4
5
CS
EN
O
I
Current sense pin proportional to output current. Connect a resistor to GND.
Active high switch control input. Do not leave floating.
6
Overvoltage protection. Programmable using an external resistor divider. If no OVP is
desired, this pin should be connected to GND.
Device ground.(1)
7
8
OVP
GND
I
—
Capacitor programmed fault timer control during disabled and retry mode. Connecting this
pin to GND holds the switch disabled until the EN pin is cycled. Do not float this pin or
connect it to VIN.
9
RTIMER
IL
I/O
I/O
10
Current limiter control. Programmable using an external resistor to GND. Do not float this pin.
Capacitor programmed fault timer control during current limiting mode. Connecting this pin to
VIN uses the internal current limit timer and connecting this pin to GND disables the internal
timer functionality for the ILTIMER as well as retry mode. In this case, the device will remain
at programmed current limit indefinitely in the event of a short without going intro retry mode.
Do not float this pin.
11
ILTIMER
SS
I
12
13
14
15
16
I/O
Switch slew rate control. See the Adjustable Rise Time section for more information.
VOUT
O
Switch output. A minimum 10-µF output capacitor is recommended.
Thermal pad (exposed center pad) for heat dissipation purposes. Thermal pad is internally
connected to seal ring and GND.
—
Thermal Pad
—
(1) Thermal pad is internally connected to the seal ring and GND.
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
Table 1. Bare Die Information
BACKSIDE
POTENTIAL
BOND PAD METALLIZATION
DIE THICKNESS
BACKSIDE FINISH
BOND PAD THICKNESS
COMPOSITION
15 mils
Silicon with backgrind
Ground
ALCU
1050 nm
4
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
Table 2. Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
679.75
286.85
286.85
679.75
286.85
679.75
286.85
679.75
286.85
679.75
286.85
679.75
286.85
679.75
286.85
679.75
286.85
679.75
286.85
679.75
61.1
Y MIN
5529
X MAX
835.25
442.35
442.35
835.25
442.35
835.25
442.35
835.25
442.35
835.25
442.35
835.25
442.35
835.25
442.35
835.25
442.35
835.25
442.35
835.25
216.6
Y MAX
5684.5
5684.5
5499
VIN
VIN
1
2
5529
VIN
3
5343.5
5343.5
5157.1
5157.1
4970.65
4970.65
4053
VIN
4
5499
VIN
5
5312.6
5312.6
5126.15
5126.15
4208.5
4208.5
4023
VIN
6
VIN
7
VIN
8
VIN
9
VIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
4053
VIN
3867.5
3867.5
3681.1
3681.1
3494.65
3494.65
2572.85
2572.85
2384.85
2384.85
2046.7
1857.2
1645.3
1080.75
451.4
VIN
4023
VIN
3836.6
3836.6
3650.15
3650.15
2728.35
2728.35
2540.35
2540.35
2202.2
2012.7
1800.8
1236.25
606.9
VIN
VIN
VIN
VIN
VIN
VIN
VIN
AVDD
AVDD
CS
61.1
216.6
61.1
216.6
EN
61.1
216.6
OVP
GND
GND
RTIMER
IL
61.1
216.6
452.45
641.95
3103.2
3683.4
3683.4
3683.4
3457.4
3064.5
3457.4
3064.5
3457.4
3064.5
3457.4
3064.5
3457.4
3064.5
3457.4
3064.5
3457.4
3064.5
3457.4
3064.5
61.1
607.95
797.45
3258.7
3838.9
3838.9
3838.9
3612.9
3220
216.6
61.1
216.6
61.1
216.6
652.7
808.2
ILTIMER
SS
1221.4
1715.65
2384.85
2384.85
2572.85
2572.85
3494.65
3494.65
3681.1
3681.1
3867.5
3867.5
4053
1376.9
1871.15
2540.35
2540.35
2728.35
2728.35
3650.15
3650.15
3836.6
3836.6
4023
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
3612.9
3220
3612.9
3220
3612.9
3220
3612.9
3220
4023
3612.9
3220
4208.5
4208.5
5126.15
5126.15
5312.6
5312.6
4053
4970.65
4970.65
5157.1
5157.1
3612.9
3220
3612.9
3220
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
Table 2. Bond Pad Coordinates in Microns (continued)
DESCRIPTION
VOUT
PAD NUMBER
X MIN
3457.4
3064.5
3457.4
3064.5
Y MIN
5343.5
5343.5
5529
X MAX
3612.9
3220
Y MAX
5499
48
49
50
51
VOUT
5499
VOUT
3612.9
3220
5684.5
5684.5
VOUT
5529
6
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
MAX UNIT
VIN
Input voltage
7.5
7.5
V
V
VOUT
EN, OVP
Output voltage
Enable and over voltage protection pins
7.5
V
CS, ILTIMER, RTIMER, IL, SS Current sense, current limit timer, retry timer, current limit and soft start pins
VIN + 0.3
9
V
IMAX
IPLS
TJ
Maximum continuous switch current
Maximum pulsed switch current (t≤5µs)
Maximum junction temperature
Storage temperature
A
45
A
–55
–65
150
°C
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
±4000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
7
UNIT
V
VIN
Input voltage
1.5
SRVIN
VOUT
IMAX
TJ
Input voltage slew rate
Output voltage
0.01
VIN
6
V/µs
V
0
Maximum continuous switch current
Operating junction temperature(1)
A
–55
125
°C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the equation: TA(max) = TJ(max) – (θJA × PD(max)).
Copyright © 2018–2019, Texas Instruments Incorporated
7
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
6.4 Thermal Information
TPS7H2201-SP
HKR (CFP)
16 PINS
THERMAL METRIC
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
POWER SUPPLIES AND CURRENTS
VINHUVLO
VINLUVLO
Internal VIN UVLO voltage, rising
1.32
1.23
V
V
Internal VIN UVLO voltage,
falling
HYSTVIN-
Internal VIN UVLO hysteresis
Quiescent current
92
mV
UVLO
IOUT = 0 mA,
IQ
IF
1, 2, 3
1, 2, 3
2.4
6.5
3
mA
mA
VIN = EN = 5 V, CS resistor of 20 kΩ to GND
EN = VOUT = GND, measured VOUT current
VIN = 5 V
VIN to VOUT forward leakage
current
1, 2, 3
1, 2, 3
1, 2, 3
0.4
0.3
0.2
3
3
3
VIN = 3.3 V
EN = GND,
IOUT = 0 mA, measured VIN
VIN = 1.8 V
ISD VIN
VIN off-state supply current
mA
mA
current
After TID = 100
krad, VIN = 1.8,
3.3, and 5 V
1
3.1
EN = 0 V, VIN = 0 to 7 V,
VOUT = 0 to 7 V for VOUT > VIN
Reverse current protection
leakage current
IRCP
1, 2, 3
0.45
2.5
EN = 7 V, VIN = 0 V,
VOUT = 0 to 7 V
SOFT START
ISS
Soft start charge current
Soft start slew rate
1 V on SS pin
1, 2, 3
65
83
µA
SRSS
SS pin floating, COUT = 10 µF
295
mV/µs
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
EN/UVLO threshold voltage,
VIHEN
rising
1, 2, 3
1, 2, 3
0.56
0.47
0.61
0.65
V
V
EN/UVLO threshold voltage,
falling
VILEN
0.51
93
0.55
124
HYSTEN
tLOW
EN/UVLO hysteresis voltage
1, 2, 3
9, 10, 11
4, 5, 6
1, 2, 3
mV
µs
EN signal low time during cycling RTIMER = GND, IL = 1 A, IVOUT = 2 A
VIN percentage for enable
20
VINEN
IEN
75%
EN pin input leakage current
EN = VIN = 5 V
12
nA
OVERVOLTAGE PROTECTION (OVP)
VOVPR
VOVPF
HYSTOVP
IOVP
OVPR thresold voltage, rising
OVPF threshold voltage, falling
OVP hysteresis voltage
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.52
0.5
0.57
0.55
20
0.63
0.59
55
V
V
1.6 V < VIN < 7 V
mV
nA
OVP pin input leakage current
15
CURRENT LIMIT AND CURRENT SENSE
Time for valid CS output after
enable
tCSEN
CSS = 120 nF
9, 10, 11
1, 2, 3
5
ms
mA
µs
Minimum VOUT current for valid CS output
750
VOUT current change to CS change delay
time
0.5-A rising step, 100 mA/µs, 1.5 V ≤ VIN ≤ 7 V
9, 10, 11
16
16
74
VOUT current change to CS change delay
time
0.5-A falling step, 100 mA/µs, 1.5 V ≤ VIN ≤ 7 V
0.75 A ≤ IVOUT ≤ 7.5 A
9, 10, 11
4, 5, 6
73
µs
V
CS pin accuracy
CS pin voltage
–10%
10%
VIN –
0.4
0.75 A ≤ IVOUT ≤ 7.5 A, no OCP
1, 2, 3
(1) For subgroup definitions, see Quality Conformance Inspection table.
8
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
1, 2, 3
MIN
TYP
MAX UNIT
IVOUT
+
IVOUT ≤ 1 A
0.5
Current limit setting, IIL
1A < IVOUT ≤ 3 A
1, 2, 3
IVOUT + 1
A
IVOUT
+
IVOUT > 3 A
1, 2, 3
1.5
Programmable current limit accuracy
Fast trip off current limit
1.5 V ≤ VIN ≤ 7 V
4, 5, 6
–20%
20%
A
VIN = 5 V, 10-mΩ short in 10 µs
VIN = 5 V, CSS = 2.7 nF
22
61
Fast trip off off-time
9, 10, 11
9, 10, 11
158
35
µs
µs
Internal current limit timer (fast trip off current
limit)
VIN = 5 V, IVOUT = 3 A, IL = 6 A, ILTIMER = VIN,
10-mΩ short in 10 µs
15
TIMERS
IILTIMER
ILTIMER charge current
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.7
0.7
1
38
1
1.38
153
1.38
153
µA
Ω
ILTIMER internal pull-down
resistance
PDILTIMER
IRTIMER
40 mV on ILTIMER pin
40 mV on RTIMER pin
RTIMER charge current
µA
Ω
RTIMER internal pull-down
resistance
PDRTIMER
38
THERMAL SHUTDOWN
Thermal shutdown
VIN = 5 V
VIN = 5 V
175
20
°C
°C
Thermal shutdown hysteresis
RESISTANCE CHARACTERISTICS
–55°C
–40°C
24
26
34
40
45
26
27
35
42
47
28
30
38
46
52
36
39
51
62
70
44
48
63
77
87
VIN = 7 V, IIL = 7.5 A
VIN = 5 V, IIL = 7.5 A
VIN = 3.3 V, IIL = 7.5 A
VIN = 1.8 V, IIL = 7.5 A
VIN = 1.5 V, IIL = 7.5 A
25°C
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
31
37
41
85°C
125°C
–55°C
–40°C
25°C
32
39
43
85°C
125°C
–55°C
–40°C
25°C
ON-state resistance, lead length
= 2.5 mm
RON
35
42
47
mΩ
85°C
125°C
–55°C
–40°C
25°C
45
55
61
85°C
125°C
–55°C
–40°C
25°C
52
63
70
85°C
125°C
Copyright © 2018–2019, Texas Instruments Incorporated
9
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = EN = 5 V, TA = 25°C (unless otherwise noted)
tON
Turn-on time
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
208
60
µs
µs
µs
µs
µs
tOFF
Turn-off time
tF
VOUT fall time
OVP assert time
OVP deassert time
90
tASSERT
tDEASSERT
4.5
9.6
VIN = EN = 1.5 V, TA = 25°C (unless otherwise noted)
tON
Turn-on time
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
RL = 10 Ω, CL = 10 µF, CSS = 1000 pF
173
64
µs
µs
µs
µs
µs
tOFF
Turn-off time
tF
VOUT fall time
OVP assert time
OVP deassert time
70
tASSERT
tDEASSERT
2.65
6.56
6.7 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
SUBGROUP
DESCRIPTION
Static tests at
TEMP (°C)
25
1
2
Static tests at
125
–55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
5
125
–55
25
6
7
8A
8B
9
125
–55
25
10
11
125
–55
10
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ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
6.8 Typical Characteristics
0.085
1 A
0.045
0.042
0.039
0.036
0.033
0.03
1 A
3 A
6 A
0.08
3 A
6 A
0.075
0.07
0.065
0.06
0.055
0.05
0.027
0.024
0.021
0.045
0.04
0.035
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D001
D002
IIL = 7.5 A
IIL = 7.5 A
图 1. On-Resistance vs Temperature Across Loads at VIN =
图 2. On-Resistance vs Temperature Across Loads at VIN =
1.5 V
5 V
0.0425
1 A
85
1.5 V
1.8 V
3.3 V
5 V
7 V
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
0.04
0.0375
0.035
0.0325
0.03
3 A
6 A
0.0275
0.025
0.0225
0.02
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D003
D004
IIL = 7.5 A
图 3. On-Resistance vs Temperature Across Loads at VIN =
图 4. RTIMER Pull-Down Resistance vs Temperature Across
7 V
VIN
0.004
85
1.5 V
1.8 V
3.3 V
5 V
7 V
1.5 V
1.8 V
3.3 V
5 V
7 V
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
0.0035
0.003
0.0025
0.002
0.0015
0.001
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D005
D006
图 5. ILTIMER Pull-Down Resistance vs Temperature Across
图 6. IQ vs Temperature Across VIN
VIN
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Typical Characteristics (接下页)
0.002
0.002
0.0018
0.0016
0.0014
0.0012
0.001
VOUT(1.5 V) - VIN(0 V) = 1.5 V
VOUT(1.5 V) - VIN(0 V) = 1.5 V
VOUT(1.8 V) - VIN(0 V) = 1.8 V
VOUT(3.3 V) - VIN(0 V) = 3.3 V
VOUT(5 V) - VIN(0 V) = 5 V
VOUT(7 V) - VIN(0 V) = 7 V
0.0018
VOUT(1.8 V) - VIN(0 V) = 1.8 V
VOUT(3.3 V) - VIN(0 V) = 3.3 V
0.0016
VOUT(5 V) - VIN(0 V) = 5 V
VOUT(7 V) - VIN(0 V) = 7 V
0.0014
0.0012
0.001
0.0008
0.0006
0.0004
0.0002
0
0.0008
0.0006
0.0004
0.0002
0
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D007
D008
图 7. IRCP vs Temperature With EN = 7 V
图 8. IRCP vs Temperature With EN = GND
0.00055
0.0005
0.00045
0.0004
0.00035
0.0003
0.00025
0.0002
0.00015
0.0001
1.14E-6
1.12E-6
1.1E-6
1.08E-6
1.06E-6
1.04E-6
1.02E-6
1E-6
1.8 V
3.3 V
5 V
1.5 V
1.8 V
3.3 V
5 V
7 V
9.8E-7
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D009
D010
图 9. ISD VIN vs Temperature Across VIN
图 10. ILTIMER Charge Current vs Temperature Across VIN
7.2E-5
1.12E-6
1.1E-6
1.08E-6
1.06E-6
1.04E-6
1.02E-6
1E-6
1.5 V
1.8 V
3.3 V
5 V
7 V
1.5 V
1.8 V
3.3 V
5 V
7 V
7.1E-5
7E-5
6.9E-5
6.8E-5
6.7E-5
6.6E-5
6.5E-5
6.4E-5
6.3E-5
6.2E-5
9.8E-7
9.6E-7
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D011
D012
图 11. RTIMER Charge Current vs Temperature Across VIN
图 12. SS Charge Current vs Temperature Across VIN
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Typical Characteristics (接下页)
0.66
0.55
0.54
0.53
0.52
0.51
0.5
1.5 V
1.8 V
3.3 V
5 V
7 V
1.5 V
1.8 V
3.3 V
5 V
7 V
0.65
0.64
0.63
0.62
0.61
0.6
0.59
0.58
0.57
0.49
0.48
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D013
D014
EN pin driven directly
EN pin driven directly
图 13. VIHEN vs Temperature Across VIN
图 14. VILEN vs Temperature Across VIN
0.62
0.61
0.6
0.61
0.6
1.5 V
1.8 V
3.3 V
5 V
7 V
1.5 V
1.8 V
3.3 V
5 V
7 V
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.59
0.58
0.57
0.56
0.55
0.54
0.53
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D015
D016
OVP pin driven directly
OVP pin driven directly
图 15. VOVPR vs Temperature Across VIN
图 16. VOVPF vs Temperature Across VIN
8
7.5
7
6.5
6
5.5
5
4.5
4
1800
1600
1400
1200
1000
800
Current Limit at 25èC, 1.5 V to 3 V
Current Limit at -55èC, 1.5 V to 3 V
Current Limit at 125èC, 1.5 V to 3 V
Current Limit at 25èC, 3 V to 7 V
Current Limit at -55èC, 3 V to 7 V
Current Limit at 125èC, 3 V to 7 V
Slew Rate 1.5 V, 6 A, 25èC
Slew Rate 1.5 V, 6 A, -55èC
Slew Rate 1.5 V, 6 A, 125èC
Slew Rate 7 V, 6 A, 25èC
Slew Rate 7 V, 6 A, -55èC
Slew Rate 7 V, 6 A, 125èC
3.5
3
600
2.5
2
400
1.5
1
200
0.5
0
0
20000
40000
60000
80000
100000
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
RIL (kW)
SS Capacitor (mF)
D017
D018
图 17. IIL vs RIL Across Temperature
图 18. SS Slew Rate vs SS Capacitor Across Temperature
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7 Parameter Measurement Information
50%
EN
tF
tOFF
90%
tON
50%
50%
VOUT
10%
图 19. tON/tOFF Waveforms
0.63 V
0.50 V
0.61 V
OVP
0.52 V
tASSERT
VOUT
tDEASSERT
90% VOUT
10% VOUT
图 20. tASSERT/tDEASSERT Waveforms
VIN
0.65 V
EN
20% IOUT
IOUT
tCSEN
90% of 0.2*IOUT/41500
图 21. tCSEN Waveforms
CS
14
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ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
Internal ILTIMER
IL
IOUT
0.5 V
RTIMER
图 22. Internal ILTIMER Waveforms
0.8*0.5 A + IOUT
100 mA/µs
100 mA/µs
0.5 A
IOUT
0.2*0.5 A + IOUT
IOUT to CS
change rising
(0.8*0.5 A + IOUT) / 41500
IOUT to CS
change falling
(0.2*0.5 A + IOUT) / 41500
CS
图 23. VOUT Current to CS Change Delay Time
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8 Detailed Description
8.1 Overview
The TPS7H2201-SP device is a single channel, 6-A load switch with a programmable slew rate for applications
that require specific rise-time as well as programmable current limit for protection purposes. In addition, the
TPS7H2201-SP features a reverse current protection capability for power distribution applications.
8.2 Functional Block Diagram
VIN
Overcurrent
Protection
IL
CS
VREF
+
EN
+
0.65 V
0.47 V
-
STARTUP
CONTROL
LOGIC
+
OVP
0.63 V
0.50 V
-
VOUT
Thermal
Shutdown
RAMP CONTROL
ILTIMER
SS
RTIMER
16
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8.3 Feature Description
8.3.1 Enable, Undervoltage, and Overvoltage Protection
图 24 shows how resistor dividers from VIN connected to the EN and OVP pins can be used to set the UVLO
and OVP trip voltages. The EN pin controls the ON and OFF state of the internal FET. A voltage at this pin
greater than VIHEN turns on the FET and a voltage less than VILEN turns it off. The addition of an external resistor
divider from VIN allows the EN pin to configure a different enable rising voltage or an undervoltage monitor
(UVLO) based on the VIHEN and VILEN specifications respectively. Typically, applications are optimized to either
configure the enable rising voltage or the UVLO threshold. As an example, 公式 1 can be used to calculate the
UVLO trip point fixing RTOP_EN = 100 kΩ.
In a similar way to the EN pin, the overvoltage protection (OVP) feature of the device can be configured using a
resistor divider from VIN connected to the OVP pin. The trip voltage for the OVP has to be less than the absolute
maximum VIN voltage. A voltage at the OVP pin greater than VOVPR will trip the OVP feature and will turn off the
FET and a voltage less than VOVPF will keep the FET on. If this feature is not desired, the OVP pin should be
grounded. 公式 2 can be used to calculated the rising OVP trip point fixing RTOP_OVP = 100 kΩ.
TPS7H2201-SP
VIN
RTOP_OVP
EN
RTOP_EN
EN
ON
+
OFF
0.65 V
0.47 V
-
OVP
OVP
+
0.63 V
0.50 V
-
RBOT_EN
RBOT_OVP
GND
图 24. UVLO and OVP Thresholds Set by Resistor Dividers
47
:
;
RBOT _EN ´À Q
VUVLO _TRIP (V) F 0.47
63
(1)
(2)
:
;
RBOT _OVP ´À R
VOVP _TRIP (V) F 0.63
8.3.2 Adjustable Rise Time
An external capacitor, CSS, connected between the VOUT and SS pins sets the slew rate. The desired slew rate
VOUTSR is determined by tr, the rise time in seconds, and ΔV, the change in VOUT voltage in Volts as shown in
公式 3.
¿VOUT (V)
:
;
VOUTSR V/s =
tr(s)
(3)
In order to avoid false trips due to the programmable current limit, the desired slew rate must be less than
VOUTSR,MAX as shown in 公式 4, where IL is the programmed current limit, IVOUT is the normal operation current
flowing through the switch, and COUT is the output capacitor.
: ;
0.8 × IL A F 0.95 × IVOUT (A)
:
;
VOUTSR,MAX V/s <
COUT (F)
(4)
17
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Feature Description (接下页)
Once the slew rate has been calculated and meeting the constraint in 公式 4, the CSS capacitor is then calculated
using 公式 5 for VIN < 3-V and IOUT ≥ 3-A applications. For all other applications, use 公式 6.
45
:
;
CSS µF =
:
;
VOUTSR V/s
for VIN < 3 V and IOUT ≥ 3 A
(5)
(6)
65
:
;
CSS µF =
:
;
VOUTSR V/s
for all other conditions
8.3.3 Programmable Current Limiting
A current limit can be programmed using an external resistor connected from the IL pin to GND. This
programmed current limit (±20% accurate) refers to the continuous current through the device and therefore,
when operated at its maximum current rating (6 A), the programmed current limit needs to be set 20% higher. As
shown in 图 25, a current limit event of this nature is defined as a soft short. The resistor value RIL, can be
calculated using 公式 7 for VIN ≤ 3 V, and 公式 8 for VIN > 3 V, where IL is the programmed current limit value in
amperes. This programmable current limiting feature is different from the internal current limiting activated during
fast trip mode as shown in 图 26. A current limit event in this case is defined as a hard short and this current limit
(typical of 22 A) cannot be programmed.
45500
: ;
IL A
RIL(À) =
for VIN ≤ 3 V
(7)
(8)
49000
: ;
IL A
RIL(À) =
for VIN > 3 V
8.3.4 Programmable Fault Timer
A capacitor connected from the ILTIMER pin to GND determines the programmable current limit fault time
duration. The ILTIMER pin will charge the capacitor to 0.5 V during an overload condition and will discharge it
otherwise through an internal pull down resistance. The time that the device will be in current limit before turning
off is configured by CILTIMER and the time can be calculated using 公式 9. Connecting this pin to VIN will cause
the device to be disabled once the internal current limit timer expires as shown in 图 22. However, connecting it
to GND will disable the internal timer functionality completely and therefore, in the case of a short, the device will
remain at the programmed current limit indefinitely. When using the internal timer, only the fast trip off current
limit is active.
C(pF)
: ;
t µs =
(9)
The time that the device remains disabled after the current limit timer expires is configurable through a capacitor
connected from the RTIMER pin to GND. The RTIMER pin will charge the capacitor to 0.5 V after the switch is
turned off and will discharge it otherwise. The time can be calculated using 公式 9. Connecting this pin to GND
will keep the device disabled and it will require the device to be enabled by cycling the EN pin. The behavior of
the ILTIMER and RTIMER pins for a soft short, hard short and internal timer conditions are shown in 图 25, 图
26, and 图 27, respectively. Please notice that 图 25 and 图 26 assume the fault is not present after the switch
has been disabled and enabled again (retry mode). If the fault is present after the retry mode, the device will go
into current limit mode and this cycle will repeat until the fault is no longer present.
18
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Feature Description (接下页)
tILTIMER
Programmable IL
tSS
Fault is not present anymore
tRTIMER
TIME
Current
limit mode
Normal operation
Disable and retry mode
tSS
tILTIMER
tRTIMER
TIME
Current
limit mode
Normal operation
Disable and retry mode
0.5 V
TIME
Current
limit mode
Normal operation
Disable and retry mode
图 25. Soft Short Programmable Fault Timer Operation Connecting Capacitors to ILTIMER and RTIMER
Pins
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Feature Description (接下页)
Internal IL t 22 A (typ)
Fault is not
present anymore
tSS
tILTIMER
Programmable IL
tSS
Fast trip
mode
tRTIMER
TIME
Current
limit mode
Normal operation
Disable and retry mode
tSS
tSS
tILTIMER
Fast trip
mode
tRTIMER
TIME
Current
limit mode
Normal operation
Disable and retry mode
0.5 V
TIME
Current
limit mode
Fast trip
mode
Normal operation
Disable and retry mode
图 26. Hard Short Programmable Fault Timer Operation Connecting Capacitors to ILTIMER and RTIMER
Pins
20
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Feature Description (接下页)
Internal IL t 22 A (typ)
Internal timer
Programmable IL
Current limit behavior is gone and switch returned to
normal operation before internal current limit expired
Fast trip
mode
Switch disabled as internal current limit timer expired
TIME
Internal timer
tSS
Current limit behavior is gone and switch returned to
normal operation before internal current limit expired
Switch disabled as internal current limit timer expired
Fast trip
mode
TIME
VIN
GND
TIME
Fast trip
mode
Normal operation
Disabled mode
Current
图 27. Programmable Fault Timer Operation Using the Internal Current Limit Timer and Disabling the
Retry Mode
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Feature Description (接下页)
The programmable fault timers, ILTIMER and RTIMER, should be set in such a way that the capacitor for one
timer is discharged before the other timer expires to ensure proper operation. In the specific case of using the
internal ILTIMER, the RTIMER capacitor should be sized such that it is discharged before the internal ILTIMER
expires, assuming the fault is still present. 图 28 shows a situation where this constraint is not met as the
RTIMER is much larger than the ILTIMER and therefore, the CRTIMER is not discharged before the CILTIMER
reaches 0.5 V, which is when the ILTIMER will expire. In order to avoid this situation, the constraint shown in 公
式 10 must be met. Using this equation, once a capacitor for a timer has been selected (C1 in 公式 10), the
maximum value for the capacitor of the second timer can be determined. The internal pull-down resistance for
each of the timers can be found in the Electrical Characteristics table. For the situation shown in 图 28, C1 and
RPD1 in 公式 10 correspond to the RTIMER.
Fault is still present
tILTIMER
Programmable IL
Disable and retry mode
tRTIMER
TIME
Normal operation
Current limit mode
Retry timer
0.5 V
Timer capacitor must be discharged
before other timer expires
TIME
Normal operation
Current limit timer
图 28. Programmable Fault Timer Capacitors Constraint
C2(pF)
:
;
C1 µF <
8 × RPD1(À)
(10)
22
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Feature Description (接下页)
8.3.5 Current Sense
This pin will output a current proportional to the output current of the switch for current sensing applications. A
resistor to GND will convert this current to voltage for current sensing purposes. The output current will be the
switch current divided by 41,500. The CS pin will have a valid output 5 ms after the device has been enabled.
8.3.6 Parallel Operation
The TPS7H2201-SP can be configured in parallel operation either to increase the current capability, up to 12 A,
or to reduce the on-state resistance. In this case, all pins are shared as shown in 图 29, except the current limit
resistor (RIL) for proper operation of the internal current limit loop. The current limiting resistors must be sized as
described in the Programmable Current Limiting section.
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Feature Description (接下页)
VIN
VOUT
VIN
VOUT
CSS
SS-MASTER
CS-MASTER
SS
CS
RTIMER-MASTER
EN-MASTER
TPS7H2201-SP
RTIMER
EN
CRTIMER
ILTIMER-MASTER
OVP-MASTER
ILTIMER
IL
OVP
GND
CILTIMER
RIL
VIN
VOUT
CS-MASTER
SS-MASTER
SS
CS
RTIMER-MASTER
EN-MASTER
TPS7H2201-SP
RTIMER
EN
OVP-MASTER
ILTIMER-MASTER
ILTIMER
IL
OVP
GND
RIL
图 29. Parallel Configuration to Reduce Resistance or Increase Current Capability
24
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ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
8.4 Device Functional Modes
表 3 lists the VOUT pin states as determined by the EN pin.
表 3. VOUT Connection
EN PIN
< VILEN
> VIHEN
TPS7H2201-SP
Open
VIN
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS7H2201-SP device is a single channel, 6-A load switch with multiple programmable features such as
current limit, undervoltage and overvoltage, current limit and retry timers, and soft start. In addition, the
TPS7H2201-SP features a reverse current protection capability for power distribution applications and current
sensing for load monitoring purpose. The TPS7H2201-SP user's guide is available on the TI website,
TPS7H2201EVM-CVAL Evaluation Module (EVM) User's Guide. The guide highlights standard EVM
configurations, test results, schematic, and BOM for reference.
9.2 Typical Applications
In addition to the standard power management applications where a power switch can be used, there are 2 main
applications in which the TPS7H2201-SP can be used in space power applications:
•
•
Redundancy for primary and secondary voltage rails common in satellite applications
Protection for critical or SEL sensitive loads
9.2.1 Redundancy
In applications where primary and secondary (redundant) power rails are present, the TPS7H2201-SP is ideal to
implement redundancy because of its reverse current blocking capability. In this case, since the load switch is
placed at the input of the point of load regulator, the on-resistance of the switch is not as critical.
26
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TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
Typical Applications (接下页)
5 V
5 V Primary
VOUT
2.5 V
VIN
VOUT
CSS
SS
CS
EN Primary
TPS7H2201-SP
EN
RTIMER
ON
OFF
CRTIMER
TPS50601A-SP
(PoL REGULATOR)
ILTIMER
IL
OVP
GND
CILTIMER
RIL
5 V Secondary
VIN
VOUT
CSS
SS
CS
EN Secondary
TPS7H2201-SP
EN
RTIMER
ON
OFF
CRTIMER
ILTIMER
IL
OVP
GND
CILTIMER
图 30. Redundancy Example Using the TPS7H2201-SP
9.2.2 Protection
The protection features of the TPS7H2201-SP can also be used for SEL sensitive loads. In such case, the on-
resistance of the switch might be more relevant as it is placed after the point of load regulator but in such case,
two load switches can be placed in parallel to reduce the on-resistance if needed. The main advantages of using
the load switch at this location is faster response to SEL events and automatic recovery due to the retry mode of
the programmable fault timer.
版权 © 2018–2019, Texas Instruments Incorporated
27
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
Typical Applications (接下页)
2.5 V
5 V
VIN
VIN
VOUT
POINT OF LOAD
REGULATOR
LATCHUP SENSITIVE
DEVICE
Current sense flag
Device restart
SS
CS
TPS7H2201-SP
RTIMER
EN
ILTIMER
IL
OVP
GND
RIL
图 31. Protection Example Using the TPS7H2201-SP
9.2.3 Design Requirements
图 32 shows a typical application schematic that is applicable to both the redundancy and the protection
applications previously discussed.
VIN=5 V
VIN
VOUT
340 µF
340 µF
CSS
REN_TOP
ROVP_TOP
SS
CS
RCS
TPS7H2201-SP
RTIMER
EN
REN_BOT
CRTIMER
ILTIMER
IL
OVP
GND
ROVP_BOT
CILTIMER
RIL
图 32. Typical Application Schematic
表 4 shows the design parameters.
28
版权 © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
表 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
5 V
3.5 V
6.5 V
6 A
Undervoltage lockout set point
Overvoltage protection set point
Output current
Current limit
7.5 A
1 ms
1 ms
9 ms
340 µF
Current limit timer
Retry timer
Soft start time
Input and output capacitors
9.2.4 Detailed Design Procedure
9.2.4.1 Undervoltage Lockout
The undervoltage lockout set point is configured using the resistor divider, REN_TOP and REN_BOT connected to the
EN pin. Set the REN_TOP = 100 kΩ and, using 公式 1, calculate the value for REN_BOT. For an UVLO = 3.5 V,
REN_BOT = 15.5 kΩ. When choosing the UVLO set point, the resistor divider must ensure that the device will still
get enabled for the VIN used in the application. This is achieved by making sure that the VIHEN requirement is still
met with the chosen resistor divider and that the VIN needed to meet the requirement is smaller than the VIN
used in the application. 公式 11 shows this VIN and VIHEN requirement to set the UVLO point. For this particular
application, the requirement is met as the result is 4.84 V.
REN_TOP + REN_BOT
V
IHEN
×
Q VIN
REN_BOT
(11)
9.2.4.2 Overvoltage Protection
In a similar way to the UVLO set point, the overvoltage protection set point is configured using the resistor
divider, ROVP_TOP and ROVP_BOT connected to the OVP pin. Set the ROVP_TOP = 100 kΩ and, using 公式 2,
calculate the value for ROVP_BOT. For an OVP = 6.5 V, ROVP_BOT = 10.7 kΩ. When choosing the OVP set point,
the resistor divider must ensure that the device will still get enabled for the VIN used in the application. This is
achieved by making sure that the VOVPF requirement is still met with the chosen resistor divider and that the VIN
needed to meet the requirement is larger than the VIN used in the application. 公式 12 shows this VIN and VOVPF
requirement to set the OVP point. For this particular application, the requirement is met as the result is 5.16 V.
ROVP _TOP + ROVP _BOT
VOVPF
×
R VIN
ROVP _BOT
(12)
9.2.4.3 Current Limit
The current limit is configured using RIL. Based on the output current for this design, the minimum current limit
that can be programmed is IOUT + 1.5 A for a total of 7.5 A. As a result, using 公式 8, the resistor value is 6.53
kΩ.
9.2.4.4 Programmable Fault Timers
The programmable fault timers are configured using the CILTIMER and the CRTIMER capacitors. For this particular
design, both timers are set to 1 ms. Therefore, using 公式 9, the value for each capacitor is 2000 pF. These
capacitor values meet the requirement in 公式 10.
版权 © 2018–2019, Texas Instruments Incorporated
29
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
9.2.4.5 Soft Start Time
The soft start time is configured using the CSS capacitor. In order to calculate the value of the capacitor, the
VOUT slew rate needs to be calculated using 公式 3 to make sure the maximum VOUT slew rate requirement
shown in 公式 4 is satisfied. This requirement is particularly important for space applications where large output
capacitance is typically used, which translates to a lower maximum allowable VOUT slew rate. For this particular
design, the VOUT slew rate is 555 V/s which is less than the maximum VOUT slew rate of 882 V/s, meeting the
requirement from 公式 4. Now, the soft start capacitor value can be calculated as 117 nF using 公式 6, since VIN
= 5 V for this application.
9.2.5 Application Curves
The power-up behavior of this design example is shown in 图 33 and the current limit behavior is shown in 图 34.
VIN
ILTIMER
RTIMER
EN
VOUT
IOUT
IOUT
图 33. Power-up Behavior of the TPS7H2201-SP
图 34. ILTIMER and RTIMER Waveforms When IL is Set to
7.5 A
30
版权 © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
10 Power Supply Recommendations
The TPS7H2201-SP is designed to operate from an input voltage supply range between 1.5 V to 7 V. This
supply voltage must be well regulated and proper local bypass capacitors should be used for proper electrical
performance from VIN to GND. Due to stringent requirements for space applications, typically numerous input
bypass capacitors are used and the total capacitance is much larger than for commercial applications. The
TPS7H2201-SP Evaluation Module uses one 330-µF tantalum capacitor in parallel with one 10-µF and one 0.1-
µF ceramic capacitor.
11 Layout
11.1 Layout Guidelines
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects.
In general, the components should be placed close to the device such that traces remain as short as possible to
avoid parasitic capacitance. In addition, due to the possibility of large power dissipation in fault conditions (short
at VOUT), thermal vias should be placed in the PCB for the thermal pad.
11.2 Layout Example
16
15
14
13
1
2
3
4
VOUT
VOUT
VOUT
VOUT
SS
VIN
VIN
VIN
VIN
CS
As close to the
device as possible
TPS7H2201-SP
12
11
5
6
ILTIMER
IL
EN
Short
traces
10
9
7
8
OVP
GND
RTIMER
Thermal
vias
图 35. Layout Recommendation
版权 © 2018–2019, Texas Instruments Incorporated
31
TPS7H2201-SP
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
德州仪器 (TI)，《TPS7H2201EVM-CVAL 评估模块 (EVM) 用户指南》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
版权 © 2018–2019, Texas Instruments Incorporated
TPS7H2201-SP
www.ti.com.cn
ZHCSIS8B –SEPTEMBER 2018–REVISED MAY 2019
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2019, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-1722001VXC
ACTIVE
CFP
HKR
16
1
RoHS-Exempt
& Green
NIAU
N / A for Pkg Type
-55 to 125
5962-1722001VXC
TPS7H2201MHKRV
Samples
5962R1722001V9A
5962R1722001VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HKR
0
25
1
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
16
RoHS-Exempt
& Green
5962R1722001VXC
TPS7H2201MHKRV
TPS7H2201HKR/EM
TPS7H2201Y/EM
ACTIVE
ACTIVE
CFP
HKR
KGD
16
0
1
5
RoHS-Exempt
& Green
NIAU
N / A for Pkg Type
N / A for Pkg Type
25 to 25
25 to 25
TPS7H2201HKREM
Samples
Samples
XCEPT
RoHS & Green
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-1722001VXC
5962R1722001VXC
TPS7H2201HKR/EM
HKR
HKR
HKR
CFP
CFP
CFP
16
16
16
1
1
1
506.98
506.98
506.98
26.16
26.16
26.16
6220
6220
6220
NA
NA
NA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
TPS7H2201Y/EM
KGD
XCEPT
0
5
5 x 5
70
6.35
3.81
610
1.3
8.89
8.13
Pack Materials-Page 2
PACKAGE OUTLINE
HKR0016A
CFP - 2.416 mm max height
S
C
A
L
E
0
.
7
0
0
CERAMIC DUAL FLATPACK
9.88
9.38
B
METAL LID
A
PIN 1 ID
14X 1.27
16
1
11.26
10.76
(10.41)
2X 8.89
8
9
0.482
16X
0.382
(9.14)
0.2
C A B
METAL LID
C
2.416
1.850
0.177
0.097
(6.59)
1.04
0.84
25.142
24.642
HEATSINK
8
9
8.95
8.65
16
1
6.74
6.44
PIN 1 ID
4226020/C 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. Lid is connected to Heatsink.
4. The terminals are gold plated.
5. Falls within MIL-STD-1835 CDFP-F11A.
www.ti.com
EXAMPLE BOARD LAYOUT
HKR0016A
CFP - 2.416 mm max height
CERAMIC DUAL FLATPACK
(6.59)
(1.2) TYP
(0.6)
(1.2) TYP
(0.6)
(8.8)
PKG
(
0.2) TYP
(R0.05) TYP
PKG
HEATSINK LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
4226020/C 08/2022
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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Copyright © 2022，德州仪器 (TI) 公司
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