5962-8682601EA [TI]
High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register; 高速CMOS逻辑4位双向通用移位寄存器
| 型号： | 5962-8682601EA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register |
| 文件： | 总15页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC194, CD74HC194,
CD74HCT194
Data sheet acquired from Harris Semiconductor
SCHS164G
High-Speed CMOS Logic
4-Bit Bidirectional Universal Shift Register
September 1997 - Revised May 2006
Features
Description
• Four Operating Modes
The ’HC194 and CD74HCT194 are 4-bit shift registers with
Asynchronous Master Reset (MR). In the parallel mode (S0
and S1 are high), data is loaded into the associated flip-flop
and appears at the output after the positive transition of the
clock input (CP). During parallel loading serial data flow is
inhibited. Shift left and shift right are accomplished
synchronously on the positive clock edge with serial data
entered at the shift left (DSL) serial input for the shift left
mode, and at the shift right (DSR) serial input for the shift
- Shift Right, Shift Left, Hold and Reset
• Synchronous Parallel or Serial Operation
[ /Title
(CD74
HC194,
CD74H
CT194)
/Sub-
• Typical f
MAX
= 60MHz at V
= 5V, C = 15pF,
CC L
o
T = 25 C
A
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
right mode. Clearing the register is accomplished by a Low
applied to the Master Reset (MR) pin.
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
ject
(High-
Speed
CMOS
Logic
4-Bit
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
o
PART NUMBER
CD54HC194F3A
CD74HC194E
( C)
PACKAGE
16 Ld CERDIP
16 Ld PDIP
• Significant Power Reduction Compared to LSTTL
Logic ICs
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
CD74HC194M
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC194MT
CD74HC194M96
CD74HC194NSR
CD74HC194PW
CD74HC194PWR
CD74HC194PWT
CD74HCT194E
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
CD54HC194 (CERDIP)
CD74HC194 (PDIP, SOIC, SOP, TSSOP)
CD74HCT194 (PDIP)
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
TOP VIEW
MR
1
2
3
4
5
6
7
8
16 V
CC
DSR
15 Q
14 Q
13 Q
12 Q
0
1
2
3
D
D
D
D
0
1
2
3
11 CP
10 S1
DSL
9
S0
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2006, Texas Instruments Incorporated
1
CD54HC194, CD74HC194, CD74HCT194
Functional Diagram
3
4
5
6
15
14
13
12
D
D
D
D
Q
Q
Q
Q
0
1
2
3
0
1
2
3
7
2
9
10
1
11
GND = 8
= 16
DSL
DSR
S0
V
CC
S1
MR
CP
TRUTH TABLE
INPUTS
OUTPUT
OPERATING
MODE
Reset (Clear)
Hold (Do Nothing)
Shift Left
CP
X
X
↑
MR
L
S1
S0
X
l
DSR
DSL
X
D
Q
Q
Q
Q
n
0
1
2
3
X
l
X
X
X
X
l
X
L
L
L
L
H
X
X
X
X
X
X
q
q
q
q
q
q
q
q
d
q
q
q
q
q
d
q
0
1
1
1
2
2
0
0
1
2
3
3
1
1
2
3
H
h
h
l
l
l
L
↑
H
l
h
H
Shift Right
↑
H
h
h
h
X
L
q
2
2
3
↑
H
l
h
X
X
H
q
d
Parallel Load
↑
H
h
X
d
d
0
n
H = High Voltage Level,
h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,
L = Low Voltage Level,
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,
d
(q ) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock
n
n
Transition,
X = Don’t Care,
↑ = Transition from Low to High Level
2
CD54HC194, CD74HC194, CD74HCT194
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 2):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
3
CD54HC194, CD74HC194, CD74HCT194
DC Electrical Specifications
(Continued)
TEST
o
o
o
o
o
CONDITIONS
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Leakage
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
Current
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 3)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
CP
MR
0.6
0.55
0.25
1.10
DSL, DSR, D
Sn
n
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
4
CD54HC194, CD74HC194, CD74HCT194
Prerequisite For Switching Function
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Max. Clock Frequency
(Figure 1)
f
-
-
-
-
-
-
-
-
-
2
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
100
20
17
100
20
17
90
18
15
75
15
13
100
20
17
90
18
15
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
120
24
20
120
24
20
105
21
19
90
18
15
120
24
20
105
21
18
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
80
16
14
70
14
12
60
12
10
80
16
14
70
14
12
0
6
2
MR Pulse Width
(Figure 2)
t
t
W
W
4.5
6
ns
ns
Clock Pulse Width
(Figure 1)
2
ns
4.5
6
ns
ns
Set-up Time
Data to Clock (Figure 3)
t
2
ns
SU
4.5
6
ns
ns
Removal Time,
MR to Clock (Figure 2)
t
REM
2
ns
4.5
6
ns
ns
Set-Up Time
S1, S0 to Clock (Figure 4)
t
2
ns
SU
SU
4.5
6
ns
ns
Set-up Time
DSL, DSR to Clock (Figure 4)
t
2
ns
4.5
6
ns
ns
Hold Time
S1, S0 to Clock (Figure 4)
t
t
2
ns
H
H
4.5
6
0
0
0
ns
0
0
0
ns
Hold Time
Data to Clock (Figure 3)
2
0
0
0
ns
4.5
6
0
0
0
ns
0
0
0
ns
HCT TYPES
Max. Clock Frequency (Figure 1)
f
MAX
-
-
-
-
4.5
4.5
4.5
4.5
27
16
16
14
-
-
-
-
22
20
20
18
-
-
-
-
18
24
24
21
-
-
-
-
MHz
ns
MR Pulse Width (Figure 2)
Clock Pulse Width (Figure 1)
t
W
W
t
ns
Set-up Time, Data to Clock
(Figure 3)
t
ns
SU
Removal Time MR to Clock
(Figure 2)
t
-
4.5
12
-
15
-
18
-
ns
REM
5
Prerequisite For Switching Function (Continued)
TEST
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
PARAMETER
SYMBOL CONDITIONS
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Set-up Time
S1, S0 to Clock (Figure 4)
t
-
-
-
-
4.5
20
-
-
-
-
25
-
30
-
ns
SU
SU
Set-up Time
DSL, DSR to Clock (Figure 4)
t
4.5
4.5
4.5
14
0
18
0
-
-
-
21
0
-
-
-
ns
ns
ns
Hold Time
S1, S0 to Clock (Figure 4)
t
H
H
Hold Time
t
0
0
0
Data to Clock (Figure 3)
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
(V)
TYP
MAX
MAX
MAX
UNITS
Propagation Delay,
Clock to Output (Figure 1)
t
, t
PLH PHL
C = 50pF
L
2
-
-
175
35
30
-
220
44
37
-
265
53
45
-
ns
ns
ns
ns
4.5
6
-
Propagation Delay,
Clock to Q
t , t
PLH PHL
-
5
14
Output Transition Time
(Figure 1)
t
, t
TLH THL
C = 50pF
2
4.5
6
-
-
75
15
13
140
28
24
10
-
95
19
16
175
35
30
10
-
110
22
19
210
42
36
10
-
ns
ns
L
-
ns
Propagation Delay,
MR to Output (Figure 2)
t
C = 50pF
L
2
-
ns
PHL
4.5
6
-
ns
-
ns
Input Capacitance
C
-
-
-
-
-
pF
MHz
pF
IN
Maximum Clock Frequency
f
5
60
55
MAX
Power Dissipation
C
5
-
-
-
PD
Capacitance (Notes 4, 5)
HCT TYPES
Propagation Delay,
Clock to Output (Figure 1)
t
, t
PLH PHL
C = 50pF
L
4.5
5
-
15
-
37
-
46
-
56
-
ns
ns
ns
ns
Propagation Delay,
Clock to Q
t , t
PLH PHL
-
Output Transition Times
(Figure 1)
t
, t
TLH THL
C = 50pF
4.5
4.5
15
40
19
50
22
60
L
Propagation Delay,
t
C = 50pF
L
-
PHL
MR to Output (Figure 2)
Input Capacitance
C
-
-
-
-
-
10
-
10
-
10
-
pF
MHz
pF
IN
Maximum Clock Frequency
f
5
5
50
60
MAX
Power Dissipation
C
-
-
-
PD
Capacitance (Notes 4, 5)
NOTES:
3. C
is used to determine the dynamic power consumption, per gate.
PD
4. P = V
2
2
f + ∑ (C V
) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
CC
i
L
6
Test Circuits and Waveforms
t
t
f
r
INPUT LEVEL
CP
90%
MR
INPUT LEVEL
GND
V
10%
S
V
S
V
10%
S
V
V
S
S
t
GND
t
W
t
W
PLH
t
REM
INPUT LEVEL
GND
V
t
PHL
S
CP
Q
Q
t
PHL
90%
S
10%
V
V
S
V
S
t
t
TLH
THL
FIGURE 1. CLOCK PREREQUISITE TIMES AND
FIGURE 2. MASTER RESET PREREQUISITE TIMES AND
PROPAGATION DELAYS
PROPAGATION AND OUTPUT TRANSITION TIMES
VALID
VALID
S OR DS
INPUT LEVEL
INPUT LEVEL
V
S
DATA
CP
V
S
GND
GND
t
t
SU
H
t
SU
t
H
INPUT LEVEL
INPUT LEVEL
V
S
V
S
CP
GND
GND
FIGURE 3. DATA PREREQUISITE TIMES
FIGURE 4. PARALLEL LOAD OR SHIFT-LEFT/SHIFT-RIGHT
PREREQUISITE TIMES
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
5962-8682601EA
CD54HC194F3A
CD74HC194E
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC194EE4
CD74HC194M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC194M96
CD74HC194M96E4
CD74HC194ME4
CD74HC194MT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC194MTE4
CD74HC194NSR
CD74HC194NSRE4
CD74HC194PW
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
PW
PW
PW
PW
PW
PW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC194PWE4
CD74HC194PWR
CD74HC194PWRE4
CD74HC194PWT
CD74HC194PWTE4
CD74HCT194E
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT194EE4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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