5962-9050101Q2A [TI]
并联负载 8 位移位寄存器 | FK | 20 | -55 to 125;
| 型号： | 5962-9050101Q2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 并联负载 8 位移位寄存器 | FK | 20 | -55 to 125 移位寄存器 |
| 文件： | 总9页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
SN54HC166 . . . J OR W PACKAGE
SN74HC166 . . . D OR N PACKAGE
(TOP VIEW)
Synchronous Load
Direct Overriding Clear
Parallel-to-Serial Conversion
SER
V
CC
SH/LD
H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
A
B
C
Q
H
G
D
CLK INH
CLK
F
description
E
GND
CLR
The ’HC166 parallel-in or serial-in, serial-out
registers feature gated clock (CLK, CLK INH)
inputs and an overriding clear (CLR) input. The
parallel-in or serial-in modes are established by
the shift/load (SH/LD) input. When high, SH/LD
enables the serial (SER) data input and couples
the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel
(broadside) data inputs are enabled, and
synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is
inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input
positive-NORgate permitting one input to be used
asaclock-enableorclock-inhibitfunction. Holding
either CLK or CLK INH high inhibits clocking;
holding either low enables the other clock input.
This allows the system clock to be free running,
and the register can be stopped on command with
the other clock input. CLK INH should be changed
to the high level only when CLK is high. CLR
overrides all other inputs, including CLK, and
resets all flip-flops to zero.
SN54HC166 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
H
Q
B
4
5
6
7
8
C
NC
17
16
15
14
H
NC
G
D
F
CLK INH
9 10 11 12 13
NC – No internal connection
The SN54HC166 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC166 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
FUNCTION TABLE
OUTPUTS
INTERNAL
INPUTS
Q
PARALLEL
A . . . H
H
CLK INH CLK
SER
Q
Q
B
CLR
SH/LD
A
L
X
X
L
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
L
L
L
H
H
H
H
H
X
Q
Q
Q
H0
h
A0
B0
a . . . h
a
H
L
b
H
H
X
X
X
X
Q
Q
Gn
Q
Gn
Q
H0
An
An
B0
Q
Q
X
Q
A0
†
logic symbol
9
SRG8
CLR
R
15
M1 [Shift]
M2 [Load]
SH/LD
6
7
CLK INH
CLK
≥1
C3/1
1
SER
A
1, 3D
2, 3D
2, 3D
2
3
B
4
C
5
D
10
11
12
14
E
F
G
13
H
Q
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
logic diagram (positive logic)
A
B
C
D
E
F
G
H
2
3
4
5
10
11
12
14
15
1
SH/LD
SER
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
6
7
CLK INH
CLK
9
13
CLR
Q
H
Pin numbers shown are for the D, J, N, and W packages.
typical clear, shift, load, inhibit, and shift sequence
CLK
CLK INH
CLR
SER
SH/LD
A
H
L
B
C
H
L
D
Parallel
Inputs
E
H
L
F
G
H
H
H
L
L
L
Q
H
H
H
H
H
H
Inhibit
Serial Shift
Serial Shift
Clear
Load
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC166
MIN NOM
SN74HC166
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
‡
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
A
–55
–40
°C
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC166
SN74HC166
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 4 mA
4.5 V
6 V
0.26
0.26
±100
8
0.4
0.33
0.33
±1000
80
OL
= 5.2 mA
0.15
0.4
OL
I
I
V = V
I
or 0
6 V
±0.1
±1000
160
10
nA
µA
pF
I
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
C
2 V to 6 V
3
10
10
i
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC166
SN74HC166
A
V
UNIT
CC
MIN
0
MAX
6
MIN
0
MAX
4.2
21
MIN
0
MAX
5
2 V
4.5 V
6 V
f
Clock frequency
Pulse duration
0
31
0
0
25
MHz
clock
0
36
0
25
0
29
2 V
100
20
17
80
16
14
145
29
25
80
16
14
100
20
17
80
16
14
40
8
150
30
26
120
24
20
220
44
38
120
24
20
150
30
26
120
24
20
60
12
10
0
125
25
21
100
20
17
180
36
31
100
20
17
125
25
21
100
20
17
50
10
9
CLR low
4.5 V
6 V
t
w
ns
2 V
CLK high or low
4.5 V
6 V
2 V
SH/LD high before CLK↑
SER before CLK↑
4.5 V
6 V
2 V
4.5 V
6 V
2 V
t
su
Setup time
CLK INH low before CLK↑
Data before CLK↑
CLR inactive before CLK↑
SH/LD high after CLK↑
SER after CLK↑
4.5 V
6 V
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
7
2 V
0
0
4.5 V
6 V
0
0
0
0
0
0
2 V
5
5
5
4.5 V
6 V
5
5
5
5
5
5
t
h
Hold time
ns
2 V
4.5 V
6 V
0
0
0
5
5
5
0
0
0
5
5
5
0
0
0
5
5
5
CLK INH high after CLK↑
Data after CLK↑
2 V
4.5 V
6 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
11
SN54HC166
SN74HC166
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
f
t
t
t
31
36
36
25
29
MHz
max
PHL
pd
45
25
2 V
62
120
24
180
36
150
30
CLR
CLK
Q
Q
4.5 V
6 V
18
ns
ns
ns
H
H
13
20
31
26
2 V
75
150
30
225
45
190
38
4.5 V
6 V
15
13
26
38
32
2 V
38
75
110
22
95
Any
4.5 V
6 V
8
15
19
t
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
50
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC166, SN74HC166
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS117B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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