5962-9564201V2A_技术文档

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ꢌ ꢍꢌ ꢎꢅ ꢉꢏꢆ ꢐ ꢑꢆꢉꢄ ꢏꢒꢀ ꢆ ꢓꢉꢁꢀ ꢑꢔ ꢕ ꢅꢔ ꢓ ꢀ

ꢖ ꢕꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐ ꢒꢆ ꢗꢒ ꢆꢀ

SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

D

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

)

CC

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

= 3.3 V, T = 25°C

D

Latch-Up Performance Exceeds 500 mA Per

JESD 17

A

Support Unregulated Battery Operation

Down to 2.7 V

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

I

and Power-Up 3-State Support Hot

off

Insertion

SN74LVTH245A . . . RGY PACKAGE

(TOP VIEW)

SN54LVTH245A . . . FK PACKAGE

(TOP VIEW)

SN54LVTH245A . . . J OR W PACKAGE

SN74LVTH245A . . . DB, DW, NS,

OR PW PACKAGE

(TOP VIEW)

1

20

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

DIR

A1

V

CC

3

2

1 20 19

18

19

18

17

16

15

14

13

12

2

3

4

5

6

7

8

9

A3

A4

A5

A6

A7

B1

B2

B3

B4

B5

4

5

6

7

8

A1

A2

A3

A4

A5

A6

A7

A8

OE

B1

B2

B3

B4

B5

B6

B7

OE

B1

B2

B3

B4

B5

B6

B7

B8

17

16

15

14

A2

A3

A4

A5

9 10 11 12 13

A6

A7

A8

10

11

GND

description/ordering information

These octal bus transceivers are designed specifically for low-voltage (3.3-V) V

capability to provide a TTL interface to a 5-V system environment.

operation, but with the

CC

ORDERING INFORMATION

ORDERABLE

†

T

A

PACKAGE

TOP-SIDE MARKING

PART NUMBER

SN74LVTH245ARGYR

SN74LVTH245ADW

SN74LVTH245ADWR

SN74LVTH245ANSR

SN74LVTH245ADBR

SN74LVTH245APW

SN74LVTH245APWR

SN74LVTH245AGQNR

SN74LVTH245AZQNR

SNJ54LVTH245AJ

QFN − RGY

SOIC − DW

Tape and reel

Tube

LXH245A

LVTH245A

Tape and reel

Tube

SOP − NS

LVTH245A

LXH245A

SSOP − DB

−40°C to 85°C

TSSOP − PW

LXH245A

Tape and reel

VFBGA − GQN

Tape and reel

VFBGA − ZQN (Pb-free)

CDIP − J

Tube

SNJ54LVTH245AJ

SNJ54LVTH245AW

SNJ54LVTH245AFK

−55°C to 125°C

CFP − W

SNJ54LVTH245AW

SNJ54LVTH245AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢖꢕ ꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐꢒꢆ ꢗ ꢒꢆꢀ

SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

description/ordering information (continued)

These devices are designed for asynchronous communication between data buses. They transmit data from

the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)

input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup

or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

SN74LVTH245A . . . GQN OR ZQN PACKAGE

(TOP VIEW)

terminal assignments

1

2

3

4

1

A1

2

3

4

A

B

C

D

E

A

B

C

D

E

DIR

B2

A4

B6

A8

V

OE

B1

B3

B5

B7

CC

A3

A2

B4

A6

B8

A5

A7

GND

FUNCTION TABLE

INPUTS

OPERATION

OE

L

DIR

L

B data to A bus

A data to B bus

Isolation

L

H

X

logic diagram (positive logic)

1

2

DIR

19

18

OE

A1

B1

To Seven Other Channels

Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.

2

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ꢖ ꢕꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐ ꢒꢆ ꢗꢒ ꢆꢀ

SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

O

CC

Current into any output in the low state, I : SN54LVTH245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

O

SN74LVTH245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Current into any output in the high state, I (see Note 2): SN54LVTH245A . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

SN74LVTH245A . . . . . . . . . . . . . . . . . . . . . . 64 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

JA

(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W

(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W

(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The package thermal impedance is calculated in accordance with JESD 51-7.

4. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 5)

SN54LVTH245A SN74LVTH245A

UNIT

MIN

2.7

2

MAX

MIN

2.7

2

MAX

V

Supply voltage

3.6

V

CC

High-level input voltage

Low-level input voltage

Input voltage

IH

0.8

5.5

−24

48

0.8

5.5

−32

64

V

IL

V

I

High-level output current

Low-level output current

Input transition rise or fall rate

Power-up ramp rate

mA

ns/V

µs/V

°C

OH

OL

∆t/∆v

∆t/∆V

Outputs enabled

10

200

−55

200

−40

CC

T

A

Operating free-air temperature

125

85

NOTE 5: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

3

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ꢌꢍ ꢌꢎꢅ ꢉ ꢏꢆ ꢐꢑ ꢆꢉꢄ ꢏꢒ ꢀ ꢆꢓ ꢉꢁ ꢀꢑ ꢔꢕ ꢅ ꢔ ꢓꢀ

ꢖꢕ ꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐꢒꢆ ꢗ ꢒꢆꢀ

SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVTH245A

SN74LVTH245A

PARAMETER

TEST CONDITIONS

I = −18 mA

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 2.7 V,

−1.2

V

IK

CC

I

= 2.7 V to 3.6 V,

= 2.7 V,

I

= −100 µA

= −8 mA

= −24 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 48 mA

= 64 mA

V

−0.2

CC

2.4

V

−0.2

CC

2.4

OH

OL

V

OH

2

V

= 3 V

CC

2

0.2

0.5

0.2

0.5

0.4

0.5

V

= 2.7 V

0.4

V

OL

0.5

V

CC

= 3 V

0.55

1

V

= 3.6 V,

V = V

I CC

or GND

1

10

20

1

CC

Control inputs

= 0 or 3.6 V,

V = 5.5 V

I

10

20

1

CC

V = 5.5 V

I

µA

‡

V = V

V

CC

= 3.6 V

A or B ports

I

CC

V = 0

−5

100

I

V

= 0,

V or V = 0 to 4.5 V

I

µA

off

CC

O

V = 0.8 V

75

I

= 3 V

CC

V = 2 V

I

−75

A or B ports

I(hold)

500

−750

§

V

= 3.6 V ,

V = 0 to 3.6 V

I

CC

= 0 to 1.5 V, V = 0.5 V to 3 V,

CC

O

∗

100

µA

I

OZPU

OE = don’t care

V

= 1.5 V to 0, V = 0.5 V to 3 V,

CC

OE = don’t care

O

100

OZPD

Outputs high

Outputs low

0.19

5

0.19

5

V

I

= 3.6 V,

CC

= 0,

I

mA

O

CC

V = V

I

or GND

CC

Outputs disabled

0.19

V

= 3 V to 3.6 V, One input at V − 0.6 V,

CC

Other inputs at V

¶

0.2

∆I

CC

or GND

CC

C

V = 3 V or 0

4

9

4

9

pF

i

I

V

O

= 3 V or 0

io

∗

†

‡

§

¶

On products compliant to MIL-PRF-38535, this parameter is not production tested.

All typical values are at V = 3.3 V, T = 25°C.

CC

Unused terminals are at V

A

or GND.

CC

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

CC

4

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ꢌ ꢍꢌ ꢎꢅ ꢉꢏꢆ ꢐ ꢑꢆꢉꢄ ꢏꢒꢀ ꢆ ꢓꢉꢁꢀ ꢑꢔ ꢕ ꢅꢔ ꢓ ꢀ

ꢖ ꢕꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐ ꢒꢆ ꢗꢒ ꢆꢀ

SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

SN54LVTH245A

= 3.3 V

SN74LVTH245A

V

= 3.3 V

V

FROM

(INPUT)

TO

(OUTPUT)

CC

V

CC

= 2.7 V

PARAMETER

UNIT

CC

MIN

0.3 V

†

MIN

0.7

1.2

1.6

1.8

MAX

3.7

5.7

6.2

5.3

MIN

MAX

4.2

7.4

6.8

5.5

MIN TYP

MAX

3.5

5.5

5.9

5

MAX

4

t

1.2

1.3

1.7

2.2

2.3

2.1

3.2

3.4

3.5

3.4

PLH

PHL

PZH

PZL

PHZ

PLZ

A or B

OE

B or A

A or B

ns

4

7.1

6.5

5.1

OE

†

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

5

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ꢖꢕ ꢆ ꢇ ꢌ ꢎꢀꢆꢉꢆ ꢔ ꢐꢒꢆ ꢗ ꢒꢆꢀ

SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

PARAMETER MEASUREMENT INFORMATION

6 V

TEST

S1

Open

GND

500 Ω

From Output

Under Test

t

/t

PLH PHL

Open

6 V

t

/t

PLZ PZL

C

= 50 pF

t

/t

GND

L

PHZ PZH

500 Ω

(see Note A)

2.7 V

0 V

LOAD CIRCUIT

Timing Input

Data Input

1.5 V

t

w

t

h

su

2.7 V

0 V

2.7 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

Input

t

PLZ

PZL

t

PHL

PLH

PHL

Output

Waveform 1

S1 at 6 V

3 V

V

OH

1.5 V

t

Output

V

+ 0.3 V

OL

V

OL

(see Note B)

t

PZH

PHZ

PLH

Output

Waveform 2

S1 at GND

V

OH

V

OH

− 0.3 V

OH

1.5 V

Output

≈0 V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

5962-9564201Q2A

5962-9564201QRA

5962-9564201QSA

5962-9564201V2A

5962-9564201VRA

5962-9564201VSA

SN74LVTH245ADBLE

SN74LVTH245ADBR

ACTIVE

OBSOLETE

ACTIVE

FK

J

20

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

FK

J

LCCC

CDIP

CFP

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

Call TI

W

DB

SSOP

Call TI

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH245ADBRG4

SN74LVTH245ADW

ACTIVE

SSOP

SOIC

DB

DW

GQN

20

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH245ADWE4

SN74LVTH245ADWG4

SN74LVTH245ADWR

SN74LVTH245ADWRE4

SN74LVTH245ADWRG4

SN74LVTH245AGQNR

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

BGA MI

CROSTA

R JUNI

OR

1000

TBD

SNPB

Level-1-240C-UNLIM

SN74LVTH245ANSR

SN74LVTH245ANSRE4

SN74LVTH245APW

ACTIVE

SO

NS

PW

20

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH245APWE4

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH245APWLE

SN74LVTH245APWR

OBSOLETE TSSOP

PW

20

TBD

Call TI

ACTIVE

TSSOP

QFN

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH245APWRE4

SN74LVTH245APWRG4

SN74LVTH245ARGYR

SN74LVTH245ARGYRG4

SN74LVTH245AZQNR

PW

20

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

RGY

ZQN

1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR

no Sb/Br)

QFN

1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR

no Sb/Br)

BGA MI

CROSTA

R JUNI

1000 Green (RoHS &

no Sb/Br)

SNAGCU

Level-1-260C-UNLIM

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

OR

SNJ54LVTH245AFK

SNJ54LVTH245AJ

SNJ54LVTH245AW

ACTIVE

LCCC

CDIP

CFP

FK

J

20

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to

discontinue any product or service without notice. Customers should obtain the latest relevant information

before placing orders and should verify that such information is current and complete. All products are sold

subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent

TI deems necessary to support this warranty. Except where mandated by government requirements, testing

of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible

for their products and applications using TI components. To minimize the risks associated with customer

products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent

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endorsement thereof. Use of such information may require a license from a third party under the patents or

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property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for

that product or service voids all express and any implied warranties for the associated TI product or service

and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Amplifiers

Data Converters

DSP

Interface

Applications

Audio

Automotive

Broadband

Digital Control

Military

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Logic

Power Mgmt

Microcontrollers

Low Power Wireless

power.ti.com

microcontroller.ti.com

www.ti.com/lpw

Optical Networking

Security

Telephony

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Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	5962-9564201V2A
厂家：	TEXAS INSTRUMENTS
描述：	3.3-V ABT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 3.3 -V ABT八路缓冲器/驱动器，具有三态输出驱动器输出元件
文件：	总21页 (文件大小：943K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5962-9564201V2A [TI]

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