5962R1822201VXC [TI]
具有同步整流功能的耐辐射 QMLV、2MHz、双输出 PWM 控制器 | HFT | 22 | -55 to 125;
| 型号： | 5962R1822201VXC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有同步整流功能的耐辐射 QMLV、2MHz、双输出 PWM 控制器 | HFT | 22 | -55 to 125 控制器 |
| 文件： | 总74页 (文件大小：4274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7H5001-SP, TPS7H5002-SP, TPS7H5003-SP, TPS7H5004-SP
ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
TPS7H500x-SP 耐辐射加固保障2-MHz 电流模式PWM 控制器
1 特性
3 说明
• 辐射性能：
TPS7H500x-SP 耐辐射加固保障高速 PWM 控制器系
列。这些控制器提供的许多功能有助于设计面向太空应
用的直流/直流转换器拓扑。控制器具有精密的内部基
准 (0.613V +0.7%/-1% ） ， 可配置开关频率高达
2MHz。每个器件都提供可编程斜坡补偿和软启动功
能。
– 耐辐射加固保障(RHA) 高达
100krad(Si) TID
– SEL、SEB 和SEGR 抗扰度
LET = 75MeV-cm2/mg
– SET 和SEFI 额定抗扰度高达
LET = 75MeV-cm2/mg
TPS7H500x-SP 系列可通过 SYNC 引脚使用外部时钟
来驱动，也可使用内部振荡器以用户编程的频率来驱
动。此控制器系列为用户提供了各种选项，用于选择开
关输出、同步整流功能、死区时间（固定或可配置）、
前沿消隐时间（ 固定或可配置） 和占空比限制。
TPS7H500x-SP 系列中的每个器件都采用 22 引脚
CFP 封装。
– SET 表征期间未发现控制器输出跨导事件
• 输入电压：4V 至14V
• 在温度、辐射以及线路和负载调节范围内提供
0.613V +0.7%/-1% 的电压基准
• 开关频率范围为100kHz 至2MHz
• 外部时钟同步功能
• 同步整流输出
– TPS7H5001-SP、TPS7H5002-SP、
TPS7H5003-SP
• 可调死区时间
表3-1. 器件信息
等级(2)
器件型号(1)
封装
5962R1822201VXC
5962R1822202VXC
5962R1822203VXC
5962R1822204VXC
TPS7H5001HFT/EM
TPS7H5002HFT/EM
TPS7H5003HFT/EM
TPS7H5004HFT/EM
5962R1822201V9A
5962R1822202V9A
5962R1822203V9A
5962R1822204V9A
TPS7H5001Y/EM
TPS7H5002Y/EM
TPS7H5003Y/EM
TPS7H5004Y/EM
– TPS7H5001-SP、TPS7H5002-SP
• 可调前沿消隐时间
飞行等级QMLV-
RHA
100krad(Si)
– TPS7H5001-SP、TPS7H5002-SP、
TPS7H5004-SP
• 可配置的占空比限值
CFP (22)
6.21mm × 7.69mm
质量= 415.6mg(4)
工程样片(3)
– TPS7H5001-SP、TPS7H5002-SP、
TPS7H5003-SP
• 可调斜坡补偿和软启动
• 热增强型CFP 封装
飞行等级QMLV-
RHA KGD
100krad(Si)
2 应用
• 用于FPGA、微控制器、数据转换器和ASIC 的太
空卫星负载点电源
• 通信负载
• 命令和数据处理
• 卫星电力系统
芯片
工程样片(3)
H/K
VBUS
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Driver
IN1 OUT1
Output
LP1
LP2
VIN
LS1
LS2
OUTB
Feedback Network
IN2 OUT2
+
VO
FAULT
OUTA
RT
Compensation Network
TPS7H5001-SP
(2) 有关器件等级的其他信息，请查看SLYB235。
(3) 这些器件仅适用于工程评估。器件按照不合规的流程进行加工
处理。这些器件不适用于鉴定、生产、辐射测试或飞行用途。
这些零器件无法在–55°C 至125°C 的完整MIL 额定温度范围
内或运行寿命中保证其性能。
RSC
COMP
VSENSE
SP
SS
REFCAP
CS_ILIM
SRA
PS
SRB
AVSS
RCS
Dead Time Control
(4) 质量误差在±10% 以内。
Driver
IN1 OUT1
Current Sense Filter
IN2 OUT2
Isolation
Isolation
TPS7H5001-SP 的典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSF07
TPS7H5001-SP, TPS7H5002-SP, TPS7H5003-SP, TPS7H5004-SP
ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................29
8.2 Functional Block Diagram.........................................30
8.3 Feature Description...................................................34
8.4 Device Functional Modes..........................................52
9 Application and Implementation..................................53
9.1 Application Information............................................. 53
9.2 Typical Application.................................................... 53
9.3 Power Supply Recommendations.............................63
9.4 Layout....................................................................... 63
10 Device and Documentation Support..........................66
10.1 Documentation Support ......................................... 66
10.2 接收文档更新通知................................................... 66
10.3 支持资源..................................................................66
10.4 Trademarks.............................................................66
10.5 静电放电警告.......................................................... 66
10.6 术语表..................................................................... 66
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications................................................................ 11
7.1 Absolute Maximum Ratings...................................... 11
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions.......................11
7.4 Thermal Information..................................................11
7.5 Electrical Characteristics: All Devices.......................12
7.6 Electrical Characteristics: TPS7H5001-SP...............14
7.7 Electrical Characteristics: TPS7H5002-SP...............15
7.8 Electrical Characteristics: TPS7H5003-SP...............15
7.9 Electrical Characteristics: TPS7H5004-SP...............16
7.10 Typical Characteristics............................................17
8 Detailed Description......................................................29
Information.................................................................... 67
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (September 2022) to Revision D (February 2023)
Page
• 将TPS7H5002-SP、TPS7H5003-SP 和TPS7H5004-SP 的器件状态从预告信息更改为量产数据.................1
Changes from Revision B (August 2022) to Revision C (September 2022)
Page
• 将TPS7H5002-SP、TPS7H5003-SP 和TPS7H5004-SP 器件状态更改为预告信息........................................1
• Updated Pin Configuration and Functions, Fuctional Block Diagram, and Current Sense and PWM
Generation (CS_ILIM) sections to detail 150-mV offset on CS_ILIM pin at PWM comparator input..................4
Changes from Revision A (February 2022) to Revision B (August 2022)
Page
• 将TPS7H5002-SP、TPS7H5003-SP 和TPS7H5004-SP 的器件状态从预告信息更改为量产数据.................1
• 更改了特性部分和整个文档中的电压基准容差说明，以更准确地反映规格限制................................................ 1
Changes from Revision * (July 2021) to Revision A (February 2022)
Page
• 将TPS7H5001-SP 器件状态从预告信息更改为量产数据.................................................................................1
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
5 Device Comparison Table
表5-1. TPS7H500x-SP Device Comparison
SYNCHRONOUS
RECTIFIER
LEADING EDGE
BLANK TIME
SETTING
DEAD-TIME
SETTING
DUTY CYCLE LIMIT
OPTIONS
DEVICE
PRIMARY OUTPUTS
OUTPUTS
Resistor
programmable
Resistor
programmable
TPS7H5001-SP
2
2
50%, 75%, 100%
Resistor
programmable
Resistor
programmable
TPS7H5002-SP
TPS7H5003-SP
TPS7H5004-SP
1
1
2
1
1
0
75%, 100%
75%, 100%
50%
Fixed (50-ns typical) Fixed (50-ns typical)
Resistor
Not applicable
programmable
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6 Pin Configuration and Functions
1
2
3
4
22
21
20
19
1
2
3
4
22
21
20
19
COMP
VSENSE
SS
COMP
VSENSE
SS
RT
PS
RT
PS
SP
SP
LEB
RSC
LEB
RSC
5
6
18
17
REFCAP
FAULT
CS_ILIM
VLDO
HICC
SYNC
DCL
EN
5
6
18
17
REFCAP
FAULT
CS_ILIM
VLDO
HICC
SYNC
DCL
EN
TPS7H5001-SP
TPS7H5002-SP
7
16
7
16
8
9
15
14
8
9
15
14
VIN
AVSS
VIN
AVSS
10
11
13
12
10
11
13
12
OUTA
OUTB
SRA
SRB
OUTA
NC
SRA
NC
图6-1. TPS7H5001-SP HFT Package
22-Pin CFP With Thermal Pad
(Top View)
图6-2. TPS7H5002-SP HFT Package
22-Pin CFP With Thermal Pad
(Top View)
1
2
3
4
22
21
20
19
1
2
3
4
22
21
20
19
COMP
VSENSE
SS
COMP
VSENSE
SS
RT
NC
NC
NC
RT
NC
NC
RSC
LEB
RSC
5
6
18
17
REFCAP
FAULT
CS_ILIM
VLDO
HICC
SYNC
DCL
EN
5
6
18
17
REFCAP
FAULT
CS_ILIM
VLDO
HICC
SYNC
DCL
EN
TPS7H5003-SP
TPS7H5004-SP
7
16
7
16
8
9
15
14
8
9
15
14
VIN
AVSS
VIN
AVSS
10
11
13
12
10
11
13
12
OUTA
NC
SRA
NC
OUTA
OUTB
NC
NC
图6-3. TPS7H5003-SP HFT Package
22-Pin CFP With Thermal Pad
(Top View)
图6-4. TPS7H5004-SP HFT Package
22-Pin CFP With Thermal Pad
(Top View)
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP
In internal oscillation mode, the RT pin
must be populated with a resistor to
AVSS. When the RT pin is floating, a
200-kHz to 4-MHz external clock is
required at the SYNC pin. The
RT
1
1
1
1
I/O
frequency of the external clock must be
twice the desired switching frequency.
Primary off to synchronous rectifier on
dead-time set. Programmable through
an external resistor to AVSS.
PS
SP
2
3
4
2
3
4
I/O
I/O
I/O
—
—
—
—
—
4
Synchronous rectifier off to primary on
dead-time set. Programmable through
an external resistor to AVSS.
Leading edge blank time set.
Programmable through an external
resistor to AVSS.
LEB
Cycle-by-cycle current limit time delay
and hiccup time setting. Delay time and
hiccup time determined by capacitor
from HICC to AVSS. Connecting this
pin to AVSS disables hiccup mode.
HICC
5
5
5
5
I/O
When the RT pin is floating, SYNC is
configured as an input for a 200-kHz to
4-MHz external clock. In this case, the
external clock input gets inverted and
the system clock will run at half the
frequency of the external clock input.
When the RT pin is populated with a
resistor to AVSS, SYNC outputs a 200-
kHz to 4-MHz clock signal at twice the
device switching frequency in phase
with the switching of the device.
SYNC
6
6
6
6
I/O
Duty cycle limit configurability. For
TPS7H5001-SP, connect to AVSS for
50% duty cycle limit, floating for 75%,
and VLDO for 100%. For TPS7H5002-
SP and TPS7H5003-SP, the DCL pin
can be left floating or connected to
VLDO to set the maximum duty cycle to
75% or 100%, respectively. For
DCL
7
7
7
7
I/O
TPS7H5004-SP, this pin must be
connected to AVSS in order to obtain
the 50% maximum duty cycle.
Connecting the EN pin to the VLDO pin
or external source greater than 0.6 V
enables the device. In addition, input
undervoltage lockout (UVLO) can be
adjusted with two resistors.
EN
8
8
8
8
I
Input supply to the device. Input voltage
range is from 4 V to 14 V.
VIN
9
9
9
9
I
OUTA
OUTB
10
11
10
—
10
—
10
11
O
O
Primary switching output A.
Primary switching output B. Active only
when DCL = AVSS.
Synchronous rectifier output B. Active
only when DCL = AVSS.
SRB
SRA
12
13
O
O
—
—
—
—
13
13
Synchronous rectifier output A.
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表6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP
Ground of the device. The thermal pad,
lid, and seal ring of the device are
internally connected to ground.
AVSS
14
15
14
15
14
15
14
15
—
Output of internal regulator. Requires at
least 1-μF external capacitor to AVSS.
VLDO
O
Current sense for PWM control and
cycle-by-cycle overcurrent protection.
An input voltage over 1.05 V on
CS_ILIM will trigger an overcurrent in
the PWM controller. The sensed
waveform on CS_ILIM contains a 150-
mV offset when compared to the
COMP/2 voltage at the input of the
PWM comparator.
CS_ILIM
16
16
16
16
I/O
Fault protection pin. When the rising
threshold of the FAULT pin is exceeded,
the outputs will stop switching. After the
external voltage drops below the falling
threshold, the device will restart after a
set delay. Connect this pin to AVSS to
disable FAULT.
FAULT
17
17
17
17
I
1.2-V internal reference. Requires a
470-nF external capacitor to AVSS.
REFCAP
RSC
18
19
18
19
18
19
18
19
O
A resistor from RSC to AVSS sets the
desired slope compensation.
I/O
Soft start. An external capacitor
connected to this pin sets the internal
voltage reference rise time. The voltage
on this pin overrides the internal
reference. It can be used for tracking
and sequencing.
SS
20
20
20
20
I/O
VSENSE
COMP
21
22
21
22
21
22
21
22
I
Inverting input of the error amplifier.
Error amplifier output. Connect
frequency compensation to this pin.
I/O
11, 12
2, 3, 4, 11, 12
2, 3, 12, 13
No connect. Can be connected to AVSS
to avoid floating metal if desired.
NC
N/A
—
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表6-2. TPS7H500x-SP Bare Die Information - Applicable for All Devices
BOND PAD
METALLIZATION
COMPOSITION
DIE THICKNESS
15 mils
BACKSIDE FINISH
BACKSIDE POTENTIAL
BOND PAD THICKNESS
Silicon with backgrind
GND
Al (0.5% Cu)
3000 nm
图6-5. TPS7H500x-SP Bare Die Diagram - Applicable for All Devices
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表6-3. TPS7H5001-SP Bond Pad Coordinates in Microns
DESCRIPTION
RT
PAD NUMBER
X MIN
Y MIN
3775.77
3392.37
3233.115
2955.015
2695.905
2427.705
2149.515
1923.165
1660.275
1432.53
1325.475
586.755
433.35
X MAX
Y MAX
3865.77
3482.37
3323.115
3045.015
2785.905
2517.705
2239.515
2013.165
1750.275
1522.53
1415.475
676.755
523.35
1
21.33
111.33
PS
2
21.33
111.33
SP
3
21.33
111.33
LEB
4
21.33
111.33
HICC
SYNC
DCL
5
21.33
111.33
6
32.13
122.13
7
32.13
122.13
NC
8
32.175
32.13
122.175
122.13
EN
9
VIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28.665
28.665
32.13
118.665
118.665
122.13
VIN
OUTA
OUTB
SRB
32.13
122.13
2224.62
2224.62
2235.42
2235.42
2235.42
2224.62
2224.62
2224.62
2224.62
2224.62
2235.42
2235.42
2235.42
2235.42
2235.42
132.93
2314.62
2314.62
2325.42
2325.42
2325.42
2314.62
2314.62
2314.62
2314.62
2314.62
2325.42
2325.42
2325.42
2325.42
2325.42
222.93
SRA
586.755
1053.315
1221.435
1330.425
1803.51
1912.545
2021.58
2274.3
676.755
1143.315
1311.435
1420.425
1893.51
2002.545
2111.58
AVSS
AVSS
AVSS
VLDO
VLDO
VLDO
CS_ILM
FAULT
REFCAP
RSC
2364.3
2513.16
2766.285
3033.36
3296.655
3563.64
3905.55
2603.16
2856.285
3123.36
3386.655
3653.64
3995.55
SS
VSENSE
COMP
表6-4. TPS7H5002-SP Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
111.33
111.33
111.33
111.33
111.33
122.13
122.13
122.175
122.13
118.665
118.665
122.13
122.13
2314.62
2314.62
Y MAX
RT
PS
SP
1
21.33
3775.77
3392.37
3865.77
2
21.33
3482.37
3323.115
3045.015
2785.905
2517.705
2239.515
2013.165
1750.275
1522.53
1415.475
676.755
523.35
3
21.33
3233.115
2955.015
2695.905
2427.705
2149.515
1923.165
1660.275
1432.53
1325.475
586.755
433.35
LEB
HICC
SYNC
DCL
NC
4
21.33
5
21.33
6
32.13
7
32.13
8
32.175
32.13
EN
9
VIN
10
11
12
13
14
15
28.665
28.665
32.13
VIN
OUTA
NC
32.13
NC
2224.62
2224.62
132.93
222.93
SRA
586.755
676.755
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表6-4. TPS7H5002-SP Bond Pad Coordinates in Microns (continued)
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
1143.315
AVSS
16
17
18
19
20
21
22
23
24
25
26
27
28
2235.42
2235.42
2235.42
2224.62
2224.62
2224.62
2224.62
2224.62
2235.42
2235.42
2235.42
2235.42
2235.42
1053.315
2325.42
2325.42
2325.42
2314.62
2314.62
2314.62
2314.62
2314.62
2325.42
2325.42
2325.42
2325.42
2325.42
AVSS
1221.435
1330.425
1803.51
1912.545
2021.58
2274.3
1311.435
1420.425
1893.51
2002.545
2111.58
2364.3
AVSS
VLDO
VLDO
VLDO
CS_ILM
FAULT
REFCAP
RSC
2513.16
2766.285
3033.36
3296.655
3563.64
3905.55
2603.16
2856.285
3123.36
3386.655
3653.64
3995.55
SS
VSENSE
COMP
表6-5. TPS7H5003-SP Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
RT
1
21.33
3775.77
3392.37
111.33
3865.77
3482.37
3323.115
3045.015
2785.905
2517.705
2239.515
2013.165
1750.275
1522.53
1415.475
676.755
523.35
NC
2
21.33
111.33
NC
3
21.33
3233.115
2955.015
2695.905
2427.705
2149.515
1923.165
1660.275
1432.53
1325.475
586.755
433.35
111.33
NC
4
21.33
111.33
HICC
SYNC
DCL
5
21.33
111.33
6
32.13
122.13
7
32.13
122.13
NC
8
32.175
32.13
122.175
122.13
EN
9
VIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28.665
28.665
32.13
118.665
118.665
122.13
VIN
OUTA
NC
32.13
122.13
NC
2224.62
2224.62
2235.42
2235.42
2235.42
2224.62
2224.62
2224.62
2224.62
2224.62
2235.42
2235.42
2235.42
2235.42
2235.42
132.93
2314.62
2314.62
2325.42
2325.42
2325.42
2314.62
2314.62
2314.62
2314.62
2314.62
2325.42
2325.42
2325.42
2325.42
2325.42
222.93
SRA
586.755
1053.315
1221.435
1330.425
1803.51
1912.545
2021.58
2274.3
676.755
1143.315
1311.435
1420.425
1893.51
2002.545
2111.58
AVSS
AVSS
AVSS
VLDO
VLDO
VLDO
CS_ILM
FAULT
REFCAP
RSC
SS
2364.3
2513.16
2766.285
3033.36
3296.655
3563.64
3905.55
2603.16
2856.285
3123.36
3386.655
3653.64
3995.55
VSENSE
COMP
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Y MAX
表6-6. TPS7H5004-SP Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
RT
NC
NC
1
21.33
3775.77
3392.37
111.33
3865.77
2
21.33
111.33
3482.37
3323.115
3045.015
2785.905
2517.705
2239.515
2013.165
1750.275
1522.53
1415.475
676.755
523.35
3
21.33
3233.115
2955.015
2695.905
2427.705
2149.515
1923.165
1660.275
1432.53
1325.475
586.755
433.35
111.33
LEB
4
21.33
111.33
HICC
SYNC
DCL
5
21.33
111.33
6
32.13
122.13
7
32.13
122.13
NC
8
32.175
32.13
122.175
122.13
EN
9
VIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28.665
28.665
32.13
118.665
118.665
122.13
VIN
OUTA
OUTB
NC
32.13
122.13
2224.62
2224.62
2235.42
2235.42
2235.42
2224.62
2224.62
2224.62
2224.62
2224.62
2235.42
2235.42
2235.42
2235.42
2235.42
132.93
2314.62
2314.62
2325.42
2325.42
2325.42
2314.62
2314.62
2314.62
2314.62
2314.62
2325.42
2325.42
2325.42
2325.42
2325.42
222.93
NC
586.755
1053.315
1221.435
1330.425
1803.51
1912.545
2021.58
2274.3
676.755
1143.315
1311.435
1420.425
1893.51
2002.545
2111.58
AVSS
AVSS
AVSS
VLDO
VLDO
VLDO
CS_ILM
FAULT
REFCAP
RSC
2364.3
2513.16
2766.285
3033.36
3296.655
3563.64
3905.55
2603.16
2856.285
3123.36
3386.655
3653.64
3995.55
SS
VSENSE
COMP
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
MAX
16
UNIT
VIN
RT, VSENSE, SS, RSC, COMP, PS, SP, HICC, LEB
3.3
7.5
7.5
7.5
7.5
7.5
3.3
150
150
Input
SYNC
V
EN, FAULT
DCL, CS_ILIM
OUTA, OUTB, SRA and SRB
VLDO
Output
V
REFCAP
TJ
Junction temperature
Storage temperature
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
14
UNIT
V
VIN
SRVIN
TJ
Supply voltage
4
Input voltage slew rate
Junction temperature
0.03
125
V/µs
°C
–55
7.4 Thermal Information
TP7H500x-SP
THERMAL METRIC(1)
CFP
22 PINS
33.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(bot)
RθJB
RθJC(bot)
ψJT
7.4
16.9
Junction-to-case (top) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.5
8.2
16.6
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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MAX UNIT
7.5 Electrical Characteristics: All Devices
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SUPPLY VOLTAGES AND CURRENTS
VIN
Operating input voltage
4
14
8
V
fSW = 500 kHz, No load for OUTA,
OUTB, SRA, and SRB
6.25
6.75
8.5
7.5
9
fSW = 1 MHz, No load for OUTA,
OUTB, SRA, and SRB
9.5
13.5
9.5
fSW = 2 MHz, No load for OUTA, OUTB,
SRA, and SRB
IDD
Operating supply current
mA
fSW = 500 kHz, CLOAD = 100 pF for
OUTA, OUTB, SRA, and SRB
fSW = 1 MHz, CLOAD = 100 pF for
OUTA, OUTB, SRA, and SRB
12
fSW = 2 MHz, CLOAD = 100 pF for
OUTA, OUTB, SRA, and SRB
14
19.5
IDD(dis)
VLDO
VLDO
Standby current
EN = 0 V
3
5.2
5.2
mA
V
Internal linear regulator output voltage
Internal linear regulator output voltage
4.75
4.65
5
5
5 V ≤VIN ≤14 V, fsw ≤1 MHz
5 V ≤VIN ≤14 V, fsw = 2 MHz
V
ENABLE AND UNDERVOLTAGE LOCKOUT
VENR
VENF
VENH
IEN
EN threshold rising
0.57
0.47
85
0.6
0.5
95
0.65
0.55
105
50
V
V
EN threshold falling
EN hysteresis voltage
EN pin input leakage current
mV
nA
V
VIN = 14 V, EN = 5 V
5
VLDOUVLOR VLDO UVLO rising
VLDOUVLOF VLDO UVLO falling
VLDOUVLOH VLDO UVLO hysteresis
SOFT START
3.44
3.29
115
3.55
3.4
135
3.66
3.51
160
V
mV
ISS
Soft-start current
SS = 0.3 V
1.98
2.7
3.32
µA
ERROR AMPLIFIER
EAgm
Transconductance
1150
1800
2500 µA/V
V/V
–2 µA < ICOMP < 2 µA, V(COMP) = 1 V
VSENSE = 0.6 V
EADC
DC gain
10000
EAISRC
EAISNK
EAro
Error amplifier source current
Error amplifier sink current
Error amplifier output resistance
Error amplifier input offset voltage
Error amplifier input bias current
Bandwidth
V(COMP) = 1 V, 100-mV input overdrive
V(COMP) = 1 V, 100-mV input overdrive
100
100
190
190
µA
µA
7
MΩ
mV
nA
EAOS
2
–2
EAIB
35
EABW
10
MHz
OSCILLATOR
VIN < 5 V
VIN ≥5 V
VIN < 5 V
VIN ≥5 V
0.8
0.8
SYNCIL
SYNCIH
SYNC in low-level
SYNC in high-level
V
V
3.5
3.5
200
40
FSYNC
DSYNC
SYNC in frequency range
SYNC in duty cycle
4000
60
kHz
%
Duty cycle of external clock
CLOAD = 25 pF
SYNC out low-to-high rise time (10%/
90%)
SYNCRT
6
15
ns
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7.5 Electrical Characteristics: All Devices (continued)
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SYNC out high-to-low fall time (10%/
90%)
SYNCFT
SYNCOL
CLOAD = 25 pF
IOL = 10 mA
IOH = 10 mA
6
17
500
0.5
ns
mV
V
SYNC out low level
VLDO –
SYNCOH
SYNC out high level (1)
EXTDT
Externally set frequency detection time RT = Open, f = 200 kHz
20
115
µs
95
190
105
210
RT = 1.07 MΩ
230
RT = 511 kΩ
Externally set frequency
FSWEXT
kHz
900
1000
2000
1100
2300
RT = 90.9 kΩ
1700
RT = 34.8 kΩ
VOLTAGE REFERENCE
Internal voltage reference initial
Measured at COMP, 25°C
0.609
0.613
0.615
tolerance
VREF
V
V
0.607
0.611
1.213
0.609
0.614
1.225
0.612
0.617
1.237
Measured at COMP, –55°C
Measured at COMP, 125°C
REFCAP = 470 nF
Internal voltage reference
REFCAP voltage
REFCAP
CURRENT SENSE, CURRENT LIMIT AND HICCUP
CCSR
COMP to CS_ILIM ratio
2.00
2.06
1.05
2.12
1.09
VCS_ILIM
Current limit (overcurrent) threshold
V
CS_ILIM = 1.3 V, COMP = 3 V,
VSENSE = REFCAP/2 V, CHICC = 3 nF,
LEB = 49.9 kΩ, fsw = 100 kHz
IHICC_DEL
Hiccup delay current
80
µA
IHICC_RST
VHICC_PU
VHICC_SD
VHICC_RST
Hiccup restart current
1
1.0
0.6
0.3
µA
V
Hiccup pull-up threshold
Hiccup shut-down threshold
Hiccup restart threshold
V
V
SLOPE COMPENSATION
0.033
0.066
0.333
0.666
fSW = 100 kHz, RSC = 1.18 MΩ
fSW = 200 kHz, RSC = 562 kΩ
fSW = 1000 kHz, RSC = 100 kΩ
fSW = 2000 kHz, RSC = 49.9 kΩ
Slope compensation
V/µs
FAULT
VFLTR
VFLTF
VFLTH
TFLT
FLT threshold rising
0.57
0.47
90
0.6
0.5
0.65
0.55
110
1.4
169
86
V
V
FLT threshold falling
FLT hysteresis voltage
FLT minimum pulse width
100
mV
µs
VFLT = 1 V
0.4
140
66
fsw = 100 kHz
fsw = 200 kHz
fsw = 1 MHz
fsw = 2 MHz
152
78
tDFLT
FLT delay duration
µs
14
17
21
7
11
14
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
PRIMARY AND SYNCHRONOUS RECTIFIER OUTPUTS
165
10
175
15
185
20
°C
°C
Low-level threshold
ISINK = 10 mA
0.5
V
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7.5 Electrical Characteristics: All Devices (continued)
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-level threshold
ISOURCE = 10 mA
4.5
V
RLOAD = 50 kΩ, CLOAD = 100 pF, 10% to
90%
Rise/fall time
10
17
ns
RSRC_P
RSINK_P
Output source resistance
Output sink resistance
15
15
IOUT = 20 mA, 5 V ≤VIN ≤14 V
IOUT = 20 mA, 5 V ≤VIN ≤14 V
Ω
Ω
(1) Bench verified. Not tested in production.
7.6 Electrical Characteristics: TPS7H5001-SP
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MINIMUM ON-TIME AND DEAD TIME
tMIN
Minimum on-time
85
11
ns
LEB = 10 kΩ, 5 V ≤VIN ≤14 V
PS = floating, 5 V ≤VIN ≤14 V, 90%
of OUTx falling to 10% of SRx rising,
OUTx and SRx floating
5
43
85
5
8
50
PS = 49.9 kΩ, 5 V ≤VIN ≤14 V, 90%
of OUTx falling to 10% of SRx rising,
OUTx and SRx floating
TDPS
Primary off to secondary on dead time
55
110
11
ns
PS = 107 kΩ, 5 V ≤VIN ≤14 V, 90%
of OUTx falling to 10% of SRx rising,
OUTx and SRx floating
100
8
SP = floating, 5 V ≤VIN ≤14 V, 90%
of SRx falling to 10% of OUTx rising,
OUTx and SRx floating
SP = 49.9 kΩ, 5 V ≤VIN ≤14 V, 90%
of SRx falling to 10% of OUTx rising
edge, OUTx and SRx floating
TDSP
Secondary off to primary on dead time
43
85
50
55
ns
SP = 107 kΩ, 5 V ≤VIN ≤14 V, 90%
of SRx falling to 10% of OUTx rising,
OUTx and SRx floating
100
110
LEADING EDGE BLANK TIME AND DUTY CYCLE
12
45
85
45
70
15
50
19
55
LEB = 10 kΩ, 5 V ≤VIN ≤14 V
LEB = 49.9 kΩ, 5 V ≤VIN ≤14 V
LEB = 110 kΩ, 5 V ≤VIN ≤14 V
DCL = AVSS
TLEB
Leading edge blank time
Maximum duty cycle
ns
%
100
48
110
50
DMAX
DCL = floating, clock duty cycle = 50%
DCL = VLDO
75
80
100
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7.7 Electrical Characteristics: TPS7H5002-SP
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MINIMUM ON-TIME AND DEAD TIME
tMIN
Minimum on-time
85
11
ns
LEB = 10 kΩ, 5 V ≤VIN ≤14 V
PS = floating, 5 V ≤VIN ≤14 V, 90%
of OUTx falling to 10% of SRx rising,
OUTx and SRx floating
5
43
85
5
8
50
PS = 49.9 kΩ, 5 V ≤VIN ≤14 V, 90%
of OUTx falling to 10% of SRx rising,
OUTx and SRx floating
TDPS
Primary off to secondary on dead time
55
110
11
ns
PS = 107 kΩ, 5 V ≤VIN ≤14 V, 90%
of OUTx falling to 10% of SRx rising,
OUTx and SRx floating
100
8
SP = floating, 5 V ≤VIN ≤14 V, 90%
of SRx falling to 10% of OUTx rising,
OUTx and SRx floating
SP = 49.9 kΩ, 5 V ≤VIN ≤14 V, 90%
of SRx falling to 10% of OUTx rising
edge, OUTx and SRx floating
TDSP
Secondary off to primary on dead time
43
85
50
55
ns
SP = 107 kΩ, 5 V ≤VIN ≤14 V, 90%
of SRx falling to 10% of OUTx rising,
OUTx and SRx floating
100
110
LEADING EDGE BLANK TIME AND DUTY CYCLE
12
45
85
70
15
50
19
55
LEB = 10 kΩ, 5 V ≤VIN ≤14 V
LEB = 49.9 kΩ, 5 V ≤VIN ≤14 V
LEB = 110 kΩ, 5 V ≤VIN ≤14 V
DCL = floating, clock duty cycle = 50%
DCL = VLDO
TLEB
Leading edge blank time
Maximum duty cycle
ns
%
100
75
110
80
DMAX
100
7.8 Electrical Characteristics: TPS7H5003-SP
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MINIMUM ON-TIME AND DEAD TIME
tMIN
Minimum on-time
115
60
ns
ns
5 V ≤VIN ≤14 V
5 V ≤VIN ≤14 V, 90% of OUTx falling
to 10% of SRx rising, OUTx and SRx
floating
TDPS
Primary off to secondary on dead time
40
40
50
50
5 V ≤VIN ≤14 V, 90% of SRx falling
to 10% of OUTx rising edge, OUTx and
SRx floating
TDSP
Secondary off to primary on dead time
60
ns
LEADING EDGE BLANK TIME AND DUTY CYCLE
TLEB
Leading edge blank time
45
70
50
75
55
80
ns
%
5 V ≤VIN ≤14 V
DCL = floating, clock duty cycle = 50%
DCL = VLDO
DMAX
Maximum duty cycle
100
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MAX UNIT
7.9 Electrical Characteristics: TPS7H5004-SP
TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER
MINIMUM ON-TIME
tMIN Minimum on-time
LEADING EDGE BLANK TIME AND DUTY CYCLE
TEST CONDITIONS
MIN
TYP
85
ns
LEB = 10 kΩ, 5 V ≤VIN ≤14 V
12
45
85
45
15
50
19
55
LEB = 10 kΩ, 5 V ≤VIN ≤14 V
LEB = 49.9 kΩ, 5 V ≤VIN ≤14 V
LEB = 110 kΩ, 5 V ≤VIN ≤14 V
DCL = AVSS
TLEB
Leading edge blank time
Maximum duty cycle
ns
%
100
48
110
50
DMAX
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7.10 Typical Characteristics
10
10
9
9
8
7
6
5
4
8
7
-55°C
25°C
125°C
-55°C
25°C
125°C
6
5
4
0
500
1000
Frequency (kHz)
1500
2000
0
500
1000
Frequency (kHz)
1500
2000
VIN = 5 V
图7-1. Operating Current Variation
VIN = 12 V
图7-2. Operating Current Variation
2.4
2.45
2.35
2.25
2.15
2.05
1.95
2.3
2.2
2.1
2
-55°C
25°C
125°C
1.9
1.8
1.7
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
图7-3. Standby Current Variation
VIN (V)
VIN = 5 V to 14 V
图7-4. Standby Current Variation
3.525
3.515
3.505
3.495
3.485
3.4
3.39
3.38
3.37
3.36
3.35
3.34
-55°C
25°C
125°C
-55°C
25°C
125°C
0
500
1000
Frequency (kHz)
1500
2000
0
500
1000
Frequency (kHz)
1500
2000
图7-5. VLDO UVLO Rising Variation
图7-6. VLDO UVLO Falling Variation
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7.10 Typical Characteristics (continued)
0.618
0.522
0.52
0.616
0.518
0.516
0.514
0.512
0.51
0.614
-55°C
25°C
125°C
0.612
0.61
-55°C
25°C
125°C
0.608
0.508
4
5
6
7
8
9
10
11
12
13
14
4
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
图7-7. Enable Threshold Rising Variation
图7-8. Enable Threshold Falling Variation
2.72
2.7
2.72
2.7
2.68
2.66
2.64
-55°C
25°C
125°C
2.68
2.66
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
图7-9. Soft-Start Current Variation
VIN (V)
VIN = 5 V to 14 V
图7-10. Soft-Start Current Variation
0.60933
0.60932
0.60931
0.6093
0.60936
0.609355
0.60935
0.609345
0.60934
0.609335
0.60933
0.609325
0.60932
0.60929
0.60928
0.60927
0.60926
5
6
7
8
9
10
11
12
13
14
4
4.2
4.4
4.6
4.8
5
VIN (V)
VIN (V)
VIN = 5 V to 14 V
VIN = 4 V to 5 V
Temp. = –55°C
Temp. = –55°C
图7-12. Voltage Reference Variation
图7-11. Voltage Reference Variation
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
7.10 Typical Characteristics (continued)
0.61294
0.612945
0.61294
0.612935
0.61293
0.612925
0.61292
0.61292
0.6129
0.61288
0.61286
0.61284
5
6
7
8
9
10
11
12
13
14
4
4.2
4.4
4.6
4.8
5
VIN (V)
VIN (V)
VIN = 5 V to 14 V
Temp. = 25°C
VIN = 4 V to 5 V
Temp. = 25°C
图7-14. Voltage Reference Variation
图7-13. Voltage Reference Variation
0.6138
0.61377
0.61374
0.61371
0.61368
0.61365
0.61362
0.61359
0.613815
0.61381
0.613805
0.6138
0.613795
0.61379
0.613785
0.61378
0.613775
5
6
7
8
9
10
11
12
13
14
4
4.2
4.4
4.6
4.8
5
VIN (V)
VIN (V)
VIN = 5 V to 14 V
Temp. = 125°C
VIN = 4 V to 5 V
Temp. = 125°C
图7-16. Voltage Reference Variation
图7-15. Voltage Reference Variation
1.07
1.0675
1.065
1.07
1.068
1.066
1.064
1.062
1.06
-55°C
25°C
125°C
1.0625
1.06
-55°C
25°C
125°C
1.0575
1.055
1.058
1.0525
1.056
5
4
4.2
4.4
4.6
4.8
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
图7-17. Current Limit Threshold Variation
VIN = 5 V to 14 V
图7-18. Current Limit Theshold Variation
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7.10 Typical Characteristics (continued)
104
103
102
101
104
102
100
98
-55°C
25°C
125°C
-55°C
25°C
125°C
100
99
98
97
96
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 1.07 MΩ
RT = 1.07 MΩ
图7-19. Externally Set Frequency Variation
图7-20. Externally Set Frequency Variation
214
213
212
211
210
209
208
216
214
212
210
208
206
-55°C
25°C
125°C
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 511 kΩ
RT = 511 kΩ
图7-21. Externally Set Frequency Variation
图7-22. Externally Set Frequency Variation
1060
1040
1020
1000
980
1060
1040
1020
1000
980
-55°C
25°C
125°C
-55°C
25°C
125°C
960
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 90.9 kΩ
RT = 90.9 kΩ
图7-23. Externally Set Frequency Variation
图7-24. Externally Set Frequency Variation
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
7.10 Typical Characteristics (continued)
2150
2100
2050
2000
1950
1900
1850
1800
1750
1700
2200
2150
2100
2050
-55°C
25°C
125°C
2000
1950
1900
1850
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 34.8 kΩ
RT = 34.8 kΩ
图7-25. Externally Set Frequency Variation
图7-26. Externally Set Frequency Variation
85.5
85
85.5
85
84.5
84
84.5
84
83.5
83
-55°C
25°C
125°C
82.5
82
83.5
83
-55°C
25°C
125°C
81.5
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
图7-27. Hiccup Delay Current Variation
VIN (V)
VIN = 5 V to 14 V
图7-28. Hiccup Delay Current Variation
1.06
1.04
1.02
1
1.06
1.04
1.02
1
-55°C
25°C
125°C
-55°C
25°C
125°C
0.98
0.96
0.94
0.98
0.96
0.94
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
图7-29. Hiccup Restart Current Variation
VIN (V)
VIN = 5 V to 14 V
图7-30. Hiccup Restart Current Variation
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7.10 Typical Characteristics (continued)
0.608
0.508
0.506
0.504
0.502
0.5
0.606
0.604
0.602
-55°C
25°C
125°C
-55°C
25°C
125°C
0.6
0.598
0.498
0.496
0.596
4
5
6
7
8
9
10
11
12
13
14
4
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
图7-31. FAULT Threshold Rising Variation
图7-32. FAULT Threshold Falling Variation
20
19
18
17
16
15
14
18
17
16
15
-55°C
25°C
125°C
-55°C
25°C
125°C
14
5
4
4.2
4.4
4.6
4.8
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 10 kΩ
RT = 10 kΩ
图7-33. Leading Edge Blank Time Variation
图7-34. Leading Edge Blank Time Variation
54
53
52
51
50
52
51
50
-55°C
25°C
125°C
-55°C
25°C
125°C
49
5
4
4.2
4.4
4.6
4.8
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 49.9 kΩ
RT = 49.9 kΩ
图7-35. Leading Edge Blank Time Variation
图7-36. Leading Edge Blank Time Variation
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
7.10 Typical Characteristics (continued)
110
106
-55°C
25°C
108
106
104
102
100
98
125°C
-55°C
25°C
125°C
104
102
100
98
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 100 kΩ
RT = 100 kΩ
图7-37. Leading Edge Blank Time Variation
图7-38. Leading Edge Blank Time Variation
55
54
53
52
51
50
49
53
52
51
50
49
-55°C
25°C
125°C
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
TPS7H5003-SP
VIN = 5 V to 14 V
TPS7H5003-SP
图7-39. Leading Edge Blank Time Variation
图7-40. Leading Edge Blank Time Variation
9.5
9
9
8
7
-55°C
25°C
125°C
-55°C
25°C
125°C
8.5
8
7.5
7
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
RT = Floating
VIN = 5 V to 14 V
RT = Floating
图7-41. PS Dead Time Variation
图7-42. PS Dead Time Variation
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7.10 Typical Characteristics (continued)
54
52
51
50
49
-55°C
25°C
125°C
-55°C
25°C
125°C
53
52
51
50
49
4
4.2
4.4
4.6
4.8
4.8
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 49.9 kΩ
RT = 49.9 kΩ
图7-43. PS Dead Time Variation
图7-44. PS Dead Time Variation
106
102
101
100
99
-55°C
25°C
125°C
104
102
100
98
-55°C
25°C
125°C
98
96
97
4
4.2
4.4
4.6
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 100 kΩ
RT = 100 kΩ
图7-45. PS Dead Time Variation
图7-46. PS Dead Time Variation
56
55
54
53
52
51
50
49
53
52
51
50
49
-55°C
25°C
125°C
-55°C
25°C
125°C
4
4.2
4.4
4.6
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
TPS7H5003-SP
VIN = 5 V to 14 V
TPS7H5003-SP
图7-47. PS Dead Time Variation
图7-48. PS Dead Time Variation
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
7.10 Typical Characteristics (continued)
8
8
-55°C
25°C
125°C
-55°C
25°C
125°C
7
6
5
7
6
5
4
4.2
4.4
4.6
4.8
4.8
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
RT = Floating
VIN = 5 V to 14 V
RT = Floating
图7-49. SP Dead Time Variation
图7-50. SP Dead Time Variation
51
50
49
48
50
-55°C
25°C
-55°C
25°C
125°C
125°C
49
48
47
4
4.2
4.4
4.6
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 49.9 kΩ
RT = 49.9 kΩ
图7-51. SP Dead Time Variation
图7-52. SP Dead Time Variation
102
100
98
101
100
99
-55°C
25°C
125°C
-55°C
25°C
125°C
98
97
96
96
95
94
94
92
93
4
4.2
4.4
4.6
5
5
6
7
8
9
10
VIN (V)
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 100 kΩ
RT = 100 kΩ
图7-53. SP Dead Time Variation
图7-54. SP Dead Time Variation
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7.10 Typical Characteristics (continued)
54
51
50
49
48
47
46
-55°C
25°C
125°C
52
50
48
46
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
TPS7H5003-SP
VIN = 5 V to 14 V
TPS7H5003-SP
图7-55. SP Dead Time Variation
图7-56. SP Dead Time Variation
14
13
12
11
10
9
13
12
11
10
9
-55°C
25°C
125°C
-55°C
25°C
125°C
8
8
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
图7-57. Output Rise Time Variation
VIN = 5 V to 14 V
图7-58. Output Rise Time Variation
12
11
10
9
11
10
9
-55°C
25°C
125°C
-55°C
25°C
125°C
8
8
7
7
6
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
图7-59. Output Fall Time Variation
VIN = 5 V to 14 V
图7-60. Output Fall Time Variation
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ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
7.10 Typical Characteristics (continued)
25
25
22.5
20
22.5
-55°C
25°C
125°C
-55°C
25°C
125°C
20
17.5
15
17.5
15
12.5
10
12.5
10
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
图7-61. Output Source Resistance Variation
VIN (V)
VIN = 5 V to 14 V
图7-62. Output Source Resistance Variation
25
22.5
20
22
20
18
16
14
12
10
-55°C
25°C
125°C
-55°C
25°C
125°C
17.5
15
12.5
10
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN = 4 V to 5 V
图7-63. Output Sink Resistance Variation
VIN (V)
VIN = 5 V to 14 V
图7-64. Output Sink Resistance Variation
0.04
0.038
0.036
0.034
0.032
0.03
0.04
0.038
0.036
0.034
0.032
0.03
-55°C
25°C
125°C
-55°C
25°C
125°C
5
6
7
8
9
10
11
12
13
14
4
4.2
4.4
4.6
4.8
5
VIN (V)
VIN (V)
VIN = 5 V to 14 V
VIN = 4 V to 5 V
RT = 1.18 MΩ
RT = 1.18 MΩ
图7-66. Slope Compensation Variation
图7-65. Slope Compensation Variation
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7.10 Typical Characteristics (continued)
0.0775
0.075
0.0725
0.07
0.078
0.075
0.072
0.069
0.066
0.063
0.06
-55°C
25°C
125°C
0.0675
0.065
0.0625
0.06
-55°C
25°C
125°C
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 562 kΩ
RT = 562 kΩ
图7-67. Slope Compensation Variation
图7-68. Slope Compensation Variation
0.4
0.38
0.36
0.34
0.32
0.3
0.42
0.39
0.36
0.33
0.3
-55°C
25°C
125°C
-55°C
25°C
125°C
0.28
4
0.27
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 100 kΩ
RT = 100 kΩ
图7-69. Slope Compensation Variation
图7-70. Slope Compensation Variation
0.7
0.675
0.65
0.61
0.6
-55°C
25°C
125°C
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.625
0.6
0.575
0.55
-55°C
25°C
125°C
0.525
4
4.2
4.4
4.6
4.8
5
5
6
7
8
9
10
11
12
13
14
VIN (V)
VIN (V)
VIN = 4 V to 5 V
VIN = 5 V to 14 V
RT = 49.9 kΩ
RT = 49.9 kΩ
图7-71. Slope Compensation Variation
图7-72. Slope Compensation Variation
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8 Detailed Description
8.1 Overview
The TPS7H500x-SP series is a family of radiation-hardness-assured PWM controllers. Each controller features a
voltage reference of 0.613 V with accuracy of +0.7%/-1%. The switching frequency is configurable from 100 kHz
to 2 MHz, with external clock synchronization capability. The series consists of the full-featured device
TPS7H5001-SP, as well as the three additional specialized controllers TPS7H5002-SP, TPS7H5003-SP, and
TPS7H5004-SP.
The TPS7H5001-SP is a radiation-hardness-assured, current mode, dual output PWM controller optimized for
silicon (Si) and gallium nitride (GaN) based DC-DC converters in space applications. The switching frequency of
the TPS7H5001-SP can be configured from 100 kHz to 2 MHz while still maintaining a very low current
consumption, which makes it ideal for fully exploiting the area reduction and high efficiency benefits of GaN
based DC-DC converters. The device features integrated synchronous rectifier control outputs and dead-time
programmability in order to target high efficiency and high performance topologies. In addition, the TPS7H5001-
SP supports single-ended converter topologies by providing the user flexibility to control the maximum duty
cycle. The 0.613-V +0.7%/-1% accurate internal reference allows design of high-current buck converters for
FPGA core voltages.
The TPS7H5002-SP is a single output radiation-hardness-assured PWM controller that supports buck
applications and single ended isolated topologies. The controller contains an integrated synchronous rectification
output. Optimized for GaN power semiconductor based applications, the controller has configurable dead time
and configurable leading edge blank time. The controller can be configured for maximum duty cycle of 75% or
100%. As such, the DCL pin can be left floating or connected to VLDO. Connection of the DCL pin to AVSS is
not permissible for this device.
The TPS7H5003-SP is also a single output radiation-hardness-assured PWM controller that contains an
integrated synchronous rectification output. The dead time and leading edge blank time are fixed at 50 ns for this
device. The controller can be configured for maximum duty cycle of 75% or 100%. As such, the DCL pin can be
left floating or connected to VLDO. Connection of the DCL pin to AVSS is not permissible for this device.
The TPS7H5004-SP is a dual output radiation-hardness-assured PWM controller suited for usage in non-
synchronous push-pull and full-bridge topologies. The controller has configurable leading edge blank time. The
maximum duty cycle for this device is 50% and the DCL pin must be connected to AVSS.
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8.2 Functional Block Diagram
10
11
12
13
Over
Temperature
22 COMP
EN_INT
PWM_OUT
OCP
3.55V/3.4V
+
-
↓
UVLO
EN
Switching Logic
VLDO
VIN
VIN
EN
9
8
CLK
SS
+
+
20
EA
OCP
EN Detect
-
21 VSENSE
VREF
Ready
Voltage Ref.
VREF
REFCAP 18
COMP
COMPOV2
1/CCSR
+
-
150 mV
SSPD
+
-
CS_ILIM 16
Current Limit
VIN
1.05V
Hiccup
Timer
HICC
5
BG/LDO
15 VLDO
+
-
17
FAULT
Fault
Timer
AVDD
VLDO
7
DCL
0.6V/0.5V
SP
PS
RT
3
2
1
Deadtime
RT Bias
SYNC OUT EN
Slope
Comp
14 AVSS
SYNC
Detect
OSC
SYNC
6
19
4
图8-1. TPS7H5001-SP Functional Block Diagram
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10
11
12
13
Over
Temperature
22 COMP
EN_INT
PWM_OUT
OCP
3.55V/3.4V
VLDO
VIN
+
-
↓
UVLO
EN
Switching Logic
VIN
EN
9
8
CLK
SS
20
+
+
EA
OCP
EN Detect
-
21 VSENSE
VREF
Ready
Voltage Ref.
VREF
REFCAP 18
COMP
150 mV
COMPOV2
1/CCSR
+
-
SSPD
+
-
CS_ILIM 16
Current Limit
VIN
1.05V
Hiccup
Timer
HICC
5
BG/LDO
15 VLDO
+
-
17
FAULT
Fault
Timer
AVDD
VLDO
7
DCL
0.6V/0.5V
SP
PS
RT
3
2
1
Deadtime
RT Bias
SYNC OUT EN
Slope
Comp
14 AVSS
SYNC
Detect
OSC
SYNC
6
19
4
图8-2. TPS7H5002-SP Functional Block Diagram
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10
11
12
13
Over
Temperature
22 COMP
EN_INT
PWM_OUT
OCP
3.55V/3.4V
+
-
↓
UVLO
EN
Switching Logic
VLDO
VIN
VIN
EN
9
8
CLK
SS
+
+
20
EA
OCP
EN Detect
-
21 VSENSE
VREF
Ready
Voltage Ref.
VREF
REFCAP 18
COMP
COMPOV2
1/CCSR
+
-
150 mV
SSPD
+
-
CS_ILIM 16
Current Limit
VIN
1.05V
Hiccup
Timer
HICC
5
BG/LDO
15 VLDO
+
-
17
FAULT
Fault
Timer
AVDD
VLDO
7
DCL
0.6V/0.5V
NC
NC
RT
3
2
1
Deadtime
RT Bias
SYNC OUT EN
Slope
Comp
14 AVSS
SYNC
Detect
OSC
SYNC
6
19
4
图8-3. TPS7H5003-SP Functional Block Diagram
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10
11
12
13
Over
Temperature
22 COMP
EN_INT
PWM_OUT
OCP
3.55V/3.4V
VLDO
VIN
+
-
↓
UVLO
EN
Switching Logic
VIN
EN
9
8
CLK
SS
20
+
+
EA
OCP
EN Detect
-
21 VSENSE
VREF
Ready
Voltage Ref.
VREF
REFCAP 18
COMP
150 mV
COMPOV2
1/CCSR
+
-
SSPD
+
-
CS_ILIM 16
Current Limit
VIN
1.05V
Hiccup
Timer
HICC
5
BG/LDO
15 VLDO
+
-
17
FAULT
Fault
Timer
AVDD
VLDO
7
DCL
0.6V/0.5V
NC
NC
RT
3
2
1
RT Bias
SYNC OUT EN
Slope
Comp
14 AVSS
SYNC
Detect
OSC
SYNC
6
19
4
图8-4. TPS7H5004-SP Functional Block Diagram
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8.3 Feature Description
8.3.1 VIN and VLDO
During steady state operation, the input voltage of the TPS7H500x-SP must be between 4 V and 14 V. A
minimum bypass capacitance of at least 0.1 µF is needed between VIN and AVSS. The input bypass capacitors
should be placed as close to the controller as possible.
The voltage applied at VIN serves as the input for the internal regulator that generates the VLDO voltage (5 V).
At input voltages less than 5 V, the VLDO voltage will follow the voltage at VIN. Recommended capacitance for
VLDO is 1 µF. The EN and/or DCL pin can be tied to VLDO, but otherwise it is recommended to not externally
load this pin due to limited output current capability.
A voltage divider connected between VIN and the EN pin can adjust the input voltage UVLO appropriately.
8.3.2 Start-Up
Before the primary outputs of the controller will start switching, the following conditions must be met:
• VLDO exceeds the rising UVLO threshold of 3.55 V (typical)
• The internal 0.613 V reference voltage is available
• The enable signal EN is above the rising voltage threshold of 0.6 V (typical)
• The FAULT pin voltage is below the rising voltage threshold of 0.6 V (typical)
• The device junction temperature is below the thermal shutdown threshold of 175°C (typical)
Once all of the aforementioned conditions are satisfied, the soft-start process will be initiated.
8.3.3 Enable and Undervoltage Lockout (UVLO)
There are several methods for enabling the TPS7H500x-SP through the EN pin. The pin can be tied directly to
VLDO, which would allow for the device to be enabled as soon as the voltage on VLDO surpasses the rising
edge voltage threshold of the EN pin. The pin can also be driven with an externally generated signal or a
compatible PGOOD signal for instances in which sequencing is desired. Lastly, two resistors can be used to
program the controller to enable when VIN surpasses a user determined threshold, as shown in 图8-5 . The two
resistors are configured as a divider, with one between VIN and EN and the other between EN and AVSS.
VIN
TPS7H500x-SP
VIN
RUVLO_TOP
EN
+
0.65 V
-
To internal enabling
0.47 V
circuitry
RUVLO_BOT
AVSS
图8-5. Enable Pin Configuration Using Two External Resistors
Using 方程式 1, the user can calculate the value for RUVLO_TOP for a chosen value of RUVLO_BOT based on the
desired maximum start-up voltage for the device. With these selected resistors 方程式 2 can be used to
determine the minimum start-up voltage.
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VSTART ,MAX
RUVLO _TOP = RUVLO _BOT × F
F 1G
VEN_RISING _MAX
(1)
(2)
RUVLO _TOP
VSTART ,MIN = VEN_RISING _MIN × F
+ 1G
RUVLO _BOT
In the two-resistor configuration of 图 8-5, the controller will also shut down due to undervoltage lockout when
the input voltage falls below a particular threshold. This is due to the hysteresis of the EN pin. In order to
determine the voltages at which shutdown is expected to occur, use 方程式3 and 方程式4.
RUVLO _TOP
VSTOP ,MAX = VEN_FALLING _MAX × F
+ 1G
+ 1G
RUVLO _BOT
(3)
RUVLO _TOP
VSTOP ,MIN = VEN_FALLING _MIN × F
RUVLO _BOT
(4)
It is important to note that the user should take care when selecting the values for RUVLO_TOP and RUVLO_BOT. It
is recommended to optimize the selection of these resistors for start-up in order to ensure proper operation. The
UVLO value must be approximately 75% or less of the input voltage in order to ensure that the device turns on
as expected under all circumstances. Setting the UVLO any higher may cause issues with the turn-on of the
device. 图 8-6 shows the expected start-up and UVLO voltages on a 12-V rail where the maximum start-up
voltage is 90% of the nominal input voltage. In this instance, turn-off will occur when the input voltage falls to
between 75% and 65% of its nominal value.
VIN = 12V ±10%
+10%
-10%
Maximum VSTART 10.8 V
VIN
Minimum VSTART 9.5 V
Maximum VSTOP 9.1 V
Minimum VSTOP 7.8 V
t
图8-6. Start-Up and UVLO Values for Two-Resistor Configuration With VIN = 12 V
8.3.4 Voltage Reference
Each device generates an internal 1.23-V bandgap reference that is utilized throughout the various control logic
blocks. This is the voltage present on the REFCAP pin during steady state operation. This voltage is divided
down to 0.613 V to produce the reference for the error amplifier. The error amplifier reference is measured at the
COMP pin to account for offsets in the error amplifier and maintains regulation within +0.7%/-1% across line,
load, temperature, and TID as shown in 节7. This tight reference tolerance allows for the user to design a highly
accurate power converter. A 470-nF capacitor to ground is required at the REFCAP pin for proper electrical
operation as well as to ensure robust SET performance of the device.
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8.3.5 Error Amplifier
Each TPS7H500x-SP controller uses a transconductance error amplifier. The error amplifier compares the
VSENSE pin voltage to the lower of the SS pin voltage or the internal 0.613-V voltage reference. The
transconductance of the error amplifier is 1800 µA/V during normal operation. The frequency compensation
network is connected between COMP pin and AVSS. The error amplifier DC gain is typically 10,000 V/V.
8.3.6 Output Voltage Programming
The output voltage of the power converter is set by using a resistor divider from VOUT of the converter to the
VSENSE pin. The output voltage must be divided down to nominal voltage reference of 0.613 V. 方程式5 can be
used to select RBOTTOM
.
VREF
VOUT VREF
RBOTTOM
=
× RTOP
(5)
where:
• VREF is 0.613 V (typical)
• VOUT is the desired output voltage
• RTOP is the value of the top resistor, selected by the user (i.e. 10 kΩ)
The recommendation is to use high tolerance resistors (1% or less) for RBOTTOM and RTOP for improved output
voltage setpoint accuracy.
8.3.7 Soft Start (SS)
The soft-start circuit increases the output voltage of the converter gradually until the steady-state programmed
output is reached. During soft start, the error amplifier uses the voltage on the soft-start pin as its reference until
the SS pin voltage rises above VREF. Once the voltage at SS pin is above VREF, the soft-start period is complete.
Note that the voltage at SS pin will continue to rise and once it reaches 1 V, the synchronous rectifier outputs of
the controller will become active.
A capacitor between the SS pin and AVSS controls the soft-start time of the PWM controller. The following
equation can be used to select the capacitor for the desired soft-start time:
tSS × ISS
CSS
=
VREF
(6)
where:
• tSS is the desired soft-start time
• VREF is voltage reference of 0.613 V (typical)
• ISS is the soft-start charging current of 2.7 µA (typical)
8.3.8 Switching Frequency and External Synchronization
Each TPS7H500x-SP controller has three modes for setting the switching frequency of the device: internal
oscillator, external synchronization, and primary-secondary. The device is placed on one of these modes through
unique configurations of the RT and SYNC pins. Primary-secondary mode can be used when it is desired for two
controllers to have synchronized switching without the use of the external clock.
8.3.8.1 Internal Oscillator Mode
A resistor from the RT pin to AVSS sets the switching frequency of the device. The TPS7H500x-SP controller
has a switching frequency range of 100 kHz to 2 MHz. In internal oscillator mode, the RT pin must be populated
or the controller will not perform any switching. 方程式 7 shows the calculation determining the RT value for a
desired switching frequency. The curve in 图 8-7 shows the RT value that corresponds to a given switching
frequency for the TPS7H5001-SP.
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112000
RT =
19.7
fsw
(7)
where:
• RT is in kΩ
• fsw is in kHz
1200
1000
800
600
400
200
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Switching Frequency (kHz)
图8-7. RT vs Switching Frequency
In this mode, the SYNC pin is configured as an output and produces a clock signal with a frequency that is twice
that of the switching frequency set by RT. As such, this clock signal has a range of 200 kHz to 4 MHz. This
SYNC output clock signal is in phase with the switching frequency of the device. 图8-8 shows typical waveforms
for the controller in this mode of operation. Note that the OUTB waveform is only applicable for TPS7H5001-SP
and TPS7H5004-SP.
SYNC
(Output)
Internal
Clock
OUTA
OUTB
图8-8. Switching Waveforms for Internal Oscillator Mode
8.3.8.2 External Synchronization Mode
Each controller can be used in external synchronization mode by leaving the RT pin floating and applying a clock
to the SYNC pin. Note than the RT pin configuration sets the oscillator mode of the controller and must be left
floating for this mode of operation. The external clock that is applied must be set to twice the desired switching
frequency (i.e. a 1-MHz applied clock is needed for 500-kHz switching frequency). The external clock must be in
the range of 200 kHz to 4 MHz with a duty cycle between 40% and 60%. It is recommended to use an external
clock with 50% duty cycle. The controller will internally invert the clock signal that is applied at the SYNC pin
during this mode. Since the controller does not perform any switching with RT floating, the applied clock must be
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present before OUTA and OUTB will become active for external synchronization mode. 图 8-9 shows the
switching waveforms for the controller in external synchronization mode. Note that the OUTB waveform is only
applicable for TPS7H5001-SP and TPS7H5004-SP.
SYNC
(Input)
Internal
Clock
OUTA
OUTB
图8-9. Switching Waveforms for External Synchronization Mode
8.3.8.3 Primary-Secondary Mode
Two TPS7H500x-SP controllers can be operated in a primary-secondary mode by utilizing the SYNC pin. As
mentioned in the Internal Oscillator Mode section, when RT is selected to provide the desired switching
frequency, SYNC outputs a clock signal at twice the switching frequency. As such, the clock input generated by
the primary device be used as the clock input at SYNC for the secondary controller, which would operate in
external synchronization mode. This means that the RT pin of the primary device should be populated while the
corresponding pin of the secondary device would be left floating.
The primary-secondary mode would be useful in a couple of scenarios. The first is for two independent
converters that need to be synchronized to the same switching frequency. In this instance, the converters can be
two converters can have different operating conditions or topologies. Besides the shared SYNC signal, there are
no connections between the two converters.
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VOUT1
RTOP1
VSENSE
RT
RT
RBOTTOM1
COMP
RCOMP1
CCOMP1
CHF1
TPS7H500x-SP
(Primary)
SYNC
SS
CSS1
HICC
CHICC1
VOUT2
RTOP2
RBOTTOM2
VSENSE
COMP
RT
RCOMP2
CCOMP2
CHF2
TPS7H500x-SP
(Secondary)
SYNC
SS
CSS2
HICC
CHICC2
图8-10. Primary-Secondary Mode Configuration for Two Independent Converters
In a second scenario, two controllers can be used to design a single interleaved converter with phases in
parallel. In this design, the VSENSE, COMP, SS, and HICC pins would need to be connected in addition to the
shared SYNC connection.
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VOUT
RTOP1
RBOTTOM1
VSENSE
VSENSE
COMP
RT
RT
COMP
RCOMP1
CCOMP1
CHF1
TPS7H500x-SP
(Primary)
SS
SYNC
SS
CSS1
HICC
HICC
CHICC1
VSENSE
COMP
VSENSE
COMP
RT
TPS7H500x-SP
(Secondary)
SYNC
SS
SS
HICC
HICC
图8-11. Primary-Secondary Mode Configuration for Parallel Operation
When using two controllers in primary-secondary mode, it is important to note that secondary controller will invert
the clock signal that it receives from the primary controller. As such, there will be phase shift between the
switching outputs of the primary and secondary controllers. This phase shift from an output (i.e. OUTA) on the
primary controller to the corresponding output on the secondary controller will be 90° or 270°, depending on
when the secondary device synchronizes to its clock input. Note that in 图 8-12, the waveforms for OUTB are
only applicable for TPS7H5001-SP and TPS7H5004-SP.
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SYNC
Primary Internal Clock
Primary OUTA
Primary OUTB
270°
Secondary Clock 2
Secondary OUTA 2
Secondary OUTB 2
图8-12. Switching Waveforms for Primary-Secondary Mode
The three operational modes for the controller are summarized in 表8-1.
表8-1. Oscillator Modes and Configurations
MODE
RT
SYNC
SWITCHING FREQUENCY
Configured as output. Generates
Populated with resistor to AVSS. in-phase clock at twice the
switching frequency.
Configurable from 100 kHz to 2
MHz depending on RT value.
Internal oscillator
Synchronized to SYNC input
clock at 1/2 of the clock
frequency. Switching is out-of-
phase with external clock.
Configured as input. Accepts
200-kHz to 4-MHz external clock
that is inverted internally.
External synchronization
Primary-secondary
Floating.
Configured as output on primary Configurable from 100 kHz to 2
Populated with resistor to AVSS device. Configured as input on
MHz depending on RT value of
primary device. Secondary device
switching is either 90° or 270°
out-of-phase with primary device.
on primary device. Floating on
secondary device.
secondary device. The SYNC
pins of primary and secondary
devices are connected.
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8.3.9 Primary Switching Outputs (OUTA/OUTB)
The controllers in the TPS7H500x-SP series either have a single primary output (OUTA) or dual primary outputs
(OUTA and OUTB). 表 8-2 below shows the primary switching outputs that are available for each of the devices.
Due to the roughly 150-mA peak current capability of each primary switching output, an external gate drive
solution is recommended. For those controllers that support buck and single ended isolated applications
(TPS7H5001-SP, TPS7H5002-SP, and TPS7H5003-SP), OUTA provides the gate control signal for the main
switch in the topology. For push-pull and full-bridge applications, OUTA and OUTB both provide control signals
for the main primary switches. Note that OUTB is only active when the duty cycle limit is set to 50% by
connecting DCL pin to AVSS, and this DCL option is only valid for TPS7H5001-SP and TPS7H5004-SP (see
Duty Cycle Programmability for more details). For the two output controller options, OUTA and OUTB are not
perfectly matched and will vary based on the COMP voltage in a given switching cycle.
表8-2. Available Primary Output(s) for TPS7H500x-
SP
DEVICE
OUTA
OUTB
Yes
No
TPS7H5001-SP
TPS7H5002-SP
TPS7H5003-SP
TPS7H5004-SP
Yes
Yes
Yes
No
Yes
Yes
8.3.10 Synchronous Rectifier Outputs (SRA and SRB)
For applications in which synchronous rectification (SR) is desired in order to increase overall converter
efficiency, there are TPS7H500x-SP controllers with a single SR output (SRA) or dual SR outputs (SRA and
SRB). 表 8-3 below shows the synchronous rectifier outputs that are available for each of the devices. Similar to
the primary switching outputs, the peak current capability is roughly 150 mA and an external gate drive solution
is recommended. The TPS7H5001-SP is the only controller in the series that contains the SRB output, and this
output is only active when the duty cycle limit is set to 50% by connecting the DCL pin to AVSS. The SRA/SRB
outputs will be off during the soft-start period and start switching when the voltage on SS exceeds 1 V. A small
voltage transient may appear on the converter output when SRA/SRB become active.
表8-3. Available Synchronous Rectifier Output(s)
for TPS7H500x-SP
DEVICE
SRA
Yes
Yes
Yes
No
SRB
Yes
No
TPS7H5001-SP
TPS7H5002-SP
TPS7H5003-SP
TPS7H5004-SP
No
No
8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
While the TPS7H5003-SP has a fixed dead time (50 ns typical), the TPS7H5001-SP and TPS7H5002-SP allow
for the user to program two independent dead times, TDSP and TDPS, as shown in 图 8-13. This allows for the
dead times to be optimized by the user in order to prevent shoot-though between the primary and synchronous
switches while attaining the best possible converter efficiency. The dead time TDPS between primary output
(OUTA/OUTB) turn-off to synchronous rectifier (SRA/SRB) turn-on, can be programmed using a resistor from PS
to AVSS. Likewise, the dead time TDSP between synchronous rectifier turn-off and primary output turn-on is set
using a resistor from SP to AVSS. The equation for determining the values of RPS and RSP required for a desired
dead time is shown in 方程式8.
RPS = RSP = 1.207 × DT 8.858
(8)
where:
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• DT is the desired dead time in ns
• RPS and RSP are in kΩ
If the PS and SP pins are left floating, the dead time will be set to a minimum value of 8 ns (typical). When these
pins are populated, it is recommended to use a minimum resistor value of 10 kΩ for RPS and RSP. The
maximum resistor value to be used is 300 kΩ. As mentioned in Soft Start (SS) and Synchronous Rectifier
Outputs (SRA and SRB), the SR outputs will be disabled during soft start, so the dead time is observed only
after this sequence is complete.
After OUTA or OUTB goes high, a leading edge blank time is implemented to remove any transient noise from
the current sensing loop. While the leading edge blank time is fixed (50-ns typical) for TPS7H5003-SP, the
leading edge blank time for all other devices in the TPS7H500x-SP series is programmable by placing an
external resistor from LEB to AVSS. This pin cannot be left floating and a minimum resistor value of 10 kΩ is
required from LEB to AVSS. The maximum resistor value that should be used is 300 kΩ. The equation for
determining the value of RLEB for a desired leading edge blank time is shown in 方程式9.
RLEB = 1.212 × LEB 9.484
(9)
where:
• LEB is the desired leading edge blank time in ns
• RLEB is in kΩ
表8-4. Dead Time and Leading Edge Blank Time Configurations for TPS7H500x-SP
DEVICE
DEAD TIME
LEADING EDGE BLANK TIME
TPS7H5001-SP
TPS7H5002-SP
TPS7H5003-SP
TPS7H5004-SP
Resistor programmable
Resistor programmable
Fixed (50-ns typical)
Not applicable
Resistor programmable
Resistor programmable
Fixed (50-ns typical)
Resistor programmable
In 图8-13, the dead times and leading edge blank times are shown for the switching waveforms. This figure also
illustrates the minimum on-time of the device, which is comprised of the programmed blank time TLEB and an
internal logic delay td. Note that the dead-time waveforms for OUTB/SRB are only applicable for TPS7H5001-SP.
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图8-13. Outputs Timing Waveforms
8.3.12 Pulse Skipping
In order to prevent converter operational issues related to the minimum on-time of the controller, specifically
during high frequency operation, a pulse skipping mode has been implemented for the TPS7H500x-SP
controllers. During this mode, the primary outputs (OUTA/OUTB) will stop switching periodically. For the
controllers with SR outputs, SRA/SRB remain on during pulse skipping if the soft-start period has ended. If the
device enters into pulse skipping during the soft-start sequence, SRA/SRB remain off since the outputs are not
yet active. Having a minimum on-time that is too long in duration during high frequency operation can lead to an
issue such as inductor current runaway during the soft-start period. Pulse skipping allows for overcoming this
issue by reducing the peak inductor current during the startup period. In high frequency converter designs where
the VIN to VOUT ratio of the converter may lead to required duty cycles that are less than the minimum on-time,
the controller outputs will skip pulses in order to maintain the required output voltage. Pulse skipping will occur
when both of the following conditions are present:
• The voltage at the COMP pin is less than 0.3 V at the rising edge of the system clock
• The previous duty cycle was less than 25%
When the duty cycle limit of the controller is set to 50% and both OUTA and OUTB are active, the number of
pulses skipped by each of the primary outputs will be equal. This will ensure the volt-second balance is
maintained across the transformer and that flux-walking that leads to transformer saturation is avoided in
isolated topologies such as the push-pull.
8.3.13 Duty Cycle Programmability
The TPS7H5001-SP, TPS75002-SP, and TPS7H5003-SP each have a configurable maximum duty cycle using
the DCL pin. The TPS7H5004-SP only supports 50% maximum duty cycle and the DCL pin must be connected
to AVSS. 表8-5 shows the allowable maximum duty cycle limits for each device.
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表8-5. Allowable Duty Cycle Limits for TPS7H500x-
SP
DEVICE
DUTY CYCLE LIMIT OPTIONS
50%, 75%, 100%
75%, 100%
TPS7H5001-SP
TPS7H5002-SP
TPS7H5003-SP
TPS7H5004-SP
75%, 100%
50%
For applications in which 100% duty cycle is needed, the user should select one of the three compatible devices
and connect DCL to VLDO. For other applications which require a duty cycle limit restriction, the DCL pin could
be connected to AVSS for 50% duty cycle limit or left floating for 75% maximum duty cycle. Note that only
TPS7H5001-SP and TPS7H5004-SP support the 50% duty cycle limit (DCL = AVSS), and OUTB/SRB are only
active in this configuration. The 50% duty cycle limit case is intended to support applications such as the push-
pull that require two primary switching outputs, and in the case of the TPS7H5001-SP, two synchronous
rectification outputs. If the controller is being operated in external synchronization mode, the most precise duty
cycle limiting results are obtained when the applied system clock has a 50% duty cycle. Specifically, for the case
when the duty cycle limit is set to 75% (DCL = floating) in the supported devices, there may be some variation of
the duty cycle limit that is dependent on the duty cycle of the external clock applied at SYNC.
表8-6. DCL Pin Configurations
MAXIMUM DUTY CYCLE
DCL CONNECTION
(NOMINAL)
100%
75%
50%
VLDO
Floating
AVSS
8.3.14 Current Sense and PWM Generation (CS_ILIM)
The CS_ILIM pin is driven by a signal representative of the transformer primary-side current. The current signal
has to have compatible input range of the COMP pin. As shown in 图8-14, the COMP pin voltage is used as the
reference for the peak current. Note that the OUTB waveform is only applicable for TPS7H5001-SP and
TPS7H5004-SP. The primary side signals, OUTA/OUTB, are turned on by the internal clock signal and turned off
when sensed peak current reaches the COMP/2 pin voltage. Note that this peak sensed current signal that is
compared to COMP/2 at the PWM comparator contains an offset voltage of 150 mV. The CS_ILIM pin is also
used to configure the current limit for the controller.
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图8-14. Peak Current Mode Control and PWM Generation
A resistor is needed from CS_ILIM to AVSS is used to detect current for both proper PWM operation and
overcurrent protection. The current limit threshold VCS_ILIM, is specified as 1.05 V (nominal) in the electrical
specifications. This indicates that when the voltage on this pin reaches this threshold, the device will go into
hiccup mode. 方程式 10 shows the calculation for determining the value of the sense resistor for a selected
current limit.
VCS_ILIM
RCS
=
ILIM
(10)
Note that the value of ILIM has to account for where and how the current is being sensed. For a forward converter
with sense resistor between source of primary FET to AVSS, ILIM will be referred to the primary side of the
converter.
NS
ILIM = IL,PEAK
×
NP
(11)
方程式11 shows the calculation for determining ILIM in the design of a forward converter, where:
• IL,PEAK is the peak output inductor current desired to activate the overcurrent protection
• NS is the number of secondary turns for the power transformer
• NP is the number of primary turns for the power transformer
In the design of a buck converter which senses the high side current via a current sense transformer, 方程式 12
can be used for determining ILIM for this instance.
NCSP
ILIM = IL,PEAK
×
NCSS
(12)
In this equation:
• IL,PEAK is the peak output inductor current desired to activate the overcurrent protection
• NCSP is the number of primary turns of the current sense transformer
• NCSS is the number of secondary turns of the current sense transformer
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Regardless of the topology, the user should ensure that there is sufficient margin between the peak current
during normal operation and the overcurrent trip point when determining the value of RCS
.
8.3.15 Hiccup Mode Operation (HICC)
Once the voltage at CS_ILIM exceeds 1.05 V, the device will execute cycle-by-cycle current limiting. The
controller output is turned on at the beginning of each cycle until such point that CS_ILIM voltage reaches the
current sense threshold VCS_ILIM, when the output is turned off. At the same time, each time the voltage at
CS_ILIM reaches 1.05 V, the capacitor at CHICC is charged via a 80-µA current (hiccup delay current). This
hiccup delay current is terminated at the end of the clock cycle. As long as there is still an overcurrent being
detected, the cycle-by-cycle limiting will continue until the voltage on CHICC reaches 0.6 V. This cycle-by-cycle
limiting period is referred to as the delay mode. As such, the capacitor CHICC can be chosen to dictate the
amount of time that the controller will spend in delay mode.
tdelay × 80 A
CHICC
=
0.6 V
(13)
Note that this equation is an approximation since:
• depending on the system behavior and if CHICC has been charged previously, CHICC may not start at 0 V as
assumed by the equation
• the 80-μA charging current is a pulsed current, the duration of which will be dictated by the nature of the
overcurrent (that is,. when the current sense threshold is reached during each clock cycle)
After the voltage on HICC pin reaches 0.6 V, the SS pin of the controller is discharged and switching stops. The
voltage on HICC is then quickly pulled up to 1 V with the pull-up current limited to approximately 1 mA. Once
HICC voltage reaches 1 V, the 1-µA hiccup restart current begins to discharge CHICC. The controller will not
switch until HICC voltage falls to 0.3 V. Once the voltage falls to 0.3 V, the controller will initiate its soft-start
sequence again. If the overcurrent has disappeared, normal operation will resume. The hiccup time, which is the
entire non-switching period, can be calculated using 方程式14.
CHICC × (1 V 0.3 V)
tHICC
=
1 A
(14)
In summary, the capacitor CHICC on the HICC pin controls the amount of time the controller spends performing
cycle-by-cycle limiting before switching stops, and also controls the amount of time switching is disabled before
re-start is attempted again. It is recommended to use a minimum of 3.3 nF for CHICC. 图 8-15 shows the typical
behavior during hiccup mode. Note that the OUTB and corresponding CS_ILIM waveforms are only applicable
for TPS7H5001-SP and TPS7H5004-SP.
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NORMAL
OVERCURRENT
HICCUP
SOFT-START
OUTA
OUTB
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
t
t
t
t
1 V
CS_ILIM
.
. . . . . . . . . . . . .
1 mA
IHICC
80 µA
-1 µA
.
. . . . . . . . . . . . .
-1 mA
1 V
0.6 V
0.3 V
VHICC
t
t
1.5 V
SS
图8-15. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
8.3.16 External Fault Protection (FAULT)
The FAULT pin provides the user with flexibility to implement additional protections for the converter, such as
input overcurrent protection or overvoltage protection, if desired. This pin can also be utilized in the event that
the user desires more stringent protections than what is offered by the controller (i.e. thermal shutdown). The
user can design external logic circuitry to generate the signal necessary to drive this pin based on the protection
function. If the voltage on the FAULT pin exceeds 0.6 V (typical) for a duration specified by the FAULT minimum
pulse width, a fault shutdown will occur. This FAULT minimum pulse width duration, which is between 0.4 µs and
1.4 µs, is intended to prevent any spurious triggering due to short-term transients. Since any short-term transient
event detected on this pin that is less than 1.4 µs in duration may not activate the FAULT pin, these events
should be properly evaluated by the user in order to determine the impact to the overall system. Once the fault is
detected, the SS pin is discharged and the controller outputs stop switching and stay low as long as the rising
threshold is exceeded on the pin. Once the fault has subsided and the voltage of FAULT falls below the falling
threshold of 0.5 V (typical), the TPS7H500x-SP enters a delay period that is dependent on the switching
frequency. This delay is appoximately equal to 15 switching frequency cycles in addition to an internal logic
delay. The soft-start sequence is again initiated after the delay period has finished. 方程式 15 can be used to
determine the length of the fault delay.
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14700
fsw
tdFLT
=
+ 2
(15)
In this equation:
• tdFLT is the fault delay duration in μs
• fsw is the switching frequency in kHz
If the FAULT threshold is exceeded during the delay, the entire sequence is started again. 图 8-16 shows the
switching waveforms when the fault mode has been activated in the controller. Note that the OUTB waveforms
are only applicable for TPS7H5001-SP and TPS7H5004-SP.
图8-16. Switching Waveforms During Fault Mode
8.3.17 Slope Compensation (RSC)
When utilizing peak current mode control in switching power converter design, the converter can enter into an
unstable state when the duty cycle for the main power switch rises above 50%. Essentially, the converter will be
in a state where the error between the peak current and average current increases with each subsequent
switching cycle. This instability, known as subharmonic oscillation, can be mitigated by adding slope
compensation. For the TPS7H500x-SP, the slope compensation is in the form of a voltage ramp that is
subtracted from the error amplifier output divided down by the parameter CCSR (COMP to CS_LIM ratio). The
minimum slope compensation for stability over the entire duty cycle range is equal to 0.5 × m, where m is the
inductor falling current slope. The recommended slope compensation is 1 × m, as any increase above this value
will not improve stability.
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For a typical buck converter, setting the slope compensation equal to the downward slope of the sensed current
waveform yields the calculation in 方程式16.
VOUT NCSP
×
SC =
× RCS
L
NCSS
(16)
where:
• SC is the slope compensation value in V/μs
• L is the output inductor value in μH
• NCSP is the number of primary turns of the current sense transformer
• NCSS is the number of secondary turns on the current sense transformer
• RCS is the value of the current sense resistor in Ω
If no current sense transformer is used, set NCSP / NCSS to 1.
The slope compensation for the forward converter will be similar with the note that the sensed current waveform
would also need to take into account the turns ratio of the main power transformer.
VOUT NS NCSP
×
SC =
×
× RCS
L
NP NCSS
(17)
where:
• NS is the number of secondary turns of the power transformer
• NP is the number of primary turns of the power transformer
For the TPS7H500x-SP controllers, a resistor from the RSC pin to AVSS can be used to set the desired slope
compensation. 方程式18 shows the calculation for determining the proper resistor value for RSC.
28.3
SC1.1
RSC =
(18)
where:
• SC is the desired slope compensation is V/μs
• RSC is in kΩ
8.3.18 Frequency Compensation
Since the TPS7H500x-SP uses a transconductance error amplifier (OTA), either Type 2A or Type 2B frequency
compensation can be applied. The primary difference between the two compensation schemes is that Type 2A
has an additional capacitor CHF in parallel with RCOMP and CCOMP in order to provide high-frequency noise
attenuation. These components will be connected between the COMP pin of the controller, which is the OTA
output, and AVSS.
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TPS7H500x-SP
VOUT
RTOP
Transconductance
Error Amplifier
VSENSE
-
gmea
RBOTTOM
VREF
+
CO RO
Type 2A
Type 2B
Compensation
Compensation
COMP
RCOMP
RCOMP
CHF
CCOMP
CCOMP
图8-17. TPS7H500x-SP Frequency Compensation Options
For any of the topologies supported by the TPS7H500x-SP, the following procedure and equations can be used
to select the compensation components. All parameters in the equations are in standard units unless otherwise
indicated (that is, H for inductance, F for capacitance, Hz for frequency, and so on).
1. Select the desired crossover frequency (fc) for the converter.
2. Calculate RCOMP based on the selected crossover frequency fc.
2 × fc × VOUT × COUT
RCOMP
=
gmea × VREF × gmPS
1.
(19)
where:
• gmea is the error amplifier transconductance of 1800 × 10-6 A/V (typical)
• VREF is the 0.613 V reference voltage (typical)
• gmPS is the power stage transconductance (see 方程式23)
2. Calculate CCOMP to place compensation zero at the location of the power stage dominant pole.
VOUT × COUT
CCOMP
=
IOUT × RCOMP
(20)
(21)
3. Determine the output capacitor ESR zero location (optional).
1
fESR
=
2 × COUT × ESR
4. Select the capacitor CHF to provide a high frequency pole to compensate for the ESR zero (optional).
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1
CHF
=
2 × RCOMP × fESR
(22)
For different power converter topologies, the primary change to the compensation selection procedure will be the
determination of the power stage transconductance gmPS. The power stage transconductance can be calculated
as shown in 方程式23.
NP × NCSS
gmPS
=
CCSR × RCS × NS × NCSP
(23)
where:
• NP is the number of primary turns on the main power transformer (set to 1 if no transformer is used)
• NS is the number of secondary turns on the main power transformer (set to 1 if no transformer is used)
• NCSP is the number of primary turns on the current sense transformer (set to 1 if no transformer is used)
• NCSS is the number of secondary turns of the current sense transformer (set to 1 if no transformer is used)
• RCS is the selected value of the current sense resistor
• CCSR is the ratio to COMP of CS_ILIM
Note that for the TPS7H500x-SP controllers, the sensed current waveform is compared to the voltage at COMP
divided down by the factor CCSR at the PWM comparator, which is accounted for in the denominator of the
equation. For buck converters, all turns for the main power transformer can be set equal to 1 and the equation
still applies.
8.3.19 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C (typical). The device reinitiates the power-up sequence when the junction temperature drops below 160°C
(typical).
8.4 Device Functional Modes
The TPS7H500x-SP series uses fixed frequency, peak current mode control. Each controller regulates the peak
current and duty cycle of the converter. The internal oscillator initiates the turn-on of the primary output used as
the gate driver input for the power switch. The external power switch current is sensed through an external
resistor and compared via internal comparator. The voltage generated at the COMP pin is stepped down via
internal resistors. When the sensed current reaches the stepped down COMP voltage, the power switch is then
turned off.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS7H500x-SP series is a family of radiation-hardness-assured current mode PWM controllers that can be
utilized for designing space-grade DC-DC converters. Each device should be paired with external gate drivers in
order to provide control of the power semiconductor device(s) of the converter power stage. By allowing for
switching frequencies up to 2 MHz, the controllers provide many advantages for GaN power semiconductor
based designs. The TPS7H500x-SP family can be used for the design of a number of common DC-DC converter
topologies, including but not limited to: buck, flyback, forward, active-clamp forward, push-pull, and full-bridge.
9.2 Typical Application
102
CS_ILIM
10 pF
10 k
7.5
RCD
Clamp
1:100
HOUSEKEEPING
VIN
100 µF
4×
Output Filter
10 k
2.5:1
40 µH
2 k
SYNC
OUTB
OUTA
EN
0.47 µH
22 V to 36 V
GaN Driver
LP1
LP2
LS1
LS2
VLDO
HICC
IN1
OUT1
5 V
1 µF
IN2
OUT2
10 k
TPS7H5001-SP
DCL
RT
RSC
SS
330 µF
7×
10 k
47 pF
15 nF
3.3 nF
FAULT
COMP
1.4 k
40.2 k
205 k
102 k
VSENSE REFCAP
SP
CS_ILIM
SRA
470 nF
33 nF
PS
20.5 k
20.5 k
49.9 k
CS_ILIM
LEB
SRB
AVSS
Isolator
OUT
IN
IN
GaN Driver
IN1
OUT1
IN2
OUT2
Isolator
OUT
图9-1. Typical Application Schematic
9.2.1 Design Requirements
The example provided here is to demonstrate how to design a synchronous push-pull converter using GaN
power semiconductor devices. This design example is to show how to determine the component selection for the
TPS7H5001-SP as well as key components of the converter power stage.
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表9-1. Design Parameters
DESIGN PARAMETER
VALUE
Output voltage
5 V
Maximum output current
Output current pre-load
Operating temperature
Switching frequency
Peak input current limit
Target bandwidth
20 A
0.5 mA
25°C
500 kHz
14 A
~10 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Switching Frequency
The synchronous push-pull converter was designed to operate at a switching frequency of 500 kHz. For space-
grade converter designs, the benefits of GaN power devices over silicon counterparts are readily apparent at this
switching frequency. Using 方程式 7, the required RT resistor for the desired frequency can be determined as
shown in 方程式24.
112000
RT =
19.7 = 204.3 kΩ
(24)
A standard resistor value of 205 kΩis selected for the design.
9.2.2.2 Output Voltage Programming Resistors
The converter has an output voltage of 5 V. The feedback resistor divider connected to VSENSE should be
selected to correspond to the selected VOUT. With a resistor of 10 kΩ selected for RTOP, the value of the bottom
resistor in the divider can be calculated.
VREF
RBOTTOM
=
× RTOP
VOUT
VREF
(25)
(26)
0.613 V
5 V 0.613 V
RBOTTOM
=
× 10 k = 1.397 k
The values for RTOP and RBOT needed are 10 kΩand 1.4 kΩ, respectively.
9.2.2.3 Dead Time
For GaN power semiconductor devices, a key characteristic that has to be taken into consideration is the voltage
drop of the GaN FET while it is operating in reverse conduction mode. While the GaN FET does not have a body
diode that is inherent in the silicon FET, it does still have the ability to conduct current in the reverse direction
with behavior that is similar to a diode. When conducting in the reverse direction, the source-drain voltage of the
GaN FET can be quite large. Thus, to reduce the dead-time losses and maximize efficiency, the dead time was
set to a value of approximately 25 ns. Based on the selected value, 方程式 8 can be used to calculate the
resistors needed to attain the desired dead time.
RPS = RSP = 1.207 × 25 8.858 = 21.3 kΩ
(27)
The standard resistor value of 20.5 kΩwas selected for both RPS and RSP
.
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9.2.2.4 Leading Edge Blank Time
The leading edge blank time was initially chosen to be roughly 50 ns. This value was the initial approximation
based on any ringing or transient spikes that were expected to be seen on the sensed current waveform at the
CS_ILIM pin. Using 方程式9 , the value of RLEB was calculated from this desired value.
RLEB = 1.212 × 50 9.484 = 51.1 kΩ
(28)
The value of RLEB selected was 49.9 kΩ. Note that the ringing and transient spikes on the sensed current
waveform will depend heavily on component placement and parastics in the PCB layout. The leading edge blank
time should also account for any propagation delay that is inherent to the gate driver being used in the
application. As such, the value of RLEB may need to be optimized as the design is tested in accommodate for
these factors. Recall that the leading edge blank time is also correlated to the minimum on-time of the device,
and extending this value significantly may become a limiting factor for the maximum switching frequency that can
be achieved in the design.
9.2.2.5 Soft-Start Capacitor
For this design, the soft-start time is arbitrary. The value of the soft-start capacitor selected was 33 nF. Based on
this value, the soft-start time can be calculated.
CSS × VREF
tSS
=
ISS
(29)
(30)
33 nF × 0.613 V
2.7 A
tSS
=
= 7.49 ms
The soft-start time is ~7.5 ms for the design.
9.2.2.6 Transformer
The turns ratio and primary inductance of the transformer will be determined based on the target specifications
of the converter. In order to calculate the maximum allowable turns ratio, a duty cycle limit must be selected for
the design. Even though DCL will be connected to AVSS to impose a 50% duty cycle limit from the controller to
ensure there is no overlap of the primary switching outputs, a maximum duty cycle of approximately 35% is
targeted for the design in order to provide sufficient margin to the controller limit. This is due to the fact that the
actual duty cycle is greater than calculated duty cycle when accounting for the converter efficiency, and to allow
for duty cycle increases during load transient events. 方程式 31 provides the formulate needed to calculate the
maximum turns ratio for this design.
2 × V
× DLIM
IN_MIN
NPS_MAX
=
VOUT + VSR
(31)
VSR is estimated to be 0.5 V for the application and DLIM is 35% duty cycle limit that was selected. NPS_MAX is
calculated using the values in 方程式32.
2 × 22 V × 0.35
NPS_MAX
=
= 2.8
5 V + 0.5 V
(32)
A value of 2.5 is selected for the turns ratio for the design.
In order to design for the primary inductance of the transformer, the magnetizing current must be selected. The
value of the magnetizing current is a trade-off between transformer size and efficiency, with larger magnetizing
current leading to a smaller size due to lower required inductance, but also leading to lower efficiency. A
magnetizing current equal to 6% of the output current was initially targeted for this design. With this value, the
primary inductance can be calculated using 方程式 36. The minimum duty cycle expected is needed for this
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calculation can be determined using 方程式 34, where the estimated efficiency η for the converter used in the
calculation is 85%.
VOUT + VSR
DMIN
=
2 × V
× NSP × η
IN_MAX
(33)
(34)
5 V + 0.5 V
2 × 36 V × 0.4 × 0.85
DMIN
=
= 0.22
NPS × V
× DMIN
IN_MAX
LP =
fsw × IMAG
(35)
(36)
2.5 × 36 V × 0.22
LP =
= 33 μH
500 kHz × 0.06 × 20 A
Though the calculated value of LP is 33 μH, it may often be challenging to find the exact primary inductance
value needed for the transformer design. As such, an inductance of 40 μH was used in the actual design.
The following equations detail the how to calculate transformer primary and secondary currents that are critical
for proper design of the transformer. These equations are useful for defining the physical structure of the
transformer. Note that these are ideal equations, and the final design should be optimized depending on the
application.
IL
ISEC _MAX = IOUT
+
2
(37)
(38)
8.51 A
2
ISEC _MAX = 20 +
= 24.25 A
(39)
(40)
(41)
(42)
(43)
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(44)
(45)
(46)
(47)
(48)
(49)
(50)
IPRI _MAX (VIN _MIN ) IPRI _MIN (VIN _MIN )
mPRI
=
tON _MAX
(51)
9.27 A 6.73 A
0.63 s
A
= 4072130.16 = 4.07
A
mPRI
=
s
s
(52)
(53)
(54)
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9.2.2.7 Main Switching FETs
In the push-pull topology, the switching devices on the primary side will see a voltage that is equal to twice that
of the input when the devices are off. As such, the GaN FETs selected should have a voltage rating that 3 times
higher than the input voltage. The voltage rating for the GaN FETs was conservatively chosen for the primary
side as 170 V for this application based on maximum input voltage of 36 V. This was to account for any transient
spikes that were seen during operation. Also ensure that the GaN FETs are properly sized based on the primary
current calculations in 节9.2.2.6.
9.2.2.8 Synchronous Rectificier FETs
The maximum voltage stress that will be seen by the synchronous rectifier switch on the secondary side can be
calculated using 方程式55.
V
IN_MAX
VSR_STRESS = VOUT
+
NPS
(55)
(56)
36 V
VSR_STRESS = 5 V +
= 19.4 V
2.5
Note that the maximum expected voltage is approximately 20 V, but a higher rating should be selected to allow
for transient spikes. For the design, an 80-V rated GaN FET was conservatively chosen for the synchronous
rectifier. The current rating should be sufficient to handle the maximum secondary current as calculated in 节
9.2.2.6. In order to reduce the current through GaN FET during the soft-start period, when the controller SRA
and SRB signals are off, a Schottky diode can be used in parallel with the synchronous rectifier GaN FETs. This
diode would also mitigate the reverse conduction losses attributed to the GaN FET during the dead time and
boost the overall efficiency of the system.
9.2.2.9 RCD Clamp
A resistor-capacitor-diode clamp circuit can be used to limit the voltage at the switch node. The equations below
can be used to determine initial values for the resistor and capacitor, but the circuit will need to be optimized
through testing. First, calculate the clamp voltage by determining how much overshoot is allowable at the switch
node.
(57)
The parameter KCLAMP defines the target overshoot value. For example, set KCLAMP to 1.5 for 50% allowable
overshoot.
Next, the leakage inductance LL and peak primary current IPRI_MAX of the transformer can be used to
approximate the clamp resistor. The clamp capacitor value can be determined thereafter. Note that ΔVCLAMP
defines the allowable ripple for the clamp capacitor.
(58)
VCLAMP
CCLAMP
=
VCLAMP × VCLA MP × RCLAMP × fsw
(59)
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9.2.2.10 Output Inductor
For the output inductor, a ripple current of 40% was targeted for the design. Based on the selected ripple current,
方程式 60 can be used to determine the output inductor value. KL is the current ripple factor, which will be set to
0.4 in this instance.
(60)
(61)
The value of the inductor selected for the design is 0.47 μH.
9.2.2.11 Output Capacitance and Filter
Generally, there are two different calculations that can be used to determine the output capacitance required for
the converter. The first calculates the amount of capacitance required to meet the maximum allowable voltage
deviation at the output in response to a worst-case load transient as shown in 方程式 62. The second, shown in
方程式 64, determines the amount of output capacitance that is needed to meet the output voltage ripple
requirements of the design. Once the two different calculations are performed, the maximum of these should be
chosen as the output capacitance for the design. The calculations are shown for target voltage ripple of 2% of
the output voltage and maximum allowable voltage deviation of 2.5% of the output voltage.
ISTEP
COUT
>
2 × VOUT × fc
(62)
(63)
10 A
COUT
>
= 1.27 mF
2 × 0.025 × 5 V × 10 kHz
IOUT × 2 × DMAX
VRIPPLE × fsw
COUT
>
(64)
(65)
IOUT × 2 × 0.37
COUT
>
= 294.12 F
0.02 × 5 V × 500 kHz
Based on the calculations, at least 1.3 mF of output capacitance is required. When selecting capacitors, consider
any derating of capacitance that is needed to account for aging, temperature, and DC bias.
For space-grade converter designs, there is another consideration when selecting the output capacitance. This
is the impact of radiation induced single event transients (SET). Single energetic particle strikes can lead to
momentary variation in the PWM variation of the controller, which in turn can lead to output voltage transients in
the converter. Thus, even though the value above provides a minimum value to account for voltage ripple and/or
load transients, additional capacitance is likely needed to for adequate SET mitigation. For the design example,
approximately 2.3 mF of total output capacitance was used.
An additional output filter can be used to further reduce the noise of the output stage if deemed necessary. This
output filter consists of an additional inductor and a small amount of ceramic capacitance. This ceramic
capacitance is placed immediately downstream of the main output inductor that was determined in 节 9.2.2.10.
The filter inductance is then located between the added ceramic capacitance and the bulk output capacitance
that was determined to be required for the design. This approach can drastically reduce the output voltage ripple
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without significantly increasing the size and/or number of components required. The key for the secondary filter
design is to choose the resonant frequency such that it is higher than the targeted crossover frequency yet well
below the switching frequency and ESR zero of the bulk output capacitance. 方程式 66, 方程式 67, and 方程式
68 can be used to determine the ESR zero as well as the resonant frequency and attenuation of the additional
output filter.
1
fzero
=
2 × COUT _BULK × ESRBULK
(66)
(67)
1
fresonant
=
2 × Lf × COUT _BULK
(68)
In the event that there is peaking at high frequencies due to the output filter, a resistor can be used to dampen
this peaking effect. 方程式 69 and 方程式 70 can be used to determine the frequency of the peaking and the
value of the resistor needed to provide adequate damping.
(69)
(70)
9.2.2.12 Sense Resistor
The converter was designed such that the cycle-by-cycle limiting will begin once the output current reaches
roughly 35 A. Given that the peak inductor current at maximum load current is 24.25 A, this provides about 45%
margin before an overcurrent event is detected by the controller. The primary side current is being sensed at
CS_ILIM, so the turns ratio must be accounted for when calculating the necessary value of the sense resistor.
Likewise, a current sense transformer with turns ratio of 1:100 is used to step down the primary current. The
following calcuations are used to arrive at the value of RCS that translates to the desired output overcurrent level.
NS NCSP
×
ILIM = IL,PEAK
×
NP NCSS
(71)
(72)
1
1
ILIM = 35 A ×
×
= 0.14 A
2.5 100
VCS_ILIM
RCS
=
ILIM
(73)
(74)
1.05 V
0.14 A
RCS
=
= 7.73 Ω
Based on the calculation, a 7.5-Ωresistor was selected for RCS
.
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9.2.2.13 Hiccup Capacitor
For the design, the value of the hiccup capacitor used is the minimum recommended value of 3.3 nF. Based on
this value, the delay and hiccup times of the converter after an overcurrent are detected can be calculated.
CHICC × 0.6 V
tdelay
tdelay
tHICC
tHICC
=
=
=
=
80 A
(75)
(76)
(77)
(78)
3.3 nF × 0.6 V
80 A
= 24.75 s
CHICC × (1 V 0.3 V)
1 A
3.3 nF × (1 V 0.3 V)
1 A
= 2.31 ms
Note that as mentioned in 节 8.3.15, the delay time calculation is an approximation and the actual time depends
on the nature of the overcurrent.
9.2.2.14 Frequency Compensation Components
For this design, Type 2A compensation was used. With a target crossover frequency of 10 kHz, the guidelines
shown in 节 8.3.18 are used here to determine the compensation values needed for the compensation network.
The power stage transconductance is first needed in order to calculate the frequency compensation component
values.
NP × NCSS
gmPS
=
CCSR × RCS × NS × NCSP
(79)
(80)
2.5 × 100
A
V
gmPS
=
= 16.2
2.06 × 7.5 × 1 × 1
With the power stage transconductance calculated as 16.2 A/V, the values of the external components needed
at the COMP pin can be resolved.
2 × fc × VOUT × COUT
RCOMP
=
gmea × VREF × gmPS
(81)
2 × 10 kHz × 5 V × 2.3 mF
6 A
RCOMP
=
= 40.4 kΩ
A
V
1800 × 10
× 0.613 V × 16.2
V
(82)
(83)
(84)
VOUT × COUT
IOUT × RCOMP
CCOMP
=
5 V × 2.3 mF
20 A × 40.2 k
CCOMP
=
= 14.3 nF
For the output capacitance 7 × 330-μF polymer tantalum capacitors were used to meet the 2.3-mF value that
was needed for the design. At the selected switching frequency and output voltage, each of these capacitors had
an ESR of roughly 6 mΩ. As such, the equivalent ESR used to determine the frequency of the ESR zero in the
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frequency response is equivalent the parallel resistance of these seven capacitors, which is 0.86 mΩ. The ESR
zero frequency is then used in the calculation of CHF
.
1
fESR
=
2 × COUT × ESR
(85)
(86)
1
fESR
=
= 80.73 kHz
2 × 2.3 mF × 0.86 m
1
CHF
=
2 × RCOMP × fESR
(87)
(88)
1
CHF
=
= 49.04 pF
2 × 40.2 k × 80.73 kHz
The values of RCOMP, CCOMP, and CHF selected were 40.2 kΩ, 15 nF, and 47 pF, respectively. Note that like
many other aspects of the design, the frequency compensation is often tuned during testing in order to obtain
the best possible performance.
9.2.2.15 Slope Compensation Resistor
The slope compensation for the converter should be tailored by using the RSC pin of the TPS7H5001-SP. As
recommended in 节 8.3.17, the slope compensation should be set to be equal to the falling slope of the output
inductor in order to optimize sub-harmonic damping. The slope compensation that is calculated is dependent on
the transformer turns ratio, current sense turns ratio, output inductor and current sense resistor that have been
selected for the push-pull design.
VOUT NS NCSP
×
SC =
×
× RCS
L
NP NCSS
(89)
5 V
1
1
V
× 7.5 = 319148.94 = 0.319
V
SC =
×
×
0.47 H 2.5 100
s
s
(90)
(91)
(92)
28.3
RSC =
1.1
28.3
0.3191.1
RSC =
= 99.4 kΩ
A resistor value of 102 kΩis connected between RSC and AVSS for the design.
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9.2.3 Application Curves
图9-2. VOUT Soft-Start of Push-Pull Converter With
图9-3. 5-A Load Step Response for Push Pull
IOUT = 10 A
Converter
9.3 Power Supply Recommendations
The TPS7H500x-SP controllers are designed to operate from an input voltage supply range between 4 V and 14
V. The input voltage supply for the controller should be well regulated and properly bypassed for best electrical
performance. A minimum input bypass capacitor of 0.1 µF is required from VIN to AVSS, but additional
capacitance can be used to help improve the noise and radiation performance of the controller. It is
recommended to use ceramic capacitors (X5R or better) for bypassing, and these capacitors should be placed
as close as possible to the controller with a low impedance path to AVSS. Additional bulk capacitors should be
used if the input supply is more than a few inches from TPS7H500x-SP controller.
9.4 Layout
9.4.1 Layout Guidelines
In order to increase the reliability of the converter design using the TPS7H500x-SP series, the following layout
guidelines should be followed.
• Route the feedback trace as far away as possible from power magnetics components (inductor and/or power
transformer) and other noise inducting traces on the printed circuit board (PCB) such as the switch node. If
the feedback trace is routed beneath the power magnetic component, ensure that this trace is on another
layer of the PCB with at least one ground layer separating the trace from the inductor or transformer.
• Minimize the copper area of the converter switch node for the best noise performance and reduction of
parasitic capacitance to reduce switching losses. Ensure that any noise sensitive signals, such as the
feedback trace, are routed away from this node as it contains a high dv/dt switching signal.
• All high di/dt and dv/dt switching loops in the power stage should have the paths minimized. This will help to
reduce EMI, lower stresses on the power devices, and reduce any noise coupling into the control loop.
• Keep the analog ground of the controller (AVSS) separate from the power ground of the power stage that
contains high frequency, high di/dt currents. These two grounds should be connected at a single point in the
PCB layout. The sources of power semiconductor switches, the returns for bulk input capacitors of the power
stage, and the ouput capacitor return should all be connected to the PCB power ground.
• All high current traces on the PCB should be short, direct, and as wide as possible. A good rule is to make
the traces a minimum of 15 mils (0.381 mm) per ampere.
• Place all filtering and bypass capacitors for VIN, REFCAP, and VLDO as close as possible to the controller.
Surface mount ceramic capacitors with lower ESR and ESL are recommended as these reduce the potential
for noise coupling compared to through-hole capacitors. Care should be taken to minimize the loop area
formed by the bypass capacitor connection, the respective pin, and AVSS. Each bypass capacitor should
have a good, low impedance connection to AVSS.
• External compensation components should be placed near the COMP pin of the controller. Surface mount
components are recommended here as well.
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• Attempt to keep the resistor divider used to generate the voltage at VSENSE close to the device in order to
reduce noise coupling. Minimize stray capacitance to the VSENSE pin.
• OUTA, OUTB, SRA, and SRB are used to drive the inputs of a gate driver, isolator, or gate drive transformer.
The PCB traces connected to these pins carry high dv/dt signals. Reduce noise coupling by routing these
these PCB traces away from any traces connected to VSENSE, COMP, RT, CS_ILIM, HICC, LEB, RSC, PS,
and SP.
• In addition to utilizing the leading edge blank time programmability of the controller, RC filtering may be
required for the sensed current signal input to CS_ILIM. Keep the resistor and capacitor in close vicinity to
CS_LIM to filter any ringing and/or spikes that may be present on the sensed current signal.
• When operating in internal oscillator mode with SYNC as an output, route the SYNC signal away from noise
sensitive signals/pins such as VSENSE, COMP, RT, CS_ILIM, LEB, RSC, PS, and SP. Special care should
be taken to eliminate noise from SYNC to HICC since these pins are adjacent to one another. It is
recommended that the capacitor from HICC to AVSS be at least 3.3 nF to help with the reduction of the
noise.
• Connect the backside metallization of the TPS7H500x-SP to the AVSS plane of the PCB using multiple vias.
It is recommended to avoid putting solder paste directly on top of the vias unless these vias are tented or
filled.
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www.ti.com.cn
ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
9.4.2 Layout Example
图9-4. PCB Layout Example
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP
TPS7H5001-SP, TPS7H5002-SP, TPS7H5003-SP, TPS7H5004-SP
ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
www.ti.com.cn
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS7H5001-SP Evaluation Module user's guide
• Texas Instruments, TPS7H5002/3/4-SP Evaluation Modules user's guide
• Texas Instruments, TPS7H5001-SP Total Ionizing Dose (TID) radiation report
• Texas Instruments, TPS7H5002-SP Total Ionizing Dose (TID) radiation report
• Texas Instruments, TPS7H5003-SP Total Ionizing Dose (TID) radiation report
• Texas Instruments, TPS7H5004-SP Total Ionizing Dose (TID) radiation report
• Texas Instruments, TPS7H500x-SP Single-Event Effects (SEE) radiation report
• Texas Instruments, TPS7H5001-SP Neutron Displacement Characterization test report
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP
TPS7H5001-SP, TPS7H5002-SP, TPS7H5003-SP, TPS7H5004-SP
www.ti.com.cn
ZHCSOH8D –JULY 2021 –REVISED FEBRUARY 2023
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962R1822201V9A
5962R1822201VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
22
NIAU
5962R1822201VXC
TPS7H5001MHFTV
5962R1822202V9A
5962R1822202VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
22
5962R1822202VXC
TPS7H5002MHFTV
5962R1822203V9A
5962R1822203VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
22
5962R1822203VXC
TPS7H5003MHFTV
5962R1822204V9A
5962R1822204VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
22
5962R1822204VXC
TPS7H5004MHFTV
TPS7H5001HFT/EM
ACTIVE
CFP
HFT
22
1
RoHS & Green
NIAU
N / A for Pkg Type
25 to 25
TPS7H5001HFT
EVAL ONLY
Samples
TPS7H5001Y/EM
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
25 to 25
25 to 25
Samples
Samples
TPS7H5002HFT/EM
22
TPS7H5002HFT
EVAL ONLY
TPS7H5002Y/EM
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
25 to 25
25 to 25
Samples
Samples
TPS7H5003HFT/EM
22
TPS7H5003HFT
EVAL ONLY
TPS7H5003Y/EM
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HFT
0
10
1
RoHS & Green
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
25 to 25
25 to 25
Samples
Samples
TPS7H5004HFT/EM
22
TPS7H5004HFT
EVAL ONLY
TPS7H5004Y/EM
ACTIVE
XCEPT
KGD
0
10
RoHS & Green
Call TI
N / A for Pkg Type
25 to 25
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Feb-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962R1822201VXC
5962R1822202VXC
5962R1822203VXC
5962R1822204VXC
TPS7H5001HFT/EM
TPS7H5002HFT/EM
TPS7H5003HFT/EM
TPS7H5004HFT/EM
HFT
HFT
HFT
HFT
HFT
HFT
HFT
HFT
CFP
CFP
CFP
CFP
CFP
CFP
CFP
CFP
22
22
22
22
22
22
22
22
1
1
1
1
1
1
1
1
506.98
506.98
506.98
506.98
506.98
506.98
506.98
506.98
32.77
32.77
32.77
32.77
32.77
32.77
32.77
32.77
9910
9910
9910
9910
9910
9910
9910
9910
NA
NA
NA
NA
NA
NA
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HFT0022A
CFP - 2.428mm max height
CERAMIC FLATPACK
B
METAL LID
(5.7)
4X (R0.25)
20X 0.635
1
22
7.946
7.446
(6.73)
2X 6.35
12
11
0.304
0.204
C A B
22X
0.2
6.461
5.961
A
METAL LID
0.353
0.053
0.177
0.097
2.428
1.728
4.176
3.876
C
0.715
0.555
(0.3)
27 0.5
12
11
7.946
7.446
22
1
PIN 1 ID
(0.203)
ALL AROUND
(0.635)
BACKSIDE
METALLIZATION
(THERMAL PAD)
4225791/C 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. The lid is not connected to any lead.
4. The leads are gold plated.
5. Metal lid is connected to backside metalization
www.ti.com
EXAMPLE BOARD LAYOUT
HFT0022A
CFP - 2.428mm max height
CERAMIC FLATPACK
PKG
(R0.05) TYP
(0.605)
(0.955) TYP
(1.115)
(1.14) TYP
PKG
(7.29)
(
0.2) TYP
(3.62)
HEATSINK LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
4225791/C 01/2021
www.ti.com
REVISIONS
REV
A
DESCRIPTION
ECR
DATE
ENGINEER / DRAFTER
R. RAZAK / ANIS FAUZI
R. RAZAK / ANIS FAUZI
R. RAZAK / ANIS FAUZI
RELEASE NEW DRAWING
2186323
2190485
2192775
03/13/2020
10/22/2020
01/28/2021
B
ADD LAND PATTERN VIEW / SHEET
C
UPDATE TOTAL LEAD LENGTH TO 27 0.5
REV
SCALE
SIZE
PAGE
OF
4225791
C
4
4
A
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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