5962R2021001V9A [TI]

TPS7H4002-SP Radiation-Hardness-Assured 3-V to 5.5-V Input, 3-A Synchronous Step Down Converter;


型号：	5962R2021001V9A
厂家：	TEXAS INSTRUMENTS
描述：	TPS7H4002-SP Radiation-Hardness-Assured 3-V to 5.5-V Input, 3-A Synchronous Step Down Converter
文件：	总37页 (文件大小：2192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMC1350

SBASAA6A – AUGUST 2021 – REVISED DECEMBER 2021

AMC1350 Precision, ±5-V Input, Reinforced Isolated Amplifier

1 Features

3 Description

•

Linear input voltage range: ±5 V

High input impedance: 1.25 MΩ (typ)

Fixed gain: 0.4 V/V

The AMC1350 is a precision, isolated amplifier

with an output separated from the input circuitry

by an isolation barrier that is highly resistant to

magnetic interference. This barrier is certified to

provide reinforced galvanic isolation of up to 5 kV_RMS

according to VDE V 0884-11 and UL1577, and

Low DC errors:

– Offset error ±1.5 mV (max)

– Offset drift: ±15 μV/°C (max)

– Gain error: ±0.2% (max)

supports a working voltage of up to 1.5 kV_RMS

– Gain drift: ±35 ppm/°C (max)

– Nonlinearity ±0.02% (max)

Operation on high-side and low-side: 3.3 V or 5 V

High CMTI: 100 kV/μs (min)

Fail-safe output

Safety-related certifications:

– 7070-V_PKreinforced isolation per DIN VDE V

0884-11: 2017-01

– 5000-V_RMSisolation for 1 minute per UL1577

Fully specified over the extended industrial

temperature range: –40°C to +125°C

The isolation barrier separates parts of the system

that operate on different common-mode voltage levels

and protects the low-voltage side from potentially

harmful voltages and damage.

•

The high-impedance input of the AMC1350 is

optimized for connection to high-impedance resistive

dividers or other voltage signal sources with high

output resistance. The excellent accuracy and low

temperature drift supports accurate AC and DC

voltage sensing in DC/DC converters, frequency

inverters, AC motor, and servo-drive applications over

the extended industrial temperature range from –40°C

to +125°C.

•

2 Applications

•

Isolated AC voltage sensing in:

– Motor drives

Device Information⁽¹⁾

– Frequency inverters

– Protection relays

– Power supplies

PART NUMBER

PACKAGE

BODY SIZE (NOM)

AMC1350

SOIC (8)

5.85 mm × 7.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

High-side supply

(3.3 V or 5 V)

Low-side supply

(3.3 V or 5 V)

V_AC

AMC1350

VDD1

INP

VDD2

OUTP

+5.0 V

0 V

V_CMout

±2 V

ADC

–5.0 V

INN

OUTN

GND2

GND1

Typical Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

AMC1350

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SBASAA6A – AUGUST 2021 – REVISED DECEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety Limiting Values.................................................7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics........................................10

6.11 Timing Diagram.......................................................10

6.12 Insulation Characteristics Curves............................11

6.13 Typical Characteristics............................................12

7 Detailed Description......................................................19

7.1 Overview...................................................................19

7.2 Functional Block Diagram.........................................19

7.3 Feature Description...................................................19

7.4 Device Functional Modes..........................................21

8 Application and Implementation..................................22

8.1 Application Information............................................. 22

8.2 Typical Application.................................................... 22

8.3 What To Do and What Not To Do..............................27

9 Power Supply Recommendations................................27

10 Layout...........................................................................28

10.1 Layout Guidelines................................................... 28

10.2 Layout Example...................................................... 28

11 Device and Documentation Support..........................29

11.1 Documentation Support.......................................... 29

11.2 Receiving Notification of Documentation Updates..29

11.3 Support Resources................................................. 29

11.4 Trademarks............................................................. 29

11.5 Electrostatic Discharge Caution..............................29

11.6 Glossary..................................................................29

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (August 2021) to Revision A (December 2021)

Page

•

Changed document status from Advanced Information to Production Data ......................................................1

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5 Pin Configuration and Functions

VDD1

INP

VDD2

OUTP

OUTN

GND2

INN

GND1

Not to scale

Figure 5-1. DWV Package, 8-Pin SOIC, Top View

Table 5-1. Pin Functions

NAME

TYPE

DESCRIPTION

NO.

VDD1

INP

High-side power

Analog input

High-side power supply⁽¹⁾

Noninverting analog input. Either INP or INN must have a DC current path to GND1

to define the common-mode input voltage.⁽²⁾

Inverting analog input. Either INP or INN must have a DC current path to GND1 to

define the common-mode input voltage.⁽²⁾

INN

Analog input

GND1

GND2

OUTN

OUTP

VDD2

High-side ground

Low-side ground

Analog output

High-side analog ground

Low-side analog ground

Inverting analog output

Noninverting analog output

Low-side power supply⁽¹⁾

Analog output

Low-side power

(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.

(2) See the Layout section for details.

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6 Specifications

6.1 Absolute Maximum Ratings

see⁽¹⁾

MIN

–0.3

MAX

UNIT

High-side VDD1 to GND1

Power-supply voltage

6.5

Low-side VDD2 to GND2

–0.3

6.5

Analog input voltage

Analog output voltage

Input current

INP, INN

–15

VDD2 + 0.5

OUTP, OUTN

GND2 – 0.5

–10

Continuous, any pin except power-supply pins

Junction, T_J

Storage, T_stg

150

Temperature

°C

–65

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per per ANSI/ESDA/JEDEC JS-002⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

VDD1

VDD2

High-side power-supply

Low-side power-supply

VDD1 to GND1

VDD2 to GND2

5.5

3.3

ANALOG INPUT

V_ClippingInput voltage before clipping output

V_FSR

V_IN= V_INP– V_INN

±6.25

Specified linear full-scale voltage

–5

–4

V_CM

Operating common-mode input voltage

ANALOG OUTPUT

On OUTP or OUTN to GND2

OUTP to OUTN

500

250

C_LOADCapacitive load

kΩ

R_LOAD

TEMPERATURE RANGE

Operating ambient temperature

Resistive load

On OUTP or OUTN to GND2

–55

–40

125

T_A

°C

Specified ambient temperature

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6.4 Thermal Information

AMC1350

THERMAL METRIC⁽¹⁾

DWV (SOIC)

8 PINS

84.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

28.3

R_θJB

ψ_JT

Junction-to-board thermal resistance

41.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

4.9

ψ_JB

39.1

R_θJC(bot)Junction-to-case (bottom) thermal resistance

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

VALUE

UNIT

P_D

Maximum power dissipation (both sides) VDD1 = VDD2 = 5.5 V

VDD1 = 3.6 V

Maximum power dissipation (high-side)

VDD1 = 5.5 V

P_D1

VDD2 = 3.6 V

Maximum power dissipation (low-side)

VDD2 = 5.5 V

P_D2

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UNIT

SBASAA6A – AUGUST 2021 – REVISED DECEMBER 2021

6.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

GENERAL

CLR

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance through air

≥ 8.5

CPG

Shortest pin-to-pin distance across the package surface

Minimum internal gap (internal clearance) of the double

insulation

DTI

CTI

Distance through insulation

≥ 0.021

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 600

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category

per IEC 60664-1

DIN VDE V 0884-11 (VDE V 0884-11): 2017-01

Maximum repetitive peak

isolation voltage

V_IORM

At AC voltage

2120

V_PK

At AC voltage (sine wave)

1500

2120

7070

8480

V_RMS

V_DC

Maximum-rated isolation

working voltage

V_IOWM

At DC voltage

V_TEST= V_IOTM, t = 60 s (qualification test)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production test)

Maximum transient

isolation voltage

V_IOTM

V_PK

Maximum surge

Test method per IEC 60065, 1.2/50-µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

V_IOSM

8000

≤ 5

isolation voltage⁽²⁾

Method a, after input/output safety test subgroups 2 and 3,

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.2 × V_IORM, t_m= 10 s

Method a, after environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.6 × V_IORM, t_m= 10 s

≤ 5

q_pd

Apparent charge⁽³⁾

Method b1, at routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s, V_pd(m)= 1.875

× V_IORM, t_m= 1 s

≤ 5

Barrier capacitance,

input to output⁽⁴⁾

C_IO

R_IO

V_IO= 0.5 V_PPat 1 MHz

~1.5

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Insulation resistance,

input to output⁽⁴⁾

V_IO= 500 V at 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

55/125/21

UL1577

V_TEST= V_ISO= 5000 V_RMSor 7071 V_DC, t = 60 s (qualification),

V_TEST= 1.2 × V_ISO= 6000 V_RMS, t = 1 s (100% production test)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the

printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques

such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.

(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(3) Apparent charge is electrical discharge caused by a partial discharge (pd).

(4) All pins on each side of the barrier are tied together, creating a two-pin device.

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6.7 Safety-Related Certifications

VDE

Certified according to DIN VDE V 0884-11 (VDE V 0884-11):

2017-01,

DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and

DIN EN 60065 (VDE 0860): 2005-11

Recognized under 1577 component recognition

Reinforced insulation

Single protection

Certificate number: pending

File number: E181974

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A

failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to

over-heat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_θJA= 84.6°C/W, VDDx = 5.5 V,

T_J= 150°C, T_A= 25°C

270

I_S

Safety input, output, or supply current

R_θJA= 84.6°C/W, VDDx = 3.6 V,

T_J= 150°C, T_A= 25°C

410

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

R_θJA= 84.6°C/W, T_J= 150°C, T_A= 25°C

1480

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of I_Sand P_S. These

limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum junction temperature.

P_S= I_S× VDD_max, where VDD_maxis the maximum supply voltage for high-side and low-side.

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6.9 Electrical Characteristics

minimum and maximum specifications apply from T_A= –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP

= –5 V to +5 V, and INN = GND1 (unless otherwise noted); typical specifications are at T_A= 25°C, VDD1 = 5 V, and VDD2 =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG INPUT

T_A= 25°C, INN = INP = GND1,

4.5 V ≤ VDD1 ≤ 5.5 V⁽¹⁾

–1.5

–2.5

±0.3

–0.8

1.5

2.5

V_OS

Offset voltage⁽²⁾

T_A= 25°C, INN = INP = GND1,

3.0 V ≤ VDD1 ≤ 5.5 V⁽³⁾

ΔV_OS

Offset voltage long-term stability

Offset voltage thermal drift⁽⁵⁾

10 years at T_A= 55℃

0⁽⁷⁾

±3

TCV_OS

INN = INP = GND1

–15

15 µV/°C

Offset voltage thermal drift

long-term stability

10 years at T_A= 55℃,

ΔTCV_OS

R_IN

0⁽⁷⁾

mV/°C

INN = INP = GND1

Input resistance, differential

Input resistance, single ended

2.5

1.25

0⁽⁷⁾

MΩ

1.5

INN = GND1

ΔR_IN

TCR_IN

C_IN

Input resistance long-term stability 10 years at T_A= 55℃

ppm

ppm/°C

Input resistance thermal drift

Single-ended input capacitance

Differential input capacitance

–40℃ ≤ T_A≤ 85℃

INN = HGND, f_IN= 275 kHz

f_IN= 275 kHz

C_IND

ANALOG OUTPUT

Nominal gain

0.40

±0.05%

0⁽⁷⁾

V/V

E_G

Gain error⁽¹⁾

T_A= 25℃

–0.2%

–35

0.2%

ΔE_G

TCE_G

Gain error long-term stability

Gain error thermal drift^{(1) (6)}

10 years at T_A= 55℃

±10

35 ppm/°C

ppm/°C

Gain error thermal drift

long-term stability

ΔTCE_G

10 years at T_A= 55℃

0⁽⁷⁾

Nonlineartity⁽¹⁾

–0.02%

±0.003%

0.2

0.02%

Nonlinearity thermal drift

ppm/°C

V_IN= 10 V_PP, f_IN= 10 kHz,

BW = 100 kHz

THD

SNR

Total harmonic distortion⁽⁴⁾

Signal-to-noise ratio

–87

V_IN= 10 V_PP, f_IN= 1 kHz,

BW = 10 kHz

V_IN= 10 V_PP, f_IN= 10 kHz,

BW = 100 kHz

Output noise

INN = INP = GND1, BW = 100 kHz

DC, INN = INP, V_{CM min}≤ V_CM≤ V_{CM max}

f_IN= 10 kHz, INN = INP = 10 V_PP

PSRR vs VDD1, DC

250

–72

–71

–67

–80

µVrms

CMRR

PSRR

Common-mode rejection ratio

PSRR vs VDD2, DC

Power-supply rejection ratio⁽²⁾

PSRR vs VDD1 with 10-kHz,

100-mV ripple

–65

PSRR vs VDD2 with 10-kHz,

100-mV ripple

–64

1.44

2.49

V_CMout

Output common-mode voltage

1.39

275

1.49

–2.5

V_OUT= (V_OUTP– V_OUTN),

V_IN> V_Clipping

V_CLIPout

Clipping differential output voltage

V_Fail-safe

Fail-safe differential output voltage VDD1 undervoltage or VDD1 missing

Output bandwidth

–2.57

300

kHz

R_OUT

Output resistance

On OUTP or OUTN

< 0.2

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6.9 Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP

= –5 V to +5 V, and INN = GND1 (unless otherwise noted); typical specifications are at T_A= 25°C, VDD1 = 5 V, and VDD2 =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

On OUTP or OUTN, sourcing or sinking,

INN = INP = GND1, outputs shorted to

either GND or VDD2

Output short-circuit current

Common-mode transient immunity

CMTI

POWER SUPPLY

100

150

kV/µs

VDD1 rising

2.5

2.4

2.7

2.6

2.45

2.0

6.0

7.0

5.3

5.9

2.9

VDD1 undervoltage detection

threshold

VDD1_UV

VDD2_UV

I_DD1

VDD1 falling

2.8

VDD2 rising

2.2

2.65

2.2

VDD2 undervoltage detection

threshold

VDD2 falling

1.85

3.0 V < VDD1 < 3.6 V

4.5 V < VDD1 < 5.5 V

3.0 V < VDD2 < 3.6 V

4.5 V < VDD2 < 5.5 V

8.1

9.3

High-side supply current

Low-side supply current

7.2

8.1

I_DD2

(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.

(2) This parameter is input referred.

(3) The typical value is at VDD1 = 3.3 V.

(4) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.

(5) Offset error temperature drift is calculated using the box method, as described by the following equation:

TCV_OS= (V_OS,MAX- V_OS,MIN) / TempRange where V_OS,MAXand V_OS,MINrefer to the maximum and minimum V_OSvalues measured

within the temperature range (–40 to 125℃).

(6) Gain error temperature drift is calculated using the box method, as described by the following equation:

TCE_G(ppm) = ((E_G,MAX- E_G,MIN) / TempRange) x 10⁴where E_G,MAXand E_G,MINrefer to the maximum and minimum E_Gvalues (in %)

measured within the temperature range (–40 to 125℃).

(7) Value is below measurement capability.

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6.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

1.3

MAX

UNIT

µs

t_r

t_f

Output signal rise time

Output signal fall time

µs

IN to OUTx signal delay (50% – 10%)

IN to OUTx signal delay (50% – 50%)

IN to OUTx signal delay (50% – 90%)

Unfiltered output

1.5

2.1

µs

1.6

2.5

µs

VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to

V_OUTPand V_OUTNvalid, 0.1% settling

t_AS

Analog settling time

500

800

µs

6.11 Timing Diagram

5 V

INP - INN

– 5 V

t_f

t_r

OUTN

OUTP

V_CMout

50% - 10%

50% - 50%

50% - 90%

Figure 6-1. Rise, Fall, and Delay Time Definition

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6.12 Insulation Characteristics Curves

600

1800

1600

1400

1200

1000

800

600

400

200

VDD1 = VDD2 = 3.6 V

VDD1 = VDD2 = 5.5 V

500

400

300

200

100

T_A(°C)

100

125

150

T_A(°C)

100

125

150

D070

D069

Figure 6-3. Thermal Derating Curve for Safety-Limiting Power

per VDE

Figure 6-2. Thermal Derating Curve for Safety-Limiting Current

per VDE

T_Aup to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 V_RMS, operating lifetime = 135 years

Figure 6-4. Reinforced Isolation Capacitor Lifetime Projection

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6.13 Typical Characteristics

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

2.5

0.1

0.08

0.06

0.04

0.02

T_A= -40 C

T_A= 25 C

T_A= 125 C

V_OUTP

V_OUTN

1.5

-0.02

-0.04

-0.06

-0.08

-0.1

0.5

-8

-6

-4

-2

-7 -6 -5 -4 -3 -2 -1

(V_INP- V_INN) (V)

D074

(V_INP- V_INN) (V)

D006

Total uncalibrated output error is defined as:

(V_OUT– V_IN× G) / (V_Clipping× G) where V_IN= (V_INP– V_INN),

G is the nominal gain of the device (0.4 V/V),

and V_Clippingis 6.25 V

Figure 6-6. Total Uncalibrated Output Error vs Input Voltage

Figure 6-5. Output Voltage vs Input Voltage

Device 1

2.5

Device 1

Device 2

Device 3

1.5

0.5

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

-2.5

3.5

4.5

VDD1 (V)

5.5

3.5

4.5

VDD2 (V)

5.5

D027

D027b

Figure 6-7. Input Offset Voltage vs High-Side Supply Voltage

Figure 6-8. Input Offset Voltage vs Low-Side Supply Voltage

2.5

Device 1

Device 2

Device 3

2.48

2.46

2.44

2.42

2.4

1.5

0.5

-0.5

-1

-1.5

-2

-2.5

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D072

D026

Figure 6-10. Differential Input Impedance vs Temperature

Figure 6-9. Input Offset Voltage vs Temperature

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

1.25

1.24

1.23

1.22

1.21

1.2

0.3

0.2

0.1

Device 1

Device 2

Device 3

-0.1

-0.2

-0.3

-40 -25 -10

20 35 50 65 80 95 110 125

3.5

4.5

VDD1 (V)

5.5

Temperature (°C)

D073

D020

Figure 6-11. Single-Ended Input Impedance vs Temperature

Figure 6-12. Gain Error vs High-Side Supply Voltage

0.3

Device 1

Device 2

Device 3

Device 1

Device 2

Device 3

0.2

0.1

0.2

0.1

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D020b

D021

Figure 6-13. Gain Error vs Low-Side Supply Voltage

Figure 6-14. Gain Error vs Temperature

0.02

0.015

0.01

0.02

Device 1

Device 2

Device 3

0.015

0.01

0.005

-0.005

-0.01

-0.015

-0.02

-0.005

-0.01

-0.015

-0.02

3.5

4.5

VDD1 (V)

5.5

-5

-4

-3

-2

-1

(V_INP- V_INN) (V)

D029

D028

Figure 6-16. Nonlinearity vs High-Side Supply Voltage

Figure 6-15. Nonlinearity vs Input Voltage

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

0.02

Device 1

Device 2

Device 3

0.015

0.01

0.005

-0.005

-0.01

-0.015

-0.02

3.5

4.5

VDD2 (V)

5.5

D029b

Figure 6-17. Nonlinearity vs Low-Side Supply Voltage

Figure 6-18. Nonlinearity vs Temperature

Device 1

-70

-75

Device 1

Device 2

Device 3

Device 2

Device 3

-75

-80

-85

-90

-95

-100

0.5

1.5

2.5

3.5

4.5

5.5

6.5

3.5

4.5

VDD1 (V)

5.5

|V_INP- V_INN| (V)

D049

D056

Figure 6-19. Total Harmonic Distortion vs Input Voltage

Figure 6-20. Total Harmonic Distortion vs High-Side Supply

Voltage

-70

Device 1

Device 2

Device 3

-75

-80

-85

-90

-95

-100

3.5

4.5

VDD2 (V)

5.5

D056b

Figure 6-21. Total Harmonic Distortion vs Low-Side Supply

Voltage

Figure 6-22. Total Harmonic Distortion vs Temperature

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

Device 1

Device 2

Device 3

0.5

1.5

2.5

3.5

4.5

5.5

6.5

|V_INP- V_INN| (V)

D032

Figure 6-23. Signal-to-Noise Ratio vs Input Voltage

Figure 6-24. Signal-to-Noise Ratio vs High-Side Supply Voltage

Device 1

Device 2

Device 3

Device 1

Device 2

Device 3

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D034b

D035

Figure 6-25. Signal-to-Noise Ratio vs Low-Side Supply Voltage

Figure 6-26. Signal-to-Noise Ratio vs Temperature

1000

-66

-68

-70

-72

-74

-76

Device 1

Device 2

Device 3

100

0.1

100

1000

3.5

4.5

VDD1 (V)

5.5

Frequency (kHz)

D017

D037

Figure 6-27. Input-Referred Noise Density vs Frequency

Figure 6-28. Common-Mode Rejection Ratio vs Supply Voltage

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

-66

-68

-70

-72

-74

-76

Device 1

Device 2

Device 3

Device 1

Device 2

Device 3

-20

-40

-60

-80

-100

0.01

0.1

100

1000

-40 -25 -10

20 35 50 65 80 95 110 125

f_IN(kHz)

D038

Temperature (°C)

D039

f_IN= 10 kHz

Figure 6-29. Common-Mode Rejection Ratio vs Input Frequency

Figure 6-30. Common-Mode Rejection Ratio vs Temperature

VDD1

VDD2

-20

-40

-60

-80

-20

-40

-60

-80

VDD1

VDD2

-100

0.01

-100

0.1

100

1000

-40 -25 -10

20 35 50 65 80 95 110 125

Ripple Frequency (kHz)

Temperature (°C)

D041

D042

f_Ripple= 10 kHz

Figure 6-31. Power-Supply Rejection Ratio vs Ripple Frequency

Figure 6-32. Power-Supply Rejection Ratio vs Temperature

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.39

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D009

D010

Figure 6-33. Common-Mode Output Voltage vs Supply Voltage

Figure 6-34. Common-Mode Output Voltage vs Temperature

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

0°

-45°

-5

-90°

-10

-15

-20

-25

-30

-35

-40

-135°

-180°

-225°

-270°

-315°

-360°

100

1000

100

1000

f_IN(kHz)

D008

f_IN(kHz)

D007

Figure 6-36. Output Phase vs Input Frequency

Figure 6-35. Normalized Gain vs Input Frequency

320

310

300

290

280

320

310

300

290

280

Device 1

Device 2

Device 3

Device 1

Device 2

Device 3

-40 -25 -10

20 35 50 65 80 95 110 125

3.5

4.5

VDD1 (V)

5.5

Temperature (°C)

D011

D012

Figure 6-37. Bandwidth vs Supply Voltage

Figure 6-38. Bandwidth vs Temperature

7.5

6.5

5.5

4.5

IDD1 vs VDD1

IDD2 vs VDD2

IDD1

IDD2

3.5

4.5

VDDx (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D043

D044

Figure 6-39. Supply Current vs Supply Voltage

Figure 6-40. Supply Current vs Temperature

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6.13 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and f_IN= 10 kHz (unless otherwise noted)

2.5

1.5

0.5

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D065

D066

Figure 6-41. Output Rise and Fall Time vs Supply Voltage

Figure 6-42. Output Rise and Fall Time vs Temperature

3.8

50% - 90%

50% - 50%

50% - 10%

50% - 90%

50% - 50%

50% - 10%

3.4

2.6

2.2

1.8

1.4

2.6

2.2

1.8

1.4

0.6

0.2

0.6

0.2

3.5

4.5

VDD2 (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D067

D068

Figure 6-43. Input to Output Signal Delay vs Supply Voltage

Figure 6-44. Input to Output Signal Delay vs Temperature

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7 Detailed Description

7.1 Overview

The AMC1350 is a fully differential, precision, isolated amplifier with high input impedance. The input stage

of the device consists of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator.

The modulator converts the analog input signal into a digital bitstream that is transferred across the isolation

barrier that separates the high-side from the low-side. On the low-side, the received bitstream is processed by a

fourth-order analog filter that outputs a differential signal at the OUTP and OUTN pins proportional to the input

signal.

The SiO₂-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the

ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1350

to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high reliability

and common-mode transient immunity.

7.2 Functional Block Diagram

VDD1

INP

VDD2

OUTP

OUTN

GND2

Diagnostics

Modulator

Analog Filter

INN

AMC1350

GND1

7.3 Feature Description

7.3.1 Analog Input

The single-ended, high-impedance input stage of the AMC1350 feeds a second-order, switched-capacitor, feed-

forward ΔΣ modulator. The modulator converts the analog signal into a bitstream that is transferred across the

isolation barrier, as described in the Isolation Channel Signal Transmission section.

There are two restrictions on the analog input signals INP and INN. First, if the input voltages V_INPor V_INN

exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the

absolute maximum value because the electrostatic discharge (ESD) protection turns on. In addition, the linearity

and parametric performance of the device are ensured only when the analog input voltage remains within

the linear full-scale range (V_FSR) and within the common-mode input voltage range (V_CM) as specified in the

Recommended Operating Conditions table.

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7.3.2 Isolation Channel Signal Transmission

The AMC1350 uses an on-off keying (OOK) modulation scheme, as shown in Figure 7-1, to transmit the

modulator output bitstream across the SiO₂-based isolation barrier. The transmit driver (TX) shown in the

Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier

to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the

carrier used inside the AMC1350 is 480 MHz.

The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides

the input to the fourth-order analog filter. The AMC1350 transmission channel is optimized to achieve the

highest level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the

high-frequency carrier and RX/TX buffer switching.

Internal Clock

Modulator Bitstream

on High-side

Signal Across Isolation Barrier

Recovered Sigal

on Low-side

Figure 7-1. OOK-Based Modulation Scheme

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7.3.3 Analog Output

The AMC1350 offers a differential analog output on the OUTP and OUTN pins. For differential input voltages

(V_INP– V_INN) in the range from –5 V to +5 V, the device provides a linear response with a nominal gain of 0.4

V/V. For example, for a differential input voltage of 5 V, the differential output voltage (V_OUTP– V_OUTN) is 2 V. At

zero input (INP shorted to INN), both pins output the same common-mode output voltage V_CMout, as specified in

the Electrical Characteristics table. For absolute differential input voltages greater than 5 V but less than 5.75 V,

the differential output voltage continues to increase in magnitude but with reduced linearity performance. The

outputs saturate at a differential output voltage of V_CLIPout, as shown in Figure 7-2, if the differential input voltage

exceeds the V_Clippingvalue.

Maximum input range before clipping (V_Clipping

)

Linear input range (V_FSR

)

V_OUTN

V_CLIPout

V_OUTP

V_Fail-safe

V_CMout

6.25 V

5 V

Differential Input Voltage (V_INP– V_INN

)

Figure 7-2. Output Behavior of the AMC1350

The AMC1350 output offers a fail-safe feature that simplifies diagnostics on a system level. Figure 7-2 shows the

fail-safe condition, in which the AMC1350 outputs a negative differential output voltage that does not occur under

normal operating conditions. The fail-safe output is active in two cases:

•

When the high-side supply VDD1 of the AMC1350 device is missing

When the high-side supply VDD1 falls below the undervoltage threshold VDD1_UV

Use the maximum V_Fail-safevoltage specified in the Electrical Characteristics table as a reference value for

fail-safe detection on a system level.

7.4 Device Functional Modes

The AMC1350 is operational when the power supplies VDD1 and VDD2 are applied as specified in the

Recommended Operating Conditions table.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The high input impedance, low input bias current, bipolar input voltage range, excellent accuracy, and low

temperature drift make the AMC1350 a high-performance solution for industrial applications where isolated AC

or DC voltage sensing is required.

8.2 Typical Application

Isolated amplifiers are widely used for voltage measurements in high-voltage applications that must be isolated

from a low-voltage domain. Typical applications are AC line voltage measurements, either line-to-neutral or

line-to-line in grid-connected equipment.

Figure 8-1 illustrates a simplified schematic of a solar inverter application that uses three AMC1350 devices

to measure the AC line voltage on each phase of a three-phase system. The AC line voltage is divided down

to an approximate ±5-V level across the bottom resistor (RSNS) of a high-impedance resistive divider that is

sensed by the AMC1350. The output of the AMC1350 is a differential analog output voltage proportional to the

input voltage but is galvanically isolated from the high-side by a reinforced isolation barrier. A common high-side

power supply (VDD1) for all three AMC1350 devices is generated from the low-side supply (VDD2) of the system

by an isolated DC/DC converter circuit. A low-cost solution is based on the push-pull driver SN6501 and a

transformer that supports the desired isolation voltage ratings.

The high-impedance input, high input voltage range, and the high common-mode transient immunity (CMTI) of

the AMC1350 ensure reliable and accurate operation even in high-noise environments.

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Solar Panel Array

DC-Link

+ DC-Bus

DC/DC

EMI

Contactor

Filter

Number of unit resistors

depends on

design requirements.

RSNS

DC-Bus

Low-side supply

(3.3 V or 5 V)

100 nF 1 uF

AMC1350

VDD1

VDD2

OUTP

OUTN

GND2

INP

ADC

INN

GND1

1 μF 100 nF

100 nF 1 uF

AMC1350

VDD1

VDD2

OUTP

OUTN

GND2

INP

INN

GND1

100 nF 1 uF

AMC1350

VDD1

VDD2

OUTP

OUTN

GND2

INP

INN

GND1

TPS76350

SN6501

GND

VCC

V_OUT= 5 V

OUT

GND

10 μF 100 nF

10 μF

100 nF 4.7 μF

Figure 8-1. Using the AMC1350 for AC Line-Voltage Sensing in a Solar Inverter Application

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8.2.1 Design Requirements

Table 8-1 lists the parameters for this typical application.

Table 8-1. Design Requirements

PARAMETER

120-V_RMSLINE VOLTAGE

120 V ±10%, 60 Hz

3.3 V or 5 V

230-V_RMSLINE VOLTAGE

System input voltage

230 V ±10%, 50 Hz

3.3 V or 5 V

75 V

High-side supply voltage

Low-side supply voltage

3.3 V or 5 V

Maximum resistor operating voltage

75 V

Voltage drop across the sense resistor (RSNS) for a linear response

Current through the resistive divider, I_CROSS

±5 V (maximum)

100 μA

±5 V (maximum)

100 μA

8.2.2 Detailed Design Procedure

This discussion covers the 230-V_RMSexample. The procedure for calculating the resistive divider for the 120-

V_RMSuse case is identical.

The 100-μA, cross-current requirement at peak input voltage (360 V) determines that the total impedance of

the resistive divider is 3.6 MΩ. The impedance of the resistive divider is dominated by the top resistors (shown

exemplary as R1 and R2 in Figure 8-1) and the voltage drop across RSNS can be neglected for a short time.

The maximum allowed voltage drop per unit resistor is specified as 75 V; therefore, the total minimum number of

unit resistors in the top portion of the resistive divider is 360 V / 75 V = 5. The calculated unit value is 3.6 MΩ / 5

= 720 kΩ and the next closest value from the E96 series is 715 kΩ.

The effective sense resistor value RSNS_EFFis the parallel combination of the external resistor RSNS and the

input impedance of the AMC1350, R_IN. RSNS_EFFis sized such that the voltage drop across the impedance at

maximum input voltage (360 V) equals the linear full-scale input voltage (V_FSR) of the AMC1350 (that is, +5 V).

RSNS_EFFis calculated as RSNS_EFF= V_FSR/ (V_Peak– V_FSR) × R_TOPwhere R_TOPis the total value of the top

resistor string (5 × 715 kΩ = 3575 kΩ). The resulting value for RSNS_EFFis 9.96 kΩ. In a final step, RSNS is

calculated as RSNS = R_IN× RSNS_EFF/ (R_IN– RSNS_EFF). With R_IN= 1.25 MΩ (typical), RSNS equals 52.47 kΩ

and the next closest value from the E96 series is 52.3 kΩ.

Table 8-2 summarizes the design of the resistive divider.

Table 8-2. Resistor Value Examples

PARAMETER

120-V_RMSLINE VOLTAGE

230-V_RMSLINE VOLTAGE

Peak voltage

190 V

634 kΩ

360 V

715 kΩ

Unit resistor value, R_TOP

Number of unit resistors in R_TOP

Sense resistor value, RSNS

53.6 kΩ

1953.4 kΩ

97.3 μA

4.993 V

6 mW

52.3 kΩ

3625.2 kΩ

99.3 μA

4.982 V

7.1 mW

35.7 mW

Total resistance value (R_TOP+ RSNS)

Resulting current through resistive divider, I_CROSS

Resulting full-scale voltage drop across sense resistor RSNS

Peak power dissipated in R_TOPunit resistor

Total peak power dissipated in resistive divider

18.5 mW

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8.2.2.1 Input Filter Design

Placing an RC filter in front of the isolated amplifier improves signal-to-noise performance of the signal path. In

practice, however, the impedance of the resistor divider is so high that adding a filter capacitor on the INN or INP

pin limits the signal bandwidth to an unacceptable low limit, such that the filter capacitor is omitted. When used,

design the input filter such that:

•

The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency

(20 MHz) of the internal ΔΣ modulator

The input bias current does not generate significant voltage drop across the DC impedance of the input filter

Most voltage-sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale

down the input voltage. In that case, no additional resistor is needed and a single capacitor (as shown in Figure

8-2) is sufficient to filter the input signal.

AMC1350

VDD1

VDD2

OUTP

OUTN

GND2

1 nF

INP

INN

GND1

Figure 8-2. Input Filter

8.2.2.2 Differential to Single-Ended Output Conversion

Figure 8-3 shows an example of a TLV6001-based signal conversion and filter circuit for systems using single-

ended input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage

equals (V_OUTP– V_OUTN) + V_REF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the

system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ

and C1 = C2 = 330 pF yields good performance.

AMC1350

VDD1

VDD2

OUTP

OUTN

GND2

INP

–

ADC

To MCU

INN

TLV6001

GND1

V_REF

Figure 8-3. Connecting the AMC1350 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see

the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data

Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.

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8.2.3 Application Curve

One important aspect of system design is the effective detection of an overvoltage condition to protect switching

devices and passive components from damage. To power off the system quickly in the event of an overvoltage

condition, a low delay caused by the isolated amplifier is required. Figure 8-4 shows the typical full-scale step

response of the AMC1350.

VOUTP

VOUTN

VIN

Figure 8-4. Step Response of the AMC1350

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8.3 What To Do and What Not To Do

Do not leave the inputs of the AMC1350 unconnected (floating) when the device is powered up. If the device

inputs are left floating, the input bias current may drive the inputs to a positive or negative value that exceeds the

operating common-mode input voltage and the device output is undetermined.

Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current

path between INN and GND1 is required to define the input common-mode voltage. Take care not to exceed

the input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy,

route the ground connection as a separate trace that connects directly to the sense resistor rather than shorting

GND1 to INN directly at the input to the device. See the Layout section for more details.

Do not connect protection diodes to the inputs (INP or INN) of the AMC1350. Diode leakage current can

introduce significant measurement error especially at high temperatures. The input pin is protected against high

voltages by its ESD protection circuit and the high impedance of the external restive divider.

9 Power Supply Recommendations

In a typical application, the high-side power supply (VDD1) for the AMC1350 is generated from the low-side

supply (VDD2) by an isolated DC/DC converter. A low-cost solution is based on the push-pull driver SN6501 and

a transformer that supports the desired isolation voltage ratings.

The AMC1350 does not require any specific power-up sequencing. The high-side power supply (VDD1) is

decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-μF capacitor (C2). The low-side

power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-μF

capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. Figure 9-1

shows a decoupling diagram for the AMC1350.

VAC

VDD1

VDD2

C2 1 µF

C4 1 µF

AMC1350

C1 100 nF

C3 100 nF

VDD1

VDD2

OUTP

OUTN

GND2

INP

to RC filter / ADC

RSNS

INN

GND1

Figure 9-1. Decoupling of the AMC1350

Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they

experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their

nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting

these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is

higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves

that greatly simplify component selection.

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Product Folder Links: AMC1350

AMC1350

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SBASAA6A – AUGUST 2021 – REVISED DECEMBER 2021

10 Layout

10.1 Layout Guidelines

Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as

possible to the AMC1350 supply pins) and placement of the other components required by the device. For best

performance, place the sense resistor close to the device input pin (IN).

10.2 Layout Example

Clearance area, to be

kept free of any

conductive materials.

to RC filter / ADC

INP

INN

OUTP

OUTN

GND2

AMC1350

Top Metal

Inner or Bottom Layer Metal

Via

Figure 10-1. Recommended Layout of the AMC1350

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SBASAA6A – AUGUST 2021 – REVISED DECEMBER 2021

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

•

Texas Instruments, Isolation Glossary application report

Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report

Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive

Systems data sheet

•

Texas Instruments, TPS763 Low-Power, 150-mA, Low-Dropout Linear Regulator data sheet

Texas Instrument, SN6501 Transformer Driver for Isolated Power Supplies data sheet

Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise

reference guide

•

Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference

guide

•

Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool

Texas Instruments, Best in Class Radiated Emissions EMI Performance with the AMC1300B-Q1 Isolated

Amplifier technical white paper

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: AMC1350

PACKAGE OPTION ADDENDUM

www.ti.com

13-Dec-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

AMC1350DWV

ACTIVE

SOIC

DWV

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

AMC1350

AMC1350DWVR

1000 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

13-Dec-2021

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC1350DWVR

SOIC

DWV

1000

330.0

16.4

12.05 6.15

3.3

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DWV

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

AMC1350DWVR

1000

Pack Materials-Page 2

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

SOIC

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE 3

3.81

0.51

0.31

7.6

7.4

0.25

C A

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

5962R2021001V9A [TI]

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