5962R7802005QEA [TI]
QUAD LINE RECEIVER, CDIP16, CERAMIC, DIP-16;
| 型号： | 5962R7802005QEA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD LINE RECEIVER, CDIP16, CERAMIC, DIP-16 CD |
| 文件： | 总13页 (文件大小：691K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS26F32MQML
DS26F32MQML Quad Differential Line Receivers
Literature Number: SNOSAS5
March 2006
DS26F32MQML
Quad Differential Line Receivers
The DS26F32 offers optimum performance when used with
the DS26F31 Quad Differential Line Driver.
General Description
The DS26F32 is a quad differential line receiver designed to
meet the requirements of EIA Standards RS-422 and RS-
423, and Federal Standards 1020 and 1030 for balanced
and unbalanced digital data transmission.
Features
n Input voltage range of 7.0V (differential or common
mode) 0.2V sensitivity over the input voltage range
n High input impedance
The DS26F32 offers improved performance due to the use
of state-of-the-art L-FAST bipolar technology. The L-FAST
technology allows for higher speeds and lower currents by
utilizing extremely short gate delay times. Thus, the
DS26F32 features lower power, extended temperature
range, and improved specifications.
n Operation from single +5.0V supply
n Input pull-down resistor prevents output oscillation on
unused channels
n TRI-STATE outputs, with choice of complementary
enables, for receiving directly onto a data bus
The device features an input sensitivity of 200 mV over the
input common mode range of 7.0V. The DS26F32 provides
an enable function common to all four receivers and TRI-
®
STATE outputs with 8.0 mA sink capability. Also, a fail-safe
input/output relationship keeps the outputs high when the
inputs are open.
Ordering Information
NS Part Number
SMD Part Number
5962–7802005M2A
5962–7802005MEA
5962–7802005MFA
5962–7802005MZA
5962R7802005M2A
5962R7802005QEA
5962R7802005QFA
5962–7802005VEA
5962–7802005VFA
5962–7802005VZA
5962R7802005VEA
100k rd(Si)
NS Package Number
E20A
Package Description
20LD Leadless Chip Carrier
16LD Ceramic DIP
DS26F32ME/883
DS26F32MJ/883
J16A
DS26F32MW/883
DS26F32MWG/883
DS26F32MER-QML
DS26F32MJR-QML
DS26F32MWR-QML
DS26F32MJ-QMLV
DS26F32MW-QMLV
DS26F32MWG-QMLV
DS26F32MJRQMLV
W16A
16LD Ceramic FLatpack
16LD Ceramic SOIC
20LD Leadless Chip Carrier
16LD Ceramic DIP
WG16A
E20A
J16A
W16A
16LD Ceramic FLatpack
16LD Ceramic DIP
J16A
W16A
16LD Ceramic FLatpack
16LD Ceramic SOIC
16LD Ceramic DIP
WG16A
J16A
DS26F32MWRQMLV
DS26F32MWGRQMLV
5962R7802005VFA
100k rd(Si)
W16A
16LD Ceramic FLatpack
16LD Ceramic SOIC
5962R7802005VZA
100k rd(Si)
WG16A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS201633
www.national.com
Connection Diagrams
20163307
20-Lead Ceramic Leadless Chip Carrier
See NS Package Number E20A
20163301
Top View
16-Lead Ceramic DIP Pictured
See NS Package Number WG16A, J16A or W16A
Function Table
(Each Receiver)
Differential Inputs
Enables
Outputs
VID = (V +) − (VI−)
E
E
X
L
OUT
H
I
VID ≥ 0.2V
VID ≤ −0.2V
X
H
X
H
X
L
H
X
L
L
L
H
Z
H = High Level
L = Low Level
X = Immaterial
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2
Absolute Maximum Ratings (Note 1)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 sec)
Supply Voltage
−65˚C ≤ TA ≤ +150˚C
−55˚C ≤ TA ≤ +125˚C
300˚C
7.0V
Common Mode Voltage Range
Differential Input Voltage
Enable Voltage
25V
25V
7.0V
Output Sink Current
50 mA
500 mW
Maximum Power Dissipation (PD maxat 25˚C (Note 2), (Note 3)
Thermal Resistance
θJA
Ceramic DIP
100˚C/W
142˚C/W
87˚C/W
Ceramic Flatpack
Leadless Chip Carrier
θJC
Junction-to- case
See MIL-STD-1835
Recommended Operating Range
Operating Temperature
−55˚C ≤ TA ≤ +125˚C
Supply Voltage
4.5V to 5.5V
Radiation Features
DS26F32MJRQMLV
DS26F32MWRQMLV
DS26F32MWGRQMLV
100 krads (Si)
100 krads (Si)
100 krads (Si)
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp ˚C
25
1
2
Static tests at
Static tests at
125
-55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
5
125
-55
25
6
7
8A
8B
9
125
-55
25
10
11
12
13
14
125
-55
25
125
-55
3
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DS26F32 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
DC:
VCC = 5V (Note 7)
Parameter
Sub-
groups
1, 2, 3
Symbol
Conditions
Pin under test
Notes
Min Max
Units
IIn
Input Current
2.3
mA
VCC = 4.5V, VI = 15V
Other inputs -15V ≤ VI ≤ +15V
Pin under test
-2.8
mA
1, 2, 3
VCC = 5.5V, VI = -15V
Other inputs -15V ≤ VI ≤ +15V
VCC = 5.5V, VEn = 0.4V
VCC = 5.5V, VI = 2.7V
VCC = 5.5V, VI = 5.5V
VCC = 4.5V, II = -18mA
VCC = 4.5V, IOH = -440µA,
∆VI = 1V, VEn = .8 = VEn
IIL
Logical "0" Enable Current
Logical "1" Enable Current
Logical "1" Enable Current
Input Clamp Voltage (Enable)
Logical "1" Output Voltage
-360
µA
µA
µA
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
IIH
II
10
50
VIK
VOH
-1.5
2.5
V
VOL
Logical "0" Output Voltage
VCC = 4.5V, VEn =0.8V = VEn
,
0.4
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
IOL = 4mA, ∆VI = -1V
VCC = 4.5V, VEn = 8V = VEn
IOL = 8mA, ∆VI = -1V
VCC = 5.5V, All VI = Gnd,
VEn = 0V, VEn = 2V
,
.45
ICC
IOZ
Supply Current
50
mA
µA
µA
Off-State Output Current
VCC = 5.5V, VO = 0.4V,
VEn = 0.8V, VEn = 2V
VCC = 5.5V, VO = 2.4V,
VEn = 0.8V, VEn = 2V
-15 ≤ VCM ≤ 15V
-20
20
RI
Input Resistance
14
KΩ
1, 2, 3
1, 2, 3
VTh
Differential Input Voltage
VCC = 4.5V, VOUT = VOL or VOH (Note 4)
-0.2
0.2
0.2
0.8
V
-7V ≤ VCM ≤ 7V,
VEn = VEn = 2.5V
VCC = 5.5V, VOUT = VOL or VOH (Note 4)
-7V ≤ VCM ≤ 7V,
VEn = VEn = 2.5V
-0.2
V
1, 2, 3
VIL
Logical "0" Input Voltage
(Enable)
VCC = 5.5V
VCC = 4.5V
(Note 4)
(Note 4)
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VIH
Logical "1" Input Voltage
(Enable)
2.0
-15
ISC Min
ISC Max
Output Short Circuit Current
VCC = 4.5V, VO = 0V,
∆VI = 1V
mA
mA
Output Short Circuit Current
VCC = 5.5V, VO = 0V,
∆VI = 1V
-85
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4
DS26F32 Electrical Characteristics (Continued)
AC Parameters
The following conditions apply, unless otherwise specified.
AC:
VCC = 5V (Note 7)
Parameter
Sub-
groups
9
Symbol
Conditions
Notes
Min Max
Units
tPLH
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 5pF
(Note 6)
(Note 6)
(Note 5)
(Note 5)
(Note 6)
(Note 6)
(Note 5)
(Note 5)
(Note 6)
(Note 6)
(Note 5)
(Note 5)
(Note 6)
(Note 6)
(Note 5)
(Note 5)
(Note 6)
(Note 6)
(Note 5)
(Note 5)
(Note 6)
(Note 6)
(Note 5)
(Note 5)
23
31
22
30
23
31
22
30
18
29
16
27
20
29
18
27
55
62
20
27
30
42
18
30
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
10, 11
9
10, 11
9
tPHL
tPZH
tPZL
tPHZ
tPLZ
10, 11
9
10, 11
9
Enable Time
Enable Time
Disable Time
Disable Time
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
CL = 50pF
CL = 5pF
10, 11
9
10, 11
DC Drift Parameters
This section applies to -QMLV devices only. Devices shall be read & recorded at TA = 25˚C before and after each burn-in and
shall not change by more than the limits indicated. The delta rejects shall be included in the PDA calculation.
Sub-
groups
Symbol
VOH
VOL
Parameter
Conditions
Notes
Min Max
Units
Logical "1" Output Voltage
VCC = 4.5V, IOH = -440µA,
∆VI = 1V, VEn = 0.8V = VEn
VCC = 4.5V, IOL = 4mA,
∆VI = -1V, VEn = 0.8V = VEn
VCC = 4.5V, IOL = 8mA,
∆ VI = -1V, VEn = 0.8V = VEn
Pin under test
-250 250
mV
1
Logical "0" Output Voltage
Input Current
-45
-45
45
45
mV
mV
mA
1
1
1
II
-0.28 0.28
-0.28 0.28
VCC = 4.5V, VI = 15V
Other inputs -15V ≤ VI ≤ +15V
Pin under test
mA
1
VCC = 5.5V, VI = -15V
Other inputs -15V ≤ VI ≤ +15V
5
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Derate J package 10.0mW/˚C above +25˚C, derate W package 7.1mW/˚C above +25˚C, derate E package 11.5mW/˚C above +25˚C.
Note 3: Power dissipation must be externally controlled at elevated temperatures.
Note 4: Parameter tested go-no-go only.
Note 5: Tested at 50pF guarantees limit at 15pF & 5pF.
Note 6: Tested at 50pF, system capacitance exceeds 5pF to 15pF.
Note 7: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space
environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in Mil-Std-883, Method 1019.5, Condition A
20163302
FIGURE 1. Logic Symbol
20163303
FIGURE 2. Load Test Circuit for Three-State Outputs
20163304
FIGURE 3. Propagation Delay (Notes 8, 9, 10)
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6
20163305
Note 8: Diagram shown for ENABLE Low.
Note 9: S1 and S2 of Load Circuit are closed except where shown.
Note 10: Pulse Generator of all Pulses: Rate ≤ 1.0 MHz, Z = 50Ω, t ≤ 6.0 ns, t ≤ 6.0 ns.
O
r
f
Note 11: All diodes are IN916 or IN3064.
Note 12: C includes probe and jig capacitance.
L
FIGURE 4. Enable and Disable Times (Notes 8, 9, 10)
Typical Application
20163306
FIGURE 5.
7
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Revision History
Released
Revision
Section
Originator
Changes
03/01/06
A
New Release, Corporate format
L. Lytle
1 MDS data sheet converted into one Corp.
data sheet format. MNDS26F32M-X-RH Rev
0C0 will be archived.
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8
Physical Dimensions inches (millimeters) unless otherwise noted
20LD Leadless Chip Carrier (E)
NS Package Number E20A
Ceramic Dual-In-Line Package (J)
NS Package Number J16A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16LD Ceramic Flatpack (W)
NS Package Number W16A
16LD Ceramic SOIC (WG)
NS Package Number WG16A
www.national.com
10
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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