5962R8768106VYC [TI]
耐辐射 QMLV、30V 输入、2A 双输出 1MHz PWM 控制器 | HKT | 16 | -55 to 125;
| 型号： | 5962R8768106VYC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射 QMLV、30V 输入、2A 双输出 1MHz PWM 控制器 | HKT | 16 | -55 to 125 控制器 |
| 文件： | 总34页 (文件大小：1374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1825B-SP
ZHCSJJ9A –APRIL 2019 –REVISED DECEMBER 2020
UC1825B-SP V 类耐辐射高速PWM 控制器
1 特性
3 说明
• 符合QML-V 标准，SMD 5962-8768106
• 5962R8768106VYC：
– 耐辐射加固保障(RHA) 能力高达100krad(Si) 总
电离剂量(TID) 1
• 与电压或电流模式拓扑兼容
• 实际工作开关频率高达1MHz
• 50ns 传播延迟到输出
• 大电流双图腾柱输出（2A 峰值）
• 宽带宽误差放大器
• 带有双脉冲抑制功能的全锁存逻辑
• 逐脉冲电流限制
• 软启动/最大占空比控制
• 带有迟滞功能的欠压锁定
• 低启动电流(1.1mA)
UC1825B-SP PWM 控制器件针对高频开关模式电源应
用进行了优化。对在大大增加误差放大器的带宽和转换
率的同时，大大减小通过比较器和逻辑电路的传播延迟
给与了特别关注。这个控制器设计用于电流模式或电压
模式系统，此系统具有输出电压前馈功能。
保护电路包括一个阈值电压为 1V 的电流限制比较器、
一个 TTL 兼容关断端口和一个软启动引脚，此引脚可
对折为一个最大占空比钳位。此逻辑被完全锁存以提供
无抖动运行，并且抑制了输出上的多脉冲。一个具有
800mV 滞后的欠压闭锁部分可确保低启动电流。欠压
闭锁期间，输出为高阻抗。
这个器件特有推挽式输出，此输出被设计用来拉、灌来
自电容负载（诸如一个功率金属氧化物半导体场效应晶
体管 (MOSFET) 的栅极）的高峰值电流。导通状态设
计为高电平。
2 应用
• 耐辐射直流/直流转换器
• 卫星总线和有效载荷
• 通信负载
• 光学成像有效载荷
• 雷达成像有效载荷
• 太空运载火箭
器件信息
等级(2)
器件型号(1)
封装
CFP (16)
飞行等级QMLV-
RHA 100krad(Si)
5962R8768106VYC
UC1825BHKT/EM
10.16mm x 7.10mm
工程样片(3)
飞行等级QMLV-
RHA KGD
100krad(Si)
• 支持多种拓扑结构：
– 反激、正激、降压、升压
5962R8768106V9A
裸片
– 推挽、半桥、全桥（采用外部接口电路时）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CLOCK
R
4
5
T
(2) 有关器件等级的其他信息，请查看SLYB235。
(3) 这些器件仅适用于工程评估。器件按照不合规的流程进行加工
处理。这些器件不适用于鉴定、生产、辐射测试或飞行用途。
这些零器件无法在–55°C 至125°C 的完整MIL 额定温度范围
内或运行寿命中保证其性能。
OSC
PWM Latch
(Set Dom.)
C
6
T
1.25 V
R
RAMP
7
S
E/A Out
3
Wide Bandwidth
Error Amp.
V
IN
2
1
NI
+
−
Error
Amp
INV
Inhibit
9 µA
Toggler F/F
T
Vc
13
11
Out A
Soft Start
8
9
I
LIM
CPRTR
14 Out B
12
1 V
Shutdown
CPRTR
Pwr GND
I
/ SD
LIM
1.4 V
Output
Inhibit
V
15
CC
Internal
Bias
9 V
UVLO
4 V
V
Good
REF
GND 10
REF
Gen
V
REF
Gate
16
V
Good
CC
VDG−92032−2
方框图
1
辐射耐受性是基于初始器件认证（剂量率= 10mrad(Si)/s）获得的典型值。提供辐射批次验收测试- 详细信息请联系厂家。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDD5
UC1825B-SP
ZHCSJJ9A –APRIL 2019 –REVISED DECEMBER 2020
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 16
8.3 Application Curves....................................................22
9 Power Supply Recommendations................................26
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Documentation Support.......................................... 28
11.2 接收文档更新通知................................................... 28
11.3 支持资源..................................................................28
11.4 Trademarks............................................................. 28
11.5 静电放电警告...........................................................28
11.6 术语表..................................................................... 28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................7
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................14
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2019) to Revision A (December 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added Bare Die Information table to Pin Configuration and Functions section..................................................3
• Added UC1825B-SP Bare Die Pin Number Locations figure to Pin Configuration and Functions section.........3
• Added Bond Pad Coordinates in Microns table to Pin Configuration and Functions section............................. 3
• Updated Synchronization section......................................................................................................................11
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English Data Sheet: SLUSDD5
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5 Pin Configuration and Functions
图5-1. HKT Package
16-Pin CFP
Top View
表5-1. Pin Functions
NAME
NO.
I/O
DESCRIPTION
CLK
4
O
Output of the internal oscillator.
Timing capacitor connection pin for oscillator frequency programming. The timing
capacitor should be connected to the device ground using minimal trace length.
CT
6
I
EAOUT
GND
3
10
9
O
Output of the error amplifier for compensation.
Analog ground return pin.
—
I
ILIM/SD
INV
Input to the current limit comparator and the shutdown comparator.
Inverting input to the error amplifier.
1
I
NI
2
I
Non-inverting input to the error amplifier.
OUTA
OUTB
PGND
11
14
12
O
O
High-current totem pole output A of the on-chip drive stage.
High-current totem pole output B of the on-chip drive stage.
Ground return pin for the output driver stage.
—
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage
mode operation this serves as the input voltage feed-forward function by using the CT
ramp. In peak current mode operation, this serves as the slope compensation input.
RAMP
7
I
RT
SS
5
8
I
I
Timing resistor connection pin for oscillator frequency programming.
Soft-start input pin which also doubles as the maximum duty cycle clamp.
Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF
monolithic ceramic low ESL capacitor with minimal trace lengths.
VC
13
15
16
—
—
O
Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic
ceramic low ESL capacitor with minimal trace lengths.
VCC
VREF
5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic
ceramic low ESL capacitor and minimal trace length to the ground plane.
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表5-2. Bare Die Information
BACKSIDE POTENTIAL
GND
BOND PAD
METALLIZATION
COMPOSITION
DIE THICKNESS
BACKSIDE FINISH
BOND PAD THICKNESS
15 mils
Backgrind Si - Finish
AlCu
2000 nm
图5-2. UC1825B-SP Bare Die Pin Number Locations
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表5-3. Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
962.66
754.38
147.32
Y MIN
2933.7
2938.78
2451.1
X MAX
1064.26
855.98
248.92
Y MAX
3035.3
3040.38
2552.7
INV
NI
1
2
3
EAOUT
CLK
4
124.46
165.1
2052.32
1244.6
708.66
167.64
167.64
307.34
66.04
226.06
266.7
2153.92
1346.2
810.26
269.24
269.24
408.94
167.64
853.44
1564.64
1562.1
2273.3
3035.3
3116.58
RT
9
CT
10
11
12
13
15
16
17
18
19
20
21
134.62
429.26
594.36
1681.48
2225.04
1879.6
2153.92
1564.64
1889.76
2207.26
1874.52
236.22
530.86
695.96
1783.08
2326.64
1981.2
2255.52
1666.24
1991.36
2308.86
1976.12
RAMP
SS
ILIM/SD
GND
OUTA
PGND
VC
751.84
1463.04
1460.5
2171.7
2933.7
3014.98
OUTB
VCC
RAMP
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
Supply voltage
VC, VCC
DC
30
0.5
2.0
7
V
Output current, source or sink, OUTA, OUTB
A
V
Pulse (0.5 μs)
INV, NI, RAMP
SS, ILIM/SD
CLK
–0.3
–0.3
Analog inputs
6
Clock output current
mA
mA
mA
mA
W
–5
5
Error amplifier output current
Soft-start sink current
EAOUT
SS
20
Oscillator charging current
Power dissipation
RT
–5
1
Lead temperature (soldering, 10 seconds)
Storage temperature
300
150
°C
Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to GND; all currents are positive into, negative out of part; pin numbers refer to CFP-16 package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (TA = TJ = –55°C to 125°C), unless otherwise noted.
MIN
10
0
MAX
UNIT
V
VCC
Supply voltage
30
100
10
Sink/source output current (continuous or time average)
Reference load current
mA
mA
0
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6.4 Thermal Information
UC1825B-SP
THERMAL METRIC(1)
HKT (CFP)
16 PINS
32.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
13.8
15.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7
ψJT
14.6
ψJB
RθJC(bot)
5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Unless otherwise stated, these specifications apply for RT = 3.65 kΩ, CT = 1 nF, VCC = 15 V, –55°C < TA < 125°C, TA = TJ
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
REFERENCE
Output voltage
Line regulation
TJ = 25°C, IO = 1 mA
5.024
5.1
2
5.176
20
V
10 V < VCC < 30 V
1 mA < IO < 10 mA
Line, load, temperature
10 Hz < f < 10 kHz
VREF = 0 V
mV
mV
V
Load regulation
5
20
Total output variation
Output noise voltage
Short-circuit current
OSCILLATOR SECTION
Initial accuracy
5
5.2
50
μV
mA
–15
–50
–100
TJ = 25°C
360
400
0.2%
5%
440
2%
kHz
Voltage stability
10 V < VCC < 30 V
TMIN < TA < TMAX
Line, Temperature
Temperature stability
Total variation
16%
460
340
3.9
kHz
V
Clock out high
4.5
2.3
2.8
1
Clock out low
2.9
3
V
Ramp peak(1)
2.6
0.7
1.6
V
Ramp valley(1)
1.25
2.1
V
Ramp valley to peak(1)
ERROR AMPLIFIER
Input offset voltage
Input bias current
Input offset current
Open-loop gain
1.8
V
10
3
mV
μA
μA
dB
0.6
0.1
95
1
1 V < VO < 4 V
1.5 V < VCM < 5.5 V
10 V < VCC < 30 V
VE/AOut= 1 V
60
CMRR
75
95
dB
PSRR
85
110
2.5
–1.3
4.7
0.5
10.5
9
dB
Output sink current
Output source current
Output high voltage
Output low voltage
Gain bandwidth product(1)
Slew rate(1)
1
mA
mA
V
VE/AOut = 4 V
–0.5
4
0
5
4
5.
1
IE/AOut = –0.5 mA
IE/AOut = 1 mA
f = 200 kHz
V
MHz
V/μs
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6.5 Electrical Characteristics (continued)
Unless otherwise stated, these specifications apply for RT = 3.65 kΩ, CT = 1 nF, VCC = 15 V, –55°C < TA < 125°C, TA = TJ
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
PWM COMPARATOR
Ramp bias current
Duty cycle range
VRamp = 0 V
VRamp = 0 V
–1
–5
μA
0%
1.1
80%
E/A out zero dc threshold
Delay to output(1)
1.25
50
V
80
20
ns
SOFT-START
Charge current
VSoft Start = 0.5 V
VSoft Start = 1 V
3
1
9
μA
Discharge current
mA
CURRENT LIMIT/SHUTDOWN
Current limit/shutdown bias current
Current limit threshold
Shutdown threshold
Delay to output(1)
0 < VILIM/SD < 4 V
15
1.1
μA
V
0.9
1
1.4
50
1.25
1.55
80
V
ns
OUTPUT
IOUT = 20 mA
IOUT = 200 mA
IOUT = –20 mA
IOUT = –200 mA
VC = 30 V
0.25
1.2
13.5
13
0.4
2.2
Low-level output voltage
High-level output voltage
V
V
13
12
Collector leakage
Rise/fall time(1)
10
500
75
μA
CL = 1 nF
30
ns
UNDERVOLTAGE LOCKOUT
Start threshold
8.8
0.4
9.2
0.8
9.6
1.2
V
V
UVLO hysteresis
SUPPLY CURRENT SECTION
Startup current
VCC = 8 V
1.1
22
2.5
33
mA
mA
ICC
VINV = VRamp = VILIM/SD = 0 V, VNI = 1 V
(1) Parameters ensured by design and/or characterization, if not production tested.
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6.6 Typical Characteristics
Light
Full
130
120
110
100
90
130
Gain-Light Load
Gain-Full Load
120
110
100
90
80
70
80
70
60
50
60
50
40
40
30
20
10
0
-10
-20
-30
30
20
10
0
-10
-20
-30
CTL–
Outpu Light Load
CTL–
Output Full Load
100
101
102
103
104
105
106
107
100
101
102
103
104
105
106
107
Frequency (Hz)
Frequency (Hz)
0
0
Phase
Phase
-90
-90
180
180
图6-1. Gain: Light Load
图6-2. Gain: Full Load
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7 Detailed Description
7.1 Overview
UC1825B-SP PWM controller is a radiation hardened version of the standard UC1825 family. Error amplifier gain
bandwidth product is 10.5 MHz. Protection circuitry includes a current limit comparator with a 1-V threshold, a
TTL compatible shutdown port, and a soft start pin which will double as a maximum duty-cycle clamp. The logic
is fully latched to provide jitter-free operation and prohibit multiple pulses at an output. An undervoltage lockout
section with 800 mV of hysteresis assures low start up current. During undervoltage lockout, the outputs are high
impedance. This device features totem pole outputs designed to source and sink high peak currents from
capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level.
7.2 Functional Block Diagram
CLOCK
R
4
5
T
OSC
PWM Latch
(Set Dom.)
C
T
6
1.25 V
R
RAMP
7
S
E/A Out
3
Wide Bandwidth
Error Amp.
V
IN
2
1
NI
+
−
Error
Amp
INV
Inhibit
9 µA
Toggler F/F
T
Vc
13
11
Out A
Soft Start
8
9
I
LIM
CPRTR
Out B
14
12
1 V
Shutdown
CPRTR
Pwr GND
I
/ SD
LIM
1.4 V
Output
Inhibit
15
10
V
CC
Internal
Bias
9 V
UVLO
4 V
V
Good
REF
GND
REF
Gen
V
Gate
16
REF
V
Good
CC
VDG−92032−2
7.3 Feature Description
UC1825B-SP can be configured as current mode controller, used to support various topologies such as forward,
flyback, buck, boost and using an external interface circuit will also support half-bridge, full bridge, and push-pull
configurations.
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7.3.1 Control Methods
图7-1 shows the control methods.
Voltage Mode
Current Mode
ISWITCH
6
7
Oscillator
6
7
Oscillator
CT
CT
CT
1.25 V
1.25 V
RAMP
RAMP
RSENSE
CT
from E/A
from E/A
UDG-95110
图7-1. Control Methods
7.3.2 Synchronization
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor (see 图 7-2).
Program the free running frequency of the oscillator to be 10% to 15% slower than the desired synchronous
frequency. The pulse width must be greater than 10 ns and less than half the discharge time of the oscillator. 图
7-3 shows how to synchronize two ICs, with one as primary and one as secondary. 图 7-4 shows the waveforms
in a primary and secondary configuration.
RT
5
VSYNC
CT
RT
39 Ω
6
10 Ω
50-Ω
External
Clock
UDG-95111
图7-2. General Oscillator Synchronization
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4
39 pF 120 Ω
CT
6
4.7 kΩ
22 Ω
Primary
Secondary
CT
RT
6
5
1.5 × RT
5
图7-3. Two Unit Interface
VSYNC
VCT
UDG-95112
图7-4. Operational Waveforms
7.3.3 High Current Outputs
Each totem pole output of the UC1825B-SP can deliver a 2-A peak current into a capacitive load. The output can
slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground
(PGND) pins help decouple the analog circuitry of the device from the high-power gate drive noise. The use of
3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the 图 10-1 from each output to both VC and
PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of
inductive or capacitive load, typical of a MOSFET gate, as shown in 图 7-5. Schottky diodes must be used
because a low forward voltage drop is required.
备注
Do not use standard silicon diodes.
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VC
VCC
1 nF
10 μF
D1
OUT
6.8 Ω
D2
PGND
GND
D1. D2 = 1N5820
UDG-95114
图7-5. Power MOSFET Drive Circuit
7.3.4 Open Loop Test Circuit
This test fixture is useful for exercising many functions of this device family and measuring their specifications
(see 图 7-6). As with any wideband circuit, careful grounding and bypass procedures must be followed. TI highly
recommends using a ground plane.
UC1825
4
5
6
7
Clock
V
15
13
15 V
CC
0.1 mF
0.1 mF
R
3.65 kW
T
Oscillator
R
C
L
V
15 V
C
1 nF
C
T
T
10 mF
Ramp
11
14
Out A
Out B
50 W
E/A Out
3
27 kW
4.7 kW
2 x 1N5820
68 kW
Error
Amp
22 kW
Pwr Gnd 12
Gnd 10
2
1
8
Non INV
INV
10 kW
27 kW
4.7 kW
10 mF
Soft Start
0.1 mF
V
REF
5.1 V 16
10 kW
9
I
Shutdown
LIM
3.3 kW
VDG−92032−2
图7-6. Open Loop Test Circuit Schematic
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7.4 Device Functional Modes
The UC1825B-SP is compatible with voltage-mode or current-mode topologies. The UC1825B-SP uses fixed
frequency, peak current mode control. An internal oscillator initiates the turn-on of the driver to high-side power
switch. The external power switch current is sensed through an external resistor and is compared through
internal comparator. The voltage generated at the COMP pin is stepped down through internal resistors. When
the sensed current reaches the stepped down COMP voltage, the high-side power switch is turned off.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The oscillator of the UC1825B-SP is a saw tooth (see 图 8-1). The rising edge is governed by a current
controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets
dead time for the outputs. Selection of RT must be done first, based on desired maximum duty cycle (see 图
8-3). CT can then be chosen based on the desired frequency (RT) and DMAX (see 图 8-2). 方程式 1 shows the
design equations.
ǒ1.6 D
Ǔ
MAX
3 V
10 mA ǒ1 * D
R +
C +
T
T
Ǔ
ǒR fǓ
T
(
)
MAX
(1)
Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended.
IR
RT
5
3 V
IC = IR
CT
6
CLK
ID = 10 mA
4
R
C
LEB
VTH
UDG-95102
图8-1. Oscillator
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10M
100
95
90
85
80
75
70
1M
100k
10k
10k
1k
100k
1k
10k
100k
Timing Resistance (Ω)
Timing Resistance (Ω)
图8-2. Oscillator Frequency vs Timing Resistance
图8-3. Maximum Duty Cycle vs Timing Resistance
8.2 Typical Application
The UC1825B-SP as a dual output controller that has integrated drivers for a push-pull topology and can be
used for half bridge and full bridge applications by using external high side drivers. While the UC1825B-SP
originally supported voltage mode topologies, the device with minimal external components can support current
mode topologies as well. The RAMP pin is used for the input current sense and the ILIM pin is used as the
current limit pin. External components are needed to ensure slope compensation is implemented.
图8-4. Typical Application
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表8-1. Design Parameters
PARAMETER
SPECIFICATIONS
Input Power Supply
Output Voltage
22 to 48 VDC
5 VDC
0 to 10 A
0.5 mA
25°C
Output Current
Output Current Pre-load
Operating Temperature
Switching Frequency of UC1825B-SP
Peak Input Current Limit
Bandwidth
215 kHz
7 A
~5 kHz
~80°
Phase Margin
8.2.1 System Design Theory
8.2.1.1 Switching Frequency
Choosing a switching frequency has a trade off between efficiency and bandwidth. Higher switching frequencies
will have larger bandwidth, but a lower efficiency than lower switching frequencies. A switching frequency of 215
kHz was chosen as a trade off between bandwidth and efficiency. Using 方程式 2 for the UC1825B-SP, RT and
CT were chosen to be 10 kΩand 680 pF, respectively.
1 . 46
f
≈
≈
(2)
(3)
osc
osc
R × C
t
t
1 . 46
×
f
= 215 kHz
680 pF
7 . 15 kΩ
8.2.1.2 Transformer
The transformer of the design consists of two major values, turns ratio and primary side inductance. There is no
minimum limit to the turns ratio of the transformer, just a maximum limit. The equation below will give the turns
ratio as a function of duty cycle which if the maximum duty cycle of the converter is used will give you a
maximum turns ratio. The UC1825B-SP design targeted a duty cycle of 30%. Since this design is for a dual
output device the duty cycle must stay below 50%. If both outputs were running above 50% duty cycle they
would have to overlap which is not possible for the topology. The equation of the turns ratio of the transformer is
方程式4.
2 × V
× D
lim
inMIN
+ V
N
=
=
(4)
(5)
psMAX
psMAX
V
out
Diode
2 × 22 V × 0 . 3
N
= 2 . 31
5
V + 0 . 7 V
Often the turns ratio will slightly change in design due to how the transformer is manufactured. For the
UC1825B-SP design a turns ratio of 2.2 was used. Another turns ratio that is important is the turns ratio of the
auxiliary winding. The auxiliary winding is found by figuring out what positive voltage is needed from the auxiliary
winding. Selecting this voltage lets one pick the turns ratio from the secondary to the auxiliary winding, which in
turn allows for the turns ratio from primary to auxiliary to be found. The equation for the turns ratio is 方程式6.
N
× V
aux
ps
V
N
=
=
(6)
(7)
as
as
inMIN
2 . 2 × 15
22
V
N
= 1 . 5
V
An auxiliary winding of 1.5 was used for the UC1825B-SP design. The primary inductance of the transformer is
found from picking an appropriate magnetizing current. The magnetizing current of the transformer is the amount
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of current drawn through the windings of the transformer when the output is open circuited. Decreasing the
magnetizing current will increase the inductance of the transformer, perhaps to unreasonable values. Increasing
the magnetizing current will cause efficiency to decrease. It is desirable to keep the magnetizing current low,
thus 6% was picked for the design value. The equation for the auxiliary winding turns ratio is 方程式8.
N
× V
inMAX
× D
× I
ps
MIN
out
L =
(8)
(9)
p
f
× %
osc
mag
2 . 2 × 48 × 0 . 13
215 kHz × 0 . 06 × 10
L =
= 106 μH
p
There are quite a few physical limitations when making transformers that will affect the inductance value. For the
UC1825B-SP design a primary inductance of 120 µH was used. The output inductor was then picked based on
the output inductor ripple current with 方程式10.
V
inMAX
− V − V
out
× D
MIN
f
N
ps
L
=
=
(10)
(11)
inductor
f
× I × %
out ripple
osc
48
2 . 2
215 kHz × 10 A × 0 . 45
V
− 0 . 7 V − 5
V × 0 . 13
L
= 2 . 14 μH
inductor
In the final design, a 2.2-μH inductor was used. The peak and primary currents of the transformer are also
generally useful for figuring out the physical structure of the transformer, so equations are listed below. Note
these equations are only true for continuous conduction mode. Peak currents are higher at the maximum input
voltage while the RMS current is highest at the minimum input voltage. These are also idea values and don't
take into account efficiency. Final designs needs to be optimized depending on the specific application
requirements. Equations that show how to calculate these for this design are below:
I
= I
+ 0 . 5 × %
× I
out
(12)
(13)
secMAX
secMAX
out
ripple
I
= 10 A
+
0 . 5 × 0 . 445 × 10 A
=
12 . 23 A
I
+ 0 . 5 × %
× I
mag
secMAX
out
I
=
=
(14)
(15)
priMAX
priMAX
N
ps
12 . 23 A + 0 . 5 × 0 . 06 × 10
A
I
= 5 . 7 A
2 . 2
V
inMIN
D
×
−
V
+ V
f
MAX
out
× L
inductor
N
ps
I
= I
+
(16)
secMAX VinMIN
out
2 × f
osc
22
2 . 2
V
0 . 285 ×
− 5 V + 0 . 7 V
I
I
I
= 10 A +
= 11 . 3 A
(17)
(18)
(19)
secMAX VinMIN
priMAX VinMIN
priMIN VinMIN
2 × 215 kHz × 2 . 2 μH
I
+ 0 . 5 × %
× I
secMAX VinMIN
mag out
=
=
N
ps
11 . 3
A
+ 0 . 5 × 0 . 06 × 10
2 . 2
= 5 . 27 A
V
inMIN
D
×
−
V
+ V
f
MAX
out
× L
inductor
N
ps
I
I
= I
−
(20)
(21)
secMIN VinMIN
out
2 × f
osc
22
2 . 2
V
0 . 285 ×
− 5 V + 0 . 7 V
= 10 A −
= 8 . 7 A
secMIN VinMIN
2 × 215 kHz × 2 . 2 μH
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I
− 0 . 5 × %
× I
mag out
secMIN VinMIN
I
I
=
=
(22)
(23)
priMIN VinMIN
N
ps
8 . 7
A
− 0 . 5 × 0 . 06 × 10
= 3 . 82 A
priMIN VinMIN
2 . 2
V
+ V × N
out
f
ps
t
t
=
=
(24)
(25)
(26)
(27)
onMAX
2 × f
× V
osc
inMIN
5
V + 0 . 7 V × 2 . 2
= 1 . 33 μs
V
onMAX
2 × 215 kHz × 22
I
− I
priMAX VinMIN
t
priMIN VinMIN
m
m
=
=
pri
onMAX
5 . 27 − 3 . 82
1 . 33 μs
= 1090226 A/s
pri
2
m
× t
onMAX
3
m
pri
2
pri
2
I
=
=
D
×
+
× I
× t
+ I
priMIN VinMIN
(28)
priRMS
priRMS
MIN
priMIN VinMIN
onMAX
2
2
1090226 A/s × 1 . 33 μs
1090226 A/s
I
0 . 285 ×
+
× 3 . 82 A × 1 . 33 μs + 3 . 82 A
= 2 . 27 A
(29)
3
2
8.2.1.3 RCD and Diode Clamp
For the UC1825BEVM-CVAL a resistor and capacitor in combination with a diode was used to clamp the voltage
of the switch node. The resistor and capacitor is generally a value that is found through testing, but starting
values can be obtained. To figure out the resistor and capacitor needed for the RCD clamp, one must first decide
how much the node is allowed to overshoot. The equation for finding the voltage of the clamp is 方程式30.
V
= K
× N × V
+ V
Diode
(30)
clamp
clamp
ps
out
Note that Kclamp is recommended to be 1.5 as this will allow for only around 50% overshoot. Knowing the
parasitic inductance of the transformer and how much the RCD clamp voltage is allowed to change over the
switching cycle, can allow one to figuring out starting values for the resistor and capacitor using 方程式 31 and
方程式32.
2
V
clamp
R
=
=
(31)
(32)
clamp
V
clamp
1
2
2
× L
× I
×
× f
osc
leakage
PriPeak
V
− N × V
+ V
Diode
clamp
ps out
V
clamp
× R
C
clamp
ΔV
clamp
× V
× f
clamp osc
clamp
A starting value of 10% is generally used for ΔVclamp
.
8.2.1.4 Output Diode
The voltage stress by the converter on the diode can be found with 方程式33.
V
inMAX
V
= V
+
(33)
(34)
DiodeStress
DiodeStress
out
N
ps
48
2 . 2
V
V
= 5 V +
= 26 . 8 V
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Note that any diode picked should have a voltage rating of well above this value as it does not include parasitic
spikes in the equation. The UC1825-SP diode was picked to have a voltage rating of 60 V.
8.2.1.5 Main Switching MOSFETs
Each switch applies the input voltage across the transformer and the voltage is then divided down by the turns
ratio and applied to the secondary side. Since the magnitude of the voltage across the windings is the input
voltage, when the switch is off the primary switching MOSFETs will see twice the input voltage as the voltage
stress plus some amount of ringing. This means the MOSFETs chosen for a push-pull topology should have a
voltage rating of about 2.5 to 3 times higher than the input voltage.
8.2.1.6 Output Filter and Capacitance
For most designs, a ripple voltage is picked and the output capacitance is figured out from that value. The output
capacitance value needs to be able to withstand a full output current step as well as keep the voltage ripple of
the output low. The UC1825B-SP design started similar to that using the equations for voltage ripple and load
step with 方程式35 and 方程式37.
I
× 2 × D
MAX
out
V
C
C
C
C
>
>
>
>
(35)
(36)
(37)
(38)
out
out
out
out
× f
Ripple
osc
10 A × 2 × 0 . 3
= 600 μF
50 mV × 200 kHz
ΔI
step
2π × ΔV
× f
out
co
10
A
= 1060 μ F
2π × 0 . 3 V × 5 kHz
A value of around 1145 µF was chosen to keep output voltage ripple low. Note that the output voltage ripple in
the design was further decreased by adding an output filter and by adding an inductor after a small portion of the
output capacitance. This was done in order to keep output voltage ripple as low as possible. Six ceramic
capacitors were picked to be placed before the output filter and then the large tantalum capacitors with some
small ceramics were added to be part of the output filter. The initial ceramics will help with the initial current
ripple, but have a very large output voltage ripple. This voltage ripple will be attenuated by the inductor and
capacitor combination placed between the ceramic capacitors and the output. The equations below allow for
finding the amount of attenuation that will come from a specific output filter inductance. An inductance of 500 nH
was chosen to attenuate the output voltage ripple. The value was chosen to put the resonant frequency pole well
before the switching frequency of the design as well as the zero from the ESR of the bulk capacitors to provide
more attenuation.
1
F
=
=
(39)
resonant
2π ×
L
× C
oBulk
Filter
1
F
F
F
= 6 . 7 kHz
(40)
(41)
(42)
(43)
(44)
resonant
2π × 0 . 5 nH × 1127 μF
1
Zero =
Zero =
2π × C
× ESR
oBulk
oBulk
1
= 15 . 69 kHz
Ω
2π × 1127 μF × 0 . 009
f
f
osc
osc
Attenuation
Attenuation
= 40 × log
− 20 × log
10
f
fsw
fsw
10
10
f
resonant
zero
200 kHz
6 . 7 kHz
200 kHz
15 . 69 kHz
= 40 × log
− 20 × log
= 36 . 88 dB
10
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Sometimes the output filter can cause peaking at high frequencies. This can be damped by adding a resistor in
parallel with the inductor which will decrease efficiency. For the UC1825B-SP design 0.5 Ω was used as a very
conservative value. The resistance needed to damp the peaking can be calculated using the following equations:
2 C
+ C
oCerm
× C
oBulk
ω =
(45)
(46)
o
L
× C
Filter
oCerm
oBulk
2 19 μF + 1127 μF
500 nH × 19 μF × 1127 μF
ω =
= 463 kHz
o
L
Filter
R
× L
Filter
×
C
+ C
oBulk
−
o
oCerm
+ C
oBulk
ω
o
R
R
=
=
(47)
(48)
Filter
Filter
R
× C
oCerm
o
− L
Filter
× C
oCerm
ω
o
500 nH
463 kHz
0 . 5 × 500 nH × 19 μF + 1127 μF
0 . 5 × 19 μF + 1127 μF
−
= 0 . 232 Ω
− 500 nH × 19 μF
463 kHz
8.2.1.7 Compensation
Type IIB compensation was picked for the topology, adding a pole and a zero to the frequency response. The
location of where the pole and zero should be placed will depend on the desired crossover frequency and the
ESR zero of the output capacitors. The zero in compensation should be placed at least a decade before the
crossover frequency for the maximum phase boost. Note that compensation values were picked with a crossover
frequency of 5 kHz in mind for this design. The pole from the compensation should be placed at the zero created
by the ESR of the output capacitor.
1
1
f
f
f
=
=
= 15 . 43 kHz
(49)
(50)
(51)
zESR
2π × C
× ESR
2π × 1146 μF × 0 . 009 Ω
out
1
1
=
=
=
= 15 . 23 kHz
pCOMP
zCOMP
2π × R
× C
2π × 4 . 75 kΩ × 2200 pF
COMP
HF
1
1
=
= 279 Hz
2π × R
× C
2π × 4 . 75 kΩ × 0 . 12 μF
COMP
COMP
The zero from compensation was placed well before the 500-Hz mark which is appropriate. The pole from
compensation was optimized while the circuit was tested and thus it was found that placing the pole a little bit
earlier smoothed out the frequency response.
8.2.1.8 Sense Resistor
The sense resistor is used to sense the ripple current from the transformer as well as shutdown the switching
cycle if the peak current of the converter is over the current limit set. The voltage threshold of the CS pin is
around 1 V and the shutdown current should be above the max current you expect. The max current limit will
depend on the specific design. The equation used to find the max current limit is 方程式52.
V
CS Tℎresℎold
R
=
(52)
(53)
cs
I
limit
1
V
R
=
= 0 . 15 Ω
CS
6 . 66
A
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8.3 Application Curves
VGS(Q1) Æ
IG(Q1) Æ
VGS(Q2) Æ
IG(Q2) Æ
2 ´ VCC
VDS(Q1)
VDS(Q2)
VCC
2 ´ VCC
VCC
VSAT
IPRI Æ
V
SEC Æ
VD1 Æ
IO
ID1
IO/2
Æ
ISEC
IO
Æ
图8-5. Basic Push-Pull Waveforms
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图8-6. Voltage Stress Across Main Switching MOSFETS Q1 and Q2
The test in 图8-6 was done with 48-V input and a 10-A output load.
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图8-7. Output Voltage Ripple With 48 VIN
Output voltage ripple test in 图8-7 was done with 48-V input and 10-A output current.
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图8-8. Full Output Voltage Transient With 48 VIN
Full step up transient in 图8-8 was done with 48-V input and output current was stepped from 0 A to 10 A.
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9 Power Supply Recommendations
The UC182B-SP is designed to operate from an input voltage supply range between 10 V and 30 V. This input
supply should be well regulated. If the input supply is located more than few inches from the UC1825B-SP
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A tantalum
capacitor with a value of 100 μF is a typical choice; however, this may vary depending upon the output power
being delivered.
The UC1825B-SP controller can be used to convert power efficiently using any of several standard topologies
such as push-pull, forward, half-bridge, or full bridge. Design tradeoffs of cost, size, and performance narrow the
field to the one that is most appropriate. For a typical application, such as in 节 8.2, push-pull converter topology
is highlighted.
10 Layout
10.1 Layout Guidelines
Always use a low EMI inductor with a ferrite-type closed core. Some examples would be toroid and encased E
core inductors. Open core can be used if they have low EMI characteristics and are located a bit more away
from the low power traces and components. Make the poles perpendicular to the PCB as well if using an open
core. Stick cores usually emit the most unwanted noise.
10.1.1 Feedback Traces
Run the feedback trace as far from the inductor and noisy power traces as possible. The feedback trace should
be as direct as possible and somewhat thick, which sometimes involves a trade-off, but keeping the feedback
trace away from inductor EMI and other noise sources is more critical. Run the feedback trace on the side of the
PCB opposite of the inductor with a ground plane separating the two.
10.1.2 Input/Output Capacitors
When using a low-value ceramic input filter capacitor, it must be located as close as possible to the VIN pin of
the IC. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner
voltage supply. Some designs require the use of a feed-forward capacitor connected from the output to the
feedback pin as well, usually for stability reasons. In this case, it must also be positioned as close as possible to
the IC. Using surface-mount capacitors also reduces lead length and lessens the chance of noise coupling into
the effective antenna created by through-hole components.
10.1.3 Compensation Components
External compensation components for stability must also be placed close to the IC. Surface mount components
are recommended here as well for the same reasons discussed for the filter capacitors. Locate the surface-
mount components away from the inductor.
10.1.4 Traces and Ground Planes
Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a
standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. The inductor,
output capacitors, and output diode must be as close as possible to each other. This helps reduce the EMI
radiated by the power traces due to the high switching currents through them. This will also reduce lead
inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce
voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) must
be connected close together directly to a ground plane. It would also be a good idea to have a ground plane on
both sides of the PCB. This will reduce noise as well by reducing ground loop errors as well as by absorbing
more of the EMI radiated by the inductor. For multilayer boards with more than two layers, a ground plane can be
used to separate the power plane (where the power traces and components are) and the signal plane (where the
feedback, compensation, and components are) for improved performance. On multilayer boards, the use of vias
will be required to connect traces and different planes. It is good practice to use one standard via per
200 mA of current if the trace must conduct a significant amount of current from one plane to the other. Arrange
the components so that the switching current loops curl in the same direction. Due to the way switching
regulators operate, there are two power states. One state when the switch is on and one state when the switch is
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off. During each state there will be a current loop made by the power components that are currently conducting.
Place the power components so that during each of the two states the current loop is conducting in the same
direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces
radiated EMI.
10.1.5 Ground Planes
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct
operation of the chip. A ground plane must be employed. A unique section of the ground plane must be
designated for high di/dt currents associated with the output stages. This point is the power ground to which the
PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a
single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC
must be bypassed directly to power ground with a good high frequency capacitor. The sources of the power
MOSFET must connect to power ground as must the return connection for input power to the system and the
bulk input capacitor. The output must be clamped with a high current Schottky diode to both VCC and PGND.
Nothing else should be connected to power ground.
VREF must be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor.
TI recommends low ESR/ESL ceramic 1-mF capacitors for both VCC and VREF. All analog circuitry must
likewise be bypassed to the signal ground plane. See 图10-1.
10.2 Layout Example
VIN
VC
VCC
To Analog Circuitry
+
Power Stage
VCC
OUT
+
CBULK
CT
VREF
GND
PGND
RTN
Signal Ground
Power Ground
UDG-95115
图10-1. Ground Planes Diagram
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ZHCSJJ9A –APRIL 2019 –REVISED DECEMBER 2020
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Unitrode Application Note U-93, SLUA075
• Unitrode Application Note U-97, SLUA101
• Unitrode Application Note U-110, SLUA053
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDD5
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SLUSDD5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962R8768106V9A
5962R8768106VYC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HKT
0
25
1
RoHS & Green
Call TI
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
16
RoHS-Exempt
& Green
Call TI
5962R8768106VY
C
UC1825BHKT-SP
UC1825BHKT/EM
ACTIVE
CFP
HKT
16
1
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
25 to 25
UC1825BHKT/EM
EVAL ONLY
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962R8768106VYC
UC1825BHKT/EM
HKT
HKT
CFP (HSL)
CFP (HSL)
16
16
1
1
506.98
506.98
26.16
26.16
6220
6220
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HKT0016A
CFP - 2.13 mm max height
S
C
A
L
E
0
.
7
0
0
CERAMIC DUAL FLATPACK
7.442
7.137
B
A
14X 1.27
16
1
10.414
9.652
2X 8.89
8
9
0.482
16X
0.382
0.2
C A
B
0.177
0.097
C
2.13 MAX
5.36
5.06
0.432
0.254
25.400
24.384
(5.21)
9
8
(10.03)
1
16
PIN 1 ID
4221021/B 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. Lid and cavity are electrically isolated
4. The terminals are gold plated.
5. Falls within MIL-STD-1835 CDFP-F11A.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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