66AK2G12ABY60 [TI]

高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核 | ABY | 625 | 0 to 90;


型号：	66AK2G12ABY60
厂家：	TEXAS INSTRUMENTS
描述：	高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核 \| ABY \| 625 \| 0 to 90 以太网：16GBASE-T PC 外围集成电路
文件：	总232页 (文件大小：2869K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

66AK2G1x 多核 DSP+Arm KeyStone II 片上系统 (SoC)

1 器件概述

1.1 特性

处理器内核：

• Arm^®Cortex^®-A15 微处理器单元 (Arm A15) 子系

统，频率高达 1000MHz

– 一个具有两个 MII 端口的以太网 MII_RT 模块，

可配置为与每个 PRU 连接；支持多种工业通信

协议

– 支持完全实现 Armv7-A 架构指令集

– 集成式 SIMDv2（ Arm^®Neon™技术）和 VFPv4

（矢量浮点）

– 用于管理和生成工业以太网功能的工业以太网外

设 (IEP)

– 内置的通用异步接收器和发送器 (UART)

16550，具有专用的 192MHz 时钟，支持

12Mbps 的速率 PROFIBUS^®

– 内置的工业以太网 64 位计时器

– 内置的增强型捕捉模块 (eCAP)

存储器子系统：

– 32KB 的 L1 程序存储器

– 32KB 的 L1 数据存储器

– 512KB 的 L2 存储器

– 用于 L1 数据存储器的错误修正码 (ECC) 保护、

用于 L2 存储器的 ECC

– 用于 L1 程序存储器的奇偶校验保护

– 全局时基计数器 (GTC)

• 多核共享存储器控制器 (MSMC)，具有 1024KB 的

共享 L2 RAM

– 用于为 Arm A15 内部计时器提供时基的 64 位

自由运行计数器

– 提供与内部共享 SRAM 和 DDR EMIF 的高性能

互连，以实现 Arm A15 和 C66x 访问

– 支持 Arm I/O 一致性，其中 Arm A15 与访问

MSMC-SRAM 或 DDR EMIF 的其他系统器件保

持缓存一致

– 符合用于通用计时器的 Armv7 MPCore 架构

• 频率高达 1000MHz 的 C66x 定点和浮点 VLIW

DSP 子系统

– 目标代码与 C67x+ 和 C64x+ 内核完全兼容

– 32KB 的 L1 程序存储器

– 32KB 的 L1 数据存储器

– 1024KB 的 L2，可配置为 L2 RAM 或缓存

– 用于 L1 程序存储器的错误检测

– 用于 L1 数据存储器的 ECC

– 用于 L2 数据存储器的 ECC

工业子系统：

– 支持 SRAM 上的 ECC

• 高达 36 位 DDR 外部存储器接口 (EMIF)

– 支持高达 1066MT/s 速率的 DDR3L

– 支持 4GB 存储器地址范围

– 支持 32 位 SDRAM 数据总线（具有 4 位 ECC

功能）

– 支持 16 位和 32 位 SDRAM 数据总线（不具有

ECC 功能）

• 多达两个可编程实时单元和工业通信子系统 (PRU-

ICSS)，每个子系统支持：

• 通用存储器控制器 (GPMC)

– 灵活的 8 位和 16 位异步存储器接口，具有多达

四个片选

– 两个具有增强型乘法器和累加器的可编程实时单

元 (PRU)，每个 PRU 支持：

– 支持 NOR、Muxed-NOR、SRAM

– 支持具有以下模式的通用存储器端口扩展：

– 异步读取和写入访问

– 16KB 的程序存储器（具有 ECC 功能）

– 8KB 的数据存储器（具有 ECC 功能）

– CRC32 和 CRC16 硬件加速器

– 20 个增强型 GPIO

– 异步读取页面访问（4、8、16 字）

– 同步读取和写入访问

– 串行捕捉单元 (SCU)，支持直接连接、16 位

并行捕捉、28 位移位、MII_RT、EnDat 2.2

协议和 Σ-Δ 解调

– 不具有折返功能的同步读取脉冲访问（4、8、

16 字）

网络子系统 (NSS)：

– 便笺本和 XFR 直接连接

• 以太网 MAC 子系统 (EMAC)

– 单端口千兆位以太网：RMII、MII、RGMII

– 支持 10、100、1000Mbps 全双工

– 支持 10、100Mbps 半双工

– 64KB 的通用存储器（具有 ECC 功能）

– 支持以太网音频视频桥接 (eAVB)

– 最大帧大小 2016 字节（采用 VLAN 时为 2020

字节）

– 8 个优先级 QOS 支持 (802.1p)

– IEEE 1588v2（2008 附件 D、附件 E 和

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SPRSP07

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

附件 F），有助于实现音频视频桥接 802.1AS 精

密时间协议

• 自动感应/检测输入采样频率

• 采样时钟抖动衰减

– 具有时间戳支持的 CPTS 模块，适用于 IEEE

• 16、18、20、24 位数据输入/输出

• 8kHz 至 216kHz 的音频采样率

• 16:1 至 1:16 的输入/输出采样比

• 主模式，其中多个 ASRC 块针对输入或输出使用相

同的计时回路

1588v2

– DSCP 优先级映射（IPv4 和 IPv6）

– 用于 PHY 管理的 MDIO 模块

– 增强型统计信息收集

• Navigator 子系统 (NAVSS)

• 线性相位 FIR 滤波器

• 可控软静音

• 每个输入和输出时钟区具有独立的时钟发生器以及

速率和时间戳发生器

– 内置的数据包 DMA 控制器，用于实现优化的网

络处理

– 内置的队列管理器，用于实现优化的网络处理

– 支持多达 128 个队列

– 内部队列 RAM 中支持 2048 个缓冲区

• 加密引擎 (SA) 支持：

• 每个通道和组具有单独的输入和输出 DMA 事件

高速串行接口：

• 具有集成 PHY 的 PCI Express ^®2.0 端口：

– 与第 2 代兼容的单通道端口

– 根复合体 (RC) 和端点 (EP) 模式

• 多达 2 个具有集成 PHY 的 USB 2.0 高速双角色端

口，支持：

– 用于 AES、DES、3DES、SHA1、MD5、

SHA2-224 和 SHA2-256 运算的加密函数库

– 通过硬件内核支持的块数据加密

– 具有 128、192 和 256 位密钥支持的 AES

– 具有 1、2 或 3 个不同密钥支持的 DES 和

– 双角色器件 (DRD) 功能，使用：

3DES

– USB 2.0 外设（或器件），具有

– 可编程模式控制引擎 (MCE)

– 椭圆曲线加密公钥加速器 (PKA)

– 基于椭圆曲线迪菲-赫尔曼 (ECDH) 的密钥交换和

数字签名 (ECDSA) 应用

– 针对 SHA1、MD5、SHA2-224 和 SHA2-256 的

验证

HS (480Mbps) 和 FS (12Mbps) 的速度

– USB 2.0 主机，具有 HS (480Mbps)、

FS (12Mbps) 和 LS (1.5Mbps) 的速度

– USB 2.0 静态外设和静态主机操作

– 具有以下特性的 xHCI 控制器：

– 主机模式下与 xHCI 规范（版本 1.1）兼容

– 所有传输模式（控制、批量、中断和等时）

– 15 个发送 (TX) 端点、15 个接收 (RX) 端点

(EP) 以及 1 个双向 EP0 端点

闪存媒体接口：

– 通过硬件内核进行的带密钥的 HMAC 运算

– 真随机数发生器 (TRNG)

显示子系统：

• 支持一个具有回路中调节功能和颜色空间的视频管

线

• QSPI™具有 XIP 以及多达四个片选，支持：

• 转换和背景颜色叠加

– 用于执行闪存数据传输和执行闪存 (XIP) 中的代

码的存储器映射直接操作模式

• 输入数据格式：BITMAP、RGB16、RGB24、

RGB32、ARGB16、ARGB32、YUV420、YUV422

和 RGB565-A8

• 支持的显示接口：

– MIPI^®DPI 2.0 并行接口

– 高达 QVGA (30fps) 的 RFBI (MIPI-DBI 2.0)

– BT.656 4:2:2

– 高达 1920 × 1080 (30fps) 的 BT.1120 4:2:2

• 回路中调节功能

• LCD 显示接口支持：

– 有源矩阵 (TFT)

– 支持高达 96MHz 的频率

– 具有 ECC 功能的内部 SRAM 缓冲区

– 高速读取数据采集机制

• 2 个多媒体卡 (MMC) 和安全数字 (SD) 端口

– 支持符合 SDA3.00 标准的 JEDEC JESD84

v4.5-A441 和 SD3.0 物理层

– MMC0 支持 3.3V I/O，用于：

– SD DS 和 HS 模式

– eMMC 模式 HS-SDR

（频率高达 48MHz）

– MMC1 支持 eMMC 的 1.8V I/O 模式，包括 HS-

SDR 和 DDR（频率高达 48MHz，具有 4 位和 8

位总线宽度）

– 无源矩阵 (STN)

– 灰度

– TDM

音频外设：

• 三个多通道音频串行端口 (McASP) 外设

– 高达 50MHz 的发送和接收时钟

– 交流偏置控制

– 抖动

– CPR

– 每个 McASP 具有两个独立的时钟区和独立的发

送和接收时钟

异步音频采样率转换器 (ASRC)

• 具有 140dB 信噪比 (SNR) 的高性能异步采样率转

换器

– 分别为 McASP0、McASP1 和 McASP2 提供多

达 16、10、6 个串行数据引脚

• 多达 8 个视频流（16 个音频通道）

器件概述

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

– 支持 TDM、I2S 和类似的格式

– 支持 DIT 模式

– 2 个片选

• 3 个 UART 接口

– 用于优化的系统通信流量的内置 FIFO 缓冲区

• 多通道缓冲串行端口 (McBSP)

– 高达 50MHz 的发送和接收时钟

– 2 个时钟区和 2 个串行数据引脚

– 支持 TDM、I2S 和类似的格式

汽车外设：

– 所有 UART 都与 16C750 兼容并以高达 3M 的波

特率运行

– UART0 支持 8 个具有完全调制解调器控制功能

的引脚，支持 DSR、DTR、DCD 和 RI 信号

– UART1 和 UART2 是 4 引脚接口

• 通用 I/O (GPIO)

– 与其他接口多路复用多达 212 个 GPIO

– 可配置为中断引脚

计时器和其他模块：

• 两个控制器局域网 (CAN) 端口

– 支持 CAN v2.0 A、B 部分 (ISO 11898-1) 协议

– 高达 1Mbps 的比特率

– 双时钟源

– 针对消息 RAM 的 ECC 保护

• 一条媒体本地总线 (MLB)

• 7 个 64 位计时器：

– 2 个专用于 Arm A15 和 DSP 内核的 64 位计时

器（每个内核 1 个计时器）

– 看门狗和通用 (GP)

– 4 个 64 位计时器共用于一般用途

– 每个 64 位计时器可配置为 2 个独立的 32 位计时

器

– 支持 3 引脚（高达 MOST50，1024 × Fs）和 6

引脚（高达 MOST150，2048 × Fs）版本的

MediaLB^®物理层规范 v4.2

– 支持在 64 个逻辑通道上进行所有类型的数据传

输（同步流、等时、异步数据包、控制消息）

– 1 个专用于 PMMC 的 64 位计时器

– 2 个计时器输入/输出引脚对

• 处理器间通信：

– 支持三线制 MOST 150 协议

实时控制接口：

– 消息管理器可促进对 PMMC 的多处理器访问：

• 6 个增强型高分辨率脉宽调制 (eHRPWM) 模块，每

个计数器支持：

– 提供硬件加速，以将消息推入逻辑队列/从逻辑

队列弹出消息

– 可进行周期和频率控制的专用 16 位时基

– 2 个具有单边操作模式的独立 PWM 输出

– 2 个具有双边对称操作模式的独立 PWM 输出

– 1 个具有双边非对称操作模式的独立 PWM 输出

• 2 个 32 位增强型捕捉模块 (eCAP)：

– 支持多达 64 个队列和 128 个消息

– 具有多达 64 个独立信号量和 16 个主器件（器件

内核）的信号量模块

• 具有 128 (2 × 64) 个通道和

1024 (2 × 512) 个 PaRAM 条目的 EDMA

Keystone II 片上系统 (SoC) 架构：

• 安全性

– 支持 1 个捕捉输入或 1 个辅助 PWM 输出配置选

项

– 4 事件时间戳寄存器（每个 32 位）

– 4 个事件中的任何一个上具有中断

• 3 个 32 位增强型正交脉冲编码器模块 (eQEP)，每

个模块支持：

– 支持通用 (GP) 和高安全性 (HS) 器件

– 支持安全引导

– 支持客户辅助密钥

– 用于客户密钥的 4KB 一次性可编程 (OTP) ROM

• 电源管理

– 正交解码

– 用于位置测量的位置计数器和控制单元

– 用于速度和频率测量的单位时基

通用连接：

– 集成式电源管理微控制器 (PMMC) 技术

• 支持通过 UART、I²C、SPI、GPMC、SD 或

eMMC、USB 器件固件升级 v1.1、 PCIe^®和以太网

接口进行主引导

• 3 个内部集成电路 (I²C) 端口，每个端口支持：

– 标准（高达 100kHz）和

快速（高达 400kHz）模式

– 7 位寻址模式

• 具有集成式 Arm CoreSight™支持和跟踪功能的

Keystone II 调试架构

工作温度 (T_J)：

– 支持高达 4Mb 的 EEPROM 大小

• 4 个串行外设接口 (SPI)，每个接口支持：

• –40°C 至 125°C（汽车）

• –40°C 至 105°C（扩展）

• 0°C 至 90°C（商用）

– 主模式下的运行频率高达 50MHz，从模式下的运

行频率高达 25MHz

1.2 应用

•

工业通信和控制

汽车音频放大器

家用音频

•

电源保护

其他嵌入式系统

专业音频

器件概述

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

1.3 说明

66AK2G1x 是基于 TI 经实践检验的 Keystone II (KS2) 架构的异构多核片上系统 (SoC) 器件系列。这些器件

适用于需要 DSP 和 Arm 性能的应用，集成了高速外设和存储器接口、针对网络和加密功能的硬件加速以及

高级操作系统 (HLOS) 支持。

66AK2G1x 与基于 KS2 的现有 SoC 器件类似，使 DSP 和 Arm 内核能够控制系统中的所有存储器和外设。

此架构有助于最大限度地提高软件灵活性，可以实现以 DSP 或 Arm 为中心的系统设计。

66AK2G1x 通过在处理器内核、共享存储器、模块中的嵌入式存储器和外部存储器接口中广泛实现错误修正

码 (ECC)，显著提高了器件的可靠性。完整的软错误率 (SER) 和通电时间 (POH) 分析显示，指定的

66AK2G1x 器件满足各种工业和汽车要求。

66AK2G1x

开发平台附带新的处理器 SDK，该开发平台使主线开源 Linux、CCS 6.x、各种独立于操作系统的器件驱动

程序以及支持在各个处理器内核上进行无缝任务管理的 TI-RTOS 实现了前所未有的易用性。此外，该器件

还采用包含 TI 和 Arm 最新创新成果（例如系统跟踪和 Arm CoreSight 组件的无缝集成）的先进调试和跟

踪技术。

还可以实现引导，以实现防克隆和非法软件更新保护。有关安全引导的更多信息，请与 TI 销售代表联系。

器件信息⁽¹⁾

封装

器件编号

封装尺寸

66AK2G12

FCBGA (625)

21.0mm × 21.0mm

(1) 有关更多信息，请参阅第 9 节，机械封装和可订购产品信息。

器件概述

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

1.4 功能方框图

图 1-1 是器件的方框图。

66AK2G1x

Memory Subsystem

1x Arm®

1x C66x DSP

MSMC

1MB RAM w/ ECC

Cortex®–A15

EMIF 36-bits

DDR3L w/ ECC

GPMC

512KB L2 w/ ECC

1MB L2 w/ ECC

Algorithm Accelerators and Application-specific Subsystems

7x Timers

64-bits

Network Subsystem

Industrial Subsystem

EMAC

2x PRU-ICSS

Message Manager

eAVB/1588v2

RGMII/RMII/MII

Display Subsystem

EDMA

NAVSS

1x Video Pipeline

Blend/Scale/CSC

PMMC

Queue Manager

PKTDMA

LCD

DPI

Crypto Engine

Semaphore

ASRC

TeraNet

High-Speed

Serial Interfaces

Automotive Interfaces

2x DCAN

Control Interfaces General Connectivity

PCIe®

Single Lane

6x ePWM

2x eCAP

3x eQEP

2x GPIO

3x UART

4x SPI

Gen 2

MediaLB®

MOST150

2x USB 2.0

Dual Role

+ PHY

Audio Peripherals

3x McASP

3x I2C

Media & Data Storage

McBSP

QSPI

2x MMC/SD

intro_001

图 1-1. 功能方框图

器件概述

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

内容

器件概述.................................................... 1

1.1 特性 ................................................... 1

1.2 应用 ................................................... 3

1.3 说明 ................................................... 4

1.4 功能方框图 ........................................... 5

修订历史记录............................................... 7

Device Comparison ..................................... 8

3.1 Related Products ..................................... 9

Terminal Configuration and Functions ............ 10

4.1 Pin Diagram ......................................... 10

4.2 Pin Attributes ........................................ 10

4.3 Signal Descriptions.................................. 42

4.4 Pin Multiplexing ..................................... 72

4.5 Connections for Unused Pins ....................... 83

Specifications ........................................... 85

5.1 Absolute Maximum Ratings......................... 85

5.2 ESD Ratings ........................................ 86

5.3 Power-On-Hour (POH) Limits^(1)(2)(3)................ 87

5.4 Recommended Operating Conditions............... 87

5.5 Operating Performance Points...................... 88

5.6 Power Consumption Summary...................... 88

5.7 Electrical Characteristics ............................ 88

6.2 Functional Block Diagram ......................... 172

6.3 Arm A15 ........................................... 173

6.4 C66x DSP Subsystem ............................. 174

6.5 C66x Cache Subsystem ........................... 175

6.6 PRU-ICSS.......................................... 175

6.7 Memory Subsystem................................ 177

6.8 Interprocessor Communication .................... 179

6.9 EDMA .............................................. 181

6.10 Peripherals ......................................... 182

Applications, Implementation, and Layout ...... 199

7.1

7.2

7.3

DDR3L Board Design and Layout Guidelines ..... 199

High Speed Differential Signal Routing Guidance. 219

Power Distribution Network (PDN) Implementation

Guidance........................................... 219

7.4 Single-Ended Interfaces ........................... 221

7.5 Clock Routing Guidelines .......................... 221

Device and Documentation Support.............. 223

8.1 Device Nomenclature.............................. 223

8.2 Tools and Software ................................ 224

8.3 Documentation Support............................ 224

8.4

Receiving Notification of Documentation Updates. 225

8.5 静电放电警告....................................... 225

8.6 Community Resources............................. 225

8.7 商标 ................................................ 225

8.8 Glossary............................................ 225

5.8

Thermal Resistance Characteristics for ABY

Package ............................................. 93

5.9 Timing and Switching Characteristics............... 94

Detailed Description.................................. 171

6.1 Overview ........................................... 171

Mechanical Packaging and Orderable

Information............................................. 226

9.1 Packaging Information ............................. 226

内容

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

2 修订历史记录

Changes from July 15, 2018 to March 6, 2019 (from D Revision (July 2018) to E Revision)

Page

•

从产品说明书特性列表中与 MMC0 相关的“- eMMC 模式 HS-SDR 和 DDR（频率高达 48MHz）”项目符号中删除

了“和 DDR”，因为 3.3V MMC0 接口不支持 DDR。.............................................................................. 2

Updated Community Resources section........................................................................................ 225

Updated Trademarks section .................................................................................................... 225

Updated 节 9, Mechanical Packaging and Orderable Information .......................................................... 226

•

修订历史记录

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

3 Device Comparison

表 3-1 lists the features of the 66AK2G1x devices.

表 3-1. Device Comparison

FEATURES

PROCESSORS AND ACCELERATORS

REFERENCE NAME

66AK2G12

Speed Grades

See 表 5-1

Yes

Arm Cortex-A15 Microprocessor Subsystem

C66x VLIW Digital Signal Processor

Power Management Micro Controller

Display Subsystem

Arm A15

C66x

Yes

PMMC

DSS

Yes

PROGRAM AND DATA STORAGE

Up to 1MB (On-Chip Shared

SRAM With ECC)

Multicore Shared Memory Controller

MSMC

General-Purpose Memory Controller

DDR External Memory Interface

GPMC

Up to 1GB

Up to 4GB (32-Bit data)

Yes

EMIF

SECDED/ECC

PERIPHERALS

Dual Controller Area Network Interface

Enhanced Direct Memory Access

DCAN

EDMA

EMAC

NAVSS

Yes

RMII, MII, RGMII With eAVB

Network Subsystem

PKTDMA and QM

Yes

General-Purpose I/O

GPIO

Up to 212

Inter-Integrated Circuit Interface

Message Manager

I2C

MSGMGR

SEM

Yes

Semaphore

Media Local Bus Subsystem

Multichannel Buffered Serial Port

Audio Asynchronous Sample Rate Converter

MLB

Yes (3-pin or 6-pin Modes)

Yes

McBSP

ASRC

McASP0

McASP1

McASP2

MMC0

Yes

16 Serializers

10 Serializers

6 Serializers

Multichannel Audio Serial Port

eMMC, SD (3.3 V) -

8-bits

MultiMedia Card, Secure Digital Interface (MMC/SD)

PCI Express 2.0 Port with Integrated PHY

MMC1

eMMC (1.8 V) - 8-bits

PCIESS

PRU-ICSS

Yes (Single-Lane Mode)

Programmable Real-Time Unit Subsystem and Industrial Communication

Subsystem

Serial Peripheral Interface

SPI

Yes

Quad SPI

QSPI

General-Purpose Timers

TIMER_1 to TIMER_4

TIMER_5

TIMER_0

TIMER_6

ePWM

General-Purpose or Watchdog Timer Dedicated to Arm

General-Purpose or Watchdog Timer Dedicated to DSP

Dedicated to PMMC Timer

Enhanced PWM Module

Enhanced Capture Module

eCAP

Enhanced Quadrature Encoder Pulse Module

Universal Asynchronous Receiver and Transmitter

eQEP

UART

Device Comparison

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 3-1. Device Comparison (continued)

FEATURES

REFERENCE NAME

66AK2G12

Universal Serial Bus (USB2.0) High Speed Dual-Role-Device (DRD) Ports

with PHY

USB

3.1 Related Products

Digital Signal Processors DSPs bring computing performance, real-time processing, and power

efficiency to diverse applications ranging from sensors to servers. Our product range spans

high-performance real-time needs, to power-efficient processors with industry-leading lowest

active power needs. Choose one of the following scalable solutions.

C6000 Multicore DSP + Arm SoC TI DSP + Arm processors include a wide range of device choices that

deliver the highest performance at the lowest power levels and costs. TI DSP + Arm

solutions range from single core Arm9 + C674x DSP to quad-core Arm Cortex-A15 + 8xC66x

DSP cores.

66AK2x Multicore DSP + Arm Processors

Companion Products for 66AKG0x/66AKG1x Review products that are frequently purchased or used in

conjunction with this product.

Reference Designs for 66AKG0x/66AKG1x TI Designs Reference Design Library is a robust reference

design library spanning analog, embedded processor and connectivity. Created by TI experts

to help you jump-start your system design, all TI Designs include schematic or block

diagrams, BOMs and design files to speed your time to market. Search and download

designs at ti.com/tidesigns.

Device Comparison

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

4 Terminal Configuration and Functions

注

The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An

attempt is made to use 'ball' only when referring to the physical package.

4.1 Pin Diagram

图 4-1 shows the ball locations for the 625 plastic ball grid array (FCBGA) package that are used in

conjunction with 表 4-1 through 表 4-27 to locate signal names and ball grid numbers.

图 4-1. ABY FCBGA-N625 Package (Bottom View)

4.2 Pin Attributes

表 4-1 describes the terminal characteristics and the signals multiplexed on each ball.

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

C17

A17

AUDOSC_IN

1.8 V

DVDD18

Analog

AUDOSC_OUT

AVDDA_ARMPLL

AVDDA_DDRPLL

AVDDA_DSSPLL

AVDDA_ICSSPLL

AVDDA_MAINPLL

AVDDA_NSSPLL

AVDDA_UARTPLL

BOOTCOMPLETE

CPTS_REFCLK_N

CPTS_REFCLK_P

CVDD

DVDD18

AVDDA_ARMPLL

AVDDA_DDRPLL

AVDDA_DSSPLL

AVDDA_ICSSPLL

AVDDA_MAINPLL

AVDDA_NSSPLL

AVDDA_UARTPLL

BOOTCOMPLETE

CPTS_REFCLK_N

CPTS_REFCLK_P

PWR

W20

N20

M19

G14

G10

3.3 V

1.8 V

DVDD33

DVDD18

Yes

LVCMOS

LVDS

PU/PD

L21

K21

LVDS

J10, J14, J16, K11, CVDD

K13, K15, K17, K9,

L10, L12, L14, L16,

L18, M11, M13,

PWR

M15, M17, M9,

N10, N12, N14,

N16, P11, P13,

P15, P17, P9, R10,

R12, R14, R16,

R18, R8, T11, T15,

T17, T9, U16

J12, M5, N18, N8, CVDD1

T13

CVDD1

PWR

DCAN0_RX

GPIO1_57

DCAN0_TX

GPIO1_56

DDR3_CASn

3.3 V

1.35 V

DVDD33

Yes

LVCMOS

SSTL

PU/PD

IOZ

DCAN0_TX

DVDD33

AC13

DDR3_CASn

OFF

DRIVE 1

(OFF)

DVDD_DDR

Y11

DDR3_CBDQM

DDR3_CBDQS_N

DDR3_CBDQS_P

DDR3_RASn

DDR3_CBDQM

DDR3_CBDQS_N

DDR3_CBDQS_P

DDR3_RASn

IOZ

OFF

1.35 V

DVDD_DDR

SSTL

PU/PD

AD12

AE12

AE13

OFF

DRIVE 1

(OFF)

Y18

DDR3_RESETn

DDR3_VREFSSTL

DDR3_WEn

DDR3_RESETn

DDR3_VREFSSTL

DDR3_WEn

OFF

DRIVE 0

(OFF)

1.35 V

DVDD_DDR

SSTL

Analog

SSTL

0.5 x

DVDD_DDR

Y13

DRIVE 1

(OFF)

1.35 V

PU/PD

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

AC15

Y15

DDR3_A00

DDR3_A01

DDR3_A02

DDR3_A03

DDR3_A04

DDR3_A05

DDR3_A06

DDR3_A07

DDR3_A08

DDR3_A09

DDR3_A10

DDR3_A11

DDR3_A12

DDR3_A13

DDR3_A14

DDR3_A15

DDR3_BA0

DDR3_BA1

DDR3_BA2

OFF

DRIVE 0

(OFF)

1.35 V

DVDD_DDR

SSTL

PU/PD

DDR3_A01

DDR3_A02

DDR3_A03

DDR3_A04

DDR3_A05

DDR3_A06

DDR3_A07

DDR3_A08

DDR3_A09

DDR3_A10

DDR3_A11

DDR3_A12

DDR3_A13

DDR3_A14

DDR3_A15

DDR3_BA0

DDR3_BA1

DDR3_BA2

DRIVE 0

(OFF)

DVDD_DDR

AC16

AA15

AB16

AE17

AC14

AB15

AC17

AB17

AB14

AA16

AA17

AA12

Y17

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

Y16

DRIVE 0

(OFF)

AA14

AB13

AD17

DRIVE 0

(OFF)

DRIVE 0

(OFF)

DRIVE 0

(OFF)

AA11

AB11

AC11

AC12

AD13

DDR3_CB00

DDR3_CB01

DDR3_CB02

DDR3_CB03

DDR3_CEn0

DDR3_CB00

DDR3_CB01

DDR3_CB02

DDR3_CB03

DDR3_CEn0

IOZ

OFF

1.35 V

DVDD_DDR

SSTL

PU/PD

DRIVE 1

(OFF)

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

AB18

DDR3_CKE0

OFF

DRIVE 0

(OFF)

1.35 V

DVDD_DDR

SSTL

PU/PD

AD15

AD16

AE15

AE16

AD2

DDR3_CLKOUT_N0

DDR3_CLKOUT_N1

DDR3_CLKOUT_P0

DDR3_CLKOUT_P1

DDR3_D00

DDR3_D01

DDR3_D02

DDR3_D03

DDR3_D04

DDR3_D05

DDR3_D06

DDR3_D07

DDR3_D08

DDR3_D09

DDR3_D10

DDR3_D11

DDR3_D12

DDR3_D13

DDR3_D14

DDR3_D15

DDR3_D16

DDR3_D17

DDR3_D18

DDR3_D19

DDR3_D20

DDR3_D21

DDR3_D22

DDR3_D23

DDR3_D24

DDR3_D25

DDR3_D26

DDR3_D27

DDR3_D28

DDR3_D29

DDR3_D30

DDR3_CLKOUT_N0

DDR3_CLKOUT_N1

DDR3_CLKOUT_P0

DDR3_CLKOUT_P1

DDR3_D00

DDR3_D01

DDR3_D02

DDR3_D03

DDR3_D04

DDR3_D05

DDR3_D06

DDR3_D07

DDR3_D08

DDR3_D09

DDR3_D10

DDR3_D11

DDR3_D12

DDR3_D13

DDR3_D14

DDR3_D15

DDR3_D16

DDR3_D17

DDR3_D18

DDR3_D19

DDR3_D20

DDR3_D21

DDR3_D22

DDR3_D23

DDR3_D24

DDR3_D25

DDR3_D26

DDR3_D27

DDR3_D28

DDR3_D29

DDR3_D30

OFF

1.35 V

DVDD_DDR

SSTL

PU/PD

IOZ

OFF

AC3

AC2

AE3

AA4

AD3

AB3

AA6

AC5

AB6

AC4

AB5

AB7

AB8

AC7

AA7

AA8

AC6

AE7

AD7

AA10

AE10

AD10

AC10

AC9

AB10

AB9

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

DDR3_D31

IOZ

OFF

1.35 V

DVDD_DDR

SSTL

PU/PD

AB4

AA5

AC8

AA9

AE2

AD1

AE4

AD4

AD6

AE6

AD9

AE9

AA13

DDR3_DQM0

DVDD_DDR

DDR3_DQM1

DDR3_DQM2

DDR3_DQM3

DDR3_DQS0_N

DDR3_DQS0_P

DDR3_DQS1_N

DDR3_DQS1_P

DDR3_DQS2_N

DDR3_DQS2_P

DDR3_DQS3_N

DDR3_DQS3_P

DDR3_ODT0

DDR3_DQS0_N

DDR3_DQS0_P

DDR3_DQS1_N

DDR3_DQS1_P

DDR3_DQS2_N

DDR3_DQS2_P

DDR3_DQS3_N

DDR3_DQS3_P

DDR3_ODT0

IOZ

OFF

DRIVE 0

(OFF)

W12

DDR3_RZQ0

DDR3_RZQ1

DDR_CLK_N

DDR_CLK_P

DSS_DATA0

DDR3_RZQ0

DDR3_RZQ1

DDR_CLK_N

DDR_CLK_P

DSS_DATA0

GPMC_A1

DVDD_DDR

DVDD18

Analog

LVDS

AD24

AE24

V22

1.8 V

3.3 V

DVDD18

LVDS

IOZ

DVDD33

Yes

LVCMOS

PU/PD

GPIO0_53

DSS_RFBI_DATA0

DSS_DATA1

GPMC_A2

U21

DSS_DATA1

DSS_DATA2

3.3 V

DVDD33

Yes

LVCMOS

eQEP2_S

GPIO0_52

DSS_RFBI_DATA1

DSS_DATA2

GPMC_A3

W22

OFF

3.3 V

eQEP2_I

GPIO0_51

DSS_RFBI_DATA2

MAINPLL_OD_SEL

Bootstrap

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

V23

DSS_DATA3

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPMC_A4

eQEP2_B

GPIO0_50

IOZ

DSS_RFBI_DATA3

BOOT_RSVD

DSS_DATA4

GPMC_A5

Bootstrap

U23

DSS_DATA4

3.3 V

DVDD33

Yes

LVCMOS

eQEP2_A

GPIO0_49

IOZ

DSS_RFBI_DATA4

NODDR

Bootstrap

V24

T21

DSS_DATA5

DSS_DATA6

DSS_DATA5

GPMC_A6

IOZ

3.3 V

DVDD33

Yes

LVCMOS

eQEP1_S

GPIO0_48

DSS_RFBI_DATA5

DSS_DATA6

GPMC_A7

OFF

3.3 V

eQEP1_I

GPIO0_47

EMU19

DSS_RFBI_DATA6

DSS_DATA7

GPMC_A8

U22

DSS_DATA7

OFF

3.3 V

DVDD33

Yes

LVCMOS

eQEP1_B

GPIO0_46

IOZ

EMU18

DSS_RFBI_DATA7

DSS_DATA8

GPMC_A9

T22

DSS_DATA8

OFF

3.3 V

DVDD33

Yes

LVCMOS

eQEP1_A

GPIO0_45

IOZ

EMU17

DSS_RFBI_DATA8

BOOTMODE15

Bootstrap

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

R21

DSS_DATA9

OFF

3.3 V

DVDD33

Yes

LVCMOS

GPMC_A10

eQEP0_S

IOZ

GPIO0_44

EMU16

DSS_RFBI_DATA9

BOOTMODE14

DSS_DATA10

GPMC_A11

eQEP0_I

Bootstrap

U24

V25

T24

P21

DSS_DATA10

DSS_DATA11

DSS_DATA12

DSS_DATA13

IOZ

DVDD33

Yes

GPIO0_43

EMU15

DSS_RFBI_DATA10

BOOTMODE13

DSS_DATA11

GPMC_A12

eQEP0_B

Bootstrap

GPIO0_42

IOZ

EMU14

DSS_RFBI_DATA11

BOOTMODE12

DSS_DATA12

GPMC_A13

eQEP0_A

Bootstrap

GPIO0_41

IOZ

EMU13

DSS_RFBI_DATA12

BOOTMODE11

DSS_DATA13

GPMC_A14

eHRPWM_TZn2

GPIO0_40

Bootstrap

IOZ

EMU12

DSS_RFBI_DATA13

BOOTMODE10

Bootstrap

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

U25

DSS_DATA14

OFF

3.3 V

DVDD33

Yes

LVCMOS

GPMC_A15

IOZ

eHRPWM2_B

GPIO0_39

EMU11

DSS_RFBI_DATA14

BOOTMODE09

DSS_DATA15

GPMC_A16

Bootstrap

R22

P23

R24

N22

DSS_DATA15

DSS_DATA16

DSS_DATA17

DSS_DATA18

IOZ

DVDD33

Yes

LVCMOS

eHRPWM2_A

GPIO0_38

EMU10

DSS_RFBI_DATA15

BOOTMODE08

DSS_DATA16

GPMC_A17

Bootstrap

eHRPWM_TZn1

GPIO0_37

IOZ

EMU09

DSS_RFBI_CSn0

BOOTMODE07

DSS_DATA17

GPMC_A18

Bootstrap

IOZ

eHRPWM1_B

GPIO0_36

EMU08

DSS_RFBI_CSn1

BOOTMODE06

DSS_DATA18

GPMC_A19

Bootstrap

IOZ

eHRPWM1_A

GPIO0_35

EMU07

DSS_RFBI_HSYNC1

BOOTMODE05

Bootstrap

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

T25

DSS_DATA19

OFF

3.3 V

DVDD33

Yes

LVCMOS

GPMC_A20

IOZ

eHRPWM0_SYNCO

GPIO0_34

EMU06

DSS_RFBI_TEVSYNC1

BOOTMODE04

DSS_DATA20

GPMC_A21

Bootstrap

N24

P24

P25

N23

M25

DSS_DATA20

DSS_DATA21

DSS_DATA22

DSS_DATA23

DSS_DE

OFF

3.3 V

DVDD33

Yes

LVCMOS

eHRPWM0_SYNCI

GPIO0_33

IOZ

EMU05

BOOTMODE03

DSS_DATA21

GPMC_A22

Bootstrap

eHRPWM_TZn0

GPIO0_32

IOZ

EMU04

BOOTMODE02

DSS_DATA22

GPMC_A23

Bootstrap

IOZ

eHRPWM0_B

GPIO0_31

EMU03

BOOTMODE01

DSS_DATA23

GPMC_A24

Bootstrap

IOZ

eHRPWM0_A

GPIO0_30

EMU02

BOOTMODE00

DSS_DE

Bootstrap

IOZ

PU/PD

GPMC_A0

PR1_EDIO_OUTVALID

GPIO0_57

DSS_RFBI_WEn

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

L25

DSS_FID

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_EDIO_OUTVALID

GPIO0_58

IOZ

DSS_RFBI_A0

P22

N25

R25

DSS_HSYNC

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPMC_A26

PR1_eCAP0_eCAP_SYNCIN

GPIO0_55

IOZ

DSS_RFBI_HSYNC0

DSS_PCLK

IOZ

3.3 V

PU/PD

GPMC_A27

PR1_eCAP0_eCAP_SYNCOUT

GPIO0_56

DSS_RFBI_REn

DSS_VSYNC

3.3 V

GPMC_A25

PR1_eCAP0_eCAP_CAPIN_APWM_O

GPIO0_54

DSS_RFBI_TEVSYNC0

DVDD18

F17, F19, G6, H5, DVDD18

J6, K19, L20, L6,

M7, U18, U6, V19,

PWR

AA23, E23, F11,

F15, F21, F7, G12,

G16, G20, H11,

H13, H15, H9, J20,

P19, P7, R20, R6,

T19, T23, T7, U20,

V21

DVDD33

PWR

G18, H17

DVDD33_USB

DVDD_DDR

PWR

AD11, AD18, AD5, DVDD_DDR

AE14, AE8, U10,

U12, U14, U8, V11,

V13, V15, V17, V7,

W16, W18

W10, W14, W8

A23

DVDD_DDRDLL

eHRPWM3_A

DVDD_DDRDLL

PR0_EDIO_DATA3

GPIO0_73

PWR

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

eHRPWM3_A

IOZ

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

B22

eHRPWM3_B

PR0_EDIO_DATA2

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO0_74

IOZ

eHRPWM3_B

PR0_EDIO_DATA1

GPIO0_75

C22

D23

eHRPWM3_SYNCI

eHRPWM3_SYNCO

DVDD33

Yes

eHRPWM3_SYNCI

PR0_EDIO_DATA0

GPIO0_76

IOZ

eHRPWM3_SYNCO

EMU00

M22

L22

EMU00

IOZ

OFF

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

EMU01

AC21

GPMC_AD0

GPIO0_00

AE20

AD22

AD20

AE21

AE22

AC20

AD21

AE23

AB20

AA20

AD23

AA21

GPMC_AD1

GPMC_AD2

GPMC_AD3

GPMC_AD4

GPMC_AD5

GPMC_AD6

GPMC_AD7

GPMC_AD8

GPMC_AD9

GPMC_AD10

GPMC_AD11

GPMC_AD12

GPMC_AD1

GPIO0_01

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPMC_AD2

GPIO0_02

GPMC_AD3

GPIO0_03

GPMC_AD4

GPIO0_04

GPMC_AD5

GPIO0_05

GPMC_AD6

GPIO0_06

GPMC_AD7

GPIO0_07

GPMC_AD8

GPIO0_08

GPMC_AD9

GPIO0_09

GPMC_AD10

GPIO0_10

GPMC_AD11

GPIO0_11

GPMC_AD12

GPIO0_12

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

BALL NUMBER [1]

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

TYPE [12]

LVCMOS

STATE [7]

AB21

AB22

AA22

AC23

AC24

AB24

AB23

AB25

W24

GPMC_AD13

IOZ

3.3 V

DVDD33

Yes

PU/PD

GPIO0_13

IOZ

GPMC_AD14

GPMC_AD15

GPMC_ADVn_ALE

GPMC_BEn0_CLE

GPMC_BEn1

GPMC_AD14

GPIO0_14

DVDD33

Yes

GPMC_AD15

GPIO0_15

GPMC_ADVn_ALE

GPIO0_17

GPMC_BEn0_CLE

GPIO0_20

GPMC_BEn1

GPIO0_21

GPMC_CLK

GPIO0_16

GPMC_CSn0

GPMC_CSn1

GPMC_CSn0

GPIO0_26

GPMC_CSn1

MLB_DAT

GPIO0_27

W23

Y25

GPMC_CSn2

GPMC_CSn3

GPMC_DIR

GPMC_CSn2

TIMI1

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO0_28

IOZ

GPMC_CSn3

TIMO1

GPIO0_29

AA25

GPMC_DIR

MLB_SIG

GPIO0_25

AC22

Y24

GPMC_OEn_REn

GPMC_WAIT0

GPMC_WAIT1

GPMC_OEn_REn

GPIO0_18

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPMC_WAIT0

GPIO0_22

IOZ

AA24

GPMC_WAIT1

MLB_CLK

GPIO0_23

IOZ

Y22

GPMC_WEn

GPIO0_19

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

W25

GPMC_WPn

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO0_24

I2C0_SCL

IOZ

IOD

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

OFF

3.3 V

DVDD33

I2C OPEN

DRAIN

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

IOD

I2C OPEN

DRAIN

I2C OPEN

DRAIN

I2C OPEN

DRAIN

I2C OPEN

DRAIN

I2C OPEN

DRAIN

J8, L8

H19, J18

LDO_PCIE_CAP

LDO_USB_CAP

LRESETn

LDO_PCIE_CAP

LDO_USB_CAP

LRESETn

CAP

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

LRESETNMIENn

MDIO_CLK

LRESETNMIENn

MDIO_CLK

GPIO0_98

IOZ

MDIO_DATA

MII_COL

MDIO_DATA

GPIO0_97

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

B25

G22

MII_COL

GPIO0_83

IOZ

MII_CRS

RMII_CRS_DV

GPIO0_84

IOZ

A22

B24

MII_RXCLK

MII_RXD0

MII_RXCLK

RGMII_RXC

GPIO0_72

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

MII_RXD0

RGMII_RXD0

RMII_RXD0

GPIO0_80

IOZ

C23

MII_RXD1

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

RGMII_RXD1

RMII_RXD1

GPIO0_79

IOZ

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

B23

MII_RXD2

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

RGMII_RXD2

GPIO0_78

IOZ

F22

A24

F23

C25

G23

MII_RXD3

MII_RXDV

MII_RXER

MII_TXCLK

MII_TXD0

MII_RXD3

DVDD33

Yes

LVCMOS

RGMII_RXD3

GPIO0_77

IOZ

MII_RXDV

RGMII_RXCTL

GPIO0_81

IOZ

MII_RXER

RMII_RXER

GPIO0_82

IOZ

MII_TXCLK

RGMII_TXC

GPIO0_85

IOZ

MII_TXD0

RGMII_TXD0

RMII_TXD0

GPIO0_94

G24

MII_TXD1

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

RGMII_TXD1

RMII_TXD1

GPIO0_93

G25

D25

H25

MII_TXD2

MII_TXD3

MII_TXEN

MII_TXD2

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

RGMII_TXD2

GPIO0_92

MII_TXD3

RGMII_TXD3

GPIO0_91

MII_TXEN

RGMII_TXCTL

RMII_TXEN

GPIO0_95

H24

MII_TXER

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_eCAP0_eCAP_SYNCIN

GPIO0_96

IOZ

eHRPWM_TZn3

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

L23

M23

K22

K23

M24

L24

MLBP_CLK_N

1.8 V

DVDD18

MLB LVDS

LVCMOS

MLBP_CLK_P

MLBP_DAT_N

MLBP_DAT_P

MLBP_SIG_N

MLBP_SIG_P

MMC1_CLK

MLBP_CLK_P

MLBP_DAT_N

MLBP_DAT_P

MLBP_SIG_N

MLBP_SIG_P

MMC1_CLK

GPIO0_67

DVDD18

IOZ

Yes

PU/PD

MMC1_CMD

MMC1_POW

MMC1_SDCD

MMC1_SDWP

MMC1_DAT0

MMC1_DAT1

MMC1_DAT2

MMC1_DAT3

MMC1_DAT4

MMC1_DAT5

MMC1_DAT6

MMC1_DAT7

MMC1_CMD

GPIO0_68

1.8 V

DVDD18

Yes

LVCMOS

MMC1_POW

GPIO0_71

MMC1_SDCD

GPIO0_69

IOZ

MMC1_SDWP

GPIO0_70

IOZ

MMC1_DAT0

GPIO0_66

MMC1_DAT1

GPIO0_65

MMC1_DAT2

GPIO0_64

MMC1_DAT3

GPIO0_63

MMC1_DAT4

GPIO0_62

MMC1_DAT5

GPIO0_61

MMC1_DAT6

GPIO0_60

MMC1_DAT7

GPIO0_59

NMIn

3.3 V

1.8 V

DVDD33

LVCMOS

LVDS

OBSCLK_N

OBSCLK_P

OBSPLL_LOCK

PCIE_CLK_N

OBSCLK_N

OBSCLK_P

OBSPLL_LOCK

PCIE_CLK_N

DVDD18

LVDS

DVDD18

Yes

LVCMOS

LVDS

PU/PD

DVDD18 / VDDAHV

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

BALL NUMBER [1]

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

PCIE_CLK_P

1.8 V

DVDD18 / VDDAHV

n/a

LVDS

Analog

CML

PCIE_REFRES

PCIE_RXN0

PCIE_RXP0

PCIE_TXN0

PCIE_TXP0

PORn

PCIE_REFRES

PCIE_RXN0

DVDD18 / VDDAHV

DVDD33

PCIE_RXP0

CML

PCIE_TXN0

CML

AA3

A10

PCIE_TXP0

CML

PORn

3.3 V

Yes

LVCMOS

PR0_MDIO_DATA

GPIO1_04

IOZ

DVDD33

Yes

PU/PD

MCASP0_AXR3

PR0_MDIO_MDCLK

GPIO1_05

C10

E18

D18

PR0_MDIO_MDCLK

PR1_MDIO_DATA

PR1_MDIO_MDCLK

PR0_PRU0_GPO0

3.3 V

DVDD33

LVCMOS

MCASP0_AXR4

PR1_MDIO_DATA

GPIO1_46

eCAP0_IN_APWM0_OUT

PR1_MDIO_MDCLK

GPIO1_47

eCAP1_IN_APWM1_OUT

PR0_PRU0_GPO0

PR0_PRU0_GPI0

GPIO0_108

IOZ

MCASP2_AXR0

PR0_PRU0_GPO1

PR0_PRU0_GPI1

GPIO0_109

PR0_PRU0_GPO1

PR0_PRU0_GPO2

PR0_PRU0_GPO3

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

MCASP2_AXR1

PR0_PRU0_GPO2

PR0_PRU0_GPI2

GPIO0_110

IOZ

MCASP2_AXR2

PR0_PRU0_GPO3

PR0_PRU0_GPI3

GPIO0_111

IOZ

MCASP2_AXR3

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

PR0_PRU0_GPO4

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_PRU0_GPI4

GPIO0_112

IOZ

MCASP2_AXR4

PR0_PRU0_GPO5

PR0_PRU0_GPI5

GPIO0_113

PR0_PRU0_GPO5

PR0_PRU0_GPO6

PR0_PRU0_GPO7

PR0_PRU0_GPO8

PR0_PRU0_GPO9

DVDD33

Yes

IOZ

MCASP2_AXR5

PR0_PRU0_GPO6

PR0_PRU0_GPI6

GPIO0_114

IOZ

MCASP2_ACLKR

PR0_PRU0_GPO7

PR0_PRU0_GPI7

GPIO0_115

IOZ

MCASP2_AFSR

PR0_PRU0_GPO8

PR0_PRU0_GPI8

GPIO0_116

IOZ

MCASP2_AHCLKR

PR0_PRU0_GPO9

PR0_PRU0_GPI9

XREFCLK

GPIO0_117

IOZ

MCASP2_AMUTE

PR0_PRU0_GPO10

PR0_PRU0_GPI10

GPIO0_118

PR0_PRU0_GPO10

PR0_PRU0_GPO11

PR0_PRU0_GPO12

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

MCASP2_AFSX

PR0_PRU0_GPO11

PR0_PRU0_GPI11

GPIO0_119

IOZ

MCASP2_AHCLKX

PR0_PRU0_GPO12

PR0_PRU0_GPI12

GPIO0_120

IOZ

MCASP2_ACLKX

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

PR0_PRU0_GPO13

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_PRU0_GPI13

GPIO0_121

IOZ

MCASP1_ACLKR

PR0_PRU0_GPO14

PR0_PRU0_GPI14

GPIO0_122

PR0_PRU0_GPO14

PR0_PRU0_GPO15

PR0_PRU0_GPO16

PR0_PRU0_GPO17

DVDD33

Yes

LVCMOS

IOZ

MCASP1_AFSR

PR0_PRU0_GPO15

PR0_PRU0_GPI15

GPIO0_123

IOZ

MCASP1_AHCLKR

PR0_PRU0_GPO16

PR0_PRU0_GPI16

GPIO0_124

IOZ

MCASP1_ACLKX

PR0_PRU0_GPO17

PR0_PRU0_GPI17

PR1_UART0_RXD

GPIO0_125

IOZ

MCASP1_AFSX

PR0_PRU0_GPO18

PR0_PRU0_GPI18

PR0_EDC_LATCH0_IN

GPIO0_126

PR0_PRU0_GPO18

PR0_PRU0_GPO19

PR0_PRU1_GPO0

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

MCASP1_AHCLKX

PR0_PRU0_GPO19

PR0_PRU0_GPI19

PR0_EDC_SYNC0_OUT

GPIO0_127

IOZ

MCASP1_AMUTE

PR0_PRU1_GPO0

PR0_PRU1_GPI0

GPIO0_128

IOZ

MCASP1_AXR0

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

PR0_PRU1_GPO1

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_PRU1_GPI1

GPIO0_129

IOZ

MCASP1_AXR1

PR0_PRU1_GPO2

PR0_PRU1_GPI2

GPIO0_130

PR0_PRU1_GPO2

PR0_PRU1_GPO3

PR0_PRU1_GPO4

PR0_PRU1_GPO5

PR0_PRU1_GPO6

PR0_PRU1_GPO7

PR0_PRU1_GPO8

PR0_PRU1_GPO9

DVDD33

Yes

IOZ

MCASP1_AXR2

PR0_PRU1_GPO3

PR0_PRU1_GPI3

GPIO0_131

IOZ

MCASP1_AXR3

PR0_PRU1_GPO4

PR0_PRU1_GPI4

GPIO0_132

IOZ

MCASP1_AXR4

PR0_PRU1_GPO5

PR0_PRU1_GPI5

GPIO0_133

IOZ

MCASP1_AXR5

PR0_PRU1_GPO6

PR0_PRU1_GPI6

GPIO0_134

IOZ

MCASP1_AXR6

PR0_PRU1_GPO7

PR0_PRU1_GPI7

GPIO0_135

IOZ

MCASP1_AXR7

PR0_PRU1_GPO8

PR0_PRU1_GPI8

GPIO0_136

IOZ

MCASP1_AXR8

PR0_PRU1_GPO9

PR0_PRU1_GPI9

GPIO0_137

IOZ

MCASP1_AXR9

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

PR0_PRU1_GPO10

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_PRU1_GPI10

GPIO0_138

IOZ

MCASP0_AMUTE

PR0_PRU1_GPO11

PR0_PRU1_GPI11

GPIO0_139

PR0_PRU1_GPO11

PR0_PRU1_GPO12

PR0_PRU1_GPO13

PR0_PRU1_GPO14

PR0_PRU1_GPO15

PR0_PRU1_GPO16

PR0_PRU1_GPO17

DVDD33

Yes

LVCMOS

IOZ

MCASP0_ACLKR

PR0_PRU1_GPO12

PR0_PRU1_GPI12

GPIO0_140

IOZ

MCASP0_AFSR

PR0_PRU1_GPO13

PR0_PRU1_GPI13

GPIO0_141

IOZ

MCASP0_AHCLKR

PR0_PRU1_GPO14

PR0_PRU1_GPI14

GPIO0_142

IOZ

MCASP0_ACLKX

PR0_PRU1_GPO15

PR0_PRU1_GPI15

GPIO0_143

IOZ

MCASP0_AFSX

PR0_PRU1_GPO16

PR0_PRU1_GPI16

GPIO1_00

IOZ

MCASP0_AHCLKX

PR0_PRU1_GPO17

PR0_PRU1_GPI17

PR1_UART0_TXD

GPIO1_01

IOZ

MCASP0_AXR0

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

PR0_PRU1_GPO18

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR0_PRU1_GPI18

PR0_EDC_LATCH1_IN

GPIO1_02

IOZ

MCASP0_AXR1

PR0_PRU1_GPO19

PR0_PRU1_GPI19

PR0_EDC_SYNC1_OUT

GPIO1_03

B10

PR0_PRU1_GPO19

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

MCASP0_AXR2

PR1_PRU0_GPO0

PR1_PRU0_GPI0

GPIO1_06

E10

D10

F10

C11

D11

PR1_PRU0_GPO0

PR1_PRU0_GPO1

PR1_PRU0_GPO2

PR1_PRU0_GPO3

PR1_PRU0_GPO4

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

MCASP0_AXR5

PR1_PRU0_GPO1

PR1_PRU0_GPI1

GPIO1_07

IOZ

MCASP0_AXR6

PR1_PRU0_GPO2

PR1_PRU0_GPI2

GPIO1_08

IOZ

MCASP0_AXR7

PR1_PRU0_GPO3

PR1_PRU0_GPI3

GPIO1_09

IOZ

MCASP0_AXR8

PR1_PRU0_GPO4

PR1_PRU0_GPI4

MMC0_POW

IOZ

GPIO1_10

MCASP0_AXR9

PR1_PRU0_GPO5

PR1_PRU0_GPI5

MMC0_SDWP

E11

PR1_PRU0_GPO5

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO1_11

IOZ

MCASP0_AXR10

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

F12

PR1_PRU0_GPO6

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR1_PRU0_GPI6

MMC0_SDCD

GPIO1_12

IOZ

MCASP0_AXR11

PR1_PRU0_GPO7

PR1_PRU0_GPI7

MMC0_DAT7

E12

C12

B11

B12

PR1_PRU0_GPO7

PR1_PRU0_GPO8

PR1_PRU0_GPO9

PR1_PRU0_GPO10

DVDD33

Yes

LVCMOS

IOZ

GPIO1_13

MCASP0_AXR12

PR1_PRU0_GPO8

PR1_PRU0_GPI8

MMC0_DAT6

IOZ

GPIO1_14

MCASP0_AXR13

PR1_PRU0_GPO9

PR1_PRU0_GPI9

MMC0_DAT5

IOZ

GPIO1_15

MCASP0_AXR14

PR1_PRU0_GPO10

PR1_PRU0_GPI10

MMC0_DAT4

IOZ

GPIO1_16

MCASP0_AXR15

PR1_PRU0_GPO11

PR1_PRU0_GPI11

MMC0_DAT3

A12

A11

A13

PR1_PRU0_GPO11

PR1_PRU0_GPO12

PR1_PRU0_GPO13

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

GPIO1_17

PR1_PRU0_GPO12

PR1_PRU0_GPI12

MMC0_DAT2

IOZ

GPIO1_18

PR1_PRU0_GPO13

PR1_PRU0_GPI13

MMC0_DAT1

IOZ

GPIO1_19

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

B13

PR1_PRU0_GPO14

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR1_PRU0_GPI14

MMC0_DAT0

IOZ

GPIO1_20

F13

C13

E13

PR1_PRU0_GPO15

PR1_PRU0_GPO16

PR1_PRU0_GPO17

PR1_PRU0_GPO15

PR1_PRU0_GPI15

MMC0_CLK

DVDD33

Yes

IOZ

GPIO1_21

PR1_PRU0_GPO16

PR1_PRU0_GPI16

MMC0_CMD

IOZ

GPIO1_22

PR1_PRU0_GPO17

PR1_PRU0_GPI17

GPIO1_23

IOZ

eHRPWM_TZn4

eHRPWM_SOCA

PR1_PRU0_GPO18

PR1_PRU0_GPI18

PR1_EDC_LATCH0_IN

GPIO1_24

D12

D13

PR1_PRU0_GPO18

PR1_PRU0_GPO19

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

eHRPWM4_A

PR1_PRU0_GPO19

PR1_PRU0_GPI19

PR1_EDC_SYNC0_OUT

GPIO1_25

3.3 V

IOZ

eHRPWM4_B

A14

B14

C14

PR1_PRU1_GPO0

PR1_PRU1_GPO1

PR1_PRU1_GPO2

PR1_PRU1_GPO0

PR1_PRU1_GPI0

GPIO1_26

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

PR1_PRU1_GPO1

PR1_PRU1_GPI1

GPIO1_27

IOZ

PR1_PRU1_GPO2

PR1_PRU1_GPI2

GPIO1_28

IOZ

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

E14

PR1_PRU1_GPO3

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR1_PRU1_GPI3

GPIO1_29

IOZ

D14

A15

F14

B15

C15

D15

PR1_PRU1_GPO4

PR1_PRU1_GPO5

PR1_PRU1_GPO6

PR1_PRU1_GPO7

PR1_PRU1_GPO8

PR1_PRU1_GPO9

PR1_PRU1_GPO4

PR1_PRU1_GPI4

GPIO1_30

DVDD33

Yes

LVCMOS

IOZ

PR1_PRU1_GPO5

PR1_PRU1_GPI5

GPIO1_31

IOZ

PR1_PRU1_GPO6

PR1_PRU1_GPI6

GPIO1_32

IOZ

PR1_PRU1_GPO7

PR1_PRU1_GPI7

GPIO1_33

IOZ

PR1_PRU1_GPO8

PR1_PRU1_GPI8

GPIO1_34

IOZ

PR1_PRU1_GPO9

PR1_PRU1_GPI9

MCBSP_DR

GPIO1_35

IOZ

A16

E15

B16

PR1_PRU1_GPO10

PR1_PRU1_GPO11

PR1_PRU1_GPO12

PR1_PRU1_GPO10

PR1_PRU1_GPI10

MCBSP_DX

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

GPIO1_36

PR1_PRU1_GPO11

PR1_PRU1_GPI11

MCBSP_FSX

IOZ

GPIO1_37

PR1_PRU1_GPO12

PR1_PRU1_GPI12

MCBSP_CLKX

GPIO1_38

IOZ

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

C16

PR1_PRU1_GPO13

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

PR1_PRU1_GPI13

MCBSP_FSR

IOZ

GPIO1_39

D17

PR1_PRU1_GPO14

PR1_PRU1_GPI14

MCBSP_CLKR

GPIO1_40

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

C18

D16

F16

PR1_PRU1_GPO15

PR1_PRU1_GPO16

PR1_PRU1_GPO17

PR1_PRU1_GPO15

PR1_PRU1_GPI15

GPIO1_41

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

PR1_PRU1_GPO16

PR1_PRU1_GPI16

GPIO1_42

IOZ

PR1_PRU1_GPO17

PR1_PRU1_GPI17

GPIO1_43

IOZ

eHRPWM_TZn5

eHRPWM_SOCB

PR1_PRU1_GPO18

PR1_PRU1_GPI18

PR1_EDC_LATCH1_IN

GPIO1_44

E17

E16

PR1_PRU1_GPO18

PR1_PRU1_GPO19

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

eHRPWM5_A

PR1_PRU1_GPO19

PR1_PRU1_GPI19

PR1_EDC_SYNC1_OUT

GPIO1_45

3.3 V

IOZ

eHRPWM5_B

K25

J25

H23

QSPI_CLK

QSPI_CSn0

QSPI_CSn1

QSPI_CLK

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO1_58

QSPI_CSn0

GPIO1_64

QSPI_CSn1

CLKOUT

GPIO1_65

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

H22

QSPI_CSn2

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

DCAN1_TX

PR1_UART0_CTSN

GPIO1_66

IOZ

USB0_EXT_TRIGGER

QSPI_CSn3

DCAN1_RX

PR1_UART0_RTSN

GPIO1_67

H21

QSPI_CSn3

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

USB1_EXT_TRIGGER

QSPI_D0

J23

J22

J21

J24

K24

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_RCLK

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO1_60

QSPI_D1

GPIO1_61

QSPI_D2

GPIO1_62

QSPI_D3

GPIO1_63

QSPI_RCLK

GPIO1_59

IOZ

RESETFULLn

RESETn

RESETFULLn

RESETn

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

RESETSTATn

DRIVE 0

(OFF)

DRIVE 0

(OFF)

D24

RMII_REFCLK

PR0_eCAP0_eCAP_SYNCOUT

SPI0_CLK

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

SPI0_CLK

SPI0_SIMO

SPI0_SOMI

SPI1_CLK

SPI1_SIMO

SPI1_SOMI

SPI2_CLK

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

SPI0_SIMO

SPI0_SOMI

SPI1_CLK

SPI1_SIMO

SPI1_SOMI

SPI2_CLK

GPIO0_103

SPI2_SIMO

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO0_105

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

SPI2_SOMI

GPIO0_104

SPI3_CLK

IOZ

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

E24

SPI3_CLK

SPI3_SIMO

SPI3_SOMI

DVDD33

Yes

PR0_UART0_TXD

GPIO0_88

F24

F25

SPI3_SIMO

PR0_UART0_RTSN

GPIO0_90

3.3 V

LVCMOS

PU/PD

SPI3_SOMI

PR0_UART0_CTSN

GPIO0_89

IOZ

SPI0_SCSn0

SPI0_SCSn1

SPI0_SCSn0

SPI0_SCSn1

GPIO0_99

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

SPI1_SCSn0

SPI1_SCSn1

SPI1_SCSn0

SPI1_SCSn1

GPIO0_100

SPI2_SCSn0

GPIO0_101

SPI2_SCSn1

GPIO0_102

SPI3_SCSn0

PR0_eCAP0_eCAP_CAPIN_APWM_O

GPIO0_86

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

SPI2_SCSn0

SPI2_SCSn1

SPI3_SCSn0

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

C24

E25

SPI3_SCSn1

PR0_UART0_RXD

GPIO0_87

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

M21

SYSCLKOUT

SYSCLKSEL

SYSCLK_N

SYSCLK_P

SYSOSC_IN

SYSOSC_OUT

TCK

SYSCLKOUT

SYSCLKSEL

SYSCLK_N

3.3 V

1.8 V

3.3 V

DVDD33

DVDD18

DVDD33

Yes

LVCMOS

LVDS

AC25

AD25

AC19

AE19

SYSCLK_P

LVDS

SYSOSC_IN

SYSOSC_OUT

TCK

Analog

Yes

LVCMOS

PU/PD

TDI

TDO

OFF

TMS

Yes

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

BALL NUMBER [1]

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

TRSTn

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

UART0_CTSn

TIMI0

DVDD33

Yes

PU/PD

GPIO0_106

IOZ

UART0_RTSn

TIMO0

3.3 V

DVDD33

Yes

LVCMOS

GPIO0_107

UART0_RXD

UART0_TXD

UART1_CTSn

UART0_RXD

UART0_TXD

UART1_CTSn

GPIO1_50

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

IOZ

UART1_RTSn

UART1_RXD

UART1_TXD

UART2_CTSn

UART1_RTSn

GPIO1_51

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

UART1_RXD

GPIO1_48

IOZ

UART1_TXD

GPIO1_49

D22

UART2_CTSn

PR1_EDIO_DATA1

UART0_DTRn

GPIO1_54

IOZ

CPTS_TS_SYNC

UART2_RTSn

PR1_EDIO_DATA0

UART0_RIN

C21

E21

D21

UART2_RTSn

UART2_RXD

UART2_TXD

3.3 V

DVDD33

Yes

LVCMOS

PU/PD

GPIO1_55

IOZ

CPTS_TS_COMP

UART2_RXD

PR1_EDIO_DATA3

UART0_DCDn

GPIO1_52

IOZ

CPTS_HW1_TSPUSH

UART2_TXD

PR1_EDIO_DATA2

UART0_DSRn

GPIO1_53

IOZ

CPTS_HW2_TSPUSH

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

B18

A18

USB0_DM

USB0_DP

DVDD18 /

DVDD33_USB

USB0_PHY

USB0_DP

DVDD18 /

DVDD33_USB

E19

A19

USB0_DRVVBUS

USB0_ID

USB0_DRVVBUS

USB0_ID

3.3 V

DVDD33_USB

Yes

LVCMOS

PU/PD

DVDD18 /

USB0_PHY

DVDD33_USB

C19

USB0_TXRTUNE_RKELVIN

DVDD18 /

USB0_PHY

DVDD33_USB

B19

D19

USB0_VBUS

USB0_XO

USB0_VBUS

USB0_XO

5.0 V

1.8 V

n/a - Fail-safe

USB0_PHY

DVDD18 /

DVDD33_USB

A20

B20

USB1_DM

USB1_DP

USB1_DM

USB1_DP

DVDD18 /

DVDD33_USB

USB1_PHY

DVDD18 /

DVDD33_USB

B21

E20

USB1_DRVVBUS

USB1_ID

USB1_DRVVBUS

USB1_ID

3.3 V

DVDD33_USB

Yes

LVCMOS

PU/PD

DVDD18 /

USB1_PHY

DVDD33_USB

D20

USB1_TXRTUNE_RKELVIN

DVDD18 /

USB1_PHY

DVDD33_USB

A21

C20

USB1_VBUS

USB1_XO

USB1_VBUS

USB1_XO

5.0 V

1.8 V

n/a - Fail-safe

USB1_PHY

DVDD18 /

DVDD33_USB

VDDAHV

VPP

VDDAHV

VPP

PWR

Y21

W21

VPP2

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

BALL NUMBER [1]

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-1. Pin Attributes (continued)

BALL

RESET

REL.

MUXMODE

[8]

BALL

RESET

REL.

BALL

RESET

STATE [6]

PULL

MUXMODE

[4]

I/O VOLTAGE

VALUE [9]

BUFFER

TYPE [12]

BALL NAME [2]

SIGNAL NAME [3]

TYPE [5]

POWER [10]

HYS [11]

UP/DOWN DSIS [14]

TYPE [13]

STATE [7]

A1, A25, AD14,

VSS

GND

AD8, AE1, AE11,

AE18, AE25, AE5,

C1, E2, E22, F1,

F20, F3, F6, F8,

G11, G13, G15,

G17, G19, G21, G7,

G9, H10, H12, H14,

H16, H18, H20, H6,

H8, J1, J11, J13,

J15, J17, J19, J7,

J9, K10, K12, K14,

K16, K18, K20, K6,

K8, L11, L13, L15,

L17, L19, L7, L9,

M10, M12, M14,

M16, M18, M20,

M6, M8, N11, N13,

N15, N17, N19,

N21, N7, N9, P10,

P12, P14, P16,

P18, P20, P6, P8,

R11, R13, R15,

R17, R19, R23, R7,

R9, T10, T12, T14,

T16, T18, T20, T6,

T8, U11, U13, U15,

U17, U19, U7, U9,

V10, V12, V14,

V16, V18, V20, V8,

W11, W13, W15,

W17, W7, W9, Y10,

Y23

B17

VSS_OSC_AUDIO

VSS_OSC_SYS

VSS_OSC_AUDIO

VSS_OSC_SYS

GND

AD19

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

The following list describes the table column headers:

1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.

2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).

3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the

signal name in muxmode 0).

注

Many device pins support multiple signal functions. Some signal functions are selected via a

single layer of multiplexers associated with pins. Other signal functions are selected via two

or more layers of multiplexers, where one layer is associated with the pins and other layers

are associated with peripheral logic functions.

表 4-1, Pin Attributes only describes signal multiplexing at the pins. For more information,

related to signal multiplexing at the pins, see section Pad Configuration Registers in section

Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Refer to

the respective peripheral chapter of the Device TRM for information associated with

peripheral signal multiplexing.

4. MUXMODE: Multiplexing mode number:

a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default

muxmode.

注

The default muxmode is the mode at the release of the reset; also see the BALL RESET

REL. MUXMODE column.

b. MUXMODE 1 through 5 are possible muxmodes for alternate functions. On each pin, some

muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only

MUXMODE values which correspond to defined functions should be used.

c. Bootstrap are Special Configuration Pins, latched on rising edge of PORn / RESETFULLn. These

are not programable MUXMODE.

d. An empty box means Not Applicable.

5. TYPE: Signal type and direction:

–

I = Input

O = Output

IO = Input or Output

IOD = Input or Open-drain Output

IOZ = Input or Three-state Output

OZ = Three-state Output

A = Analog

PWR = Power

GND = Ground

CAP = LDO Capacitor.

6. BALL RESET STATE: The state of the terminal at power-on reset:

–

DRIVE 0 (OFF): The buffer drives V_OL(pulldown or pullup resistor not activated).

DRIVE 1 (OFF): The buffer drives V_OH(pulldown or pullup resistor not activated).

OFF: High-impedance

PD: High-impedance with an active pulldown resistor

PU: High-impedance with an active pullup resistor

An empty box means Not Applicable.

7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal:

DRIVE 0 (OFF): The buffer drives V_OL(pulldown or pullup resistor not activated).

–

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DRIVE 1 (OFF): The buffer drives V_OH(pulldown or pullup resistor not activated).

DRIVE CLK (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).

OFF: High-impedance

PD: High-impedance with an active pulldown resistor

PU: High-impedance with an active pullup resistor

An empty box means Not Applicable.

For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see

chapter Device Configuration of the Device TRM.

8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the

rstoutn signal.

An empty box means Not Applicable.

9. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).

An empty box means Not Applicable.

10. POWER: The voltage supply that powers the terminal IO buffers.

An empty box means Not Applicable.

11. HYS: Indicates if the input buffer has hysteresis:

–

Yes: With hysteresis

No: Without hysteresis

An empty box means No.

For more information, see the hysteresis values in 节 5.7, Electrical Characteristics.

12. BUFFER TYPE: This column describes the associated output buffer type.

An empty box means Not Applicable.

For drive strength of the associated output buffer, refer to 节 5.7, Electrical Characteristics.

13. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and

pulldown resistors can be enabled or disabled via software.

–

PU: Internal pullup

PD: Internal pulldown

PU/PD: Internal pullup and pulldown

An empty box means No pull.

14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0",

logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx

registers:

–

0: Logic 0 driven on the input signal port of the peripheral.

1: Logic 1 driven on the input signal port of the peripheral.

An empty box means Not Applicable.

注

Configuring two pins to the same input signal is not supported as it can yield unexpected

results. This can be easily prevented with the proper software configuration.

注

When a pad is set into a multiplexing mode that is not defined by pin multiplexing, behavior

of that pad is undefined, this configuration shall be avoided.

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4.3 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing

options.

The following list describes the column headers:

1. SIGNAL NAME: The name of the signal passing through the pin.

2. DESCRIPTION: Description of the signal.

3. PIN TYPE: Signal direction and type:

–

I = Input

O = Output

IO = Input or Output

IOD = Input or Open-drain Output

IOZ = Input or Three-state Output

OZ = Three-state Output

A = Analog

PWR = Power

GND = Ground

CAP = LDO Capacitor

4. ABY BALL: Associated balls bottom.

For more information on the I/O cell configurations, see section Pad Configuration Registers in section

Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM.

4.3.1 DSS

表 4-2. DSS Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

DSS_DATA0

DSS_DATA1

DSS_DATA2

DSS_DATA3

DSS_DATA4

DSS_DATA5

DSS_DATA6

DSS_DATA7

DSS_DATA8

DSS_DATA9

DSS data output

V22

U21

W22

V23

U23

V24

T21

U22

T22

R21

U24

V25

T24

P21

U25

R22

P23

R24

N22

T25

N24

P24

P25

DSS_DATA10

DSS_DATA11

DSS_DATA12

DSS_DATA13

DSS_DATA14

DSS_DATA15

DSS_DATA16

DSS_DATA17

DSS_DATA18

DSS_DATA19

DSS_DATA20

DSS_DATA21

DSS_DATA22

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表 4-2. DSS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

DSS_DATA23

DSS_DE

DSS data output

N23

M25

L25

DSS data enable output

DSS_FID

DSS field ID output. This signal is not used for embedded

sync modes

DSS_HSYNC

DSS horizontal sync output. This signal is not used for

embedded sync modes

P22

DSS_PCLK

DSS clock output

N25

R25

DSS_VSYNC

DSS vertical sync output. This signal is not used for

embedded sync modes

DSS RFBI Mode

DSS_RFBI_A0

RFBI A0 indicate the status of the data: command or data

(Polarity is programmable)

L25

DSS_RFBI_CSn0

DSS_RFBI_CSn1

DSS_RFBI_DATA0

RFBI LCD chip select 0 (Polarity is programmable)

RFBI LCD chip select 1 (Polarity is programmable)

P23

R24

V22

RFBI data read/write to LCD panel clock reference:

asynchronous

IOZ

DSS_RFBI_DATA1

DSS_RFBI_DATA2

DSS_RFBI_DATA3

DSS_RFBI_DATA4

DSS_RFBI_DATA5

DSS_RFBI_DATA6

DSS_RFBI_DATA7

DSS_RFBI_DATA8

DSS_RFBI_DATA9

DSS_RFBI_DATA10

DSS_RFBI_DATA11

DSS_RFBI_DATA12

DSS_RFBI_DATA13

DSS_RFBI_DATA14

DSS_RFBI_DATA15

DSS_RFBI_HSYNC0

DSS_RFBI_HSYNC1

DSS_RFBI_REn

RFBI data read/write to LCD panel lclock reference:

asynchronous

IOZ

U21

W22

V23

U23

V24

T21

U22

T22

R21

U24

V25

T24

P21

U25

R22

P22

N22

N25

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI data read/write to LCD panel clock reference:

asynchronous

RFBI data read/write to LCD panel lclock reference:

asynchronous

RFBI horizontal synchronization input 0 HSYNC pulse

signals clock reference: asynchronous

RFBI horizontal synchronization input 1 HSYNC pulse

signals clock reference: asynchronous

RFBI read enable (Polarity is programmable) indicate

when a read is on going from the embedded emory in the

LCD panel clock reference.

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表 4-2. DSS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DSS_RFBI_TEVSYNC0

DESCRIPTION [2]

ABY BALL [4]

RFBI vertical synchronization input 0 TE (Tearing Effect)

pulse signal or the LCD panel VSYNC (Vertical

Synchronization) clock reference: asynchronous

R25

T25

M25

DSS_RFBI_TEVSYNC1

RFBI vertical synchronization input 1 TE (Tearing Effect)

pulse signal or the LCD panel VSYNC (Vertical

Synchronization) clock reference: asynchronous

DSS_RFBI_WEn

RFBI LCD write enable (Polarity is programmable)

4.3.2 DDR EMIF

表 4-3. DDR External Memory Interface Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

EMIF address bit 00 output

ABY BALL [4]

DDR3_A00

IOZ

AC15

Y15

DDR3_A01

EMIF address bit 01 output

DDR3_A02

EMIF address bit 02 output

AC16

AA15

AB16

AE17

AC14

AB15

AC17

AB17

AB14

AA16

AA17

AA12

Y17

DDR3_A03

EMIF address bit 03 output

DDR3_A04

EMIF address bit 04 output

DDR3_A05

EMIF address bit 05 output

DDR3_A06

EMIF address bit 06 output

DDR3_A07

EMIF address bit 07 output

DDR3_A08

EMIF address bit 08 output

DDR3_A09

EMIF address bit 09 output

DDR3_A10

EMIF address bit 10 output

DDR3_A11

EMIF address bit 11 output

DDR3_A12

EMIF address bit 12 output

DDR3_A13

EMIF address bit 13 output

DDR3_A14

EMIF address bit 14 output

DDR3_A15

EMIF address bit 15 output

Y16

DDR3_BA0

EMIF bank address 0 output

AA14

AB13

AD17

AC13

AA11

AB11

AC11

AC12

Y11

DDR3_BA1

EMIF bank address 1 output

DDR3_BA2

EMIF bank address 2 output

DDR3_CASn

DDR3_CB00

DDR3_CB01

DDR3_CB02

DDR3_CB03

DDR3_CBDQM

DDR3_CBDQS_N

DDR3_CBDQS_P

DDR3_CEn0

DDR3_CKE0

DDR3_CLKOUT_N0

DDR3_CLKOUT_P0

DDR3_CLKOUT_N1

DDR3_CLKOUT_P1

DDR3_D00

EMIF column address strobe output

EMIF ECC check bit 00 input/output

EMIF ECC check bit 01 input/output

EMIF ECC check bit 02 input/output

EMIF ECC check bit 03 input/output

EMIF ECC check bits data mask output

EMIF ECC check bit data strobe input/output (negative)

EMIF ECC check bit data strobe input/output (positive)

EMIF chip enable 0 output (Active Low)

EMIF clock enable 0 output

AD12

AE12

AD13

AB18

AD15

AE15

AD16

AE16

AD2

EMIF differential clock 0 output (negative)

EMIF differential clock 0 output (positive)

EMIF differential clock 1 output (negative)

EMIF differential clock 1 output (positive)

EMIF data bit 00 input/output

DDR3_D01

EMIF data bit 01 input/output

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表 4-3. DDR External Memory Interface Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

DDR3_D02

DDR3_D03

DDR3_D04

DDR3_D05

DDR3_D06

DDR3_D07

DDR3_D08

DDR3_D09

DDR3_D10

DDR3_D11

DDR3_D12

DDR3_D13

DDR3_D14

DDR3_D15

DDR3_D16

DDR3_D17

DDR3_D18

DDR3_D19

DDR3_D20

DDR3_D21

DDR3_D22

DDR3_D23

DDR3_D24

DDR3_D25

DDR3_D26

DDR3_D27

DDR3_D28

DDR3_D29

DDR3_D30

DDR3_D31

DDR3_DQM0

DDR3_DQM1

DDR3_DQM2

DDR3_DQM3

DDR3_DQS0_N

EMIF data bit 02 input/output

IOZ

AC3

AC2

AE3

AA4

AD3

AB3

AA6

EMIF data bit 03 input/output

EMIF data bit 04 input/output

EMIF data bit 05 input/output

EMIF data bit 06 input/output

EMIF data bit 07 input/output

EMIF data bit 08 input/output

EMIF data bit 09 input/output

EMIF data bit 10 input/output

EMIF data bit 11 input/output

AC5

AB6

EMIF data bit 12 input/output

EMIF data bit 13 input/output

EMIF data bit 14 input/output

AC4

AB5

AB7

AB8

AC7

AA7

AA8

AC6

AE7

AD7

AA10

AE10

AD10

AC10

AC9

AB10

AB9

EMIF data bit 15 input/output

EMIF data bit 16 input/output

EMIF data bit 17 input/output

EMIF data bit 18 input/output

EMIF data bit 19 input/output

EMIF data bit 20 input/output

EMIF data bit 21 input/output

EMIF data bit 22 input/output

EMIF data bit 23 input/output

EMIF data bit 24 input/output

EMIF data bit 25 input/output

EMIF data bit 26 input/output

EMIF data bit 27 input/output

EMIF data bit 28 input/output

EMIF data bit 29 input/output

EMIF data bit 30 input/output

EMIF data bit 31 input/output

EMIF data mask 0 output for byte 0 of the 32-bit data bus

EMIF data mask 1 output for byte 1 of the 32-bit data bus

EMIF data mask 2 output for byte 2 of the 32-bit data bus

EMIF data mask 3 output for byte 3 of the 32-bit data bus

AB4

AA5

AC8

AA9

AE2

EMIF differential data strobe 0 negative input/output for

byte 0 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

IOZ

DDR3_DQS0_P

DDR3_DQS1_N

DDR3_DQS1_P

DDR3_DQS2_N

EMIF differential data strobe 0 positive input/output for

byte 0 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

IOZ

AD1

AE4

AD4

AD6

EMIF differential data strobe 1 negative input/output for

byte 1 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

EMIF differential data strobe 1 positive input/output for

byte 1 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

EMIF differential data strobe 2 negative input/output for

byte 2 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

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表 4-3. DDR External Memory Interface Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DDR3_DQS2_P

DESCRIPTION [2]

ABY BALL [4]

EMIF differential data strobe 2 positive input/output for

byte 2 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

IOZ

AE6

AD9

AE9

DDR3_DQS3_N

DDR3_DQS3_P

EMIF differential data strobe 3 negative input/output for

byte 3 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

EMIF differential data strobe 3 positive input/output for

byte 3 of the 32-bit data bus. This signal is a output to the

DDR3L memory when writing and a input when reading.

DDR3_ODT0

DDR3_RASn

DDR3_RESETn

DDR3_RZQ0

EMIF on-die termination output for chip select 0

EMIF row address strobe output

AA13

AE13

Y18

EMIF reset output (DDR3L-SDRAM only)

EMIF calibration resistor. An external 240 Ω ±1% resistor

W12

must be connected between this pin and VSS.

DDR3_RZQ1

EMIF calibration resistor. An external 240 Ω ±1% resistor

must be connected between this pin and VSS.

DDR3_WEn

DDR_CLK_N

DDR_CLK_P

EMIF write enable output

Y13

EMIF DPLL differential reference clock input (Negative)

EMIF DPLL differential reference clock input (Positive)

AD24

AE24

For more information, see section DDR Extrenal Memory Interface (EMIF) in chapter Memory Subsystem

of the Device TRM.

4.3.3 GPMC

表 4-4. GPMC Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

GPMC_A0

GPMC_A1

GPMC_A2

GPMC_A3

GPMC_A4

GPMC_A5

GPMC_A6

GPMC_A7

GPMC_A8

GPMC_A9

GPMC_A10

GPMC_A11

GPMC_A12

GPMC address 0. Only used to effectively address 8-bit

data nonmultiplexed memories.

M25

GPMC address 1 in A/D nonmultiplexed mode and

address 17 in A/D multiplexed mode

V22

U21

W22

V23

U23

V24

T21

U22

T22

R21

U24

V25

GPMC address 2 in A/D nonmultiplexed mode and

address 18 in A/D multiplexed mode

GPMC address 3 in A/D nonmultiplexed mode and

address 19 in A/D multiplexed mode

GPMC address 4 in A/D nonmultiplexed mode and

address 20 in A/D multiplexed mode

GPMC address 5 in A/D nonmultiplexed mode and

address 21 in A/D multiplexed mode

GPMC address 6 in A/D nonmultiplexed mode and

address 22 in A/D multiplexed mode

GPMC address 7 in A/D nonmultiplexed mode and

address 23 in A/D multiplexed mode

GPMC address 8 in A/D nonmultiplexed mode and

address 24 in A/D multiplexed mode

GPMC address 9 in A/D nonmultiplexed mode and

address 25 in A/D multiplexed mode

GPMC address 10 in A/D nonmultiplexed mode and

address 26 in A/D multiplexed mode

GPMC address 11 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

GPMC address 12 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

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表 4-4. GPMC Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

GPMC_A13

GPMC_A14

GPMC_A15

GPMC_A16

GPMC_A17

GPMC_A18

GPMC_A19

GPMC_A20

GPMC_A21

GPMC_A22

GPMC_A23

GPMC_A24

GPMC_A25

GPMC_A26

GPMC_A27

GPMC_AD0

GPMC_AD1

GPMC_AD2

GPMC_AD3

GPMC_AD4

GPMC_AD5

GPMC_AD6

GPMC_AD7

GPMC_AD8

GPMC_AD9

GPMC_AD10

GPMC_AD11

GPMC address 13 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

IOZ

T24

GPMC address 14 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

P21

U25

GPMC address 15 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

GPMC address 16 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

R22

GPMC address 17 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

P23

GPMC address 18 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

R24

GPMC address 19 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

N22

GPMC address 20 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

T25

GPMC address 21 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

N24

GPMC address 22 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

P24

GPMC address 23 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

P25

GPMC address 24 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

N23

GPMC address 25 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

R25

GPMC address 26 in A/D nonmultiplexed mode and

unused in A/D multiplexed mode

P22

GPMC address 27 in A/D nonmultiplexed mode and

address 27 in A/D multiplexed mode

N25

GPMC data 0 in A/D nonmultiplexed mode and

additionally address 1 in A/D multiplexed mode

AC21

AE20

AD22

AD20

AE21

AE22

AC20

AD21

AE23

AB20

AA20

AD23

GPMC data 1 in A/D nonmultiplexed mode and

additionally address 2 in A/D multiplexed mode

GPMC data 2 in A/D nonmultiplexed mode and

additionally address 3 in A/D multiplexed mode

GPMC data 3 in A/D nonmultiplexed mode and

additionally address 4 in A/D multiplexed mode

GPMC data 4 in A/D nonmultiplexed mode and

additionally address 5 in A/D multiplexed mode

GPMC data 5 in A/D nonmultiplexed mode and

additionally address 6 in A/D multiplexed mode

GPMC data 6 in A/D nonmultiplexed mode and

additionally address 7 in A/D multiplexed mode

GPMC data 7 in A/D nonmultiplexed mode and

additionally address 8 in A/D multiplexed mode

GPMC data 8 in A/D nonmultiplexed mode and

additionally address 9 in A/D multiplexed mode

GPMC data 9 in A/D nonmultiplexed mode and

additionally address 10 in A/D multiplexed mode

GPMC data 10 in A/D nonmultiplexed mode and

additionally address 11 in A/D multiplexed mode

GPMC data 11 in A/D nonmultiplexed mode and

additionally address 12 in A/D multiplexed mode

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表 4-4. GPMC Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

GPMC_AD12

DESCRIPTION [2]

ABY BALL [4]

GPMC data 12 in A/D nonmultiplexed mode and

additionally address 13 in A/D multiplexed mode

IOZ

AA21

AB21

AB22

AA22

GPMC_AD13

GPMC_AD14

GPMC_AD15

GPMC data 13 in A/D nonmultiplexed mode and

additionally address 14 in A/D multiplexed mode

GPMC data 14 in A/D nonmultiplexed mode and

additionally address 15 in A/D multiplexed mode

GPMC data 15 in A/D nonmultiplexed mode and

additionally address 16 in A/D multiplexed mode

GPMC_ADVn_ALE

GPMC_BEn1

GPMC_BEn0_CLE

GPMC_CLK⁽¹⁾

GPMC_CSn0

GPMC_CSn1

GPMC_CSn2

GPMC_CSn3

GPMC_DIR

GPMC address valid active low or address latch enable

GPMC upper-byte enable (Active Low)

GPMC lower-byte enable (Active Low)

GPMC clock output

IOZ

AC23

AB24

AC24

AB23

AB25

W24

W23

Y25

GPMC chip select 0 (Active Low)

GPMC chip select 1 (Active Low)

GPMC chip select 2 (Active Low)

GPMC chip select 3 (Active Low)

GPMC direction

AA25

AC22

Y24

GPMC_OEn_REn

GPMC_WAIT0

GPMC_WAIT1

GPMC_WEn

GPMC output enable (Active Low) or read enable

GPMC external indication of wait 0

GPMC external indication of wait 1

GPMC write enable (Active Low)

GPMC flash write protect (Active Low)

AA24

Y22

GPMC_WPn

W25

(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock

input.

For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory

Subsystem of the Device TRM.

4.3.4 Timers

表 4-5. Timer Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

Timer input for TIMERS [4:0]

ABY BALL [4]

TIMI0

TIMI1

TIMO0

TIMO1

W23

Timer input for TIMERS [4:0]

Timer output for TIMERS [4:0]

Y25

For more information, see section Timers in chapter Peripherals of the Device TRM.

4.3.5 I2C

表 4-6. I2C Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

I2C0_SCL⁽¹⁾

I2C0_SDA

I2C1_SCL⁽¹⁾

I2C1_SDA

I2C0 clock I/O

I2C0 data I/O

I2C1 clock I/O

I2C1 data I/O

IOD

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表 4-6. I2C Signal Descriptions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

TYPE [3]

I2C2_SCL⁽¹⁾

I2C2_SDA

I2C2 clock I/O

I2C2 data I/O

IOD

(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock

input.

For more information, see section Inter-IC module (I2C) in chapter Peripherals of the Device TRM.

4.3.6 UART

表 4-7. UART Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

UART0_CTSn

DESCRIPTION [2]

ABY BALL [4]

UART0 clear to send (Active Low)

UART0 data carrier detect (Active Low)

UART0 data set ready (Active Low)

UART0 data terminal ready (Active Low)

UART0 ring indicator input

E21

D21

D22

C21

UART0_DCDn

UART0_DSRn

UART0_DTRn

UART0_RIN

UART0_RTSn

UART0_RXD

UART0_TXD

UART1_CTSn

UART1_RTSn

UART1_RXD

UART1_TXD

UART2_CTSn

UART2_RTSn

UART2_RXD

UART2_TXD

UART0 request to send (Active Low)

UART0 receive data input

UART0 transmit data output

UART1 clear to send (Active Low)

UART1 request to send (Active Low)

UART1 receive data input

UART1 transmit data output

UART2 clear to send (Active Low)

UART2 request to send (Active Low)

UART2 receive data input for UART mode

UART2 transmit data output

D22

C21

E21

D21

For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter

Peripherals of the Device TRM.

4.3.7 SPI

表 4-8. SPI Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

SPI0_CLK⁽¹⁾

SPI0_SCSn0

SPI0_SCSn1

SPI0_SIMO

SPI0_SOMI

SPI1_CLK⁽¹⁾

SPI1_SCSn0

SPI1_SCSn1

SPI1_SIMO

SPI1_SOMI

SPI2_CLK⁽¹⁾

SPI clock I/O

IOZ

SPI chip select I/O (Active Low)

SPI data output

SPI data input

SPI clock I/O

SPI chip select I/O (Active Low)

SPI data output

SPI data input

SPI clock I/O

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表 4-8. SPI Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

SPI2_SCSn0

SPI2_SCSn1

SPI2_SIMO

SPI2_SOMI

SPI3_CLK⁽¹⁾

SPI3_SCSn0

SPI3_SCSn1

SPI3_SIMO

SPI3_SOMI

SPI chip select I/O (Active Low)

SPI data output

IOZ

SPI data input

SPI clock I/O

E24

C24

E25

F24

F25

SPI chip select I/O (Active Low)

SPI data output

SPI data input

(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock

input.

For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the Device

TRM.

4.3.8 QSPI

表 4-9. QSPI Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

QSPI serial clock output

ABY BALL [4]

QSPI_CLK⁽¹⁾

QSPI_CSn0

K25

J25

QSPI chip select 0 (Active Low). This pin is used for

QSPI boot modes.

QSPI_CSn1

QSPI_CSn2

QSPI_CSn3

QSPI_D0

QSPI chip select 1 (Active Low)

QSPI chip select 2 (Active Low)

QSPI chip select 3 (Active Low)

IOZ

H23

H22

H21

J23

QSPI data 0. This pin is output data for all commands

and writes. For dual read and quad read modes, it

becomes input data pin during read phase.

QSPI_D1

QSPI_D2

QSPI data 1. Input read data in all modes.

IOZ

J22

J21

QSPI data 2. This pin is used only in quad read mode as

input data pin during read phase.

QSPI_D3

QSPI data 3. This pin is used only in quad read mode as

input data pin during read phase.

IOZ

J24

QSPI_RCLK⁽¹⁾

QSPI return clock input. Must be connected from

K24

QSPI_SCLK on PCB. Refer to PCB Guidelines for QSPI.

(1) QSPI uses an external loopback clock strategy to support higher operating frequencies. QSPI_CLK is the clock source which must be

connected to the clock input of all attached devices including QSPI_RCLK which is the clock input for this device. The QSPI clock PCB

signal trace shall be designed using signal integrity analysis to insure impedance mismatches of this multi-point connection does not

produce non-monotonic events while the clock transitions through the switching threshold of attached input buffers. If this occurs, the

non-monotonic events may create internal clock glitches that cause unpredictable behavior of QSPI.

For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the

Device TRM.

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4.3.9 McASP

表 4-10. McASP Signal Descriptions

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

TYPE [3]

MCASP0_ACLKR⁽¹⁾

MCASP0_ACLKX⁽¹⁾

MCASP0_AFSR

MCASP0_AFSX

MCASP0_AHCLKR⁽¹⁾

MCASP0_AHCLKX⁽¹⁾

MCASP0_AMUTE

MCASP0_AXR0

MCASP0_AXR1

MCASP0_AXR2

MCASP0_AXR3

MCASP0_AXR4

MCASP0_AXR5

MCASP0_AXR6

MCASP0_AXR7

MCASP0_AXR8

MCASP0_AXR9

MCASP0_AXR10

MCASP0_AXR11

MCASP0_AXR12

MCASP0_AXR13

MCASP0_AXR14

MCASP0_AXR15

MCASP1_ACLKR⁽¹⁾

MCASP1_ACLKX⁽¹⁾

MCASP1_AFSR

MCASP1_AFSX

MCASP1_AHCLKR⁽¹⁾

MCASP1_AHCLKX⁽¹⁾

MCASP1_AMUTE

MCASP1_AXR0

MCASP1_AXR1

MCASP1_AXR2

MCASP1_AXR3

MCASP1_AXR4

MCASP1_AXR5

MCASP1_AXR6

MCASP1_AXR7

MCASP1_AXR8

MCASP1_AXR9

MCASP2_ACLKR⁽¹⁾

MCASP2_ACLKX⁽¹⁾

MCASP2_AFSR

MCASP2_AFSX

MCASP2_AHCLKR⁽¹⁾

McASP0 receive bit clock I/O

IOZ

McASP0 transmit bit clock I/O

McASP0 receive frame sync I/O

McASP0 transmit frame sync I/O

McASP0 receive high-frequency master clock I/O

McASP0 transmit high-frequency master clock output

McASP0 mute

IOZ

McASP0 transmit and receive data I/O

McASP1 receive bit clock I/O

B10

A10

C10

E10

D10

F10

C11

D11

E11

F12

E12

C12

B11

B12

McASP1 transmit bit clock I/O

McASP1 receive frame sync I/O

McASP1 transmit frame sync I/O

McASP1 receive high-frequency master clock I/O

McASP1 transmit high-frequency master clock output

McASP1 mute

IOZ

McASP1 transmit and receive data I/O

McASP2 receive bit clock I/O

McASP2 transmit bit clock I/O

McASP2 receive frame sync I/O

McASP2 transmit frame sync I/O

McASP2 receive high-frequency master clock I/O

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表 4-10. McASP Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

MCASP2_AHCLKX⁽¹⁾

DESCRIPTION [2]

ABY BALL [4]

McASP2 transmit high-frequency master clock output

McASP2 mute

IOZ

MCASP2_AMUTE

MCASP2_AXR0

MCASP2_AXR1

MCASP2_AXR2

MCASP2_AXR3

MCASP2_AXR4

MCASP2_AXR5

McASP2 transmit and receive data I/O

(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock

input.

For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the

Device TRM.

4.3.10 USB

表 4-11. USB Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

USB0_DM

USB0_DP

USB0 differential data signal pair (negative)

USB0 differential data signal pair (positive)

USB0 drive VBUS output

B18

A18

E19

H22

A19

USB0_DRVVBUS

USB0_EXT_TRIGGER

USB0_ID

USB0 external trigger Input

USB0 identify device, connection to resistor that

determines mode of operation

USB0_TXRTUNE_RKELVIN

USB0 Kelvin connection to termination calibration resistor

C19

(200 Ω ±1%)

USB0_VBUS

USB0 VBUS comparator input

B19

D19

A20

B20

B21

H21

E20

D20

USB0_XO

USB0 optional PHY reference clock input

USB1 differential data signal pair (negative)

USB1 differential data signal pair (positive)

USB1 drive VBUS output

USB1_DM

USB1_DP

USB1_DRVVBUS

USB1_EXT_TRIGGER

USB1_ID

USB1 external trigger Input

USB1 identify device pin, determines mode of operation

USB1_TXRTUNE_RKELVIN

USB1 Kelvin connection to termination calibration resistor

(200 Ω ±1%)

USB1_VBUS

USB1_XO

USB1 VBUS comparator input

A21

C20

USB1 optional PHY reference clock input

For more information, see section Universal Serial Bus Subsystem (USB) in chapter Peripherals of the

Device TRM.

4.3.11 PCIESS

表 4-12. PCIESS Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

PCIE_CLK_N

PCIE_CLK_P

PCIe clock input (negative)

PCIe clock input (positive)

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表 4-12. PCIESS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

PCIE_REFRES

PCIE_RXN0

PCIE_RXP0

PCIE_TXN0

PCIE_TXP0

PCIe SerDes reference resistor input (3 kΩ ±1%)

PCIe receive data lane 0 (negative)

PCIe receive data lane 0 (positive)

PCIe transmit data lane 0 (negative)

PCIe transmit data lane 0 (positive)

For more information, see section Peripheral Component Interconnect Express Subsystem (PCIe SS) in

chapter Peripherals of the Device TRM.

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4.3.12 DCAN

表 4-13. DCAN Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

DCAN0_RX

DCAN0_TX

DCAN1_RX

DCAN1_TX

DCAN0 receive data pin

DCAN0 transmit data pin

DCAN1 receive data pin

DCAN1 transmit data pin

H21

H22

For more information, see section Dual Controller Area Network (DCAN) Interface in chapter Peripherals

of the Device TRM.

4.3.13 EMAC

表 4-14. EMAC Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

CPTS_HW1_TSPUSH

DESCRIPTION [2]

ABY BALL [4]

CPTS hardware time stamp push input 1

CPTS hardware time stamp push input 2

CPTS time stamp counter compare output

CPTS time stamp counter bit output

MDIO clock

E21

D21

C21

D22

CPTS_HW2_TSPUSH

CPTS_TS_COMP

CPTS_TS_SYNC

MDIO_CLK

MDIO_DATA

MII_COL

MDIO data

IOZ

MII collision detect (sense) input

MII carrier sense input

MII receive clock

B25

G22

A22

B24

C23

B23

F22

A24

F23

C25

G23

G24

G25

D25

H25

H24

A22

A24

B24

C23

B23

F22

C25

H25

G23

G24

G25

MII_CRS

MII_RXCLK

MII_RXD0

MII receive data 0

MII_RXD1

MII receive data 1

MII_RXD2

MII receive data 2

MII_RXD3

MII receive data 3

MII_RXDV

MII receive data valid input

MII receive data error input

MII transmit clock

MII_RXER

MII_TXCLK

MII_TXD0

MII transmit data 0

MII_TXD1

MII transmit data 1

MII_TXD2

MII transmit data 2

MII_TXD3

MII transmit data 3

MII_TXEN

MII transmit data enable output

MII transmit data error output

RGMII receive clock

MII_TXER

RGMII_RXC

RGMII_RXCTL

RGMII_RXD0

RGMII_RXD1

RGMII_RXD2

RGMII_RXD3

RGMII_TXC

RGMII_TXCTL

RGMII_TXD0

RGMII_TXD1

RGMII_TXD2

RGMII receive control

RGMII receive data

RGMII transmit clock

RGMII transmit enable

RGMII transmit data

IOZ

RGMII transmit data

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表 4-14. EMAC Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

RGMII_TXD3

RGMII transmit data

D25

G22

D24

RMII_CRS_DV

RMII_REFCLK⁽¹⁾

RMII carrier sense input

50-MHz RMII clock. Typically sourced from the CLKOUT

RMII_RXD0

RMII_RXD1

RMII_RXER

RMII_TXD0

RMII_TXD1

RMII_TXEN

RMII receive data

B24

C23

F23

G23

G24

H25

RMII receive data

RMII receive data error input

RMII transmit data

RMII transmit data enable output

(1) RMII_REFCLK pad loopback is not supported on this device. An external 50 MHz clock source can be used to source RMII_REFCLK, or

CLKOUT may be configured as a 50 MHz reference clock with an external connection to RMII_REFCLK. For either case, the RMII

reference clock PCB signal trace is a multi-point connection which shall be designed using signal integrity analysis to insure impedance

mismatches of this multi-point connection does not produce non-monotonic events while the clock transitions through the switching

threshold of attached input buffers. If this occurs, the non-monotonic events may create internal clock glitches that cause unpredictable

behavior of RMII.

For more information, see section Networking Subsystem (NSS), Gigabit Ethernet MAC (EMAC)

Subsystem in chapter Peripherals of the Device TRM.

4.3.14 MLB

表 4-15. MLB Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

MLBP_CLK_N

DESCRIPTION [2]

ABY BALL [4]

Media Local Bus Subsystem (MLB) clock input differential

pair (negative)

L23

MLBP_CLK_P

MLBP_DAT_N

MLBP_DAT_P

MLBP_SIG_N

MLBP_SIG_P

Media Local Bus Subsystem (MLB) clock input differential

pair (positive)

M23

K22

K23

M24

L24

Media Local Bus Subsystem (MLB) data input and output

differential pair (negative)

Media Local Bus Subsystem (MLB) data input and output

differential pair (positive)

Media Local Bus Subsystem (MLB) signal input and

output differential pair (negative)

Media Local Bus Subsystem (MLB) signal input and

output differential pair (positive)

MLB_CLK

MLB_DAT

MLB_SIG

Media Local Bus Subsystem (MLB) clock input

AA24

W24

Media Local Bus Subsystem (MLB) data input and output

IOZ

Media Local Bus Subsystem (MLB) signal input and

output

AA25

For more information, see section Media Local Bus (MLB) in chapter Peripherals of the Device TRM.

Terminal Configuration and Functions

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4.3.15 McBSP

表 4-16. McBSP Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

MCBSP_CLKR⁽¹⁾

MCBSP_CLKX⁽¹⁾

MCBSP_DR

McBSP received serial clock

IOZ

D17

B16

D15

A16

C16

E15

McBSP transmitted serial clock

McBSP received serial data

MCBSP_DX

McBSP transmitted serial data

McBSP received frame synchronization

McBSP transmitted frame synchronization

IOZ

MCBSP_FSR

MCBSP_FSX

(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock

input.

For more information, see section Multi-channel Buffered Serial Port (McBSP) in chapter Peripherals of

the Device TRM.

4.3.16 MMC/SD

表 4-17. MMC/SD Signal Descriptions

SIGNAL NAME [1]

MMC0_CLK⁽¹⁾

DESCRIPTION [2]

ABY BALL [4]

TYPE [3]

IOZ

MMC0 clock

F13

C13

B13

A13

A11

A12

B12

B11

C12

E12

D11

F12

E11

MMC0_CMD

MMC0_DAT0

MMC0_DAT1

MMC0_DAT2

MMC0_DAT3

MMC0_DAT4

MMC0_DAT5

MMC0_DAT6

MMC0_DAT7

MMC0_POW

MMC0_SDCD

MMC0_SDWP

MMC1_CLK⁽¹⁾

MMC1_CMD

MMC1_DAT0

MMC1_DAT1

MMC1_DAT2

MMC1_DAT3

MMC1_DAT4

MMC1_DAT5

MMC1_DAT6

MMC1_DAT7

MMC1_POW

MMC1_SDCD

MMC1_SDWP

MMC0 command

MMC0 data bit 0

MMC0 data bit 1

MMC0 data bit 2

MMC0 data bit 3

MMC0 data bit 4

MMC0 data bit 5

MMC0 data bit 6

MMC0 data bit 7

MMC/SD cards on/off power supply control

MMC0 card detect

MMC0 write protect

MMC1 clock

IOZ

MMC1 command

MMC1 data bit 0

MMC1 data bit 1

MMC1 data bit 2

MMC1 data bit 3

MMC1 data bit 4

MMC1 data bit 5

MMC1 data bit 6

MMC1 data bit 7

MMC/SD cards on/off power supply control

MMC1 card detect

MMC1 write protect

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(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is required (as closeas possible to device pin) to improve signal integrity of the clock

input.

For more information, see section Multimedia Card High Speed Interface (MMCHS) in chapter Peripherals

of the Device TRM.

4.3.17 GPIO

表 4-18. GPIO Signal Descriptions

SIGNAL NAME [1]

DESCRIPTION [2]

General-purpose input/output

ABY BALL [4]

TYPE [3]

IOZ

GPIO0_00

GPIO0_01

GPIO0_02

GPIO0_03

GPIO0_04

GPIO0_05

GPIO0_06

GPIO0_07

GPIO0_08

GPIO0_09

GPIO0_10

GPIO0_11

GPIO0_12

GPIO0_13

GPIO0_14

GPIO0_15

GPIO0_16

GPIO0_17

GPIO0_18

GPIO0_19

GPIO0_100

GPIO0_101

GPIO0_102

GPIO0_103

GPIO0_104

GPIO0_105

GPIO0_106

GPIO0_107

GPIO0_108

GPIO0_109

GPIO0_110

GPIO0_111

GPIO0_112

GPIO0_113

GPIO0_114

GPIO0_115

GPIO0_116

GPIO0_117

GPIO0_118

AC21

AE20

AD22

AD20

AE21

AE22

AC20

AD21

AE23

AB20

AA20

AD23

AA21

AB21

AB22

AA22

AB23

AC23

AC22

Y22

General-purpose input/output

Terminal Configuration and Functions

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表 4-18. GPIO Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

GPIO0_119

GPIO0_120

GPIO0_121

GPIO0_122

GPIO0_123

GPIO0_124

GPIO0_125

GPIO0_126

GPIO0_127

GPIO0_128

GPIO0_129

GPIO0_130

GPIO0_131

GPIO0_132

GPIO0_133

GPIO0_134

GPIO0_135

GPIO0_136

GPIO0_137

GPIO0_138

GPIO0_139

GPIO0_140

GPIO0_141

GPIO0_142

GPIO0_143

GPIO0_20

GPIO0_21

GPIO0_22

GPIO0_23

GPIO0_24

GPIO0_25

GPIO0_26

GPIO0_27

GPIO0_28

GPIO0_29

GPIO0_30

GPIO0_31

GPIO0_32

GPIO0_33

GPIO0_34

GPIO0_35

GPIO0_36

GPIO0_37

GPIO0_38

GPIO0_39

GPIO0_40

GPIO0_41

General-purpose input/output

IOZ

General-purpose input/output

AC24

AB24

Y24

AA24

W25

AA25

AB25

W24

W23

Y25

N23

P25

P24

N24

T25

N22

R24

P23

R22

U25

P21

T24

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表 4-18. GPIO Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

GPIO0_42

GPIO0_43

GPIO0_44

GPIO0_45

GPIO0_46

GPIO0_47

GPIO0_48

GPIO0_49

GPIO0_50

GPIO0_51

GPIO0_52

GPIO0_53

GPIO0_54

GPIO0_55

GPIO0_56

GPIO0_57

GPIO0_58

GPIO0_59

GPIO0_60

GPIO0_61

GPIO0_62

GPIO0_63

GPIO0_64

GPIO0_65

GPIO0_66

GPIO0_67

GPIO0_68

GPIO0_69

GPIO0_70

GPIO0_71

GPIO0_72

GPIO0_73

GPIO0_74

GPIO0_75

GPIO0_76

GPIO0_77

GPIO0_78

GPIO0_79

GPIO0_80

GPIO0_81

GPIO0_82

GPIO0_83

GPIO0_84

GPIO0_85

GPIO0_86

GPIO0_87

GPIO0_88

General-purpose input/output

IOZ

V25

U24

R21

T22

U22

T21

V24

U23

V23

W22

U21

V22

R25

P22

N25

M25

L25

General-purpose input/output

A22

A23

B22

C22

D23

F22

B23

C23

B24

A24

F23

B25

G22

C25

C24

E25

E24

Terminal Configuration and Functions

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表 4-18. GPIO Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

GPIO0_89

GPIO0_90

GPIO0_91

GPIO0_92

GPIO0_93

GPIO0_94

GPIO0_95

GPIO0_96

GPIO0_97

GPIO0_98

GPIO0_99

GPIO1_00

GPIO1_01

GPIO1_02

GPIO1_03

GPIO1_04

GPIO1_05

GPIO1_06

GPIO1_07

GPIO1_08

GPIO1_09

GPIO1_10

GPIO1_11

GPIO1_12

GPIO1_13

GPIO1_14

GPIO1_15

GPIO1_16

GPIO1_17

GPIO1_18

GPIO1_19

GPIO1_20

GPIO1_21

GPIO1_22

GPIO1_23

GPIO1_24

GPIO1_25

GPIO1_26

GPIO1_27

GPIO1_28

GPIO1_29

GPIO1_30

GPIO1_31

GPIO1_32

GPIO1_33

GPIO1_34

GPIO1_35

General-purpose input/output

IOZ

F25

F24

D25

G25

G24

G23

H25

H24

General-purpose input/output

B10

A10

C10

E10

D10

F10

C11

D11

E11

F12

E12

C12

B11

B12

A12

A11

A13

B13

F13

C13

E13

D12

D13

A14

B14

C14

E14

D14

A15

F14

B15

C15

D15

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表 4-18. GPIO Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

GPIO1_36

GPIO1_37

GPIO1_38

GPIO1_39

GPIO1_40

GPIO1_41

GPIO1_42

GPIO1_43

GPIO1_44

GPIO1_45

GPIO1_46

GPIO1_47

GPIO1_48

GPIO1_49

GPIO1_50

GPIO1_51

GPIO1_52

GPIO1_53

GPIO1_54

GPIO1_55

GPIO1_56

GPIO1_57

GPIO1_58

GPIO1_59

GPIO1_60

GPIO1_61

GPIO1_62

GPIO1_63

GPIO1_64

GPIO1_65

GPIO1_66

GPIO1_67

General-purpose input/output

IOZ

A16

E15

B16

C16

D17

C18

D16

F16

E17

E16

E18

D18

General-purpose input/output

E21

D21

D22

C21

K25

K24

J23

J22

J21

J24

J25

H23

H22

H21

For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the Device

TRM.

4.3.18 ePWM

表 4-19. ePWM Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

eCAP0_IN_APWM0_OUT

DESCRIPTION [2]

ABY BALL [4]

eCAP0 capture input and PWM output

eCAP1 capture input and PWM output

eHRPWM0 output A

IOZ

E18

D18

N23

P25

N24

T25

N22

eCAP1_IN_APWM1_OUT

eHRPWM0_A

eHRPWM0_B

eHRPWM0 output B

eHRPWM0_SYNCI

eHRPWM0_SYNCO

eHRPWM1_A

eHRPWM0 sync input

eHRPWM0 sync output

IOZ

eHRPWM1 output A

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表 4-19. ePWM Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

eHRPWM1_B

DESCRIPTION [2]

ABY BALL [4]

eHRPWM1 output B

eHRPWM2 output A

eHRPWM2 output B

eHRPWM3 output A

eHRPWM3 output B

IOZ

R24

R22

U25

A23

B22

C22

D23

D12

D13

E17

E16

E13

F16

P24

P23

P21

H24

E13

F16

T24

V25

U24

R21

T22

U22

T21

V24

U23

V23

W22

U21

eHRPWM2_A

eHRPWM2_B

eHRPWM3_A

eHRPWM3_B

eHRPWM3_SYNCI

eHRPWM3_SYNCO

eHRPWM4_A

eHRPWM4_B

eHRPWM5_A

eHRPWM5_B

eHRPWM_SOCA

eHRPWM_SOCB

eHRPWM_TZn0

eHRPWM_TZn1

eHRPWM_TZn2

eHRPWM_TZn3

eHRPWM_TZn4

eHRPWM_TZn5

eQEP0_A

eHRPWM3 sync input

eHRPWM3 sync output

IOZ

eHRPWM4 output A

eHRPWM4 output B

eHRPWM5 output A

eHRPWM5 output B

ePWM ADC output A

ePWM ADC output B

eHRPWM0 trip zone input (Active Low)

eHRPWM1 trip zone input (Active Low)

eHRPWM2 trip zone input (Active Low)

eHRPWM3 trip zone input (Active Low)

eHRPWM4 trip zone input (Active Low)

eHRPWM5 trip zone input (Active Low)

eQEP0 quadrature input A

eQEP0 quadrature input B

eQEP0 index input / output

eQEP0 strobe input / output

eQEP1 quadrature input A

eQEP1 quadrature input B

eQEP1 index input / output

eQEP1 strobe input / output

eQEP2 quadrature input A

eQEP2 quadrature input B

eQEP2 index input / output

eQEP2 strobe input / output

eQEP0_B

eQEP0_I

IOZ

eQEP0_S

eQEP1_A

eQEP1_B

eQEP1_I

IOZ

eQEP1_S

eQEP2_A

eQEP2_B

eQEP2_I

IOZ

eQEP2_S

For more information, see section Enhanced PWM (ePWM) Module in chapter Peripherals of the Device

TRM.

4.3.19 PRU-ICSS

表 4-20. PRU-ICSS Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

PR0_eCAP0_eCAP_CAPIN_APWM_O

PR0_eCAP0_eCAP_SYNCIN

PR0_eCAP0_eCAP_SYNCOUT

PR0_EDC_LATCH0_IN

Capture input and PWM output

Capture sync input

Capture sync output

Latch input 0

IOZ

C24

H24

D24

PR0_EDC_LATCH1_IN

Latch input 1

PR0_EDC_SYNC0_OUT

PR0_EDC_SYNC1_OUT

PR0_EDIO_DATA0

SYNC 0 output

IOZ

SYNC 1 output

B10

D23

Digital input

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表 4-20. PRU-ICSS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

PR0_EDIO_DATA1

PR0_EDIO_DATA2

PR0_EDIO_DATA3

PR0_EDIO_OUTVALID

PR0_MDIO_DATA

PR0_MDIO_MDCLK

PR0_PRU0_GPI0

PR0_PRU0_GPI1

PR0_PRU0_GPI2

PR0_PRU0_GPI3

PR0_PRU0_GPI4

PR0_PRU0_GPI5

PR0_PRU0_GPI6

PR0_PRU0_GPI7

PR0_PRU0_GPI8

PR0_PRU0_GPI9

PR0_PRU0_GPI10

PR0_PRU0_GPI11

PR0_PRU0_GPI12

PR0_PRU0_GPI13

PR0_PRU0_GPI14

PR0_PRU0_GPI15

PR0_PRU0_GPI16

PR0_PRU0_GPI17

PR0_PRU0_GPI18

PR0_PRU0_GPI19

PR0_PRU0_GPO0

PR0_PRU0_GPO1

PR0_PRU0_GPO2

PR0_PRU0_GPO3

PR0_PRU0_GPO4

PR0_PRU0_GPO5

PR0_PRU0_GPO6

PR0_PRU0_GPO7

PR0_PRU0_GPO8

PR0_PRU0_GPO9

PR0_PRU0_GPO10

PR0_PRU0_GPO11

PR0_PRU0_GPO12

PR0_PRU0_GPO13

PR0_PRU0_GPO14

PR0_PRU0_GPO15

PR0_PRU0_GPO16

PR0_PRU0_GPO17

PR0_PRU0_GPO18

PR0_PRU0_GPO19

PR0_PRU1_GPI0

Digital input

IOZ

C22

B22

A23

L25

A10

C10

Digital out valid signal

MDIO data

MDIO clock

PRU0 general-purpose input

PRU0 general-purpose output

PRU1 general-purpose input

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表 4-20. PRU-ICSS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

PR0_PRU1_GPI1

DESCRIPTION [2]

ABY BALL [4]

PRU1 general-purpose input

PR0_PRU1_GPI2

PRU1 general-purpose input

PRU1 general-purpose output

UART clear-to-send

PR0_PRU1_GPI3

PR0_PRU1_GPI4

PR0_PRU1_GPI5

PR0_PRU1_GPI6

PR0_PRU1_GPI7

PR0_PRU1_GPI8

PR0_PRU1_GPI9

PR0_PRU1_GPI10

PR0_PRU1_GPI11

PR0_PRU1_GPI12

PR0_PRU1_GPI13

PR0_PRU1_GPI14

PR0_PRU1_GPI15

PR0_PRU1_GPI16

PR0_PRU1_GPI17

PR0_PRU1_GPI18

PR0_PRU1_GPI19

PR0_PRU1_GPO0

PR0_PRU1_GPO1

PR0_PRU1_GPO2

PR0_PRU1_GPO3

PR0_PRU1_GPO4

PR0_PRU1_GPO5

PR0_PRU1_GPO6

PR0_PRU1_GPO7

PR0_PRU1_GPO8

PR0_PRU1_GPO9

PR0_PRU1_GPO10

PR0_PRU1_GPO11

PR0_PRU1_GPO12

PR0_PRU1_GPO13

PR0_PRU1_GPO14

PR0_PRU1_GPO15

PR0_PRU1_GPO16

PR0_PRU1_GPO17

PR0_PRU1_GPO18

PR0_PRU1_GPO19

PR0_UART0_CTSN

PR0_UART0_RTSN

PR0_UART0_RXD

PR0_UART0_TXD

PR1_eCAP0_eCAP_CAPIN_APWM_O

PR1_eCAP0_eCAP_SYNCIN

PR1_eCAP0_eCAP_SYNCOUT

PR1_EDC_LATCH0_IN

B10

F25

F24

E25

E24

R25

P22

N25

D12

UART ready-to-send

UART receive data

UART transmit data

IOZ

Capture input and PWM output

Capture sync input

Cpature sync output

Latch input 0

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表 4-20. PRU-ICSS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

PR1_EDC_LATCH1_IN

PR1_EDC_SYNC0_OUT

PR1_EDC_SYNC1_OUT

PR1_EDIO_DATA0

PR1_EDIO_DATA1

PR1_EDIO_DATA2

PR1_EDIO_DATA3

PR1_EDIO_OUTVALID

PR1_MDIO_DATA

PR1_MDIO_MDCLK

PR1_PRU0_GPI0

PR1_PRU0_GPI1

PR1_PRU0_GPI2

PR1_PRU0_GPI3

PR1_PRU0_GPI4

PR1_PRU0_GPI5

PR1_PRU0_GPI6

PR1_PRU0_GPI7

PR1_PRU0_GPI8

PR1_PRU0_GPI9

PR1_PRU0_GPI10

PR1_PRU0_GPI11

PR1_PRU0_GPI12

PR1_PRU0_GPI13

PR1_PRU0_GPI14

PR1_PRU0_GPI15

PR1_PRU0_GPI16

PR1_PRU0_GPI17

PR1_PRU0_GPI18

PR1_PRU0_GPI19

PR1_PRU0_GPO0

PR1_PRU0_GPO1

PR1_PRU0_GPO2

PR1_PRU0_GPO3

PR1_PRU0_GPO4

PR1_PRU0_GPO5

PR1_PRU0_GPO6

PR1_PRU0_GPO7

PR1_PRU0_GPO8

PR1_PRU0_GPO9

PR1_PRU0_GPO10

PR1_PRU0_GPO11

PR1_PRU0_GPO12

PR1_PRU0_GPO13

PR1_PRU0_GPO14

PR1_PRU0_GPO15

PR1_PRU0_GPO16

Latch input 1

SYNC 0 output

SYNC 1 output

Digital input

IOZ

E17

D13

E16

C21

D22

D21

E21

M25

E18

D18

E10

D10

F10

C11

D11

E11

F12

E12

C12

B11

B12

A12

A11

A13

B13

F13

C13

E13

D12

D13

E10

D10

F10

C11

D11

E11

F12

E12

C12

B11

B12

A12

A11

A13

B13

F13

C13

Digital out valid signal

MDIO data

MDIO clock

PRU0 general-purpose input

PRU0 general-purpose output

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表 4-20. PRU-ICSS Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

PR1_PRU0_GPO17

DESCRIPTION [2]

ABY BALL [4]

PRU0 general-purpose output

E13

D12

D13

A14

B14

C14

E14

D14

A15

F14

B15

C15

D15

A16

E15

B16

C16

D17

C18

D16

F16

E17

E16

A14

B14

C14

E14

D14

A15

F14

B15

C15

D15

A16

E15

B16

C16

D17

C18

D16

F16

E17

E16

H22

H21

PR1_PRU0_GPO18

PR1_PRU0_GPO19

PR1_PRU1_GPI0

PR1_PRU1_GPI1

PR1_PRU1_GPI2

PR1_PRU1_GPI3

PR1_PRU1_GPI4

PR1_PRU1_GPI5

PR1_PRU1_GPI6

PR1_PRU1_GPI7

PR1_PRU1_GPI8

PR1_PRU1_GPI9

PR1_PRU1_GPI10

PR1_PRU1_GPI11

PR1_PRU1_GPI12

PR1_PRU1_GPI13

PR1_PRU1_GPI14

PR1_PRU1_GPI15

PR1_PRU1_GPI16

PR1_PRU1_GPI17

PR1_PRU1_GPI18

PR1_PRU1_GPI19

PR1_PRU1_GPO0

PR1_PRU1_GPO1

PR1_PRU1_GPO2

PR1_PRU1_GPO3

PR1_PRU1_GPO4

PR1_PRU1_GPO5

PR1_PRU1_GPO6

PR1_PRU1_GPO7

PR1_PRU1_GPO8

PR1_PRU1_GPO9

PR1_PRU1_GPO10

PR1_PRU1_GPO11

PR1_PRU1_GPO12

PR1_PRU1_GPO13

PR1_PRU1_GPO14

PR1_PRU1_GPO15

PR1_PRU1_GPO16

PR1_PRU1_GPO17

PR1_PRU1_GPO18

PR1_PRU1_GPO19

PR1_UART0_CTSN

PR1_UART0_RTSN

PR1_UART0_RXD

PR1_UART0_TXD

PRU0 general-purpose output

PRU1 general-purpose input

PRU1 general-purpose output

UART clear-to-send

UART ready-to-send

UART receive data

UART transmit data

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注

PRU-ICSS has internal-multiplexing capability of pin functions. See Programmable Real-

Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter

Processors and Accelerators of the Device TRM. Besides, EGPIO (enhanced GPIO) module

can be configured to export additional functions to EGPIO pins in place of simple GPIO. See

section PRU-ICSS PRU Cores in chapter Processors and Accelerators of the Device TRM.

4.3.20 Emulation and Debug Subsystem

表 4-21. Debug Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

EMU00

EMU01

EMU02

EMU03

EMU04

EMU05

EMU06

EMU07

EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU16

EMU17

EMU18

EMU19

TCK

Emulator pin 0

Emulator pin 1

Emulator pin 2

Emulator pin 3

Emulator pin 4

Emulator pin 5

Emulator pin 6

Emulator pin 7

Emulator pin 8

Emulator pin 9

Emulator pin 10

Emulator pin 11

Emulator pin 12

Emulator pin 13

Emulator pin 14

Emulator pin 15

Emulator pin 16

Emulator pin 17

Emulator pin 18

Emulator pin 19

IOZ

M22

L22

N23

P25

P24

N24

T25

N22

R24

P23

R22

U25

P21

T24

V25

U24

R21

T22

U22

T21

JTAG test clock input

JTAG test data input

TDI

TDO

JTAG test port data output

TMS

JTAG test port mode select input. An external pullup

resistor must be used on this ball.

TRSTn

JTAG test reset

For more information, see chapter On-chip Debug of the Device TRM.

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4.3.21 System and Miscellaneous

4.3.21.1 Boot Mode Configuration

表 4-22. Sysboot Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

BOOTCOMPLETE

DESCRIPTION [2]

ABY BALL [4]

Arm and DSP boot complete indicator

Bootmode pin 00

Bootmode pin 01

Bootmode pin 02

Bootmode pin 03

Bootmode pin 04

Bootmode pin 05

Bootmode pin 06

Bootmode pin 07

Bootmode pin 08

Bootmode pin 09

Bootmode pin 10

Bootmode pin 11

Bootmode pin 12

Bootmode pin 13

Bootmode pin 14

Bootmode pin 15

Main PLL output divide

BOOTMODE00⁽¹⁾

BOOTMODE01⁽¹⁾

BOOTMODE02⁽¹⁾

BOOTMODE03⁽¹⁾

BOOTMODE04⁽¹⁾

BOOTMODE05⁽¹⁾

BOOTMODE06⁽¹⁾

BOOTMODE07⁽¹⁾

BOOTMODE08⁽¹⁾

BOOTMODE09⁽¹⁾

BOOTMODE10⁽¹⁾

BOOTMODE11⁽¹⁾

BOOTMODE12⁽¹⁾

BOOTMODE13⁽¹⁾

BOOTMODE14⁽¹⁾

BOOTMODE15⁽¹⁾

MAINPLL_OD_SEL⁽¹⁾

BOOT_RSVD⁽¹⁾

N23

P25

P24

N24

T25

N22

R24

P23

R22

U25

P21

T24

V25

U24

R21

T22

W22

V23

Reserved – This input shall always be pulled to a valid

logic low level to insure the proper boot mode is selected

NODDR⁽¹⁾

Bootmode pin for no-DDR use case

U23

(1) Separate external pull resistors shall be connected to the balls associated with each of these signals to insure they are pulled to the

appropriate and valid logic level required to select the desired boot mode on the rising edge of PORn. These inputs are synchronously

latched after the rising edge of PORn using SYSOSC_IN or SYSCLK_P / N with setup and hold timing requirements defined in Table 5-

15, Boot Configuration Timing Requirements.

For more information, see chapter Initialization of the Device TRM.

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4.3.21.2 Reset

表 4-23. Reset Signal Descriptions

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

TYPE [3]

LRESETn

Local reset to DSP (Active Low)

LRESETNMIENn

PORn

Enable for local reset to DSP and NMIn (Active Low)

Power-on Reset (Active Low). This pin must be asserted

low until all device supplies are valid (see Section 5.9.1,

Power Supply Sequencing).

AA3

RESETFULLn

RESETn

Cold reset (Active Low)

Device reset input (Active Low)

Reset status indicator (Active Low)

RESETSTATn

For more information, see section Reset Management in chapter Device Configuration of the Device TRM.

4.3.21.3 Oscillator Reference Clocks and Clock Generator

表 4-24. Clock Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

AUDOSC_IN⁽²⁾

DESCRIPTION [2]

ABY BALL [4]

Optional audio oscillator (AUDIOOSC) input. This input

can be connected to the appropriate external crystal

circuit or the oscillator can be bypassed by connecting

this input to an LVCMOS clock source.

C17

AUDOSC_OUT

Optional audio oscillator (AUDIOOSC) output. This output

is only used when AUDIOOSC is connected to the

appropriate external crystal circuit.

A17

CLKOUT

RMII/MII reference clock output

H23

L21

CPTS_REFCLK_N

CPTS_REFCLK_P

SYSCLKOUT⁽³⁾

SYSCLK_N⁽⁴⁾

SYSCLK_P⁽⁴⁾

SYSOSC_IN⁽⁵⁾⁽⁶⁾

Differential CPTS reference clock input, negative

Differential CPTS reference clock input, positive

SYSCLK divided by 6 observation output

Differential system clock input, negative

Differential system clock input, positive

K21

M21

AC25

AD25

AC19

System oscillator (SYSOSC) input. This input can be

connected to the appropriate external crystal circuit or the

oscillator can be bypassed by connecting this input to an

LVCMOS clock source.

SYSOSC_OUT

System oscillator (SYSOSC) output. This output is only

used when SYSOSC is connected to the appropriate

external crystal circuit.

AE19

XREFCLK

Optional audio reference clock input

Observation clock output, negative

Observation clock output, positive

Observation PLL lock output

OBSCLK_N⁽¹⁾

OBSCLK_P⁽¹⁾

OBSPLL_LOCK⁽¹⁾

(1) These outputs are provided for test and debug purposes only. Performance of these outputs are not defined due to many complex

combinations of system variables. For example, these outputs may be sourced from several PLLs with each PLL supporting many

configuration options that yield various levels of performance. There are also other unpredictable contributors to performance such as

application specific noise or crosstalk which may couple into the clock circuits. Therefore, there are no plans to specify performance for

these outputs.

(2) When connecting AUDOSC_IN to an LVCMOS clock source, the LVCMOS clock source output must be disabled anytime AUDOSC is

disabled since AUDOSC_IN has a strong internal pull-down resistor which is turned on when AUDIOOSC is disabled. This requires the

LVCMOS clock source to be disabled by default and output enable controlled by a general purpose output since AUDIOOSC is disabled

by default.

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(3) This output is provided for test and debug purposes only. Performance of this output is not defined due to many complex combinations

of system variables. For example, this output is being sourced from the Main PLL supporting many configuration options that yield

various levels of performance. There are also other unpredictable contributors to performance such as application specific noise or

crosstalk which may couple into the clock circuits. Therefore, there are no plans to specify performance for this output.

(4) This input is used to source the internal system reference clock (SYS_OSCCLK) when the SYSCLKSEL input is driven high.

(5) When connecting SYSOSC_IN to an LVCMOS clock source, the LVCMOS clock source output must be disabled anytime SYSOSC is

disabled since SYSOSC_IN has a strong internal pull-down resistor which is turned on when SYSOSC is disabled.

(6) This input is used to source the internal system reference clock (SYS_OSCCLK) when the SYSCLKSEL input is driven low.

4.3.21.4 Miscellaneous

表 4-25. Miscellaneous Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

SYSCLKSEL⁽¹⁾

DESCRIPTION [2]

ABY BALL [4]

System reference clock source selection input

(1) This input is typically sourced by a pull resistor connected to VSS or DVDD33. If driven by any other source, this input must be driven to

the appropriate logic level at least 500ns before the rising edge of PORn and held at the same logic level as long as the device is

operational.

4.3.21.5 Interrupt Controllers (INTC)

表 4-26. INTC Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

NMIn

Nonmaskable interrupt (Active Low)

For more information, see chapter Interrupts of the Device TRM.

4.3.21.6 Power Supplies

表 4-27. Power Supply Signal Descriptions

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

ABY BALL [4]

AVDDA_ARMPLL

AVDDA_DDRPLL

AVDDA_DSSPLL

AVDDA_ICSSPLL

AVDDA_MAINPLL

AVDDA_NSSPLL

AVDDA_UARTPLL

CVDD

ARM_PLL analog power supply

DDR_PLL analog power supply

DSS_PLL analog power supply

ICSS_PLL analog power supply

MAIN_PLL analog power supply

NSS_PLL analog power supply

UART_PLL analog power supply

Core power supply

PWR

W20

N20

M19

G14

G10

J10, J14, J16, K11,

K13, K15, K17, K9,

L10, L12, L14, L16,

L18, M11, M13, M15,

M17, M9, N10, N12,

N14, N16, P11, P13,

P15, P17, P9, R10,

R12, R14, R16, R18,

R8, T11, T15, T17,

T9, U16

CVDD1

Core fixed power supply

1.8-V I/Os power supply

PWR

M5, J12, N18, N8,

T13

DVDD18

F17, F19, G6, H5, J6,

K19, L20, L6, M7,

U18, U6, V19, W6

Terminal Configuration and Functions

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表 4-27. Power Supply Signal Descriptions (continued)

TYPE [3]

SIGNAL NAME [1]

DESCRIPTION [2]

3.3-V I/Os power supply

ABY BALL [4]

DVDD33

PWR

AA23, E23, F11, F15,

F21, F7, G12, G16,

G20, H11, H13, H15,

H9, J20, P19, P7,

R20, R6, T19, T23,

T7, U20, V21

DVDD33_USB

DVDD_DDR

USB 3.3-V supply

PWR

G18, H17

DDR EMIF I/Os power supply

AD11, AD18, AD5,

AE14, AE8, U10,

U12, U14, U8, V11,

V13, V15, V17, V7,

W16, W18

DDR3_VREFSSTL

DVDD_DDRDLL

LDO_PCIE_CAP⁽¹⁾

LDO_USB_CAP⁽¹⁾

VDDAHV

DDR EMIF reference power supply

DDR EMIF PHY DLL power supply

SERDES LDO output

PWR

CAP

PWR

GND

W10, W14, W8

J8, L8

H19, J18

USB LDO output

PCIe SERDES power supply

Reserved, leave unconnected

Customer OTP eFuse array power supply

AUDIOOSC Kelvin Ground

SYSOSC Kelvin Ground

Ground

VPP

VPP2⁽²⁾

Y21

W21

VSS_OSC_AUDIO

VSS_OSC_SYS

VSS

B17

AD19

A1, A25, AD14, AD8,

AE1, AE11, AE18,

AE25, AE5, C1, E2,

E22, F1, F20, F3, F6,

F8, G11, G13, G15,

G17, G19, G21, G7,

G9, H10, H12, H14,

H16, H18, H20, H6,

H8, J1, J11, J13, J15,

J17, J19, J7, J9, K10,

K12, K14, K16, K18,

K20, K6, K8, L11,

L13, L15, L17, L19,

L7, L9, M10, M12,

M14, M16, M18, M20,

M6, M8, N11, N13,

N15, N17, N19, N21,

N7, N9, P10, P12,

P14, P16, P18, P20,

P6, P8, R11, R13,

R15, R17, R19, R23,

R7, R9, T10, T12,

T14, T16, T18, T20,

T6, T8, U11, U13,

U15, U17, U19, U7,

U9, V10, V12, V14,

V16, V18, V20, V8,

W11, W13, W15,

W17, W7, W9, Y10,

Y23

(1) This pin must always be connected through a 1-µF, ±50% decoupling capacitor with ESR of 10-100 mΩ to VSS with less than 0.5 nH of

loop inductance.

(2) The VPP2 power supply pin is only valid for high-security (66AK2G1xS) devices. The VPP2 power source shall only be enabled while

programming the customer OTP eFuse array and shall be disabled during power-up sequence, normal operation, and power-down

sequence. When disabled, the power source shall not source current to, or sink current from the VPP2 terminal. This power supply pin is

reserved for general purpose (66AK2G1x) devices and shall not be connected to any signal, test point, or printed circuit board trace

when using 66AK2G1x devices.

For more information, see section Power Management in chapter Device Configuration of the Device

TRM.

Terminal Configuration and Functions

66AK2G12

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4.4 Pin Multiplexing

表 4-28 describes the signal multiplexing associated with pins.

注

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with

pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other

layers are associated with peripheral logic functions.

表 4-28, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see

section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Refer to

the respective peripheral chapter of the Device TRM for information associated with peripheral signal multiplexing.

注

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

注

Any balls without an associated pin multiplexing register have a dedicated function that is defined in the MUXMODE "0" column of this

table.

For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter

Device Configuration of the Device TRM.

表 4-28. Pin Multiplexing

MUXMODE AND BOOTSTRAP SETTINGS

ADDRESS OFFSET

BALL NUMBER

SYSCLKSEL

DDR3_A01

DDR3_DQM0

OBSCLK_N

DDR3_D10

DDR3_CLKOUT_P0

PORn

Bootstrap

Y15

AB4

AE15

AA3

AA17

AE7

A19

AB16

DDR3_A12

DDR3_D22

USB0_ID

DDR3_A04

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ADDRESS OFFSET

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

BALL NUMBER

C19

Bootstrap

USB0_TXRTUNE_RKE

LVIN

AE9

DDR3_DQS3_P

RESETFULLn

USB1_VBUS

DDR3_DQS1_N

DDR3_RZQ1

DDR3_CLKOUT_N1

SYSOSC_OUT

MLBP_SIG_P

DDR3_CB02

OBSCLK_P

EMU01

A21

AE4

AD16

AE19

L24

AC11

L22

A20

AD1

AE3

USB1_DM

DDR3_DQS0_P

DDR3_D04

PCIE_REFRES

MLBP_DAT_N

DDR3_D20

K22

AA8

AC14

AB8

AC17

AC6

DDR3_A06

DDR3_D17

DDR3_A08

DDR3_D21

RESETn

AD6

AA9

AB10

AA12

Y16

AA4

AA16

AA5

C17

AB15

D20

DDR3_DQS2_N

DDR3_DQM3

DDR3_D29

DDR3_A13

DDR3_A15

DDR3_D05

DDR3_A11

DDR3_DQM1

AUDOSC_IN

DDR3_A07

USB1_TXRTUNE_RKE

LVIN

DDR3_D13

PCIE_CLK_N

MLBP_CLK_N

L23

Terminal Configuration and Functions

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表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

ADDRESS OFFSET

BALL NUMBER

AD13

DDR3_CEn0

DDR3_D30

USB0_XO

Bootstrap

AB9

D19

AC25

AE16

L21

SYSCLK_N

DDR3_CLKOUT_P1

CPTS_REFCLK_N

DDR3_RZQ0

DDR_CLK_P

DDR3_D15

DDR3_A00

W12

AE24

AB5

AC15

AE10

AA15

M24

DDR3_D25

DDR3_A03

MLBP_SIG_N

PCIE_RXP0

DDR3_BA2

DDR3_D02

TDO

AD17

AC3

AC7

AD9

DDR3_D18

DDR3_DQS3_N

DDR3_D31

TCK

K23

MLBP_DAT_P

DDR3_CBDQM

DDR3_A10

Y11

AB14

Y13

DDR3_WEn

USB0_DP

A18

AD24

Y17

DDR_CLK_N

DDR3_A14

AC8

AC12

AA6

AD7

B19

DDR3_DQM2

DDR3_CB03

DDR3_D08

DDR3_D23

USB0_VBUS

DDR3_CB00

DDR3_D27

DDR3_A05

AA11

AC10

AE17

AE12

AA14

DDR3_CBDQS_P

DDR3_BA0

PCIE_CLK_P

Terminal Configuration and Functions

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ADDRESS OFFSET

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

BALL NUMBER

AC4

Bootstrap

DDR3_D14

DDR3_VREFSSTL

PCIE_TXN0

DDR3_CKE0

DDR3_D12

USB1_ID

AB18

AB6

E20

TRSTn

AC19

AD3

B20

AE6

AB7

M22

SYSOSC_IN

DDR3_D06

USB1_DP

DDR3_DQS2_P

DDR3_D16

EMU00

PCIE_RXN0

MLBP_CLK_P

DDR3_D07

DDR3_D00

AUDOSC_OUT

USB0_DM

M23

AB3

AD2

A17

B18

AB13

DDR3_BA1

TMS

AB17

DDR3_A09

DDR3_D09

DDR3_CLKOUT_N0

DDR3_RESETn

DDR3_CASn

DDR3_D03

PCIE_TXP0

DDR3_CBDQS_N

DDR3_D26

DDR3_RASn

DDR3_DQS0_N

DDR3_ODT0

USB1_XO

AD15

Y18

AC13

AC2

AD12

AD10

AE13

AE2

AA13

C20

TDI

AA10

K21

AA7

AC5

DDR3_D24

CPTS_REFCLK_P

DDR3_D19

DDR3_D11

Terminal Configuration and Functions

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表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

ADDRESS OFFSET

BALL NUMBER

Bootstrap

DDR3_D01

AC16

AB11

AD25

AC9

DDR3_A02

DDR3_CB01

SYSCLK_P

DDR3_D28

AD4

DDR3_DQS1_P

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

0x1000

0x1004

0x1008

0x100C

0x1010

0x1014

0x1018

0x101C

0x1020

0x1024

0x1028

0x102C

0x1030

0x1034

0x1038

0x103C

0x1040

0x1044

0x1048

0x104C

0x1050

0x1054

0x1058

0x105C

0x1060

0x1064

0x1068

PADCONFIG_0

AC21

AE20

AD22

AD20

AE21

AE22

AC20

AD21

AE23

AB20

AA20

AD23

AA21

AB21

AB22

AA22

AB23

AC23

AC22

Y22

GPMC_AD0

GPMC_AD1

GPMC_AD2

GPMC_AD3

GPMC_AD4

GPMC_AD5

GPMC_AD6

GPMC_AD7

GPMC_AD8

GPMC_AD9

GPMC_AD10

GPMC_AD11

GPMC_AD12

GPMC_AD13

GPMC_AD14

GPMC_AD15

GPMC_CLK

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_WEn

GPMC_BEn0_CLE

GPMC_BEn1

GPMC_WAIT0

GPMC_WAIT1

GPMC_WPn

GPMC_DIR

GPMC_CSn0

GPIO0_00

GPIO0_01

GPIO0_02

GPIO0_03

GPIO0_04

GPIO0_05

GPIO0_06

GPIO0_07

GPIO0_08

GPIO0_09

GPIO0_10

GPIO0_11

GPIO0_12

GPIO0_13

GPIO0_14

GPIO0_15

GPIO0_16

GPIO0_17

GPIO0_18

GPIO0_19

GPIO0_20

GPIO0_21

GPIO0_22

GPIO0_23

GPIO0_24

GPIO0_25

GPIO0_26

PADCONFIG_1

PADCONFIG_2

PADCONFIG_3

PADCONFIG_4

PADCONFIG_5

PADCONFIG_6

PADCONFIG_7

PADCONFIG_8

PADCONFIG_9

PADCONFIG_10

PADCONFIG_11

PADCONFIG_12

PADCONFIG_13

PADCONFIG_14

PADCONFIG_15

PADCONFIG_16

PADCONFIG_17

PADCONFIG_18

PADCONFIG_19

PADCONFIG_20

PADCONFIG_21

PADCONFIG_22

PADCONFIG_23

PADCONFIG_24

PADCONFIG_25

PADCONFIG_26

AC24

AB24

Y24

AA24

W25

AA25

AB25

MLB_CLK

MLB_SIG

Terminal Configuration and Functions

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ADDRESS OFFSET

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

PADCONFIG_27

BALL NUMBER

W24

Bootstrap

0x106C

0x1070

0x1074

0x1078

0x107C

0x1080

0x1084

0x1088

GPMC_CSn1

GPMC_CSn2

GPMC_CSn3

DSS_DATA23

DSS_DATA22

DSS_DATA21

DSS_DATA20

DSS_DATA19

MLB_DAT

TIMI1

GPIO0_27

GPIO0_28

GPIO0_29

GPIO0_30

GPIO0_31

GPIO0_32

GPIO0_33

GPIO0_34

PADCONFIG_28

PADCONFIG_29

PADCONFIG_30

PADCONFIG_31

PADCONFIG_32

PADCONFIG_33

PADCONFIG_34

W23

Y25

N23

P25

P24

N24

T25

TIMO1

GPMC_A24

eHRPWM0_A

EMU02

EMU03

EMU04

EMU05

EMU06

BOOTMODE00

BOOTMODE01

BOOTMODE02

BOOTMODE03

GPMC_A23

GPMC_A22

GPMC_A21

GPMC_A20

eHRPWM0_B

eHRPWM_TZn0

eHRPWM0_SYNCI

eHRPWM0_SYNCO

DSS_RFBI_TEVSYNC BOOTMODE04

0x108C

0x1090

0x1094

0x1098

0x109C

0x10A0

0x10A4

0x10A8

0x10AC

0x10B0

0x10B4

0x10B8

0x10BC

0x10C0

0x10C4

0x10C8

0x10CC

0x10D0

0x10D4

0x10D8

PADCONFIG_35

PADCONFIG_36

PADCONFIG_37

PADCONFIG_38

PADCONFIG_39

PADCONFIG_40

PADCONFIG_41

PADCONFIG_42

PADCONFIG_43

PADCONFIG_44

PADCONFIG_45

PADCONFIG_46

PADCONFIG_47

PADCONFIG_48

PADCONFIG_49

PADCONFIG_50

PADCONFIG_51

PADCONFIG_52

PADCONFIG_53

PADCONFIG_54

N22

R24

P23

R22

U25

P21

T24

V25

U24

R21

T22

U22

T21

V24

U23

V23

W22

U21

V22

R25

DSS_DATA18

DSS_DATA17

DSS_DATA16

DSS_DATA15

DSS_DATA14

DSS_DATA13

DSS_DATA12

DSS_DATA11

DSS_DATA10

DSS_DATA9

DSS_DATA8

DSS_DATA7

DSS_DATA6

DSS_DATA5

DSS_DATA4

DSS_DATA3

DSS_DATA2

DSS_DATA1

DSS_DATA0

DSS_VSYNC

GPMC_A19

GPMC_A18

GPMC_A17

GPMC_A16

GPMC_A15

GPMC_A14

GPMC_A13

GPMC_A12

GPMC_A11

GPMC_A10

GPMC_A9

GPMC_A8

GPMC_A7

GPMC_A6

GPMC_A5

GPMC_A4

GPMC_A3

GPMC_A2

GPMC_A1

GPMC_A25

eHRPWM1_A

eHRPWM1_B

eHRPWM_TZn1

eHRPWM2_A

eHRPWM2_B

eHRPWM_TZn2

eQEP0_A

GPIO0_35

GPIO0_36

GPIO0_37

GPIO0_38

GPIO0_39

GPIO0_40

GPIO0_41

GPIO0_42

GPIO0_43

GPIO0_44

GPIO0_45

GPIO0_46

GPIO0_47

GPIO0_48

GPIO0_49

GPIO0_50

GPIO0_51

GPIO0_52

GPIO0_53

EMU07

EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU16

EMU17

EMU18

EMU19

DSS_RFBI_HSYNC1 BOOTMODE05

DSS_RFBI_CSn1

BOOTMODE06

BOOTMODE07

BOOTMODE08

BOOTMODE09

BOOTMODE10

BOOTMODE11

BOOTMODE12

BOOTMODE13

BOOTMODE14

BOOTMODE15

DSS_RFBI_CSn0

DSS_RFBI_DATA15

DSS_RFBI_DATA14

DSS_RFBI_DATA13

DSS_RFBI_DATA12

DSS_RFBI_DATA11

DSS_RFBI_DATA10

DSS_RFBI_DATA9

DSS_RFBI_DATA8

DSS_RFBI_DATA7

DSS_RFBI_DATA6

DSS_RFBI_DATA5

DSS_RFBI_DATA4

DSS_RFBI_DATA3

DSS_RFBI_DATA2

DSS_RFBI_DATA1

DSS_RFBI_DATA0

eQEP0_B

eQEP0_I

eQEP0_S

eQEP1_A

eQEP1_B

eQEP1_I

eQEP1_S

eQEP2_A

NODDR

eQEP2_B

BOOT_RSVD

MAINPLL_OD_SEL

eQEP2_I

eQEP2_S

PR1_eCAP0_eCAP_C GPIO0_54

APIN_APWM_O

DSS_RFBI_TEVSYNC

0x10DC

0x10E0

PADCONFIG_55

PADCONFIG_56

P22

N25

DSS_HSYNC

DSS_PCLK

GPMC_A26

GPMC_A27

GPMC_A0

PR1_eCAP0_eCAP_S GPIO0_55

YNCIN

DSS_RFBI_HSYNC0

PR1_eCAP0_eCAP_S GPIO0_56

YNCOUT

DSS_RFBI_REn

0x10E4

0x10E8

0x10EC

0x10F0

0x10F4

0x10F8

PADCONFIG_57

PADCONFIG_58

PADCONFIG_59

PADCONFIG_60

PADCONFIG_61

PADCONFIG_62

M25

L25

DSS_DE

PR1_EDIO_OUTVALID GPIO0_57

PR0_EDIO_OUTVALID GPIO0_58

GPIO0_59

DSS_RFBI_WEn

DSS_RFBI_A0

DSS_FID

MMC1_DAT7

MMC1_DAT6

MMC1_DAT5

MMC1_DAT4

GPIO0_60

GPIO0_61

GPIO0_62

Terminal Configuration and Functions

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表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

ADDRESS OFFSET

PADCONFIG_63

BALL NUMBER

MMC1_DAT3

MMC1_DAT2

MMC1_DAT1

MMC1_DAT0

MMC1_CLK

MMC1_CMD

MMC1_SDCD

MMC1_SDWP

MMC1_POW

MII_RXCLK

Bootstrap

0x10FC

0x1100

0x1104

0x1108

0x110C

0x1110

0x1114

0x1118

0x111C

0x1120

0x1124

0x1128

0x112C

0x1130

0x1134

0x1138

0x113C

0x1140

0x1144

0x1148

0x114C

0x1150

0x1154

0x1158

GPIO0_63

GPIO0_64

GPIO0_65

GPIO0_66

GPIO0_67

GPIO0_68

GPIO0_69

GPIO0_70

GPIO0_71

GPIO0_72

GPIO0_73

GPIO0_74

GPIO0_75

GPIO0_76

GPIO0_77

GPIO0_78

GPIO0_79

GPIO0_80

GPIO0_81

GPIO0_82

GPIO0_83

GPIO0_84

GPIO0_85

PADCONFIG_64

PADCONFIG_65

PADCONFIG_66

PADCONFIG_67

PADCONFIG_68

PADCONFIG_69

PADCONFIG_70

PADCONFIG_71

PADCONFIG_72

PADCONFIG_73

PADCONFIG_74

PADCONFIG_75

PADCONFIG_76

PADCONFIG_77

PADCONFIG_78

PADCONFIG_79

PADCONFIG_80

PADCONFIG_81

PADCONFIG_82

PADCONFIG_83

PADCONFIG_84

PADCONFIG_85

PADCONFIG_86

A22

A23

B22

C22

D23

F22

B23

C23

B24

A24

F23

B25

G22

C25

C24

RGMII_RXC

PR0_EDIO_DATA3

PR0_EDIO_DATA2

PR0_EDIO_DATA1

PR0_EDIO_DATA0

RGMII_RXD3

eHRPWM3_A

eHRPWM3_B

eHRPWM3_SYNCI

eHRPWM3_SYNCO

MII_RXD3

MII_RXD2

MII_RXD1

MII_RXD0

MII_RXDV

MII_RXER

MII_COL

RGMII_RXD2

RGMII_RXD1

RMII_RXD1

RGMII_RXD0

RMII_RXD0

RMII_RXER

RMII_CRS_DV

RGMII_RXCTL

MII_CRS

MII_TXCLK

RGMII_TXC

SPI3_SCSn0

PR0_eCAP0_eCAP_C GPIO0_86

APIN_APWM_O

0x115C

0x1160

0x1164

0x1168

0x116C

0x1170

0x1174

0x1178

0x117C

0x1180

PADCONFIG_87

PADCONFIG_88

PADCONFIG_89

PADCONFIG_90

PADCONFIG_91

PADCONFIG_92

PADCONFIG_93

PADCONFIG_94

PADCONFIG_95

PADCONFIG_96

E25

E24

F25

F24

D25

G25

G24

G23

H25

H24

SPI3_SCSn1

SPI3_CLK

PR0_UART0_RXD

PR0_UART0_TXD

PR0_UART0_CTSN

PR0_UART0_RTSN

GPIO0_87

GPIO0_88

GPIO0_89

GPIO0_90

GPIO0_91

GPIO0_92

GPIO0_93

GPIO0_94

GPIO0_95

SPI3_SOMI

SPI3_SIMO

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

RGMII_TXCTL

MII_TXD3

MII_TXD2

MII_TXD1

MII_TXD0

MII_TXEN

MII_TXER

RMII_TXD1

RMII_TXD0

RMII_TXEN

PR0_eCAP0_eCAP_S GPIO0_96

YNCIN

eHRPWM_TZn3

0x1184

PADCONFIG_97

D24

RMII_REFCLK

PR0_eCAP0_eCAP_S

YNCOUT

0x1188

0x118C

PADCONFIG_98

PADCONFIG_99

MDIO_DATA

MDIO_CLK

GPIO0_97

GPIO0_98

Terminal Configuration and Functions

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ADDRESS OFFSET

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

PADCONFIG_100

BALL NUMBER

SPI0_SCSn0

SPI0_SCSn1

SPI0_CLK

Bootstrap

0x1190

0x1194

0x1198

0x119C

0x11A0

0x11A4

0x11A8

0x11AC

0x11B0

0x11B4

0x11B8

0x11BC

0x11C0

0x11C4

0x11C8

0x11CC

0x11D0

0x11D4

0x11D8

0x11DC

0x11E0

0x11E4

0x11E8

0x11EC

0x11F0

0x11F4

0x11F8

0x11FC

0x1200

0x1204

0x1208

0x120C

0x1210

0x1214

0x1218

0x121C

0x1220

0x1224

0x1228

PADCONFIG_101

PADCONFIG_102

PADCONFIG_103

PADCONFIG_104

PADCONFIG_105

PADCONFIG_106

PADCONFIG_107

PADCONFIG_108

PADCONFIG_109

PADCONFIG_110

PADCONFIG_111

PADCONFIG_112

PADCONFIG_113

PADCONFIG_114

PADCONFIG_115

PADCONFIG_116

PADCONFIG_117

PADCONFIG_118

PADCONFIG_119

PADCONFIG_120

PADCONFIG_121

PADCONFIG_122

PADCONFIG_123

PADCONFIG_124

PADCONFIG_125

PADCONFIG_126

PADCONFIG_127

PADCONFIG_128

PADCONFIG_129

PADCONFIG_130

PADCONFIG_131

PADCONFIG_132

PADCONFIG_133

PADCONFIG_134

PADCONFIG_135

PADCONFIG_136

PADCONFIG_137

PADCONFIG_138

GPIO0_99

SPI0_SOMI

SPI0_SIMO

SPI1_SCSn0

SPI1_SCSn1

SPI1_CLK

GPIO0_100

SPI1_SOMI

SPI1_SIMO

SPI2_SCSn0

SPI2_SCSn1

SPI2_CLK

GPIO0_101

GPIO0_102

GPIO0_103

GPIO0_104

GPIO0_105

SPI2_SOMI

SPI2_SIMO

UART0_RXD

UART0_TXD

UART0_CTSn

UART0_RTSn

UART1_RXD

UART1_TXD

UART1_CTSn

UART1_RTSn

UART2_RXD

UART2_TXD

UART2_CTSn

UART2_RTSn

DCAN0_TX

DCAN0_RX

QSPI_CLK

TIMI0

GPIO0_106

GPIO0_107

GPIO1_48

GPIO1_49

GPIO1_50

GPIO1_51

GPIO1_52

GPIO1_53

GPIO1_54

GPIO1_55

GPIO1_56

GPIO1_57

GPIO1_58

GPIO1_59

GPIO1_60

GPIO1_61

GPIO1_62

GPIO1_63

GPIO1_64

GPIO1_65

GPIO1_66

GPIO1_67

TIMO0

E21

D21

D22

C21

PR1_EDIO_DATA3

PR1_EDIO_DATA2

PR1_EDIO_DATA1

PR1_EDIO_DATA0

UART0_DCDn

UART0_DSRn

UART0_DTRn

UART0_RIN

CPTS_HW1_TSPUSH

CPTS_HW2_TSPUSH

CPTS_TS_SYNC

CPTS_TS_COMP

K25

K24

J23

J22

J21

J24

J25

H23

H22

H21

QSPI_RCLK

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_CSn0

QSPI_CSn1

QSPI_CSn2

QSPI_CSn3

CLKOUT

DCAN1_TX

DCAN1_RX

PR1_UART0_CTSN

PR1_UART0_RTSN

USB0_EXT_TRIGGER

USB1_EXT_TRIGGER

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

ADDRESS OFFSET

PADCONFIG_139

BALL NUMBER

Bootstrap

0x122C

0x1230

0x1234

0x1238

0x123C

0x1240

0x1244

0x1248

0x124C

0x1250

0x1254

0x1258

0x125C

0x1260

0x1264

0x1268

0x126C

0x1270

0x1274

0x1278

PR0_PRU0_GPO0

PR0_PRU0_GPO1

PR0_PRU0_GPO2

PR0_PRU0_GPO3

PR0_PRU0_GPO4

PR0_PRU0_GPO5

PR0_PRU0_GPO6

PR0_PRU0_GPO7

PR0_PRU0_GPO8

PR0_PRU0_GPO9

PR0_PRU0_GPO10

PR0_PRU0_GPO11

PR0_PRU0_GPO12

PR0_PRU0_GPO13

PR0_PRU0_GPO14

PR0_PRU0_GPO15

PR0_PRU0_GPO16

PR0_PRU0_GPO17

PR0_PRU0_GPO18

PR0_PRU0_GPO19

PR0_PRU0_GPI0

PR0_PRU0_GPI1

PR0_PRU0_GPI2

PR0_PRU0_GPI3

PR0_PRU0_GPI4

PR0_PRU0_GPI5

PR0_PRU0_GPI6

PR0_PRU0_GPI7

PR0_PRU0_GPI8

PR0_PRU0_GPI9

PR0_PRU0_GPI10

PR0_PRU0_GPI11

PR0_PRU0_GPI12

PR0_PRU0_GPI13

PR0_PRU0_GPI14

PR0_PRU0_GPI15

PR0_PRU0_GPI16

PR0_PRU0_GPI17

PR0_PRU0_GPI18

PR0_PRU0_GPI19

GPIO0_108

MCASP2_AXR0

MCASP2_AXR1

MCASP2_AXR2

MCASP2_AXR3

MCASP2_AXR4

MCASP2_AXR5

MCASP2_ACLKR

MCASP2_AFSR

MCASP2_AHCLKR

MCASP2_AMUTE

MCASP2_AFSX

MCASP2_AHCLKX

MCASP2_ACLKX

MCASP1_ACLKR

MCASP1_AFSR

MCASP1_AHCLKR

MCASP1_ACLKX

MCASP1_AFSX

MCASP1_AHCLKX

MCASP1_AMUTE

PADCONFIG_140

PADCONFIG_141

PADCONFIG_142

PADCONFIG_143

PADCONFIG_144

PADCONFIG_145

PADCONFIG_146

PADCONFIG_147

PADCONFIG_148

PADCONFIG_149

PADCONFIG_150

PADCONFIG_151

PADCONFIG_152

PADCONFIG_153

PADCONFIG_154

PADCONFIG_155

PADCONFIG_156

PADCONFIG_157

PADCONFIG_158

GPIO0_109

GPIO0_110

GPIO0_111

GPIO0_112

GPIO0_113

GPIO0_114

GPIO0_115

GPIO0_116

GPIO0_117

GPIO0_118

GPIO0_119

GPIO0_120

GPIO0_121

GPIO0_122

GPIO0_123

GPIO0_124

GPIO0_125

XREFCLK

PR1_UART0_RXD

PR0_EDC_LATCH0_IN GPIO0_126

PR0_EDC_SYNC0_OU GPIO0_127

0x127C

0x1280

0x1284

0x1288

0x128C

0x1290

0x1294

0x1298

0x129C

0x12A0

0x12A4

0x12A8

0x12AC

0x12B0

0x12B4

0x12B8

0x12BC

0x12C0

PADCONFIG_159

PADCONFIG_160

PADCONFIG_161

PADCONFIG_162

PADCONFIG_163

PADCONFIG_164

PADCONFIG_165

PADCONFIG_166

PADCONFIG_167

PADCONFIG_168

PADCONFIG_169

PADCONFIG_170

PADCONFIG_171

PADCONFIG_172

PADCONFIG_173

PADCONFIG_174

PADCONFIG_175

PADCONFIG_176

PR0_PRU1_GPO0

PR0_PRU1_GPO1

PR0_PRU1_GPO2

PR0_PRU1_GPO3

PR0_PRU1_GPO4

PR0_PRU1_GPO5

PR0_PRU1_GPO6

PR0_PRU1_GPO7

PR0_PRU1_GPO8

PR0_PRU1_GPO9

PR0_PRU1_GPO10

PR0_PRU1_GPO11

PR0_PRU1_GPO12

PR0_PRU1_GPO13

PR0_PRU1_GPO14

PR0_PRU1_GPO15

PR0_PRU1_GPO16

PR0_PRU1_GPO17

PR0_PRU1_GPI0

PR0_PRU1_GPI1

PR0_PRU1_GPI2

PR0_PRU1_GPI3

PR0_PRU1_GPI4

PR0_PRU1_GPI5

PR0_PRU1_GPI6

PR0_PRU1_GPI7

PR0_PRU1_GPI8

PR0_PRU1_GPI9

PR0_PRU1_GPI10

PR0_PRU1_GPI11

PR0_PRU1_GPI12

PR0_PRU1_GPI13

PR0_PRU1_GPI14

PR0_PRU1_GPI15

PR0_PRU1_GPI16

PR0_PRU1_GPI17

GPIO0_128

GPIO0_129

GPIO0_130

GPIO0_131

GPIO0_132

GPIO0_133

GPIO0_134

GPIO0_135

GPIO0_136

GPIO0_137

GPIO0_138

GPIO0_139

GPIO0_140

GPIO0_141

GPIO0_142

GPIO0_143

GPIO1_00

MCASP1_AXR0

MCASP1_AXR1

MCASP1_AXR2

MCASP1_AXR3

MCASP1_AXR4

MCASP1_AXR5

MCASP1_AXR6

MCASP1_AXR7

MCASP1_AXR8

MCASP1_AXR9

MCASP0_AMUTE

MCASP0_ACLKR

MCASP0_AFSR

MCASP0_AHCLKR

MCASP0_ACLKX

MCASP0_AFSX

MCASP0_AHCLKX

MCASP0_AXR0

PR1_UART0_TXD

GPIO1_01

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ADDRESS OFFSET

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

PADCONFIG_177

BALL NUMBER

Bootstrap

0x12C4

0x12C8

PR0_PRU1_GPO18

PR0_PRU1_GPO19

PR0_PRU1_GPI18

PR0_PRU1_GPI19

PR0_EDC_LATCH1_IN GPIO1_02

MCASP0_AXR1

MCASP0_AXR2

PADCONFIG_178

B10

PR0_EDC_SYNC1_OU GPIO1_03

0x12CC

0x12D0

0x12D4

0x12D8

0x12DC

0x12E0

0x12E4

0x12E8

0x12EC

0x12F0

0x12F4

0x12F8

0x12FC

0x1300

0x1304

0x1308

0x130C

0x1310

0x1314

0x1318

0x131C

0x1320

PADCONFIG_179

PADCONFIG_180

PADCONFIG_181

PADCONFIG_182

PADCONFIG_183

PADCONFIG_184

PADCONFIG_185

PADCONFIG_186

PADCONFIG_187

PADCONFIG_188

PADCONFIG_189

PADCONFIG_190

PADCONFIG_191

PADCONFIG_192

PADCONFIG_193

PADCONFIG_194

PADCONFIG_195

PADCONFIG_196

PADCONFIG_197

PADCONFIG_198

PADCONFIG_199

PADCONFIG_200

A10

C10

E10

D10

F10

C11

D11

E11

F12

E12

C12

B11

B12

A12

A11

A13

B13

F13

C13

E13

D12

D13

PR0_MDIO_DATA

PR0_MDIO_MDCLK

PR1_PRU0_GPO0

PR1_PRU0_GPO1

PR1_PRU0_GPO2

PR1_PRU0_GPO3

PR1_PRU0_GPO4

PR1_PRU0_GPO5

PR1_PRU0_GPO6

PR1_PRU0_GPO7

PR1_PRU0_GPO8

PR1_PRU0_GPO9

PR1_PRU0_GPO10

PR1_PRU0_GPO11

PR1_PRU0_GPO12

PR1_PRU0_GPO13

PR1_PRU0_GPO14

PR1_PRU0_GPO15

PR1_PRU0_GPO16

PR1_PRU0_GPO17

PR1_PRU0_GPO18

PR1_PRU0_GPO19

GPIO1_04

GPIO1_05

GPIO1_06

GPIO1_07

GPIO1_08

GPIO1_09

MCASP0_AXR3

MCASP0_AXR4

MCASP0_AXR5

MCASP0_AXR6

MCASP0_AXR7

MCASP0_AXR8

MCASP0_AXR9

MCASP0_AXR10

MCASP0_AXR11

MCASP0_AXR12

MCASP0_AXR13

MCASP0_AXR14

MCASP0_AXR15

PR1_PRU0_GPI0

PR1_PRU0_GPI1

PR1_PRU0_GPI2

PR1_PRU0_GPI3

PR1_PRU0_GPI4

PR1_PRU0_GPI5

PR1_PRU0_GPI6

PR1_PRU0_GPI7

PR1_PRU0_GPI8

PR1_PRU0_GPI9

PR1_PRU0_GPI10

PR1_PRU0_GPI11

PR1_PRU0_GPI12

PR1_PRU0_GPI13

PR1_PRU0_GPI14

PR1_PRU0_GPI15

PR1_PRU0_GPI16

PR1_PRU0_GPI17

PR1_PRU0_GPI18

PR1_PRU0_GPI19

MMC0_POW

MMC0_SDWP

MMC0_SDCD

MMC0_DAT7

MMC0_DAT6

MMC0_DAT5

MMC0_DAT4

MMC0_DAT3

MMC0_DAT2

MMC0_DAT1

MMC0_DAT0

MMC0_CLK

GPIO1_10

GPIO1_11

GPIO1_12

GPIO1_13

GPIO1_14

GPIO1_15

GPIO1_16

GPIO1_17

GPIO1_18

GPIO1_19

GPIO1_20

GPIO1_21

GPIO1_22

GPIO1_23

MMC0_CMD

eHRPWM_TZn4

eHRPWM4_A

eHRPWM4_B

eHRPWM_SOCA

PR1_EDC_LATCH0_IN GPIO1_24

PR1_EDC_SYNC0_OU GPIO1_25

0x1324

0x1328

0x132C

0x1330

0x1334

0x1338

0x133C

0x1340

0x1344

0x1348

0x134C

0x1350

0x1354

PADCONFIG_201

PADCONFIG_202

PADCONFIG_203

PADCONFIG_204

PADCONFIG_205

PADCONFIG_206

PADCONFIG_207

PADCONFIG_208

PADCONFIG_209

PADCONFIG_210

PADCONFIG_211

PADCONFIG_212

PADCONFIG_213

A14

B14

C14

E14

D14

A15

F14

B15

C15

D15

A16

E15

B16

PR1_PRU1_GPO0

PR1_PRU1_GPO1

PR1_PRU1_GPO2

PR1_PRU1_GPO3

PR1_PRU1_GPO4

PR1_PRU1_GPO5

PR1_PRU1_GPO6

PR1_PRU1_GPO7

PR1_PRU1_GPO8

PR1_PRU1_GPO9

PR1_PRU1_GPO10

PR1_PRU1_GPO11

PR1_PRU1_GPO12

PR1_PRU1_GPI0

PR1_PRU1_GPI1

PR1_PRU1_GPI2

PR1_PRU1_GPI3

PR1_PRU1_GPI4

PR1_PRU1_GPI5

PR1_PRU1_GPI6

PR1_PRU1_GPI7

PR1_PRU1_GPI8

PR1_PRU1_GPI9

PR1_PRU1_GPI10

PR1_PRU1_GPI11

PR1_PRU1_GPI12

GPIO1_26

GPIO1_27

GPIO1_28

GPIO1_29

GPIO1_30

GPIO1_31

GPIO1_32

GPIO1_33

GPIO1_34

MCBSP_DR

MCBSP_DX

MCBSP_FSX

MCBSP_CLKX

GPIO1_35

GPIO1_36

GPIO1_37

GPIO1_38

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

表 4-28. Pin Multiplexing (continued)

MUXMODE AND BOOTSTRAP SETTINGS

ADDRESS OFFSET

PADCONFIG_214

BALL NUMBER

C16

Bootstrap

0x1358

0x135C

0x1360

0x1364

0x1368

0x136C

0x1370

PR1_PRU1_GPO13

PR1_PRU1_GPO14

PR1_PRU1_GPO15

PR1_PRU1_GPO16

PR1_PRU1_GPO17

PR1_PRU1_GPO18

PR1_PRU1_GPO19

PR1_PRU1_GPI13

PR1_PRU1_GPI14

PR1_PRU1_GPI15

PR1_PRU1_GPI16

PR1_PRU1_GPI17

PR1_PRU1_GPI18

PR1_PRU1_GPI19

MCBSP_FSR

MCBSP_CLKR

GPIO1_39

GPIO1_40

GPIO1_41

GPIO1_42

GPIO1_43

PADCONFIG_215

PADCONFIG_216

PADCONFIG_217

PADCONFIG_218

PADCONFIG_219

PADCONFIG_220

D17

C18

D16

F16

E17

E16

eHRPWM_TZn5

eHRPWM5_A

eHRPWM5_B

eHRPWM_SOCB

PR1_EDC_LATCH1_IN GPIO1_44

PR1_EDC_SYNC1_OU GPIO1_45

0x1374

0x1378

PADCONFIG_221

PADCONFIG_222

E18

D18

PR1_MDIO_DATA

GPIO1_46

eCAP0_IN_APWM0_O

PR1_MDIO_MDCLK

GPIO1_47

eCAP1_IN_APWM1_O

0x1394

0x1398

0x139C

0x13AC

0x13B0

0x13B4

0x13B8

0x1408

0x140C

PADCONFIG_229

PADCONFIG_230

PADCONFIG_231

PADCONFIG_235

PADCONFIG_236

PADCONFIG_237

PADCONFIG_238

PADCONFIG_258

PADCONFIG_259

NMIn

LRESETn

LRESETNMIENn

RESETSTATn

BOOTCOMPLETE

SYSCLKOUT

OBSPLL_LOCK

USB0_DRVVBUS

USB1_DRVVBUS

M21

E19

B21

Terminal Configuration and Functions

66AK2G12

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ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

4.5 Connections for Unused Pins

This section describes the unused/reserved balls connection requirements.

注

All power balls must be supplied with the voltages specified in Section 5.4, Recommended

Operating Conditions.

表 4-29. Unused Balls Specific Connection Requirements⁽²⁾

Balls

Connection Requirements

Each of these balls must be connected to VSS through a separate

external pull resistor to insure these balls are held to a valid logic low

level if unused

L4 / AD1 / AD4 / AE6 / AE9 / AE12 / M2 / N4 / M1 / N2 / P2 / N1 /

T1 / D24 / L23

Each of these balls must be connected to the corresponding power

supply through a separate external pull resistor to insure these balls

are held to a valid logic high level if unused⁽¹⁾

L3 / W1 / W3 / K4 / AE2 / AE4 / AD6 / AD9 / AD12 / U5 / W5 / V6 /

W4 / V5 / V4 / M23 / M3 / P1 / T4 / L5 / W2 / M22 / L22

(1) To determine which power supply is associated with any IO refer to 表 4-1, Pin Attributes.

(2) Unused connection requirements for oscillator and LVDS clock inputs are defined in the respective section of Clock Specifications.

注

The following balls are reserved: AA19 (RSV1) / AB19 (RSV2) / Y20 (RSV3) / W19 (RSV4) /

D2 (RSV5) / G3 (RSV7) / F18 (RSV8) / H2 (RSV9) / AA18 (RSV10) / Y19 (RSV11) / Y14

(RSV12) / AC18 (RSV19) / AB12 (RSV20) / Y12 (RSV21)

These balls must be left unconnected.

注

The following ball is reserved: L2 (RSV6)

This ball must be connected to VSS through a separate external pull resistor to insure it is

held to a valid logic low level.

注

The following balls are reserved: Y1 (RSV13) / AA1 (RSV14) / AB1 (RSV15) / AA2 (RSV16) /

AB2 (RSV17) / AC1 (RSV18)

Each of these balls must be connected to DVDD18 through a separate external pull resistor

to insure they are held to a valid logic high level.

Terminal Configuration and Functions

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

注

All other unused signal balls with a Pad Configuration Register can be left unconnected with

their multiplexing mode set to GPIO input and internal pulldown resistor enabled.

Unused balls are defined as those which only connect to a PCB solder pad. This is the only

use case where internal pull resistors are allowed as the only source/sink to hold a valid logic

level.

Any balls connected to a via, test point, or PCB trace are considered used and must not

depend on the internal pull resistor to hold a valid logic level.

Internal pull resistors are weak and may not source enough current to maintain a valid logic

level for some operating conditions. This may be the case when connected to components

with leakage to the opposite logic level, or when external noise sources couple to signal

traces attached to balls which are only pulled to a valid logic level by the internal resistor.

Therefore, external pull resistors may be required to hold a valid logic level on balls with

external connections.

If balls are allowed to float between valid logic levels, the input buffer may enter a high-

current state which could damage the IO cell.

注

All other unused signal balls without Pad Configuration Register can be left unconnected.

Terminal Configuration and Functions

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

5 Specifications

5.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETERS

MIN

-0.3

MAX UNIT

V_SUPPLY(steady-state) Supply steady state voltage

ranges

CVDD

1.3

CVDD1

VPP2⁽⁵⁾

1.98

2.45

3.63

AVDDA_DDRPLL

AVDDA_DSSPLL

AVDDA_MAINPLL

AVDDA_NSSPLL

AVDDA_UARTPLL

AVDDA_ICSSPLL

AVDDA_ARMPLL

DVDD_DDR

DVDD_DDRDLL

VDDAHV

DVDD18

DVDD33

DVDD33_USB

All IOs which are not fail-safe

V_IO(steady-state)

Non-fail-safe IO steady-state

voltage ranges⁽³⁾⁽⁶⁾

IO supply

voltage + 0.3

DDR3_VREFSSTL

0.49 ×

0.51 ×

DVDD_DDR DVDD_DDR

Fail-safe IO steady-state

voltage ranges⁽⁷⁾

USB0_VBUS

USB1_VBUS

All supplies except VPP2

VPP2

5.25

1 × 10⁵

0.6 × 10⁵

Maximum slew rate

V/s

V_IO(transient

overshoot and

undershoot)

IO transient voltage ranges

(transient overshoot and

undershoot)⁽⁴⁾

I2C IOs⁽⁸⁾

10% overshoot / undershoot

for 10% of signal duty cycle

(see 图 5-1)

All other IOs

20% overshoot / undershoot

for 20% of signal duty cycle

(see 图 5-2)

T_STG

Storage temperature after soldered onto PC board

-65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4, Recommended

Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Refer to 表 4-1, Pin Attributes to determine which power supply is associated with an IO.

(4) Overshoot/Undershoot percentage relative to IO operating values - for example the maximum overshoot value for a standard LVCMOS

IO operating at 1.8 V is DVDD18 + (0.20 × DVDD18) and maximum undershoot value would be VSS - (0.20 × DVDD18).

(5) The VPP2 power supply pin is only valid for high-security (66AK2G1xS) devices. The VPP2 power source shall only be enabled while

programming the customer OTP eFuse array and shall be disabled during power-up sequence, normal operation, and power-down

sequence. When disabled, the power source shall not source current to, or sink current from the VPP2 terminal. This power supply pin is

reserved for general purpose (66AK2G1x) devices and shall not be connected to any signal, test point, or printed circuit board trace

when using 66AK2G1x devices.

Specifications

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

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(6) This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage. For

example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be

–0.3 V to +0.3 V. Apply special attention anytime peripheral devices are not powered from the same power sources used to power the

respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including

power supply ramp-up and ramp-down sequences.

(7) This parameter is associated with a fail-safe IO and does not have a dependence on any IO supply voltage.

(8) Designing a system that is able to meet the I2C overshoot/undershoot limit defined by this parameter should not be an issue since the

I2C specification defines a minimum rise/fall time which minimizes overshoots and undershoots. However, special design precautions

may need to be taken if the I2C IOs are connected to other devices which are not compliant to the minimum rise/fall time parameters

defined in the I2C specification.

T_overshoot

Max Overshoot = VDD + (0.1VDD)

VDD (Supply voltage of corresponding

I/O power supply)

T_period

VSS

Max Undershoot = VSS - (0.1VDD)

T_undershoot

Tovershoot + Tundershoot < 10% of Tperiod

SPRSP07_TRAN_01

图 5-1. I2C I/O transient voltage ranges

T_overshoot

Max Overshoot = VDD + (0.2VDD)

VDD (Supply voltage of corresponding

I/O power supply)

T_period

VSS

Max Undershoot = VSS - (0.2VDD)

T_undershoot

Tovershoot + Tundershoot < 20% of Tperiod

SPRSP07_TRAN_01

图 5-2. All other I/Os transient voltage ranges

5.2 ESD Ratings

VALUE

±2000

±1000

UNIT

All balls (except M5)

Ball M5

Human-body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

All balls (except H5, A1, A25,

AE1, and AE25)

Electrostatic

discharge

±500

±250

±750

V_(ESD)

Charged-device model (CDM), per JEDEC

specification JESD22-C101⁽²⁾

Ball H5

Corner balls (A1, A25, AE1,

and AE25)

Specifications

66AK2G12

www.ti.com.cn

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On-Hour (POH) Limits^(1)(2)(3)

COMMERCIAL TEMPERATURE RANGE

EXTENDED TEMPERATURE RANGE

AUTOMOTIVE TEMPERATURE RANGE

JUNCTION TEMP

LIFETIME (POH)

(Tj)

JUNCTION TEMP

LIFETIME (POH)

(Tj)

JUNCTION TEMP

LIFETIME (POH)

(Tj)

0°C to 90°C

100000

-40°C to 105°C

100000

Automotive Profile⁽⁴⁾

20000

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms

and conditions for TI semiconductor products.

(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures.

(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.

(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,

and 10%@125°C.

5.4 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)⁽⁴⁾⁽⁷⁾

MIN⁽¹⁾

NOM

MAX⁽¹⁾

UNIT

INPUT POWER SUPPLY VOLTAGE RANGE

Device Speed 60

Device Speed 100

Device Speed 60

Device Speed 100

0.855

0.95

0.855

0.95

1.71

1.28

1.71

3.135

0.49 ×

0.9

0.945

1.05

0.945

1.05

1.89

1.42

1.89

3.465

0.51 ×

CVDD

Core voltage domain supply

0.9

CVDD1

Core memory array power supply

VPP2⁽³⁾

Supply voltage range for the eFuse ROM domain

DDR PLL supply

1.80

1.35

1.80

3.3

AVDDA_DDRPLL

AVDDA_DSSPLL

AVDDA_MAINPLL

AVDDA_NSSPLL

AVDDA_UARTPLL

AVDDA_ICSSPLL

AVDDA_ARMPLL

DVDD_DDRDLL

VDDAHV

DSS PLL supply

CORE PLL supply

NSS PLL supply

UART PLL supply

ICSS PLL supply

ARM PLL supply

DDR EMIF PHY DLL supply

PCIe SERDES 1.8-V supply

DDR EMIF IO supply when using DDR EMIF

DDR EMIF IO supply when not using DDR EMIF⁽⁶⁾

1.8 V IO supply

DVDD_DDR

DVDD18

DVDD33

3.3 V IO supply

DVDD33_USB

USB 3.3-V supply

3.3

0.5 ×

DDR3_VREFSSTL

DDR EMIF reference input

DVDD_DDR DVDD_DDR DVDD_DDR

USB0_VBUS

USB1_VBUS

USB0_ID

USB0 VBUS comparator input

USB1 VBUS comparator input

5.0

5.25

5.0

(5)

USB1_ID

Automotive

–40

125

105

Operating junction temperature

range

(2)

T_J

Extended

°C

Commercial

Specifications

66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

www.ti.com.cn

(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement

includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.

(2) Refer to Section 5.3, Power-On-Hour (POH) Limits.

(3) The VPP2 power supply pin is only valid for high-security (66AK2G1xS) devices. The VPP2 power source shall only be enabled while

programming the customer OTP eFuse array and shall be disabled during power-up sequence, normal operation, and power-down

sequence. When disabled, the power source shall not source current to, or sink current from the VPP2 terminal. This power supply pin is

reserved for general purpose (66AK2G1x) devices and shall not be connected to any signal, test point, or printed circuit board trace

when using 66AK2G1x devices.

(4) All voltage values are with respect to VSS, unless otherwise noted.

(5) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring voltage of

this terminal relative to VSS. This allows the USB PHY to measure resistance of the attached ID signal. The terminal should never be

connected to any external voltage source.

(6) When DDR EMIF is not being used, the DVDD_DDR supply may be connected to a 1.8 V power source to eliminate the 1.35 V power

source which is required when using DDR EMIF.

(7) For details of additional power supply and reference voltage input requirements, see 节 7.3, Power Distribution Network (PDN)

Implementation Guidance.

5.5 Operating Performance Points

This section describes the maximum operating conditions of the device.

表 5-1 describes the operating performance point for each device speed grade.

表 5-1. Supported Max Frequency

Maximum Frequency

(MHz)

Subsystem (PLL Output)

Arm A15

(ARM_PLLOUT)

600

C66x

(CHIP_CLK1)

600

DDR EMIF

(DDR_PLLOUT)

400 (DDR3-800)

533 (DDR3-1066)

Device Speed 60

Device Speed 100

1000

5.6 Power Consumption Summary

Power consumption of this device depends on several operating parameters such as operating voltages,

frequencies, and temperature. Power consumption also varies by end applications that determine the

overall processor, MPU/DSP, and peripheral activity. For more specific power consumption details, see

66AK2G12 Power Estimation Tool [literature number SPRACD9]. This document references a

spreadsheet for estimating power based on parameters that closely resemble the end application to

generate a realistic estimate of power consumption based on use-case and operating conditions.

5.7 Electrical Characteristics

注

The interfaces or signals described in 表 5-2 through 表 5-10 correspond to the interfaces or

signals available in multiplexing mode 0 (Primary Function).

All interfaces or signals multiplexed on the balls described in these tables have the same DC

electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in

which case different DC electrical characteristics are specified for the different multiplexing

modes (Functions).

Specifications

66AK2G12

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表 5-2. DDR3L SSTL DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BALL NAMES in MUXMODE 0:

DDR3_DQM[3:0], DDR3_CB[03:00], DDR3_CBDQM, DDR3_D[31:00], DDR3_CEn0, DDR3_BA[2:0], DDR3_A[15:00], DDR3_CASn,

DDR3_RASn, DDR3_WEn, DDR3_CKE0, DDR3_ODT0, DDR3_RESETn, DDR3_DQS0_P, DDR3_DQS0_N, DDR3_DQS1_P,

DDR3_DQS1_N, DDR3_DQS2_P, DDR3_DQS2_N, DDR3_DQS3_P, DDR3_DQS3_N, DDR3_CLKOUT_P0, DDR3_CLKOUT_N0,

DDR3_CLKOUT_P1, DDR3_CLKOUT_N1, DDR3_CBDQS_P, DDR3_CBDQS_N

BALL NUMBERS: AB4, AA5, AC8, AA9, AA11, AB11, AC11, AC12, Y11, AD2, Y4, AC3, AC2, AE3, AA4, AD3, AB3, AA6, Y7, Y6, AC5,

AB6, Y5, AC4, AB5, AB7, AB8, AC7, AA7, AA8, AC6, AE7, AD7, AA10, AE10, AD10, AC10, AC9, AB10, AB9, Y8, AD13, AA14, AB13,

AD17, AC15, Y15, AC16, AA15, AB16, AE17, AC14, AB15, AC17, AB17, AB14, AA16, AA17, AA12, Y17, Y16, AC13, AE13, Y13, AB18,

AA13, Y18, AD1, AE2, AD4, AE4, AE6, AD6, AE9, AD9, AE15, AD15, AE16, AD16, AE12, AD12

V_OH

V_OL

V_IH

V_IL

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

DVDD_DDR = 1.35 V

(I_OH= -8 mA)

DVDD_DDR – 0.4

DVDD_DDR = 1.35 V

(I_OL= 8 mA)

0.4

DVDD_DDR = 1.35 V DDR3_VREFSSTL +

0.09

DVDD_DDR = 1.35 V

DDR3_VREFSSTL –

0.09

表 5-3. I2C OPEN DRAIN DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

BALL NAMES in MUXMODE 0:

I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, I2C2_SCL, I2C2_SDA

BALL NUMBERS: U5, W5, V6, W4, V5, V4

(I²C STANDARD MODE / FAST MODE – 3.3 V)

V_IH

V_IL

High-level input voltage

Low-level input voltage

Hysteresis

0.7 × VDDS⁽¹⁾

0.05 × VDDS⁽¹⁾

0.3 × VDDS⁽¹⁾

V_HYS

I_IN

—

Input leakage current. This value represents the maximum

current flowing in or out of the pin while the output driver is

disabled and the input is swept from VSS to VDD.

µA

V_OL

Low-level output voltage at 3-mA sink current

0.4

(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

表 5-4. Oscillators DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)⁽²⁾

PARAMETER

MIN

0.65 × VDDS⁽¹⁾

0.9

TYP

MAX UNIT

BALL NAMES in MUXMODE 0:

AUDOSC_IN, SYSOSC_IN

BALL NUMBERS: C17, AC19

V_IH

V_IL

I_IN

Input high-level threshold

Input low-level threshold

Input leakage current

0.35 × VDDS⁽¹⁾

Oscillator enabled, internal pull-down

±8

µA

disabled, VSS ≤ V_I≤ VDDS⁽¹⁾

Oscillator disabled, internal pull-down

enabled, V_I= VDDS⁽¹⁾

4.5

(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

(2) This table only defines input characteristics of the oscillator when being used with an LVCMOS clock source.

Specifications

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表 5-5. LVDS Input Buffer DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

BALL NAMES in MUXMODE 0:

SYSCLK_P, SYSCLK_N, DDR_CLK_N, DDR_CLK_P, CPTS_REFCLK_N, CPTS_REFCLK_P

BALL NUMBERS: AD25, AC25, AD24, AE24, L21, K21

V_I

Input Voltage

0.1

VDDS⁽¹⁾

VDDS⁽¹⁾– 0.1

V_CM

V_IDH

V_IDL

V_HYS

R_I

Common mode input voltage

Input Differential High Voltage

Input Differential Low Voltage

Input Differential Hysteresis Voltage

Input Resistance

100

-100

129

(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

表 5-6. LVDS Output Buffer DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

BALL NAMES in MUXMODE 0:

OBSCLK_N, OBSCLK_P

BALL NUMBERS: L1, K1

V_OH

V_OL

Output High Voltage

Differential Load = 100 Ω

1.5

Output Low Voltage

0.9

1.125

250

V_CM

V_ODH

V_ODL

Common mode output voltage

Output Differential High Voltage

Output Differential Low Voltage

1.275

450

Differential Load = 100 Ω

-450

-250

表 5-7. MLB LVDS Buffers DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

BALL NAMES in MUXMODE 0:

MLBP_SIG_P, MLBP_SIG_N, MLBP_DAT_P, MLBP_DAT_N, MLBP_CLK_P, MLBP_CLK_N

BALL NUMBERS: L24, M24, K23, K22, M23, L23

V_I

Input Voltage

VDDS⁽¹⁾

V_IDH

V_IDL

V_ODH

V_ODL

_ΔV_OD

Input Differential High Voltage

Input Differential Low Voltage

Output Differential High Voltage

Output Differential Low Voltage

-50

500

-300

Differential Load = 50 Ω

300

-500

-50

Difference in Differential Output Voltage, between high/low

steady-states

V_OCM

Common mode output voltage

1.0

-50

1.5

_ΔV_OCM

Difference in Common Mode Output Voltage, between high/low

steady-states

V_CMV

Variation in Common Mode Output Voltage, during logic state

transitions

150

mVpp

(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

Specifications

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表 5-8. PORn DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

BALL NAMES in MUXMODE 0:

PORn

BALL NUMBERS: AA3

V_IH

Input High-Level Threshold

Input Low-Level Threshold

Input Hysteresis Voltage

V_IL

0.8

V_HYS

200

表 5-9. 1.8-Volt I/O LVCMOS DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

BALL NAMES in MUXMODE 0:

MMC1_DAT7, MMC1_DAT6, MMC1_DAT5, MMC1_DAT4, MMC1_DAT3, MMC1_DAT2, MMC1_DAT1, MMC1_DAT0, MMC1_CLK,

MMC1_CMD, MMC1_SDCD, MMC1_SDWP, MMC1_POW, OBSPLL_LOCK

BALL NUMBERS: G5, F4, G4, E3, H4, J5, F5, H3, J4, J2, J3, K3, K2, N5

V_IH

Input High-Level Threshold

0.65 ×

VDDS⁽²⁾

V_IL

Input Low-Level Threshold

0.35 ×

VDDS⁽²⁾

V_HYS

V_OH

Input Hysteresis Voltage

228

Output High-Hevel Threshold

BUFFERCLASS = 00

(I_OH= -6 mA)

VDDS⁽²⁾

0.45

–

BUFFERCLASS = 01, 10, or 11

(I_OH= -7 mA)

VDDS⁽²⁾

–

0.45

V_OL

Output Low-Level Threshold

BUFFERCLASS = 00

(I_OL= 6 mA)

0.45

BUFFERCLASS = 01, 10, or 11

(I_OL= 7 mA)

I_IN

Input Leakage Current, Pull-up or Pull-down Inhibited

Input Leakage Current, Pull-down Enabled, V_I= VDDS⁽²⁾

Input Leakage Current, Pull-up Enabled, V_I= VSS

188

-188

µA

100

-58

-100

I_OZ

Total leakage current through the driver/receiver combination, which may

include an internal pull-up or pull-down. This value represents the maximum

current flowing in or out of the pin while the output driver is disabled, the pull-up

or pull-down is inhibited, and the input is swept from VSS to VDD.

(1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of

chapter Device Configuration of the Device TRM.

(2) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

表 5-10. 3.3-Volt I/O LVCMOS DC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)⁽¹⁾

PARAMETER

BALL NAMES in MUXMODE 0: ALL other IOs

BALL NUMBERS: ALL other IOs

MIN

TYP

MAX UNIT

V_IH

Input high-level threshold

Input low-level threshold

Input hysteresis voltage

V_IL

0.8

V_HYS

200

Specifications

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ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

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表 5-10. 3.3-Volt I/O LVCMOS DC Electrical Characteristics (continued)

over recommended operating conditions (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

TYP

MAX UNIT

V_OH

Output high-level threshold

BUFFERCLASS = 00, 01

(I_OH= -3 mA)

VDDS⁽²⁾– 0.2

BUFFERCLASS = 10, 11

(I_OH= -3.5 mA)

VDDS⁽²⁾– 0.2

VDDS⁽²⁾– 0.45

BUFFERCLASS = 10, 11

(I_OH= -6 mA)

V_OL

Output low-level threshold

BUFFERCLASS = 00, 01

(I_OL= 3 mA)

0.2

BUFFERCLASS = 10, 11

(I_OL= 3.5 mA)

BUFFERCLASS = 10, 11

(I_OL= 6 mA)

0.45

I_IN

Input leakage current, pull-up or pull-down inhibited

Input leakage current, pull-down enabled, V_I= VDDS⁽²⁾

Input leakage current, pull-up enabled, V_I= VSS

210

-200

µA

120

-60

-120

I_OZ

Total leakage current through the driver/receiver combination, which may

include an internal pull-up or pull-down. This value represents the

maximum current flowing in or out of the pin while the output driver is

disabled, the pull-up or pull-down is inhibited, and the input is swept from

VSS to VDD.

(1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of

chapter Device Configuration of the Device TRM.

(2) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

5.7.1 USB0_PHY and USB1_PHY DC Electrical Characteristics

注

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision

2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.

5.7.2 PCIe SERDES DC Electrical Characteristics

注

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®

Base Specification Revision 2.0 and PCI Express Card Electromechanical Specification

Revision 2.0.

Specifications

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5.8 Thermal Resistance Characteristics for ABY Package

This section provides the thermal resistance characteristics for the ABY package used on this device.

The Thermal Design Guide for DSP and Arm Application Processors Application Report (SPRABI3)

available from http://www.ti.com/lit/pdf/sprabi3 provides guidance for successful implementation of a

thermal solution for system designs containing this device. This document provides background

information on common terms and methods related to thermal solutions. TI only supports designs that

follow system design guidelines contained in the application report.

For reliability and operability concerns, the maximum junction temperature of the Device has to be at or

below the T_Jvalue identified in Section 5.4, Recommended Operating Conditions.

表 5-11. Thermal Resistance Characteristics for ABY Package

It is recommended to perform thermal simulations at the system level with the worst case device power consumption⁽³⁾

ABY

AIR FLOW

(m/s)⁽²⁾

NO.

NAME

DESCRIPTION

°C/W^{(1) (4)}

RΘ_JC

RΘ_JB

RΘ_JA

Junction-to-case

Junction-to-board

Junction-to-free air

0.3

4.2

14.2

9.1

8.2

7.7

0.2

3.9

3.4

3.3

3.2

N/A

0.0

1.0

2.0

3.0

0.0

1.0

2.0

3.0

0.0

1.0

2.0

3.0

RΘ_JMA

Junction-to-moving air

Ψ_JT

Junction-to-package top

T10

T11

T12

T13

T14

Ψ_JB

Junction-to-board

(1) These values were derived from thermal simulations using 1W of power dissipation and an ambient temperature of 25°C following

methods defined in the standards listed below. These values may not represent actual use conditions of the device.

The following standards define test methods used to derive JA, JMA, JB and JC:

–

JESD51-2:Integrated Circuits Thermal Test Method Environmental Conditions – Natural Convection (Still Air)

JESD51-6:Integrated Circuits Thermal Test Method Environmental Conditions – Force Convection (Moving Air)

JESD51-8: Integrated Circuits Thermal Test Method Environmental Conditions – Junction-to-Board

SEMI G30-88: Junction-to-Case Thermal Resistance Measurements of Ceramic Packages

The following standard defines the test board used in above tests:

JESD51-9: Test Boards for Area Array Surface Mount Package Thermal Measurement

–

(2) m/s = meters per second.

(3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(4) °C/W = degrees Celsius per watt.

Specifications

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5.9 Timing and Switching Characteristics

The timing parameter symbols used in Section 5.9 are created in accordance with JEDEC Standard 100.

To shorten the symbols, some pin names and other related terminologies have been abbreviated in

Table 5-12:

Table 5-12. Timing Parameters Subscripts

SYMBOL

PARAMETER

Cycle time (period)

Delay time

dis

Disable time

Enable time

Hold time

START

Setup time

Start bit

Transition time

Valid time

Pulse duration (width)

Unknown, changing, or don't care level

Fall time

High

Low

Rise time

Valid

Invalid

Active Edge

First Edge

Last Edge

High impedance

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5.9.1 Power Supply Sequencing

This section describes the power-up and power-down sequences required to ensure proper device

operation. The power supply names described in this section comprise a superset of a family of

compatible devices. Some members of this family will not include a subset of these power supplies and

their associated device modules. Refer to 节 4.2, Pin Attributes of the 节 4, Terminal Configuration and

Functions to determine which power supplies are applicable.

5.9.1.1 Power-Up Sequence

Figure 5-3 describes the Power-Up Sequencing of the device.

POWER-UP SEQUENCE

BOOT-UP PROCESS

ACTIVE MODE

Note 1

DVDD33,

DVDD33_USB

DVDD18, AVDDA_DDRPLL, AVDDA_DSSPLL,

AVDDA_MAINPLL, AVDDA_NSSPLL,

AVDDA_UARTPLL, AVDDA_ICSSPLL,

AVDDA_ARMPLL, DVDD_DDRDLL, and VDDAHV

Note 7

DVDD_DDR

DDR_CLK_P /

DDR_CLK_N

...

Note 6

Note 2

CVDD, CVDD1

PORn

Note 3

SYSOSC_IN

SYSCLK_P/N

...

Note 9

Note 4

SYSCLKSEL

BOOTMODE[15:0],

NODDR, BOOT_RSVD, MAINPLL_OD_SEL

RESETSTATn

BOOTCOMPLETE

Note 8

Hi-Z

VPP2

Hi-Z or driven

SPRS932_ELCH_01

Figure 5-3. Power-Up Sequencing

(1) Power-up begins by asserting PORn and applying DVDD33 first.

(2) PORn shall be asserted before the power-up sequence begins and held until all power supplies are within their specified recommended

operating range.

(3) Oscillator Power-up time defines where SYSOSC may start oscillation and the time required for oscillation to become stable, which is a

function the crystal circuit components selected.

(4) BOOTMODE pins are synchronously latched after the rising edge of PORn using SYSOSC_IN or SYSCLK_P / N with setup and hold

timing requirements defined in Table 5-15, Boot Configuration Timing Requirements.

(5) RESETSTATn and BOOTCOMPLETE are outputs and only shown for informational purposes.

(6) SYSOSC_IN or SYSCLK_P/N reference clock shall be valid at least 2 ms before PORn is released.

(7) If externally sourced, must be present prior to PORn.

(8) The VPP2 power supply pin is only valid for high-security (66AK2G1xS) devices. The VPP2 power source shall only be enabled while

programming the customer OTP eFuse array and shall be disabled during power-up sequence, normal operation, and power-down

sequence. When disabled, the power source shall not source current to, or sink current from the VPP2 terminal. This power supply pin is

reserved for general purpose (66AK2G1x) devices and shall not be connected to any signal, test point, or printed circuit board trace

when using 66AK2G1x devices.

(9) The SYSCLKSEL must be driven to the appropriate and valid logic level at least 500ns before the rising edge of PORn, then held at the

same logic level as long as the device is operational.

Specifications

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5.9.1.2 Power-Down Sequence

The Power-up sequence shall be reversed for the Power-down sequence.

•

Assert PORn while all power supplies are still valid.

Remove voltage sources connected to non-fail-safe inputs.

Continue to hold PORn low and DVDD33 valid while other power supplies decay.

Continue to hold PORn low while DVDD33 decays.

Figure 5-4 describes the Power-down Sequencing of the device.

ACTIVE MODE

POWER-DOWN SEQUENCE

DVDD33,

DVDD33_USB

DVDD18, AVDDA_DDRPLL, AVDDA_DSSPLL,

AVDDA_MAINPLL, AVDDA_NSSPLL,

AVDDA_UARTPLL, AVDDA_ICSSPLL,

AVDDA_ARMPLL, DVDD_DDRDLL, and VDDAHV

DVDD_DDR

DDR_CLK_P /

DDR_CLK_N

CVDD, CVDD1

PORn

SYSOSC_IN

SYSCLK_P/N

SYSCLKSEL

BOOTMODE[15:0],

NODDR, BOOT_RSVD, MAINPLL_OD_SEL

RESETSTATn

BOOTCOMPLETE

VPP2

Hi-Z or driven

Hi-Z

SPRS932_ELCH_02

Figure 5-4. Power-Down Sequencing

Specifications

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5.9.2 Reset Timing

5.9.2.1 Reset Electrical Data/Timing

For more details about features and additional description information on the subsystem multiplexing

signals, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

Table 5-13, Table 5-14, Figure 5-5, and Figure 5-6 present the reset timing requirements and switching

characteristics.

Table 5-13. Reset Timing Requirements

NO.

PARAMETER

MIN

500C⁽¹⁾

MAX

UNIT

PORn Pin

RST1

RST2

t_w(PORn)

Pulse width - pulse width PORn low

RESETn Pin

t_w(RESETn)

Pulse width - pulse width RESETn low

(1) C = 1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL.

Table 5-14. Reset Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

PORn Pin

RST3

RST4

t_{d(CVDD - PORn)}

Delay time - PORn high after CVDD/CVDD1 ramped

Delay time - RESETSTATn high after PORn high

RESETn Pin

t_{d(PORn -RESETSTATn)}

50000C⁽¹⁾

RST5

t_{d(RESETn-RESETSTATn)}

Delay time - RESETSTATn high after RESETn high

50000C⁽¹⁾

(1) C = 1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL.

RST1

PORn

RESETn

RST4

RESETSTATn

Figure 5-5. PORn Reset Timing

PORn

RESETn

RST2

RST5

RESETSTATn

Figure 5-6. Soft/Hard Reset Timing

Specifications

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Table 5-15 and Figure 5-7 present the boot configuration timing requirements.

Table 5-15. Boot Configuration Timing Requirements

NO.

BC1

BC2

PARAMETER

MIN

12C⁽¹⁾

MAX

UNIT

t_{su(BOOTMODE-PORn)}

t_{h(PORn-BOOTMODE)}

Setup time – BOOTMODE valid before PORn asserted

Hold time – BOOTMODE valid after PORn asserted

(1) C = 1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL.

BC1

PORn

BOOTMODE[15:0],

NODDR, BOOT_RSVD, MAINPLL_OD_SEL

BC2

Figure 5-7. Boot Configuration Timing

5.9.3 Clock Specifications

5.9.3.1 Input Clocks / Oscillators

Various external clock sources are required as timing references for the device. Specific clock

requirements are based on use cases supported by the application. Summary of these input clock signals

are:

•

SYSOSC_IN / SYSOSC_OUT - system oscillator (SYSOSC) pins. SYSOSC is used to source the

system reference clock (SYS_OSCCLK) when the SYSCLKSEL pin is low. The SYSOSC pins can be

connected to the appropriate external crystal circuit or the oscillator can be bypassed when using an

LVCMOS clock source connected to the SYSOSC_IN pin.

NOTE

When connecting SYSOSC_IN to an LVCMOS clock source, the LVCMOS clock source

output must be disabled anytime SYSOSC is disabled since SYSOSC_IN has a strong

internal pull-down resistor which is turned on when SYSOSC is disabled.

•

SYSCLK_P / SYSCLK_N - optional system clock LVDS differential input. This input is used to source

the system reference clock (SYS_OSCCLK) when the SYSCLKSEL pin is high.

DDR_CLK_P / DDR_CLK_N - optional DDR/EMIF clock LVDS differential input. This input is used to

produce a DDR PLL reference clock (DDR_CLK) when the DDR_CLK_MUXSEL bit is high.

AUDOSC_IN / AUDOSC_OUT - optional audio oscillator (AUDIOOSC) pins. AUDIOOSC can be used

to produce an audio reference clock (AUDIO_OSCCLK) which is one of several clock options for the

McASPs and McBSP. When used, AUDIOOSC can be connected to the appropriate external crystal

circuit or the oscillator can be bypassed when using an LVCMOS clock source connected to the

AUDOSC_IN pin.

NOTE

When connecting AUDOSC_IN to an LVCMOS clock source, the LVCMOS clock source

output must be disabled anytime AUDOSC is disabled since AUDOSC_IN has a strong

internal pull-down resistor which is turned on when AUDIOOSC is disabled. This requires the

LVCMOS clock source to be disabled by default and output enable controlled by software via

a general purpose output since AUDIOOSC is disabled by default.

•

PCIE_CLK_P / PCIE_CLK_N - PCIe reference clock LVDS differential input.

USB0_XO / USB1_XO - optional USB PHY reference clock.

Specifications

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•

CPTS_REFCLK_P / CPTS_REFCLK_N - CPTS reference clock LVDS differential input.

Figure 5-8 shows the external input clock sources to peripherals.

DEVICE

Selects Main PLL output divide-by-2

System Clock Select Input

MAINPLL_OD_SEL

SYSCLKSEL

SYSCLK_P

SYSCLK_N

Optional system reference clock input.

SYSOSC_IN

System Oscillator (SYSOSC) pins, typically connected to

an external crystal circuit.

SYSOSC_OUT

RESETn

Device Warm Reset Input

Device Cold Reset Input

Power ON Reset Input

RESETFULLn

PORn

BOOTMODE[15:0]

DDR_CLK_P

Boot Mode Configuration / devices select inputs

Optional DDR / EMIF clock input.

DDR_CLK_N

AUDOSC_IN

Optional Audio Oscillator (AUDIOOSC) pins, typically connected

to an external crystal circuit when used.

AUDOSC_OUT

PCIE_CLK_P

PCIE_CLK_N

USB0_XO

PCIe reference clock input

Optional USB0 PHY reference clock input

Optional USB1 PHY reference clock input

USB1_XO

CPTS_REFCLK_P

CPTS_REFCLK_N

XREFCLK

CPTS reference clock input

Optional audio reference clock input

SPRS932_CLOCK_01

Figure 5-8. Input Clocks Interface

For more information related to clock inputs, see section Clock Management in chapter Device

Configuration of the Device TRM.

Specifications

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5.9.3.1.1 System Oscillator (SYSOSC) with External Crystal Circuit

Figure 5-9 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit

board (PCB) designs include the optional resistor Rd in case a damping resistor is required for proper

oscillator operation when combined with production crystal circuit components. In most cases, Rd is a 0-Ω

resistor. This resistor may be removed from production PCB designs after evaluating oscillator

performance with production crystal circuit components installed on preproduction PCBs.

The SYSOSC_IN terminal has a 400-Ω to 2-kΩ internal pull-down resistor which is enabled when

SYSOSC is disabled. This internal resistor prevents the SYSOSC_IN terminal from floating to an invalid

logic level which may increase leakage current through the oscillator input buffer.

Device

SYSOSC_IN

SYSOSC_OUT

VSS_OSC_SYS

(Optional)

Crystal

C_f2

C_f1

SPRS932_CLOCK_02

Figure 5-9. Crystal Implementation⁽¹⁾

NOTE

(1) Rd = 0 Ω for no damping case.

The load capacitors, C_f1and C_f2in Figure 5-9, should be chosen such that the below

equation is satisfied. C_Lin the equation is the load specified by the crystal manufacturer. All

discrete components used to implement the oscillator circuit should be placed as close as

possible to the SYSOSC_IN and SYSOSC_OUT pins.

C_f1C_f2

⁼(C_f1+C_f2)

SPRS932_CLOCK_03

Figure 5-10. Load capacitance equation

When selecting a crystal, the system designer must consider the temperature and aging characteristics of

a crystal based on the worst case environment and life expectancy of the system.

The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-16 summarizes

the required electrical constraints.

100

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Table 5-16. SYSOSC Crystal Circuit Requirements⁽²⁾

NAME

DESCRIPTION

Parallel resonance crystal frequency

MIN

TYP

MAX UNIT

f_c

19.2, 24, 25, 26

MHz

C_f1

C_f2

C_f1load capacitance for crystal parallel resonance with C_f1= C_f2

C_f2load capacitance for crystal parallel resonance with C_f1= C_f2

ESR(C_f1, C_f2) Crystal ESR

C_O

Crystal shunt capacitance

f_{a(SYSOSC_IN)}Frequency accuracy⁽¹⁾, SYSOSC_IN

ppm

(1) Frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency stability across worst case

environmental conditions, and frequency shifts due to aging.

(2) It may be difficult to find a crystal that meets all of the requirements defined in this table when searching commonly available crystal

data sheets. Most commonly available crystal data sheets are non-part number specific and publish worst case parameters for all crystal

within the family or series. For example, the data sheet may publish a single value for ESR and shunt capacitance which represents the

worst case value for every part number within the series. However, these values may be much lower for higher frequency crystals within

the series.

The recommended approach is to search non-part number specific data sheets to identify a few candidates that meet your specific

system requirements along with the requirements defined in this table. Once a few candidates have been identified, contact the

respective crystal manufacture and request part number specific data sheets to validate each crystal specific parameter meets all

requirements

5.9.3.1.2 System Oscillator (SYSOSC) with External LVCMOS Clock Source

The internal oscillator may be bypassed by connecting to an LVCMOS clock source as shown in Figure 5-

11. The SYSOSC_IN pin is connected to the LVCMOS-Compatible clock source. The SYSOSC_OUT pin

is left unconnected. The VSS_OSC_SYS pin is connected to board ground (VSS).

Device

SYSOSC_IN

SYSOSC_OUT

VSS_OSC_SYS

SPRS932_CLOCK_06

Figure 5-11. LVCMOS-Compatible Clock Input

Table 5-17 details the SYSOSC_IN input clock timing requirements.

Table 5-17. SYSOSC_IN Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX UNIT

CK0

f_{c(SYSOSC_IN)}

Frequency, SYSOSC_IN

19.2, 24, 25, 26

MHz

1/(2.22 ×

1/(1.82 ×

f_{c(SYSOSC_IN)}

CK1

t_{w(SYSOSC_IN)}Pulse duration, SYSOSC_IN low or high

Period jitter⁽¹⁾, SYSOSC_IN

f_{c(SYSOSC_IN)}

)

t_{j(SYSOSC_IN)}

t_{R(SYSOSC_IN)}Rise time, SYSOSC_IN

t_{F(SYSOSC_IN)}Fall time, SYSOSC_IN

f_{a(SYSOSC_IN)}Frequency accuracy⁽²⁾, SYSOSC_IN

50 ppm

Specifications

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(1) Period jitter is meant here as follows:

– The maximum value is the difference between the longest measured clock period and the expected clock period

– The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) LVCMOS clock source frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency

stability across worst case environmental conditions, and frequency shifts due to aging.

CK0

CK1

SYSOSC_IN

SPRS932_CLOCK_07

Figure 5-12. SYSOSC_IN Input Clock

5.9.3.1.3 System Oscillator (SYSOSC) Not Used

SYSOSC_IN must be connected to VSS through an external pull resistor to insure this input is held to a

valid logic low level when unused since the internal pull-down resistor is disabled by default.

Device

SYSOSC_IN

SYSOSC_OUT

VSS_OSC_SYS

R_pd

SPRS932_CLOCK_011

Figure 5-13. System Oscillator (SYSOSC) Not Used

5.9.3.1.4 Optional LVDS Clock Inputs

SYSCLK_P/N is an optional LVDS clock input for the system reference clock.

DDR_CLK_P/N is an optional LVDS clock input for the DDR EMIF reference clock.

CPTS_REFCLK_P/N is optional LVDS clock input for the CPTS reference clock.

External connections to support these optional clock inputs are shown in Figure 5-14, where the

respective pins are connected to an LVDS-compatible clock source. Refer to Table 5-18 and Figure 5-15

for respective input clock requirements.

102

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Device

SYSCLK_P SYSCLK_N DDR_CLK_P DDR_CLK_N CPTS_REFCLK_P CPTS_REFCLK_N

SPRS932_CLOCK_04

Figure 5-14. LVDS-Compatible Clock Input

Table 5-18 details the SYSCLK_P/N input clock requirements.

Table 5-18. SYSCLK_P/N Input Clock Requirements⁽³⁾

NAME

DESCRIPTION

Frequency, SYSCLK_P/N

Frequency, DDR_CLK_P/N

MIN

TYP

19.2, 24, 25, 26

MAX UNIT

f_{c(SYSCLK_P/N)}

f_{c(DDR_CLK_P/N)}

CK0

CK1

MHz

f_{c(CPTS_REFCLK_P/N)}Frequency, CPTS_REFCLK_P/N

30.72

307.2

t_{w(SYSCLK_P/N)}

t_{w(DDR_CLK_P/N)}

Pulse duration, SYSCLK_P/N low or high

Pulse duration, DDR_CLK_P/N low or high

1/(2.22 ×

1/(1.82 ×

f_{c(SYSCLK_P/N)}

)

t_{w(CPTS_REFCLK_P/N)}Pulse duration, CPTS_REFCLK_P/N low or high

t_{j(SYSCLK_P/N)}

Period jitter⁽¹⁾, SYSCLK_P/N

Period jitter⁽¹⁾, DDR_CLK_P/N

t_{j(CPTS_REFCLK_P/N)}Period jitter⁽¹⁾, CPTS_REFCLK_P/N

100

t_{j(DDR_CLK_P/N)}

t_{R(SYSCLK_P/N)}

t_{R(DDR_CLK_P/N)}

Rise time, SYSCLK_P/N (10%-90%)

Rise time, DDR_CLK_P/N (10%-90%)

300

t_{R(CPTS_REFCLK_P/N)}Rise time, CPTS_REFCLK_P/N (10%-90%)

t_{F(SYSCLK_P/N)}

t_{F(DDR_CLK_P/N)}

Fall time, SYSCLK_P/N (90%-10%)

Fall time, DDR_CLK_P/N (90%-10%)

300

t_{F(CPTS_REFCLK_P/N)}Fall time, CPTS_REFCLK_P/N (90%-10%)

f_{a(SYSCLK_P/N)}

f_{a(DDR_CLK_P/N)}

Frequency accuracy⁽²⁾, SYSCLK_P/N

Frequency accuracy⁽²⁾, DDR_CLK_P/N

f_{a(CPTS_REFCLK_P/N)}Frequency accuracy⁽²⁾, CPTS_REFCLK_P/N

100 ppm

100

(1) Period jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) Frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency stability across worst case

environmental conditions, and frequency shifts due to aging.

(3) DC electrical specifications for the SYSCLK_P/N, DDR_CLK_P/N, and CPTS_REFCLK_P/N LVDS differential inputs are defined in 表 5-

5, LVDS Input Buffer DC Electrical Characteristics.

Specifications

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CK0

CK1

SYSCLK_P, DDR_CLK_P,

CPTS_REFCLK_P

SYSCLK_N, DDR_CLK_N,

CPTS_REFCLK_N

SPRS932_CLOCK_05

Figure 5-15. Optional LVDS Clock Inputs

5.9.3.2 Optional LVDS Clock Inputs Not Used

The differential LVDS clock inputs should be connected to the appropriate pull resistors when not used.

Refer to Figure 5-16 for recommended connections.

Device

SYSCLK_P

DDR_CLK_P

CPTS_REFCLK_P

SYSCLK_N

DDR_CLK_N

CPTS_REFCLK_N

(2)

R_pu

(2)

R_pd

(1)

VDDS

SPRS932_CLOCK_12

Figure 5-16. Optional LVDS Clock Input Connections Not Used

(1) VDDS in this figure stands for corresponding power supply. For more information on the power supply name and the corresponding ball,

see 表 4-1, POWER column.

(2) R_pu= R_pd= 130 Ω.

5.9.3.3 Optional Audio Oscillator (AUDOSC) with External Crystal Circuit

Figure 5-17 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit

board (PCB) designs include the optional resistor Rd in case a damping resistor is required for proper

oscillator operation when combined with production crystal circuit components. In most cases, Rd is a 0-Ω

resistor. This resistor may be removed from production PCB designs after evaluating oscillator

performance with production crystal circuit components installed on preproduction PCBs.

The AUDOSC_IN terminal has a 400-Ω to 2-kΩ internal pull-down resistor which is enabled when

AUDOSC is disabled. This internal resistor prevents the AUDOSC_IN terminal from floating to an invalid

logic level which may increase leakage current through the oscillator input buffer.

104

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Device

AUDOSC_IN

VSS_OSC_SYS

AUDOSC_OUT

(Optional)

Crystal

C_f2

C_f1

SPRS932_CLOCK_08

Figure 5-17. Crystal Implementation⁽¹⁾

NOTE

(1) Rd = 0 Ω for no damping case.

The load capacitors, C_f1and C_f2in Figure 5-17, should be chosen such that the below

equation is satisfied. C_Lin the equation is the load specified by the crystal manufacturer. All

discrete components used to implement the oscillator circuit should be placed as close as

possible to the AUDOSC_IN and AUDOSC_OUT pins.

C_f1C_f2

⁼(C_f1+C_f2)

SPRS932_CLOCK_03

Figure 5-18. Load capacitance equation

When selecting a crystal, the system designer must consider the temperature and aging characteristics of

a crystal based on the worst case environment and life expectancy of the system.

The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-19 summarizes

the required electrical constraints.

Table 5-19. AUDOSC Crystal Circuit Requirements

NAME

DESCRIPTION

Parallel resonance crystal frequency

MIN

TYP

MAX UNIT

f_c

11.2896 – 49.152

MHz

C_f1

C_f2

C_f1load capacitance for crystal parallel resonance with C_f1= C_f2

C_f2load capacitance for crystal parallel resonance with C_f1= C_f2

11.2896 MHz –15 MHz

100

15 MHz – 30 MHz

30 MHz – 40 MHz

40 MHz – 49.152 MHz

ESR(C_f1,C_f2) Crystal ESR

C_O

Crystal shunt capacitance

ppm

f_{a(AUDOSC_IN)}Frequency accuracy⁽¹⁾, AUDOSC_IN

100

Specifications

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(1) Frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency stability across worst case

environmental conditions, and frequency shifts due to aging.

(2) It may be difficult to find a crystal that meets all of the requirements defined in this table when searching commonly available crystal

data sheets. Most commonly available crystal data sheets are non-part number specific and publish worst case parameters for all crystal

within the family or series. For example, the data sheet may publish a single value for ESR and shunt capacitance which represents the

worst case value for every part number within the series. However, these values may be much lower for higher frequency crystals within

the series.

The recommended approach is to search non-part number specific data sheets to identify a few candidates that meet your specific

system requirements along with the requirements defined in this table. Once a few candidates have been identified, contact the

respective crystal manufacture and request part number specific data sheets to validate each crystal specific parameter meets all

requirements

5.9.3.4 Optional Audio Oscillator (AUDOSC) with External LVCMOS Clock Source

The internal oscillator may be bypassed by connecting to an LVCMOS clock source as shown in Figure 5-

19. The AUDOSC_IN pin is connected to the LVCMOS-Compatible clock source. The AUDOSC_OUT pin

is left unconnected. The VSS_OSC_SYS pin is connected to board ground (VSS).

Device

AUDOSC_IN

AUDOSC_OUT

VSS_OSC_SYS

SPRS932_CLOCK_09

Figure 5-19. LVCMOS-Compatible Clock Input

Table 5-20 details the AUDOSC_IN input clock timing requirements.

Table 5-20. AUDOSC_IN Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX UNIT

CK0

f_{c(AUDOSC_IN)}

t_{w(AUDOSC_IN)}

Frequency, AUDOSC_IN

11.2896 – 49.152

MHz

1/(1.82 x

f_{c(AUDOSC_IN)}

1/(2.22 x

f_{c(AUDOSC_IN)}

CK1

Pulse duration, AUDOSC_IN low or high

)

t_{j(AUDOSC_IN)}

t_{R(AUDOSC_IN)}

t_{F(AUDOSC_IN)}

f_{a(AUDOSC_IN)}

Period jitter⁽¹⁾, AUDOSC_IN

Rise time, AUDOSC_IN

100

Fall time, AUDOSC_IN

Frequency accuracy⁽¹⁾, AUDOSC_IN

100 ppm

(1) Period jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) LVCMOS clock source frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency

stability across worst case environmental conditions, and frequency shifts due to aging.

CK0

CK1

AUDOSC_IN

SPRS932_CLOCK_10

Figure 5-20. AUDOSC_IN Input Clock

106

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5.9.3.5 Optional Audio Oscillator (AUDOSC) Not Used

AUDOSC_IN may be a no-connect while the oscillator remains disabled since the internal pull-down

resistor is enabled by default.

Device

AUDOSC_IN

AUDOSC_OUT

VSS_OSC_SYS

SPRS932_CLOCK_013

Figure 5-21. Optional Audio Oscillator (AUDOSC) Not Used

5.9.3.6 Optional USB PHY Reference Clock

Each USB PHY has an optional 1.8-Volt LVCMOS reference clock input. USB0_XO is the input to USB0

and USB1_XO is the input to USB1. A valid clock source shall be connected anytime it is selected as the

reference clock. The inputs can be left floating or tied to ground if not being used.

Table 5-21. Optional USB PHY Reference Clock Requirements

NAME

DESCRIPTION

Frequency, USB0_XO

MIN

TYP

MAX UNIT

f_{c(USB0_XO)}

f_{c(USB1_XO)}

t_{w(USB0_XO)}

t_{w(USB1_XO)}

t_{j(USB0_XO)}

t_{j(USB1_XO)}

t_{R(USB0_XO)}

t_{R(USB1_XO)}

t_{F(USB0_XO)}

t_{F(USB1_XO)}

t_{a(USB0_XO)}

t_{a(USB1_XO)}

CK0

12, 19.2, 24, 50

MHz

Frequency, USB1_XO

Pulse Duration, USB0_XO low or high

Pulse Duration, USB1_XO low or high

Period Jitter⁽¹⁾, USB0_XO

Period Jitter⁽¹⁾, USB1_XO

Rise time, USB0_XO

1/(2.5 x

f_{c(USB_XO)}

1/(1.67 x

f_{c(USB_XO)}

CK1

)

100

Rise time, USB1_XO

Fall time, USB0_XO

Fall time, USB1_XO

Frequency accuracy⁽²⁾, USB0_XO

Frequency accuracy⁽²⁾, USB1_XO

400 ppm

(1) Period jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) LVCMOS clock source frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency

stability across worst case environmental conditions, and frequency shifts due to aging.

CK0

CK1

USB0_XO, USB1_XO

SPRS932_CLOCK_014

Figure 5-22. Optional USB PHY Reference Clock

Specifications

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5.9.3.7 PCIe Reference Clock

PCIe requires an external reference clock. Refer to the PCI Express Card Electromechanical Specification

for clock requirements.

5.9.3.8 Output Clocks

The device provides several system clock outputs. Summary of these output clock outputs are as follows:

•

CLKOUT

CLKOUT port provides an option to output 50 MHz or 25 MHz clock. This clock can be used as a

reference clock for RMII or MII Ethernet companion devices.

SYSCLKOUT

–

•

–

SYSCLKOUT is an LVCMOS clock output of the internal clock SYSCLK1 which has been divided

by 6. This output is provided for test and debug purposes only. Performance of this output is not

defined due to many complex combinations of system variables. For example, this output is being

sourced from the Main PLL supporting many configuration options that yield various levels of

performance. There are also other unpredictable contributors to performance such as application

specific noise or crosstalk which may couple into the clock circuits. Therefore, there are no plans to

specify performance for this output.

•

OBSCLK

OBSCLK_N / OBSCLK_P is an LVDS clock output that can be configured to observe one of 9

–

internal clocks. This output is provided for test and debug purposes only. Performance of this

output is not defined due to many complex combinations of system variables. For example, this

output may be sourced from several PLLs with each PLL supporting many configuration options

that yield various levels of performance. There are also other unpredictable contributors to

performance such as application specific noise or crosstalk which may couple into the clock circuits.

Therefore, there are no plans to specify performance for this output.

108

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5.9.3.9 PLLs

Power is supplied to the PLLs by internal regulators that derive power from the off-chip power-supply.

There are seven Phase Locked Loops (PLLs) in the device:

•

MAIN_PLL with PLL_CONTROLLER: (SoC, Peripherals) The Main PLL — which is used to drive the

switch fabrics, accelerators, and a majority of the peripheral clocks — requires a PLL controller to

manage the various clock divisions, gating, and synchronization.

•

ARM_PLL: The ARM PLL, which is used to drive the ARMSS.

DSS_PLL: (Display Subsystem) The DSS PLL, which is used to drive the DSS.

UART_PLL: (ICSS UART) The UART PLL, which is used to drive the UART in ICSS, QSPI, MMC/SD

and USB.

•

ICSS_PLL: (ICSS PRUs) The ICSS PLL, which is used to drive the ICSS.

NSS/IEP_PLL: (NSS, ICSS) The NSS/IEP PLL, which is used to drive the NSS_L and ICSS.

DDR_PLL: (DDR EMIF / DDR PHY) The DDR PLL is used to drive the DDR EMIF PHY for the DDR

EMIF.

Most of the Device is driven by the output from the main PLL except the following items:

•

ARMSS has its own dedicated PLL.

DDR subsystem has its own dedicated PLL which sources DDR EMIF and DDR EMIF PHY.

ICSS receives clocks from several PLLs – MAIN_PLL, UART_PLL, ICSS_PLL, and NSS/IEP_PLL.

DSS has its own dedicated PLL, which generates the DSS pixel clock.

PCIe subsystem receives clocks from MAIN_PLL and the external 100 MHz reference clock input.

USB has the option of being clocked from UART_PLL, NSS_PLL, or an optional external clock

reference input.

NOTE

For more information, see:

•

Device Configuration / Clock Management / PLLs section

Peripherals / Display Subsystem Overview section of the Device TRM.

NOTE

The input reference clocks (SYSCLK_P/N or SYSOSC_IN) are specified and the lock time is

guaranteed by the PLL controller, as documented in the Device Configuration chapter of the

Device TRM.

Specifications

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5.9.3.9.1 DDR_PLL Settings

Table 5-22 lists the recommended and supported values to set up the DDR3-800 configurations.

Table 5-22. DDR3-800 Configurations

Parameter

Value

Configuration Register

Configuration 1

Reference Clock Input

PLL Reference Divider

PLL Multiplier

19.2 MHz

N/A

BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD

BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM

BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD

167

166

PLL Output Divider

PHY PLL Frequency Select (In DDR3

Initialization)

N/A

DDR_PHY_PLLCR[19-18] FRQSEL

DDR_PHY_PLLCR[16-13] CPPC

0x3

0xE

PHY PLL Charge Pump Proportional

Current Control (In DDR3 Initialization)

Configuration 2

Reference Clock Input

PLL Reference Divider

PLL Multiplier

24 MHz

N/A

BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD

BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM

BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD

133

132

PLL Output Divider

PHY PLL Frequency Select (In DDR3

Initialization)

N/A

DDR_PHY_PLLCR[19-18] FRQSEL

DDR_PHY_PLLCR[16-13] CPPC

0x3

0xE

PHY PLL Charge Pump Proportional

Current Control (In DDR3 Initialization)

Configuration 3

Reference Clock Input

PLL Reference Divider

PLL Multiplier

25 MHz

N/A

BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD

BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM

BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD

128

127

PLL Output Divider

PHY PLL Frequency Select (In DDR3

Initialization)

N/A

DDR_PHY_PLLCR[19-18] FRQSEL

DDR_PHY_PLLCR[16-13] CPPC

0x3

0xE

PHY PLL Charge Pump Proportional

Current Control (In DDR3 Initialization)

Configuration 4

Reference Clock Input

PLL Reference Divider

PLL Multiplier

26 MHz

N/A

BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD

BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM

BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD

123

122

PLL Output Divider

PHY PLL Frequency Select (In DDR3

Initialization)

N/A

DDR_PHY_PLLCR[19-18] FRQSEL

DDR_PHY_PLLCR[16-13] CPPC

0x3

0xE

PHY PLL Charge Pump Proportional

Current Control (In DDR3 Initialization)

5.9.3.10 Recommended Clock and Control Signal Transition Behavior

All clocks and strobe signals must transition from V_IHto V_IL, or from V_ILto V_IHin a monotonic manner.

Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are

more susceptible to glitches due to noise, and special care must be taken for clock sources with slow

rise/fall times.

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5.9.4 Peripherals

5.9.4.1 DCAN

For more details about features and additional description information on the device Controller Area

Network Interface, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed

Description.

表 5-23, 表 5-24, and 图 5-23 present timing requirements and switching characteristics for DCANx

Interface.

表 5-23. Timing Requirements for DCANx Receive

NO.

MIN

H - 2⁽¹⁾

MAX

H + 2⁽¹⁾

UNIT

Mbps

f_baud(baud)

t_w(RX)

Maximum programmable baud rate

Pulse duration, receive data bit

CAN1

(1) H = period of baud rate, 1/programmed baud rate.

表 5-24. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit

NO.

PARAMETER

Maximum programmable baud rate

Pulse duration, transmit data bit

MIN

MAX

UNIT

Mbps

f_baud(baud)

t_w(TX)

CAN2

H - 2⁽¹⁾

H + 2⁽¹⁾

(1) H = period of baud rate, 1/programmed baud rate.

CAN1

CAN2

DCANx_RX

DCANx_TX

图 5-23. DCANx Timings

For more information, see section Dual Controller Area Network (DCAN) Interface in chapter Peripherals

of the Device TRM.

5.9.4.2 DSS

For more details about features and additional description information on the device Display Subsystem –

Video Output Ports, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed

Description.

表 5-25 and 图 5-24 assume testing over the recommended operating conditions and electrical

characteristic conditions.

表 5-25. DPI Video Output Switching Characteristics

NO.

PARAMETER

MIN

6.67

P⁽¹⁾× 0.45

0.7

MAX

UNIT

t_c(clk)

Cycle time, output pixel clock DSS_PCLK

t_w(clkL)

t_w(clkH)

t_t(clk)

Pulse duration, output pixel clock DSS_PCLK low

Pulse duration, output pixel clock DSS_PCLK high

Transition time, output pixel clock DSS_PCLK (10%-90%)

t_d(clk-ctlV)

Delay time, output pixel clock DSS_PCLK transition to output data

DSS_DATA[23:0] valid

-1.39

1.15

Specifications

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表 5-25. DPI Video Output Switching Characteristics (continued)

NO.

PARAMETER

MIN

MAX

1.15

UNIT

t_d(clk-dV)

Delay time, output pixel clock DSS_PCLK transition to output control

signals DSS_VSYNC, DSS_HSYNC, DSS_DE, and DSS_FID valid

-1.39

(1) P = output DSS_PCLK period in ns.

Falling-edge Clock Reference

Rising-edge Clock Reference

DSS_PCLK

DSS_VSYNC

DSS_HSYNC

DSS_DATA[23:0]

DSS_DE

data_1 data_2

data_n

even

DSS_FID

odd

SWPS049-018

(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.

(2) The polarity and the pulse width of DSS_HSYNC and DSS_VSYNC are programmable, refer to section Display Subsystem (DSS) in

chapter Peripherals of the Device TRM.

(3) The DSS_PCLK frequency can be configured, refer to section Display Subsystem in chapter Peripherals of the Device TRM.

图 5-24. DPI Video Output ^(1)(2)(3)

5.9.4.3 DDR EMIF

For more details about features and additional description information on the device DDR3L Memory

Interface, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

The device has a dedicated interface to DDR3L SDRAM. It supports JEDEC JESD79-3F and JESD79-3-1

standards compliant DDR3L SDRAM devices with the following features:

•

16-bit or 32-bit data path to external SDRAM memory

Memory device capacity: Up to 4 GB address space available over one chip select

5.9.4.4 EMAC

For more details about features and additional description information on the device Gigabit Ethernet

MAC, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

5.9.4.4.1 EMAC MDIO Interface Timings

表 5-26, 表 5-27, and 图 5-25 present timing requirements for MDIO.

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表 5-26. Timing Requirements for MDIO Input

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1 t_{su(MDIO_MDC)}

MDIO2 t_{h(MDIO_MDC)}

Setup time, MDIO_DATA valid before MDIO_CLK high

Hold time, MDIO_DATA valid after MDIO_CLK high

表 5-27. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

NO.

PARAMETER

Cycle time, MDIO_CLK

MIN

400

160

MAX

UNIT

MDIO3 t_c(MDC)

MDIO4 t_w(MDCH)

MDIO5 t_w(MDCL)

MDIO6 t_t(MDC)

MDIO7 t_{d(MDC_MDIO)}

Pulse Duration, MDIO_CLK high

Pulse Duration, MDIO_CLK low

Transition time, MDIO_CLK

Delay time, MDIO_CLK High to MDIO_DATA valid

390

MDIO3

MDIO4

MDIO5

MDIO_CLK

MDIO6

MDIO1

MDIO2

MDIO_DATA

(input)

MDIO7

MDIO_DATA

(output)

EMAC_MDIO_01

图 5-25. EMAC MDIO Diagrams receive and transmit

5.9.4.4.2 EMAC MII Timings

表 5-28 and 图 5-26 present timing requirements for MII in receive operation.

表 5-28. Timing Requirements for MII_RXCLK—MII Operation

NO.

PARAMETER

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

399.96

39.996

140

MAX

UNIT

MII1

t_c(RXCLK)

t_w(RXCLKH)

t_w(RXCLKL)

t_t(RXCLK)

Cycle time, MII_RXCLK

400.04

40.004

260

MII2

MII3

MII4

Pulse duration, MII_RXCLK high

Pulse duration, MII_RXCLK low

Transition time, MII_RXCLK

140

260

Specifications

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MII4

MII1

MII2

MII3

MII_RXCLK

MII4

EMAC_MII_01

图 5-26. Clock Timing (EMAC Receive)—MII operation

表 5-29 and 图 5-27 present timing requirements for MII in transmit operation.

表 5-29. Timing Requirements for MII_TXCLK—MII Operation

NO.

PARAMETER

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

MAX

UNIT

MII1

t_c(TXCLK)

t_w(TXCLKH)

t_w(TXCLKL)

t_t(TXCLK)

Cycle time, MII_TXCLK

399.96

39.996

140

400.04

40.004

260

MII2

MII3

MII4

Pulse duration, MII_TXCLK high

Pulse duration, MII_TXCLK low

Transition time, MII_TXCLK

140

260

MII1

MII4

MII2

MII3

MII_TXCLK

MII4

EMAC_MII_02

图 5-27. Clock Timing (EMAC Transmit)—MII operation

表 5-30 and 图 5-28 present timing requirements for EMAC MII Receive 10 Mbps and 100 Mbps.

表 5-30. Timing Requirements for EMAC MII Receive 10 Mbps and 100 Mbps

NO.

PARAMETER

MIN

MAX

UNIT

t_{su(RXD-RXCLK)}

MII5 t_{su(RXDV-RXCLK)}

t_{su(RXER-RXCLK)}

Setup time, receive selected signals valid before MII_RXCLK

t_h(RXCLK-RXD)

MII6 t_{h(RXCLK-RXDV)}

t_{h(RXCLK-RXER)}

Hold time, receive selected signals valid after MII_RXCLK

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MII5

MII6

MII_RXCLK (input)

MII_RXD3−MII_RXD0,

MII_RXDV, MII_RXER (inputs)

EMAC_MII_03

图 5-28. EMAC Receive Interface Timing MII operation

表 5-31 and 图 5-29 present timing requirements for EMAC MII Transmit 10 Mbps and 100 Mbps.

表 5-31. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10

Mbps and 100 Mbps

NO.

PARAMETER

SPEED

10 Mbps

100 Mbps

MIN

MAX UNIT

t_d(TXCLK-TXD)

Delay time, MII_TXCLK to transmit selected signals

valid

MII7

t_{d(TXCLK-TXEN)}

MII7

MII_TXCLK (input)

MII_TXD3−MII_TXD0,

MII_TXEN (outputs)

EMAC_MII_04

图 5-29. EMAC Transmit Interface Timing MII operation

5.9.4.4.3 EMAC RMII Timings

表 5-32, 表 5-33, and 图 5-30 present timing requirements for EMAC RMII receive.

表 5-32. Timing Requirements for EMAC RMII_REFCLK—RMII Operation

NO.

PARAMETER

MIN

MAX

20.001

UNIT

RMII1 t_c(REFCLK)

RMII2 t_w(REFCLKH)

RMII3 t_w(REFCLKL)

RMII4 t_t(REFCLK)

Cycle time, RMII_REFCLK

19.999

Pulse duration, RMII_REFCLK high

Pulse duration, RMII_REFCLK low

Transition time, RMII_REFCLK

表 5-33. Timing Requirements for EMAC RMII Receive

NO.

PARAMETER

MIN

MAX

UNIT

t_{su(RXD-REFCLK)}

RMII5

RMII6

t_{su(CRS_DV-REFCLK)}

t_{su(RXER-REFCLK)}

t_{h(REFCLK-RXD)}

Setup time, receive selected signals valid before RMII_REFCLK

Hold time, receive selected signals valid after RMII_REFCLK

t_{h(REFCLK-CRS_DV)}

t_{h(REFCLK-RXER)}

Specifications

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RMII1

RMII3

RMII5

RMII2

RMII6

RMII_REFCLK

RMII4

RMII_RXD1−RMII_RXD0,

RMII_CRS_DV, RMII_RXER (inputs)

EMAC_RMII_01

图 5-30. EMAC Receive Interface Timing RMII operation

表 5-34, 表 5-34, and 图 5-31 present switching characteristics for EMAC RMII Transmit 10 Mbps and 100

Mbps.

表 5-34. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII_REFCLK

—RMII Operation

NO.

PARAMETER

Cycle time, RMII_REFCLK

MIN

MAX UNIT

RMII7

RMII8

RMII9

t_c(REFCLK)

19.999

20.001

t_w(REFCLKH)

t_w(REFCLKL)

Pulse duration, RMII_REFCLK high

Pulse duration, RMII_REFCLK low

Transition time, RMII_REFCLK

RMII10 t_t(REFCLK)

表 5-35. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10

Mbps and 100 Mbps

NO.

PARAMETER

MIN

MAX UNIT

t_{d(REFCLK-TXD)}

t_{d(REFCLK-TXEN)}

t_r(TXD)

RMII11

Delay time, RMII_REFCLK high to selected transmit signals valid

Rise time, TXD outputs

Rise time, TXEN output

Fall time, TXD outputs

Fall time, TXEN output

RMII12

RMII13

t_r(TXEN)

t_f(TXD)

t_f(TXEN)

RMII7

RMII8

RMII9

RMII11

RMII10

RMII_REFCLK

RMII10

RMII_TXD1−RMII_TXD0,

RMII_TXEN (outputs)

RMII12

RMII13

EMAC_RMII_02

图 5-31. EMAC Transmit Interface Timing RMII Operation

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5.9.4.4.4 EMAC RGMII Timings

表 5-36, 表 5-37, and 图 5-32 present timing requirements for receive RGMII operation.

表 5-36. Timing Requirements for RGMII_RXC—RGMII Operation

NO.

PARAMETER

SPEED

10 Mbps

MIN

360

MAX

440

UNIT

RGMII1 t_c(RXC)

Cycle time, RGMII_RXC

100 Mbps

1000 Mbps

10 Mbps

7.2

160

8.8

240

RGMII2 t_w(RXCH)

RGMII3 t_w(RXCL)

RGMII4 t_t(RXC)

Pulse duration, RGMII_RXC high

Pulse duration, RGMII_RXC low

Transition time, RGMII_RXC

100 Mbps

1000 Mbps

10 Mbps

3.6

160

4.4

240

100 Mbps

1000 Mbps

10 Mbps

3.6

4.4

0.75

100 Mbps

1000 Mbps

表 5-37. Timing Requirements for EMAC RGMII Input Receive for 10 Mbps, 100 Mbps, and 1000 Mbps

NO.

PARAMETER

MIN

MAX UNIT

Setup time, receive selected signals valid before RGMII_RXC high and

low

RGMII5 t_su(RXD-RXC)

Hold time, receive selected signals valid after RGMII_RXC high and

low

RGMII6 t_h(RXC-RXD)

RGMII1

RGMII4

RGMII2

RMGII3

RGMII4

RGMII_RXC^(A)

RGMII5

1st Half-byte

RGMII6

2nd Half-byte

RGMII_RXD[3:0]^(B)

RGMII_RXCTL^(B)

RGRXD[3:0] RGRXD[7:4]

RXDV

RXERR

EMAC_RGMII_01

A. RGMII_RXC must be externally delayed relative to the data and control pins.

B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the

rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries

RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC.

图 5-32. EMAC Receive Interface Timing, RGMII operation

表 5-38, 表 5-39, and 图 5-34 present switching characteristics for transmit - RGMII for 10 Mbps, 100

Mbps, and 1000 Mbps.

表 5-38. Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII

Specifications

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表 5-38. Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII

operation for 10 Mbps, 100 Mbps, and 1000 Mbps (continued)

operation for 10 Mbps, 100 Mbps, and 1000 Mbps

NO.

PARAMETER

SPEED

10 Mbps

MIN

360

MAX

440

UNIT

RGMII1 t_c(TXC)

Cycle time, RGMII_TXC

100 Mbps

1000 Mbps

10 Mbps

7.2

160

8.8

240

RGMII2 t_w(TXCH)

RGMII3 t_w(TXCL)

RGMII4 t_t(TXC)

Pulse duration, RGMII_TXC high

Pulse duration, RGMII_TXC low

Transition time, RGMII_TXC

100 Mbps

1000 Mbps

10 Mbps

3.6

160

4.4

240

100 Mbps

1000 Mbps

10 Mbps

3.6

4.4

0.75

100 Mbps

1000 Mbps

RGMII1

RGMII4

RGMII2

RGMII4

RGMII3

RGMII_TXC

图 5-33. RGMII_TCX Timing - RGMII Mode

118

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表 5-39. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit -

RGMII_TXD[3:0], and RGMII_TXCTL - RGMII Mode ⁽¹⁾

NO.

PARAMETER

MIN

-0.35

MAX

0.65

0.75

UNIT

RGMII5 t_d(TXD-TXC)

RGMII6 t_d(TXCTL-TXC)

RGMII7 t_t(TXD)

RGMII8 t_t(TXCTL)

Delay time, TXD to TXC

Delay time, TXCTL to TXC

Transition time, TXD

Transition time, TXCTL

(1) PCB traces for RGMII_TXD[3:0] and RGMII_TXCTL should insert an additional 150ps of delay relative to the PCB trace delay of

RGMII_TXC. This provides the expected output timing as defined by the RGMII specification for a transmitter not operating in RGMII-ID

timing mode. Timing analysis should be performed on this interface using actual timing requirements/characteristics of the attached

RGMII PHY. In some cases, additional PCB delays may be required to provide proper timing margins.

RGMII_TXC^(A)

RGMII5

RGMII6

RGMII5

RGMII7

RGMII8

RGMII_TXD[3:0]^(B)

RGMII_TXCTL^(B)

2nd Half-byte

TXERR

1st Half-byte

RGMII6

TXEN

A. RGMII_TXC must be externally delayed relative to the data and control pins.

B. Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the

rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries

TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC.

图 5-34. EMAC Transmit Interface Timing RGMII Mode

表 5-40. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit -

RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode⁽¹⁾

NO.

PARAMETER

MIN

(0.25 × t_c(TXC)) - 0.24

MAX

(0.25 × t_c(TXC)) + 0.60

0.75

UNIT

RGMII5 t_d(TXD-TXC)

RGMII6 t_d(TXCTL-TXC)

RGMII7 t_t(TXD)

RGMII8 t_t(TXCTL)

Delay time, TXD to TXC

Delay time, TXCTL to TXC

Transition time, TXD

Transition time, TXCTL

0.75

(1) PCB traces for RGMII_TXD[3:0] and RGMII_TXCTL should insert an additional 150ps of delay relative to the PCB trace delay of

RGMII_TXC. This provides the expected output timing as defined by the RGMII specification for a transmitter operating in RGMII-ID

timing mode. Timing analysis should be performed on this interface using actual timing requirements/characteristics of the attached

RGMII PHY. In some cases, additional PCB delays may be required to provide proper timing margins.

RGMII_TXC^(A)

RGMII5

RGMII6

RGMII7

RGMII8

RGMII_TXD[3:0]^(B)

RGMII_TXCTL^(B)

2nd Half-byte

TXERR

1st Half-byte

RGMII6

TXEN

A. RGMII_TXC must be externally delayed relative to the data and control pins.

B. Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the

rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries

TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC.

图 5-35. EMAC Transmit Interface Timing - RGMII ID Mode

For more information, see section Networking Subsystem (NSS) in chapter Peripherals of the Device

TRM.

Specifications

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5.9.4.5 GPMC

For more details about features and additional description information on the device General-Purpose

Memory Controller, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed

Description.

5.9.4.5.1 GPMC and NOR Flash—Synchronous Mode

表 5-42 and 表 5-43 assume testing over the recommended operating conditions and electrical

characteristic conditions shown in 表 5-41 (see 图 5-36 through 图 5-40).

表 5-41. GPMC and NOR Flash Timing Conditions—Synchronous Mode

PARAMETER

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input signal rise time

Input signal fall time

0.9

3.1⁽¹⁾

Output Condition

C_LOADOutput load capacitance

(1) Max t_R& t_F= 25% of clock period when GPMC_CLK = 79.78 MHz.

表 5-42. GPMC and NOR Flash Timing Requirements—Synchronous Mode

NO.

MIN

MAX

UNIT

F12 t_su(dV-clkH)

Setup time, input data GPMC_AD[15:0] valid before output clock

GPMC_CLK high

3.5

2.5

3.5

2.5

F13 t_h(clkH-dV)

Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK

high

Setup time, input wait GPMC_WAIT[x]⁽¹⁾valid before output clock

GPMC_CLK high

Hold time, input wait GPMC_WAIT[x]⁽¹⁾valid after output clock GPMC_CLK

high

F21 t_{su(waitV-clkH)}

F22 t_{h(clkH-waitV)}

(1) In GPMC_WAIT[x], x is equal to 0 or 1.

表 5-43. GPMC and NOR Flash Switching Characteristics—Synchronous Mode⁽²⁾

NO.

PARAMETER

MIN

MAX

UNIT

MHz

1 / t_c(clk)

t_w(clkH)

t_w(clkL)

t_dc(clk)

t_J(clk)

Frequency⁽¹⁸⁾, output clock GPMC_CLK

Typical pulse duration, output clock GPMC_CLK high

Typical pulse duration, output clock GPMC_CLK low

Duty cycle error, output clock GPMC_CLK

Jitter standard deviation⁽¹⁹⁾, output clock GPMC_CLK

Rise time, output clock GPMC_CLK

100

0.5P⁽¹⁵⁾

-500

0.5P⁽¹⁵⁾

500

33.33

t_R(clk)

t_F(clk)

Fall time, output clock GPMC_CLK

t_R(do)

Rise time, output data GPMC_AD[15:0]

Fall time, output data GPMC_AD[15:0]

t_F(do)

t_d(clkH-csnV)

Delay time, output clock GPMC_CLK rising edge to output chip

select GPMC_CSn[x]⁽¹⁴⁾transition

F⁽⁶⁾- 2.2

E⁽⁵⁾- 2.2

B⁽²⁾- 4.5

-2.3

F⁽⁶⁾+ 4.5

t_{d(clkH-csnIV)}

t_d(aV-clk)

t_d(clkH-aIV)

t_{d(be[x]nV-clk)}

Delay time, output clock GPMC_CLK rising edge to output chip

select GPMC_CSn[x]⁽¹⁴⁾invalid

E⁽⁵⁾+ 4.5

B⁽²⁾+ 3.1

4.5

Delay time, output address GPMC_A[27:1] valid to output clock

GPMC_CLK first edge

Delay time, output clock GPMC_CLK rising edge to output

address GPMC_A[27:1] invalid

Delay time, output lower byte enable and command latch enable

GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n

valid to output clock GPMC_CLK first edge

B⁽²⁾- 1.9

B⁽²⁾+ 2.3

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表 5-43. GPMC and NOR Flash Switching Characteristics—Synchronous Mode⁽²⁾(continued)

NO.

PARAMETER

MIN

MAX

UNIT

t_{d(clkH-be[x]nIV)}

Delay time, output clock GPMC_CLK rising edge to output lower

byte enable and command latch enable GPMC_BE0n_CLE,

output upper byte enable GPMC_BE1n invalid⁽¹¹⁾

D⁽⁴⁾- 2.3

D⁽⁴⁾+ 1.9

t_{d(clkL-be[x]nIV)}

t_d(clkH-advn)

Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE,

GPMC_BE1n invalid⁽¹²⁾

D⁽⁴⁾- 2.3

G⁽⁷⁾- 2.3

D⁽⁴⁾+ 1.9

G⁽⁷⁾+ 4.5

Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE,

GPMC_BE1n invalid⁽¹³⁾

Delay time, output clock GPMC_CLK rising edge to output

address valid and address latch enable GPMC_ADVn_ALE

transition

t_{d(clkH-advnIV)}

Delay time, output clock GPMC_CLK rising edge to output

address valid and address latch enable GPMC_ADVn_ALE

invalid

D⁽⁴⁾- 2.3

D⁽⁴⁾+ 4.5

F10

F11

F14

F15

F17

t_d(clkH-oen)

t_{d(clkH-oenIV)}

t_d(clkH-wen)

t_d(clkH-do)

Delay time, output clock GPMC_CLK rising edge to output

enable GPMC_OEn_REn transition

H⁽⁸⁾- 2.3

I⁽⁹⁾- 2.3

H⁽⁸⁾+ 3.5

I⁽⁹⁾+ 4.5

Delay time, output clock GPMC_CLK rising edge to output

enable GPMC_OEn_REn invalid

Delay time, output clock GPMC_CLK rising edge to output write

enable GPMC_WEn transition

Delay time, output clock GPMC_CLK rising edge to output data

GPMC_AD[15:0] transition⁽¹¹⁾

J⁽¹⁰⁾- 2.3

J⁽¹⁰⁾+ 2.7

J⁽¹⁰⁾+ 1.9

t_d(clkL-do)

Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data

bus transition⁽¹²⁾

t_d(clkL-do)

Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data

bus transition⁽¹³⁾

t_{d(clkH-be[x]n)}

Delay time, output clock GPMC_CLK rising edge to output lower

byte enable and command latch enable GPMC_BE0n_CLE

transition⁽¹¹⁾

F17

F18

t_{d(clkL-be[x]n)}

t_w(csnV)

Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE,

GPMC_BE1n transition⁽¹²⁾

J⁽¹⁰⁾- 2.3

J⁽¹⁰⁾+ 1.9

Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE,

GPMC_BE1n transition⁽¹³⁾

Pulse duration, output chip select GPMC_CSn[x]⁽¹⁴⁾

low

Read

Write

Read

Write

A⁽¹⁾

C⁽³⁾

F19

F20

t_w(be[x]nV)

Pulse duration, output lower byte enable and

command latch enable GPMC_BE0n_CLE, output

upper byte enable GPMC_BE1n low

t_w(advnV)

Pulse duration, output address valid and address latch Read

K⁽¹⁶⁾

enable GPMC_ADVn_ALE low

Write

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

With n being the page burst access number.

(2) B = ClkActivationTime × GPMC_FCLK⁽¹⁷⁾

(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

With n being the page burst access number.

(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

(6) For csn falling edge (CS activated):

–

Case GpmcFCLKDivider = 0:

F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾

Case GpmcFCLKDivider = 1:

–

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–

F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and

CSOnTime are even)

F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((CSOnTime - ClkActivationTime) is a multiple of 3)

F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)

F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

(7) For ADV falling edge (ADV activated):

–

Case GpmcFCLKDivider = 0:

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾

Case GpmcFCLKDivider = 1:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and

ADVOnTime are even)

–

G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((ADVOnTime - ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)

G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

–

Case GpmcFCLKDivider = 0:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾

–

Case GpmcFCLKDivider = 1:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and

ADVRdOffTime are even)

–

G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)

G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

–

Case GpmcFCLKDivider = 0:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾

–

Case GpmcFCLKDivider = 1:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and

ADVWrOffTime are even)

–

G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)

G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)

(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):

–

Case GpmcFCLKDivider = 0:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾

–

Case GpmcFCLKDivider = 1:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and

OEOnTime are even)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((OEOnTime - ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)

H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

–

Case GpmcFCLKDivider = 0:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾

–

Case GpmcFCLKDivider = 1:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and

OEOffTime are even)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((OEOffTime - ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)

H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(9) For WE falling edge (WE activated):

–

Case GpmcFCLKDivider = 0:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾

–

Case GpmcFCLKDivider = 1:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and

WEOnTime are even)

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–

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((WEOnTime - ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)

I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

–

Case GpmcFCLKDivider = 0:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK ⁽¹⁷⁾

–

Case GpmcFCLKDivider = 1:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and

WEOffTime are even)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾if ((WEOffTime - ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)

I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) J = GPMC_FCLK⁽¹⁷⁾

(11) First transfer only for CLK DIV 1 mode.

(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.

(14) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

(15) P = GPMC_CLK period in ns

(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the

GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.

(19) The jitter probability density can be approximated by a Gaussian function.

Specifications

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GPMC_CLK

F18

GPMC_CSn[x]

GPMC_A[10:1]

Valid Address

F19

GPMC_BE0n_CLE

F19

GPMC_BE1n

F20

GPMC_ADVn_ALE

GPMC_OEn_REn

F10

F11

F13

F12

D 0

GPMC_AD[15:0]

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-36. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)

124

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GPMC_CLK

GPMC_CSn[x]

GPMCA[10:1]

Valid Address

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_OEn_REn

F10

F11

F13

F12

D 0

F22

F12

D 3

GPMC_AD[15:0]

GPMC_WAIT[x]

D 1

D 2

F21

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-37. GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)

GPMC_CLK

GPMC_CSn[x]

GPMC_A[10:1]

Valid Address

F17

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_WEn

F14

F15

D 1

F15

D 2

F15

GPMC_AD[15:0]

GPMC_WAIT[x]

D 0

D 3

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-38. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)

Specifications

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GPMC_CLK

GPMC_CSn[x]

GMPC_BE0n_CLE

Valid

GPMC_BE1n

GPMC_A[27:17]

Address (MSB)

F12

F13

Address (LSB)

F12

GPMC_AD[15:0]

GPMC_ADVn_ALE

F10

F11

GPMC_OEn_REn

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-39. GPMC and Multiplexed NOR Flash—Synchronous Burst Read

126

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GPMC_CLK

F18

GPMC_CSn[x]

GPMC_A[27:17]

Address (MSB)

F17

GPMC_BE1n

F17

BPMC_BE0n_CLE

F20

GPMC_ADVn_ALE

F14

GPMC_WEn

F15

D 1

F15

D 2

F15

GPMC_AD[15:0]

Address (LSB)

D 0

D 3

F22

F21

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-40. GPMC and Multiplexed NOR Flash—Synchronous Burst Write

Specifications

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5.9.4.5.2 GPMC and NOR Flash—Asynchronous Mode

表 5-44 and 表 5-45 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see 图 5-41 through 图 5-46).

表 5-44. GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode⁽¹⁾⁽²⁾

NO.

MIN

MAX

6.5

UNIT

FI1

Delay time, output data GPMC_AD[15:0] generation from internal functional clock

GPMC_FCLK⁽³⁾

FI2

FI3

Delay time, input data GPMC_AD[15:0] capture from internal functional clock GPMC_FCLK⁽³⁾

Delay time, output chip select GPMC_CSn[x] generation from internal functional clock

GPMC_FCLK⁽³⁾

6.5

FI4

Delay time, output address GPMC_A[27:1] generation from internal functional clock

GPMC_FCLK⁽³⁾

6.5

FI5

FI6

Delay time, output address GPMC_A[27:1] valid from internal functional clock GPMC_FCLK⁽³⁾

6.5

Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n generation from internal functional clock GPMC_FCLK⁽³⁾

FI7

FI8

FI9

Delay time, output enable GPMC_OEn_REn generation from internal functional clock

GPMC_FCLK⁽³⁾

6.5

Delay time, output write enable GPMC_WEn generation from internal functional clock

GPMC_FCLK⁽³⁾

Skew, internal functional clock GPMC_FCLK⁽³⁾

100

(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

(3) GPMC_FCLK is general-purpose memory controller internal functional clock.

表 5-45. GPMC and NOR Flash Timing Requirements—Asynchronous Mode

NO.

MIN

MAX

H⁽⁵⁾

UNIT

FA5⁽¹⁾

FA20⁽²⁾

FA21⁽³⁾

t_acc(d)

Data access time

t_{acc1-pgmode(d)}

t_{acc2-pgmode(d)}

Page mode successive data access time

Page mode first data access time

P⁽⁴⁾

H⁽⁵⁾

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock

edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾

(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾

(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

表 5-46. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode

NO.

FA0

FA1

PARAMETER

MIN

MAX

UNIT

t_R(d)

Rise time, output data GPMC_AD[15:0]

Fall time, output data GPMC_AD[15:0]

Pulse duration, output lower-byte enable and Read

command latch enable GPMC_BE0n_CLE,

output upper-byte enable GPMC_BE1n valid

t_F(d)

t_w(be[x]nV)

N⁽¹²⁾

Write

time

t_w(csnV)

Pulse duration, output chip select

GPMC_CSn[x]⁽¹³⁾low

Read

Write

A⁽¹⁾

128

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表 5-46. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (continued)

NO.

PARAMETER

MIN

MAX

UNIT

FA3

t_{d(csnV-advnIV)}

Delay time, output chip select

GPMC_CSn[x]⁽¹³⁾valid to output address

valid and address latch enable

GPMC_ADVn_ALE invalid

Read

Write

B⁽²⁾- 0.2

B⁽²⁾+ 2.0

FA4

FA9

t_{d(csnV-oenIV)}

t_d(aV-csnV)

Delay time, output chip select GPMC_CSn[x]⁽¹³⁾valid to

output enable GPMC_OEn_REn invalid (Single read)

C⁽³⁾- 0.2

J⁽⁹⁾- 0.2

C⁽³⁾+ 2.0

J⁽⁹⁾+ 2.0

Delay time, output address GPMC_A[27:1] valid to output

chip select GPMC_CSn[x]⁽¹³⁾valid

FA10

t_{d(be[x]nV-csnV)}

Delay time, output lower-byte enable and command latch

enable GPMC_BE0n_CLE, output upper-byte enable

GPMC_BE1n valid to output chip select GPMC_CSn[x]⁽¹³⁾

valid

FA12

t_{d(csnV-advnV)}

Delay time, output chip select GPMC_CSn[x]⁽¹³⁾valid to

output address valid and address latch enable

GPMC_ADVn_ALE valid

Delay time, output chip select GPMC_CSn[x]⁽¹³⁾valid to

output enable GPMC_OEn_REn valid

K⁽¹⁰⁾- 0.2

K⁽¹⁰⁾+ 2.0

L⁽¹¹⁾+ 2.0

FA13

FA16

FA18

FA20

FA25

FA27

FA28

FA29

FA37

t_d(csnV-oenV)

t_w(aIV)

t_{d(csnV-oenIV)}

t_w(aV)

L⁽¹¹⁾- 0.2

G⁽⁷⁾

Pulse durationm output address GPMC_A[26:1] invalid

between 2 successive read and write accesses

Delay time, output chip select GPMC_CSn[x]⁽¹³⁾valid to

output enable GPMC_OEn_REn invalid (Burst read)

I⁽⁸⁾- 0.2

D⁽⁴⁾

I⁽⁸⁾+ 2.0

Pulse duration, output address GPMC_A[27:1] valid - 2nd,

3rd, and 4th accesses

Delay time, output chip select GPMC_CSn[x]⁽¹³⁾valid to

output write enable GPMC_WEn valid

Delay time, output chip select GPMC_CSn[x]⁽¹³⁾valid to

output write enable GPMC_WEn invalid

t_d(csnV-wenV)

t_{d(csnV-wenIV)}

t_d(wenV-dV)

t_d(dV-csnV)

t_d(oenV-aIV)

E⁽⁵⁾- 0.2

F⁽⁶⁾- 0.2

E⁽⁵⁾+ 2.0

F⁽⁶⁾+ 2.0

2.8

Delay time, output write enable GPMC_WEn valid to

output data GPMC_AD[15:0] valid

Delay time, output data GPMC_AD[15:0] valid to output

chip select GPMC_CSn[x]⁽¹³⁾valid

J⁽⁹⁾- 0.2

J⁽⁹⁾+ 2.8

2.8

Delay time, output enable GPMC_OEn_REn valid to output

address GPMC_AD[15:0] phase end

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

with n being the page burst access number

(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK⁽¹⁴⁾

For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK⁽¹⁴⁾

(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(7) G = Cycle2CycleDelay × GPMC_FCLK⁽¹⁴⁾

(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) ×

GPMC_FCLK⁽¹⁴⁾

(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

Specifications

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(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

GPMC_FCLK

GPMC_CLK

FA5

FA1

GPMC_CSn[x]

FA9

GPMC_A[10:1]

Valid Address

FA0

FA10

Valid

FA0

GPMC_BE0n_CLE

GPMC_BE1n

Valid

FA3

FA12

GPMC_ADVn_ALE

FA4

FA13

GPMC_OEn_REn

GPMC_AD[15:0]

Data IN 0

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally

sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图 5-41. GPMC and NOR Flash—Asynchronous Read—Single Word

130

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[x]

GPMC_A[10:1]

FA5

FA1

FA16

FA9

Address 0

FA0

Address 1

FA0

FA10

Valid

FA0

Valid

FA0

GPMC_BE0n_CLE

GPMC_BE1n

Valid

FA10

FA3

FA12

GPMC_ADCn_ALE

FA4

FA13

GPMC_OEn_REn

GPMC_AD[15:0]

Data Upper

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally

sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图 5-42. GPMC and NOR Flash—Asynchronous Read—32-Bit

Specifications

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GPMC_FCLK

GPMC_CLK

FA20

Add3

FA20

Add1

FA21

FA20

Add2

FA1

GPMC_CSn[x]

FA9

Add0

Add4

GPMC_A[10:1]

FA0

FA10

GPMC_BE0n_CLE

FA0

FA10

GPMC_BE1n

FA12

GPMC_ADVn_ALE

FA18

FA13

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in

number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input

page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside

AccessTime register bits field.

C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in

number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally

sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address

phases for successive input page data (excluding first input page data). FA20 value must be stored in

PageBurstAccessTime register bits field.

D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图 5-43. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit

132

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GPMC_FCLK

GPMC_CLK

FA1

GPMC_CSn[x]

FA9

GPMC_A[10:1]

GPMC_BE0n_CLE

GPMC_BE1n

Valid Address

FA0

FA10

FA0

FA3

FA12

GPMC_ADVn_ALE

FA27

FA25

GPMC_WEn

GPMC_AD[15:0]

GPMC_WAIT[x]

FA29

Data OUT

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-44. GPMC and NOR Flash—Asynchronous Write—Single Word

Specifications

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GPMC_FCLK

GPMC_CLK

FA1

FA5

GPMC_CSn[x]

FA9

Address (MSB)

FA0

GPMC_A[27:17]

FA10

GPMC_BE0n_CLE

Valid

FA0

FA10

GPMC_BE1n

Valid

FA3

FA12

GPMC_ADVn_ALE

FA4

FA13

GPMC_OEn_REn

FA29

FA37

Data IN

Address (LSB)

GPMC_AD[15:0]

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally

sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图 5-45. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word

134

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[x]

GPMC_A[27:17]

FA1

FA9

Address (MSB)

FA0

FA10

GPMC_BE0n_CLE

GPMC_BE1n

FA0

FA3

FA12

GPMC_ADVn_ALE

FA27

FA25

GPMC_WEn

FA29

FA28

GPMC_AD[15:0]

Valid Address (LSB)

Data OUT

GPMC_WAIT[x]

A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

图 5-46. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word

For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory

Subsystem of the Device TRM.

5.9.4.6 I2C

For more details about features and additional description information on the device Inter-Integrated

Circuit, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

表 5-47 and 图 5-47 assume testing over the recommended operating conditions and electrical

characteristic conditions.

表 5-47. Timing Requirements for I2C Input Timings

STANDARD MODE

FAST MODE

NO.

UNIT

MIN

MAX

MIN

MAX

t_c(SCL)

Cycle time, SCL

2.5

µs

Setup Time, SCL high before SDA low (for a repeated

START condition)

t_{su(SCLH-SDAL)}

4.7

0.6

Hold time, SCL low after SDA low (for a START and a

repeated START condition)

t_h(SDAL-SCLL)

µs

t_w(SCLL)

Pulse duration, SCL low

4.7

1.3

0.6

100⁽¹⁾

0⁽²⁾

µs

t_w(SCLH)

Pulse duration, SCL high

t_{su(SDAV-SCLH)}

t_h(SCLL-SDAV)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0⁽²⁾

3.45⁽³⁾

0.9⁽³⁾µs

Pulse duration, SDA high between STOP and START

conditions

t_w(SDAH)

t_r(SDA)

4.7

1.3

µs

Rise time, SDA

1000 20 + 0.1Cb⁽⁴⁾

300 ns

Specifications

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表 5-47. Timing Requirements for I2C Input Timings (continued)

STANDARD MODE

FAST MODE

MIN MAX

NO.

UNIT

MIN

MAX

I10 t_r(SCL)

Rise time, SCL

1000 20 + 0.1Cb⁽⁴⁾

300 20 + 0.1Cb⁽⁴⁾

0.6

300 ns

µs

I11 t_f(SDA)

Fall time, SDA

I12 t_f(SCL)

Fall time, SCL

I13 t_{su(SCLH-SDAH)}

I14 t_w(SP)

Setup time, high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

50 ns

(1) A fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW

period of the SCL signal, it must output the next data bit to the SDA line t_{r max}+ t_su(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the

standard-mode I2C-Bus Specification) before the SCL line is released.

(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(3) The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(4) Cb is line load in pF.

I11

I2Cx_SDA

I2Cx_SCL

I14

I13

I10

I12

Stop

Start

Repeated

Start

Stop

图 5-47. I2C Receive Timing⁽¹⁾

(1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2.

表 5-48 and 图 5-48 assume testing over the recommended operating conditions and electrical

characteristic conditions.

表 5-48. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings

STANDARD MODE

FAST MODE

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

I15 t_c(SCL)

Cycle time, SCL

2.5

µs

Setup Time, SCL high before SDA low (for a repeated

START condition)

I16 t_{su(SCLH-SDAL)}

4.7

0.6

Hold time, SCL low after SDA low (for a START and a

repeated START condition)

I17 t_h(SDAL-SCLL)

µs

I18 t_w(SCLL)

Pulse duration, SCL low

4.7

1.3

0.6

100

µs

I19 t_w(SCLH)

Pulse duration, SCL high

I20 t_{su(SDAV-SCLH)}

I21 t_h(SCLL-SDAV)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

3.45

0.9 µs

Pulse duration, SDA high between STOP and START

conditions

I22 t_w(SDAH)

4.7

1.3

µs

I23 t_r(SDA)

I24 t_r(SCL)

I25 t_f(SDA)

Rise time, SDA

Rise time, SCL

Fall time, SDA

1000 20 + 0.1Cb⁽¹⁾

300 20 + 0.1Cb⁽¹⁾

300 ns

136

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表 5-48. Switching Characteristics Over Recommended Operating Conditions for I2C Output

Timings (continued)

STANDARD MODE

FAST MODE

MIN MAX

NO.

PARAMETER

Fall time, SCL

UNIT

MIN

MAX

I26 t_f(SCL)

300 20 + 0.1Cb⁽¹⁾

300 ns

µs

I27 t_{su(SCLH-SDAH)}

(1) Cb is line load in pF.

Setup time, high before SDA high (for STOP condition)

0.6

注

I2C emulation is achieved by configuring the LVCMOS buffers to output HiZ instead of

driving high when transmitting logic-1.

I26

I24

I2C[x]_SDA

I2C[x]_SCL

I23

I21

I19

I25

I28

I20

I27

I16

I18

I22

I17

I18

Stop

Start

Repeated

Start

Stop

图 5-48. I2C Transmit Timing⁽¹⁾

For more information, see section Inter-IC module (I2C) in chapter Peripherals of the Device TRM.

(1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2.

Specifications

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5.9.4.7 McASP

For more details about features and additional description information on the device Multichannel Audio

Serial Port, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed

Description.

表 5-49, 表 5-50, and 图 5-49 present timing requirements for McASP0 to McASP2.

表 5-49. Timing Requirements for McASP⁽⁴⁾

NO.

MIN

MAX

UNIT

ASP1 t_c(AHCLKRX)

ASP2 t_w(AHCLKRX)

ASP3 t_c(ACLKRX)

ASP4 t_w(ACLKRX)

Cycle time, McASP[x]_AHCLKR/X

Pulse duration, McASP[x]_AHCLKR/X high or low

Cycle time, McASP[x]_ACLKR/X

0.5P - 2.5⁽²⁾

Pulse duration, McASP[x]_ACLKR/X high or low

0.5R - 2.5⁽³⁾

ACLKR/X int

12.3

Setup time, McASP[x]_AFSR/X input valid

before McASP[x]_ACLKR/X

ASP5 t_{su(AFSRX-ACLKRX)}

ASP6 t_{h(ACLKRX-AFSRX)}

ASP7 t_{su(AXR-ACLKRX)}

ASP8 t_{h(ACLKRX-AXR)}

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

-1

Hold time, McASP[x]_AFSR/X input valid after

McASP[x]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

1.6

12.3

Setup time, McASP[x]_AXR input valid before

McASP[x]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

-1

Hold time, McASP[x]_AXR input valid after

McASP[x]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

1.6

(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

(2) P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in ns.

(3) R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns.

(4) x in McASP[x]_* is 0, 1 or 2

138

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ASP2

ASP1

McASP[x]_ACLKR/X (Falling Edge Polarity)

McASP[x]_AHCLKR/X (Rising Edge Polarity)

ASP4

ASP3

McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)^(A)

McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)^(B)

ASP6

ASP5

McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)

ASP8

ASP7

McASP[x]_AXR[x] (Data In/Receive)

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

图 5-49. McASP Input Timing

(1) x in McASP[x]_* is 0, 1 or 2

Specifications

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表 5-50 and 图 5-50 present switching characteristics over recommended operating conditions for

McASP0 to McASP2.

表 5-50. Switching Characteristics Over Recommended Operating Conditions for McASP⁽⁴⁾

NO.

MIN

20⁽²⁾

0.5P - 2.5⁽³⁾

MAX

UNIT

ASP9 t_c(AHCLKRX)

ASP10 t_w(AHCLKRX)

ASP11 t_c(ACLKRX)

ASP12 t_w(ACLKRX)

Cycle time, McASP[x]_AHCLKR/X

Pulse duration, McASP[x]_AHCLKR/X high or low

Cycle time, McASP[x]_ACLKR/X

Pulse duration, McASP[x]_ACLKR/X high or low

0.5P - 2.5⁽³⁾

ACLKR/X int

ACLKR/X ext in

7.25

Delay time, McASP[x]_ACLKR/X transmit

edge to McASP[x]_AFSR/X output valid

ASP13 t_{d(ACLKRX-AFSRX)}

Delay time, McASP[x]_ACLKR/X transmit

edge to McASP[x]_AFSR/X output valid with ACLKR/X ext out

Pad Loopback

ACLKX int

7.25

Delay time, McASP[x]_ACLKX transmit edge

to McASP[x]_AXR output valid

ACLKX ext in

ASP14 t_d(ACLKX-AXR)

Delay time, McASP[x]_ACLKX transmit edge

to McASP[x]_AXR output valid with Pad

Loopback

ACLKX ext out

Disable time, McASP[x]_ACLKX transmit

edge to McASP[x]_AXR output high

impedance

ACLKX int

7.25

ACLKX ext in

ASP15 t_{dis(ACLKX-AXR)}

Disable time, McASP[x]_ACLKX transmit

edge to McASP[x]_AXR output high

impedance with Pad Loopback

ACLKX ext out

(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

(2) 50 MHz

(3) P = AHCLKR and AHCLKX period.

(4) x in McASP[x]_* is 0, 1 or 2

140

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ASP10

ASP9

McASP[x]_ACLKR/X (Falling Edge Polarity)

McASP[x]_AHCLKR/X (Rising Edge Polarity)

ASP12

ASP11

McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)^(A)

McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)^(B)

ASP13

McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)

ASP13

McASP[x]_AXR[x] (Data Out/Transmit)

ASP14

ASP15

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

图 5-50. McASP Output Timing

(1) x in McASP[x]_* is 0, 1 or 2

For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the

Device TRM.

Specifications

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5.9.4.8 McBSP

For more details about features and additional description information on the device Multichannel Buffered

Serial Port, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed

Description.

表 5-51, 表 5-52, and 图 5-51 present timing requirements and switching characteristics for McBSP

Interface.

表 5-51. McBSP Timing Requirements⁽¹⁾

NO.

MIN

MAX UNIT

BSP2

BSP3

t_c(CKRX)

t_w(CKRX)

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

2P⁽²⁾or 20⁽³⁾

Pulse duration, CLKR/X high or CLKR/X low

P-1⁽⁴⁾

BSP5

BSP6

BSP7

BSP8

t_su(FRH-CKRL)Setup time, external FSR high before CLKR low

t_h(CKRL-FRH)Hold time, external FSR high after CLKR low

t_su(DRV-CKRL)Setup time, DR valid before CLKR low

t_h(CKRL-DRV)Hold time, DR valid after CLKR low

BSP10 t_su(FXH-CKXL)Setup time, external FSX high before CLKX low

BSP11 t_h(CKXL-FXH)Hold time, external FSX high after CLKX low

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2) P = 1/SYSCLK1 period in ns.

(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

表 5-52. McBSP Switching Characteristics⁽¹⁾

NO.

PARAMETER

MIN

MAX UNIT

Delay time, CLKS high to CLKR/X high for internal CLKR/X

generated from CLKS input.

BSP1 t_{d(CKSH-CKRXH)}

14.5

BSP2 t_c(CKRX)

BSP3 t_w(CKRX)

Cycle time, CLKR/X

CLKR/X int

2P⁽²⁾or 20⁽³⁾

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

FSX int

C – 2⁽⁴⁾

C + 2⁽⁴⁾

5.5

–4

BSP4 t_d(CKRH-FRV)

BSP9 t_d(CKXH-FXV)

BSP12 t_{dis(CKXH-DXHZ)}

BSP13 t_d(CKXH-DXV)

BSP14 t_d(FXH-DXV)

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

–4

14.5

5.5

14.5

–4

7.5

Disable time, DX HiZ following last data bit from CLKX

high

14.5

–4 + D1⁽⁵⁾

1 + D1⁽⁵⁾

–4 + D1⁽⁶⁾

–2 + D1⁽⁶⁾

5.5 + D2⁽⁵⁾

14.5 + D2⁽⁵⁾

5 + D2⁽⁶⁾

14.5 + D2⁽⁶⁾

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid applies ONLY when

in data delay 0 (XDATDLY = 00b) mode

FSX ext

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(1) Minimum delay times also represent minimum output hold times.

(2) P = 1/SYSCLK1 period in ns.

(3) Use whichever value is greater.

(4) C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK1 period in ns)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

If CLKGDV is even:

(1) H = CLKX high pulse width = (CLKGDV/2 + 1) × S

(2) L = CLKX low pulse width = (CLKGDV/2) × S

If CLKGDV is odd:

(1) H = (CLKGDV + 1)/2 × S

(2) L = (CLKGDV + 1)/2 × S

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit.

(5) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

(6) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

CLKS

BSP1

BSP2

BSP3

CLKR

BSP4

FSR (int)

BSP5

BSP6

FSR (ext)

BSP7

BSP8

Bit(n-1)

(n-2)

(n-3)

BSP2

BSP3

CLKX

BSP9

FSX (int)

BSP11

BSP10

FSX (ext)

FSX (XDATDLY=00b)

BSP13

BSP14

BSP13^(B)

Bit(n-1)

BSP12

(n-2)

(n-3)

Bit 0

图 5-51. McBSP Timing

表 5-53. McBSP Timing Requirements for FSR When GSYNC = 1

NO.

MIN

MAX

UNIT

BSPF1

BSPF2

t_su(FRH-CKSH)

t_h(CKSH-FRH)

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

Specifications

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CLKS

BSPF1

BSPF2

FSR external

CLKR/X

(no need to resync)

CLKR/X

(needs resync)

图 5-52. FSR Timing When GSYNC = 1

5.9.4.9 MLB

For more details about features and additional description information on the device Media Local Bus, see

the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

注

MLB in 6-pin mode may require pullups/ pulldowns on SIG and DAT bus signals. For

additional details, please consult the MediaLB Interface Specification.

表 5-54 and 图 5-53 present Timing Requirements for MLBCLK 3-Pin Option.

表 5-54. Timing Requirements for MLBCLK 3-Pin Option

NO.

PARAMETER

DESCRIPTION

MODE

512FS

1024FS

512FS

1024FS

512FS

1024FS

512FS

1024FS

512FS

1024FS

MIN

MAX

UNIT

M31

t_c(MLBCLK)

Cycle time, MLB_CLK

19.5

M32

M33

M34

t_w(MLBCLKH)

t_w(MLBCLKL)

t_t(MLBCLKH)

t_t(MLBCLKL)

Pulse duration, MLB_CLK high

Pulse duration, MLB_CLK low

Transition time, MLB_CLK high

Transition time, MLB_CLK low

9.3

6.1

M32

M34

M31

MLB_CLK

M33

M34

图 5-53. MLB_CLK Timing

144

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表 5-55, 表 5-56, and 图 5-54 present Timing Requirements and Switching Characteristics for MLB 3-Pin

Option.

表 5-55. Timing Requirements for Receive Data for the MLB 3-Pin Option

NO.

PARAMETER

DESCRIPTION

MODE

512FS

1024FS

512FS

1024FS

MIN

MAX

UNIT

M35

t_{su(MLBDAT-MLBCLKL)}Setup time, MLB_DAT/MLB_SIG input valid before MLB_CLK

low

M36

t_{h(MLBCLKL-MLBDAT)}

Hold time, MLB_DAT/MLB_SIG input valid after MLB_CLK

low

表 5-56. Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option

NO.

PARAMETER

DESCRIPTION

MODE

512FS

1024FS

512FS

1024FS

MIN

MAX

UNIT

M37

t_{d(MLBCLKH-MLBDATV)}Delay time, MLB_CLK rising to MLB_DAT/MLB_SIG valid

M38

t_dis(MLBCLKL-

MLBDATZ)

Disable time, MLB_CLK falling to MLB_DAT/MLB_SIG HiZ

6.1

M35

M36

MLB_CLK

MLB_SIG

MLB_DAT

(receive)

MLB_SIG

MLB_DAT

(transmit)

M37

M38

SPRS93v_MLB_TIMING_2

图 5-54. MLB 3-Pin Timing

表 5-57 and 图 5-55 present Timing Requirements for MLKCLK 6-Pin Option.

表 5-57. Timing Requirements for MLBCLK 6-Pin Option ⁽¹⁾

NO.

M61

M62

M63

M64

PARAMETER

t_c(CLKx)

DESCRIPTION

MODE

2048FS

MIN

MAX

UNIT

Cycle time, MLBP_CLK_x

t_w(CLKxH)

t_w(CLKxL)

t_t(CLKxH)

Pulse duration, MLBP_CLK_x high

Pulse duration, MLBP_CLK_x low

Transition time, MLBP_CLK_x high

Transition time, MLBP_CLK_x low

4.5

t_t(CLKxL)

(1) x in MLBP_CLK_x is P or N.

M62

M64

M61

MLBP_CLK_x

M63

M64

图 5-55. MLB_CLKP/N Timing⁽¹⁾

(1) x in MLBP_CLK_x is P or N.

Specifications

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表 5-58, 表 5-59, and 图 5-56 present Timing Requirements and Switching Characteristics for MLB 6-Pin

Option.

表 5-58. Timing Requirements for Receive Data for the MLB 6-Pin Option ⁽¹⁾

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

M65

t_{su(DATx-CLKxH)}

Setup time, MLBP_DAT_x/MLBP_SIG_x input valid before

MLBP_CLK_x rising

2048FS

M66

t_{h(CLKxH-DATx)}

Hold time, MLBP_DAT_x_/MLBP_SIG_x input valid after

MLBP_CLK_x rising

2048FS

0.5

(1) x in MLBP_CLK_x, MLBP_DAT_x, and MLBP_SIG_x is P or N.

表 5-59. Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option ⁽¹⁾

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

M67

t_{d(CLKxH-DATxV)}

Delay time, MLBP_CLK_x rising to MLB_DAT_x/MLB_SIG_x

valid

2048FS

0.5

M68

t_{dis(CLKxH-DATxZ)}

Disable time, MLBP_CLK_x rising to

MLBP_DAT_x/MLBP_SIG_x HiZ

2048FS

0.5

(1) x in MLBP_CLK_x, MLBP_DAT_x, and MLBP_SIG_x is P or N.

M65

M66

MLBP_CLK_x

MLBP_SIG_x

MLBP_DAT_x

(receive)

MLBP_SIG_x

MLBP_DAT_x

(transmit)

M68

M67

SPRS93v_MLB_TIMING_4

图 5-56. MLB 6-Pin Timing⁽¹⁾

(1) x in MLBP_CLK_x, MLBP_DAT_x, and MLBP_SIG_x is P or N.

For more information, see section Media Local Bus (MLB) in chapter Peripherals of the Device TRM.

5.9.4.10 MMC/SD

For more details about features and additional description information on the device Multi Media Card, see

the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

注

The MMC/SD/SDIOi (i = 0 to 1) controller is also referred to as MMCi.

表 5-60. MMC Timing Conditions

TIMING CONDITION PARAMETER

MIN TYP

MAX

UNIT

Input Conditions

t_r

t_f

Input signal rise time (10% to 90%)

Input signal fall time (90% to 10%)

2.2

Output Condition

C_loadOutput load capacitance

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表 5-61. Timing Requirements for MMC0_CMD and MMC0_DATn⁽¹⁾

(see 图 5-57)

3.3 V

TYP

NO.

PARAMETER

UNIT

MIN

MAX

Setup time, MMC_CMD valid before MMC_CLK

rising clock edge

MMC1 t_{su(CMDV-CLKH)}

MMC2 t_h(CLKH-CMDV)

MMC3 t_{su(DATV-CLKH)}

3.9

Hold time, MMC_CMD valid after MMC_CLK rising

clock edge

2.5

3.9

2.5

Setup time, MMC_DATn valid before MMC_CLK

rising clock edge

Hold time, MMC_DATn valid after MMC_CLK rising

clock edge

MMC4 t_h(CLKH-DATV)

(1) n in MMC_DATn is 0 to 7.

表 5-62. Timing Requirements for MMC1_CMD and MMC1_DATn when operating in SDR mode⁽¹⁾

(see 图 5-57)

1.8 V

TYP

NO.

PARAMETER

UNIT

MIN

MAX

Setup time, MMC_CMD valid before MMC_CLK

rising clock edge

MMC1 t_{su(CMDV-CLKH)}

MMC2 t_h(CLKH-CMDV)

MMC3 t_{su(DATV-CLKH)}

4.2

Hold time, MMC_CMD valid after MMC_CLK rising

clock edge

2.5

4.2

2.5

Setup time, MMC_DATn valid before MMC_CLK

rising clock edge

Hold time, MMC_DATn valid after MMC_CLK rising

clock edge

MMC4 t_h(CLKH-DATV)

(1) n in MMC_DATn is 0 to 7.

MMC1

MMC2

MMCi_CLK (Output)

MMCi_CMD (Input)

MMCi_DATn (Inputs)

MMC3

MMC4

图 5-57. MMCi_CMD and MMCi_DATn Input Timing⁽¹⁾

(1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 0 or 1, where n = 0 to 7.

表 5-63. Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode⁽³⁾

(see 图 5-58)

1.8 V

TYP

NO.

PARAMETER

UNIT

MIN

MAX

Setup time, MMC_CMD valid before MMC_CLK

rising clock edge

MMC1 t_{su(CMDV-CLKH)}

MMC2 t_h(CLKH-CMDV)

MMC3 t_{su(DATV-CLKH)}

4.2

Hold time, MMC_CMD valid after MMC_CLK rising

clock edge

2.5

Setup time, MMC_DATn valid before MMC_CLK

rising or falling clock edge

0.5⁽¹⁾

Specifications

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表 5-63. Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR

mode⁽³⁾(continued)

(see 图 5-58)

1.8 V

TYP

NO.

PARAMETER

UNIT

MIN

MAX

Hold time, MMC_CLK rising or falling clock edge

after MMC_DATn valid

MMC4 t_h(CLKH-DATV)

1.62⁽²⁾

(1) The minimum setup time of 0.5 ns is a function of the maximum output delay of 7 ns defined in the JESD84 standard plus the combined

PCB delay of the MMC_CLK and MMC_DATn signal traces. Therefore, the PCB shall be designed with less than 2.9 ns of combined

delay in the MMC_CLK and MMC_DATn signal traces when operating at the maximum frequency of 48 MHz.

(2) The minimum hold time of 1.62 ns exceeds the minimum output delay of 1.5 ns defined in the JESD84 standard. Therefore, the PCB

shall be designed with greater than 120 ps of combined delay in the MMC_CLK and MMC_DATn signal traces.

(3) n in MMC_DATn is 0 to 7.

MMC1

MMC2

MMCi_CLK (Output)

MMCi_CMD (Input)

MMCi_DATn (Inputs)

MMC3

MMC4

图 5-58. MMC1_CMD and MMC1_DATn Input Timing - DDR Mode⁽¹⁾

(1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 1, where n = 0 to 7.

(2)

表 5-64. Switching Characteristics for MMCi_CLK

(see 图 5-59)

NO.

PARAMETER

MIN

TYP

MAX UNIT

f_op(CLK)

t_cop(CLK)

f_id(CLK)

Operating frequency, MMC_CLK

MHz

Operating period: MMC_CLK

20.8

MMC5

Identification mode frequency, MMC_CLK

Identification mode period: MMC_CLK

Pulse duration, MMC_CLK low

400

kHz

t_cid(CLK)

2500

(1)

MMC6 t_w(CLKL)

(0.5 × P) - t_f(CLK)

(0.5 × P) - t_r(CLK)

(1)

MMC7 t_w(CLKH)

Pulse duration, MMC_CLK high

Rise time, All Signals (10% to 90%)

Fall time, All Signals (90% to 10%)

MMC8 t_r(CLK)

2.2

MMC9 t_f(CLK)

(1) P = MMC_CLK period.

(2) i in MMCi_CLK is 0 or 1.

MMC5

MMC6

MMC7

MMC8

MMC9

MMCi_CLK (Output)

图 5-59. MMCi_CLK Timing⁽¹⁾

(1) i in MMCi_CLK is 0 or 1.

148

Specifications

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表 5-65. Switching Characteristics for MMC0_CMD and MMC0_DATn—HSPE=0⁽¹⁾

(see 图 5-60)

3.3 V

NO.

PARAMETER

UNIT

MIN TYP

MAX

Delay time, MMC_CLK falling clock edge to

MMC_CMD transition

MMC10 t_d(CLKL-CMD)

-7.4

4.4

Delay time, MMC_CLK falling clock edge to

MMC_DATn transition

MMC11 t_d(CLKL-DAT)

4.4

(1) n in MMC_DATn is 0 to 7.

表 5-66. Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in SDR

mode⁽¹⁾

(see 图 5-60)

1.8 V

NO.

PARAMETER

UNIT

MIN TYP

MAX

Delay time, MMC_CLK falling clock edge to

MMC_CMD transition

MMC10 t_d(CLKL-CMD)

-7.4

7.4

Delay time, MMC_CLK falling clock edge to

MMC_DATn transition

MMC11 t_d(CLKL-DAT)

-7.4

7.4

(1) n in MMC_DATn is 0 to 7.

MMC10

MMCi_CLK (Output)

MMCi_CMD (Output)

MMCi_DATn (Outputs)

MMC11

图 5-60. MMCi_CMD and MMCi_DATn Output Timing—HSPE=0⁽¹⁾

(1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 0 or 1, where n = 0 to 7.

表 5-67. Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in DDR

mode

(see 图 5-61)

1.8 V

NO.

PARAMETER

UNIT

MIN TYP

MAX

Delay time, MMC_CLK falling clock edge to

MMC_CMD transition

MMC10 t_d(CLKL-CMD)

MMC11 t_d(CLKL-DAT)

-4.4

2.2

Delay time, MMC_CLK rising or falling clock edge to

MMC_DATn transition

-4.4

2.2

Specifications

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1. n in MMC_DATn is 0 to 7.

MMC10

MMCi_CLK (Output)

MMCi_CMD (Output)

MMCi_DATn (Outputs)

MMC11

图 5-61. MMC1_CMD and MMC1_DATn Output Timing—HSPE=0 – DDR Mode⁽¹⁾

(1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 1, where n = 0 to 7.

5.9.4.11 PCIESS

For more details about features and additional description information on the device Peripheral

Component Interconnect Express, see the corresponding sections within 节 4.3, Signal Descriptions and

节 6, Detailed Description.

5.9.4.12 PRU-ICSS

The device has integrated two identical PRU subsystems (PRU-ICSS_0 and PRU-ICSS_1). The

programmable nature of the PRU cores, along with their access to pins, events and all device resources,

provides flexibility in implementing fast real-time responses, specialized data handling operations, custom

peripheral interfaces, and in offloading tasks from the other processor cores of the device.

For more details about features and additional description information on the device Programmable Real-

Time Unit Subsystem and Industrial Communication Subsystem, see the corresponding sections within 节

4.3, Signal Descriptions and 节 6, Detailed Description.

注

The PRU-ICSS_0 and PRU-ICSS_1 support an internal wrapper multiplexing that expands

the device top-level multiplexing. Signal naming in this section must match the internal

wrapper multiplexing.

For more information, please refer to the Device TRM, Chapter Processors and Accelerators,

Section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem

(PRU-ICSS).

5.9.4.12.1 Programmable Real-Time Unit (PRU-ICSS PRU)

注

The PRU-ICSS PRU signals have different functionality depending on the mode of operation.

The signal naming in this section matches the naming used in the PRU Module Interface

section in the Device TRM.

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5.9.4.12.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing

表 5-68. PRU-ICSS PRU Timing Requirements - Direct Input Mode

NO.

PARAMETER

Pulse width, GPI

MIN

2 × P⁽¹⁾

MAX

UNIT

PRDI1 t_w(GPI)

(1) P = ICSS_n_COREn_CLK clock period, where n = 0 or 1.

PRDI1

GPI[m:0]

SPRS91x_TIMING_PRU_01

图 5-62. PRU-ICSS PRU Direct Input Timing

(1) m in GPI[m:0] = 19.

表 5-69. PRU-ICSS PRU Switching Requirements – Direct Output Mode

NO.

PARAMETER

Pulse width, GPO

Skew between GPO[19:0] signals

MIN

2 × P⁽¹⁾

MAX

UNIT

PRDO1 t_w(GPO)

PRDO2 t_sk(GPO)

(1) P = ICSS_n_COREn_CLK clock period, where n = 0 or 1.

PRDO1

GPO[n:0]

PRDO2

SPRS91x_TIMING_PRU_02

图 5-63. PRU-ICSS PRU Direct Output Timing

(1) n in GPO[n:0] = 19.

5.9.4.12.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing

表 5-70. PRU-ICSS PRU Timing Requirements – Parallel Capture Mode

NO.

PARAMETER

Cyle time, CLOCKIN

MIN

4.4

MAX

UNIT

PRPC1 t_w(CLOCKIN)

PRPC2 t_w(CLOCKINL)

PRPC3 t_w(CLOCKINH)

PRPC4 t_{su(DATAIN-CLOCKIN)}

PRPC5 t_{h(CLOCKIN-DATAIN)}

Pulse duration, CLOCKIN low

Pulse duration, CLOCKIN high

Setup time, DATAIN valid before CLOCKIN

Hold time, DATAIN valid after CLOCKIN

Specifications

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(1) P = ICSS_n_COREn_CLK clock period, where n = 0 or 1.

PRPC1

PRPC3

PRPC2

CLOCKIN

DATAIN

PRPC5

PRPC4

SPRS91x_TIMING_PRU_03

图 5-64. PRU-ICSS PRU Parallel Capture Timing – Rising Edge Mode

PRPC1

PRPC3

PRPC2

CLOCKIN

DATAIN

PRPC5

PRPC4

SPRS91x_TIMING_PRU_04

图 5-65. PRU-ICSS PRU Parallel Capture Timing – Falling Edge Mode

5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing

表 5-71. PRU-ICSS PRU Timing Requirements – Shift In Mode

NO.

PARAMETER

Pulse width, DATAIN

MIN

2 × P⁽¹⁾+ 3

MAX

UNIT

PRSI1 t_w(DATAIN)

(1) P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the PRUSS_GPCFGn register. For more

information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter

Processors and Accelerators of the Device TRM.

PRSI1

DATAIN

SPRS91x_TIMING_PRU_05

图 5-66. PRU-ICSS PRU Shift In Timing

表 5-72. PRU-ICSS PRU Switching Requirements – Shift Out Mode

NO.

PARAMETER

Cycle time, CLOCKOUT

Pulse width, CLOCKOUT

MIN

MAX

UNIT

PRSO1 t_c(CLOCKOUT)

PRSO2 t_w(CLOCKOUT)

13.3

0.4 × P⁽¹⁾

-1.5

0.5 × P⁽¹⁾

PRSO3 t_{d(CLOCKOUT-DATAOUT)}Delay time, CLOCKOUT to DATAOUT valid

152

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(1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the

PRUSS_GPCFGn register. For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication

Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the Device TRM.

PRSO1

PRSO2

CLOCKOUT

DATAOUT

PRSO3

SPRS91x_TIMING_PRU_06

图 5-67. PRU-ICSS PRU Shift Out Timing

5.9.4.12.2 PRU-ICSS EtherCAT™ (PRU-ICSS ECAT)

5.9.4.12.2.1 PRU-ICSS ECAT Electrical Data and Timing

表 5-73. PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx

NO.

PARAMETER

MIN

MAX

UNIT

EDCS1 t_{w(EDC_SYNCx_OUT)}

Pulse width, EDC_SYNCx_OUT

100.00

t_{su(EDIO_DATA_IN-}

EDCS2

Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT rising

edge

20.00

EDC_SYNCx_OUT)

t_{h(EDC_SYNCx_OUT-}

EDCS3

Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT rising edge

EDIO_DATA_IN)

EDC_SYNCx_OUT

EDCS1

EDCS2

EDCS3

EDIO_DATA_IN[3:0]

SPRS91x_TIMING_PRU_ECAT_02

图 5-68. PRU-ICSS ECAT Input Validated With SYNCx Timing

表 5-74. PRU-ICSS ECAT Timing Requirements – LATCHx_IN

NO.

PARAMETER

MIN

3 × P⁽¹⁾

MAX

UNIT

EDCL1 t_{w(EDC_LATCHx_IN)}

Pulse duration, EDC_LATCHx_IN

(1) P = ICSS_n_IEP_CLK, where n = 0 or 1.

EDC_LATCHx_IN

EDCL1

SPRS91x_TIMING_PRU_ECAT_04

图 5-69. PRU-ICSS ECAT LATCHx_IN Timing

Specifications

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表 5-75. PRU-ICSS ECAT Switching Requirements – Digital IOs

NO.

PARAMETER

EDIO_DATA_OUT skew

MIN

MAX

UNIT

EDIOD1 t_{sk(EDIO_DATA_OUT)}

EDIO_DATA_OUT[n:0]

EDIOD1

SPRS91x_TIMING_PRU_EDIO_DATA_OUT

图 5-70. PRU-ICSS EDIO DATA_OUT Timing

(1) n in EDIO_DATA_OUT[n:0] = 3.

5.9.4.12.3 PRU-ICSS MII_RT and Switch

5.9.4.12.3.1 PRU-ICSS MDIO Electrical Data and Timing

表 5-76. PRU-ICSS MDIO Timing Requirements – MDIO_DATA

NO.

PARAMETER

MIN

MAX

UNIT

PRMDI1 t_su(MDIO-MDC)

PRMDI2 t_h(MDIO-MDC)

Setup time, MDIO valid before MDC high

Hold time, MDIO valid from MDC high

PRMDI1

PRMDI2

MDIO_CLK (Output)

MDIO_DATA (Input)

SPRS91x_TIMING_PRU_MII_RT_01

图 5-71. PRU-ICSS MDIO_DATA Timing – Input Mode

表 5-77. PRU-ICSS MDIO Switching Characteristics – MDIO_CLK

NO.

PARAMETER

Cycle time, MDC

MIN

MAX

UNIT

PRMC1 t_c(MDC)

PRMC2 t_w(MDCH)

PRMC3 t_w(MDCL)

PRMC4 t_t(MDC)

400

160

Pulse duration, MDC high

Pulse duration, MDC low

Transition time, MDC

PRMC1

PRMC4

PRMC2

PRMC3

MDIO_CLK

PRMC4

SPRS91x_TIMING_PRU_MII_RT_02

图 5-72. PRU-ICSS MDIO_CLK Timing

154

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表 5-78. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA

NO.

PARAMETER

MIN

MAX

UNIT

PRMDO1 t_d(MDC-MDIO)

Delay time, MDC high to MDIO valid

390

PRMDO1

MDIO_CLK (Output)

MDIO_DATA (Output)

SPRS91x_TIMING_PRU_MII_RT_03

图 5-73. PRU-ICSS MDIO_DATA Timing – Output Mode

5.9.4.12.3.2 PRU-ICSS MII_RT Electrical Data and Timing

表 5-79. PRU-ICSS MII_RT Timing Requirements – MII_RXCLK

NO.

PARAMETER

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

MAX UNIT

399.96 400.04

39.996 40.004

PMIR1 t_c(RXCLK)

Cycle time, RXCLK

140

260

PMIR2 t_w(RXCLKH)

PMIR3 t_w(RXCLKL)

PMIR4 t_t(RXCLK)

Pulse duration, RXCLK high

Pulse duration, RXCLK low

Transition time, RXCLK

140

PMIR1

PMIR2

PMIR3

MII_RXCLK

PMIR4

SPRS91x_TIMING_PRU_MII_RT_04

图 5-74. PRU-ICSS MII_RXCLK Timing

表 5-80. PRU-ICSS MII_RT Timing Requirements – MII_TXCLK

NO.

PARAMETER

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

MAX UNIT

399.96 400.04

39.996 40.004

PMIT1 t_c(TXCLK)

Cycle time, TXCLK

140

260

PMIT2 t_w(TXCLKH)

PMIT3 t_w(TXCLKL)

PMIT4 t_t(TXCLK)

Pulse duration, TXCLK high

Pulse duration, TXCLK low

Transition time, TXCLK

140

Specifications

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PMIT1

PMIT4

PMIT2

PMIT3

MII_TXCLK

PMIT4

SPRS91x_TIMING_PRU_MII_RT_05

图 5-75. PRU-ICSS MII_TXCLK Timing

表 5-81. PRU-ICSS MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER

NO.

PARAMETER

SPEED

MIN

MAX UNIT

t_{su(RXD-RXCLK)}

t_{su(RXDV-RXCLK)}

t_{su(RXER-RXCLK)}

t_{su(RXD-RXCLK)}

t_{su(RXDV-RXCLK)}

t_{su(RXER-RXCLK)}

t_h(RXCLK-RXD)

t_{h(RXCLK-RXDV)}

t_{h(RXCLK-RXER)}

t_h(RXCLK-RXD)

t_{h(RXCLK-RXDV)}

t_{h(RXCLK-RXER)}

Setup time, RXD[3:0] valid before RXCLK

Setup time, RXDV valid before RXCLK

Setup time, RXER valid before RXCLK

Setup time, RXD[3:0] valid before RXCLK

Setup time, RXDV valid before RXCLK

Setup time, RXER valid before RXCLK

Hold time, RXD[3:0] valid after RXCLK

Hold time, RXDV valid after RXCLK

Hold time, RXER valid after RXCLK

Hold time, RXD[3:0] valid after RXCLK

Hold time, RXDV valid after RXCLK

Hold time, RXER valid after RXCLK

10 Mbps

PMIR5

100 Mbps

10 Mbps

100 Mbps

PMIR6

PMIR5

PMIR6

MII_RXCLK (Input)

MII_RXD[3:0],

MII_RXDV,

MII_RXER (Inputs)

SPRS91x_TIMING_PRU_MII_RT_06

图 5-76. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing

表 5-82. PRU-ICSS MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN

NO.

PARAMETER

SPEED

MIN

MAX UNIT

t_d(TXCLK-TXD)

t_{d(TXCLK-TXEN)}

t_d(TXCLK-TXD)

t_{d(TXCLK-TXEN)}

Delay time, TXCLK high to TXD[3:0] valid

Delay time, TXCLK to TXEN valid

Delay time, TXCLK high to TXD[3:0] valid

Delay time, TXCLK to TXEN valid

10 Mbps

PMIT5

100 Mbps

156

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PMIT5

MII_TXCLK (input)

MII_TXD[3:0],

MII_TXEN (outputs)

SPRS91x_TIMING_PRU_MII_RT_07

图 5-77. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing

Specifications

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5.9.4.12.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)

表 5-83. PRU-ICSS UART Timing Conditions

PARAMETER

MIN

TYP

MAX

UNIT

Output Condition

C_LOAD

Output load capacitance

表 5-84. Timing Requirements for PRU-ICSS UART Receive

NO.

PARAMETER

MIN

MAX

UNIT

(1)

PRUR1 t_w(RX)

Pulse duration, receive start, stop, data bit

0.96U⁽¹⁾1.05U

(1) U = UART baud time = 1 / programmed baud rate. For more information, see section PRU-ICSS UART Clock Generation and Control in

the Device TRM.

表 5-85. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART

Transmit

NO.

PARAMETER

MIN

U⁽¹⁾- 2

MAX

U⁽¹⁾- 2

UNIT

MHz

PRUT1 ƒ_(baud)

PRUT2 t_w(TX)

Maximum programmable baud rate

Pulse duration, transmit start, stop, data bit

(1) U = UART baud time = 1 / programmed baud rate. For more information, see section PRU-ICSS UART Clock Generation and Control in

the Device TRM.

PRUR1

Start

Bit

pri_uart0_rxd⁽¹⁾

Data Bits

PRUT2

Start

Bit

pri_uart0_txd⁽¹⁾

Data Bits

(1) i in pri_uart0_txd and pri_uart0_rxd = 1 or 2

SPRS91x_TIMING_PRU_UART_01

图 5-78. PRU-ICSS UART Timing

5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes

表 5-86. PRU-ICSS PRU Timing Requirements - Sigma Delta Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRSD1 t_{w(SDx_CLK)}

Pulse width, SDx_CLK

PRSD2 t_{su(SDx_D-SDx_CLK)}

PRSD3 t_{h(SDx_CLK-SDx_D)}

Setup time, SDx_D valid before SDx_CLK active edge

Hold time, SDx_D valid before SDx_CLK active edge

158

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PRSD1

SDx_CLK

SDx_D

PRSD1

PRSD3

PRSD2

SPRS91x_TIMING_PRU_07

图 5-79. PRU-ICSS PRU SD_CLK Falling Active Edge

PRSD1

SDx_CLK

SDx_D

PRSD3

PRSD2

SPRS91x_TIMING_PRU_08

图 5-80. PRU-ICSS PRU SD_CLK Rising Active Edge

表 5-87. PRU-ICSS PRU Timing Requirements - EnDAT Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRTE1 t_{w(ENDATx_IN)}

Pulse width, ENDATx_IN

表 5-88. PRU-ICSS PRU Switching Requirements - EnDAT Mode

NO.

PARAMETER

DESCRIPTION

MIN

UNIT

PRSE2 t_{w(ENDATx_CLK)}

Pulse width, ENDATx_CLK

PRSE3 t_{d(ENDATx_OUT-}

ENDATx_CLK)

Delay time, ENDATx_CLK fall to ENDATx_OUT

-10

PRSE4 t_{d(ENDATx_OUT_EN-}

ENDATx_CLK)

Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN

-10

Specifications

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ENDATx_IN

PRTE1

PRSE2

ENDATx_CLK

ENDATx_OUT

PRSE2

PRSE3

ENDATx_OUT_EN

PRSE4

SPRS91x_TIMING_PRU_09

图 5-81. PRU-ICSS PRU EnDAT Timing

For more information, see section Programmable Real-Time Unit Subsystem and Industrial

Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the Device TRM.

5.9.4.13 QSPI

For more details about features and additional description information on the device Quad Serial Port

Interface, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

表 5-89 and 表 5-90 present timing requirements and switching characteristics for QSPI interface.

表 5-89. Timing Requirements for QSPI

NO.

PARAMETER

MIN

MAX

UNIT

t_su(D-RTCLK)

t_h(RTCLK-D)

Setup time, QSPI_D[3:0] valid before active QSPI_RTCLK

edge

1.5

Hold time, QSPI_D[3:0] valid after inactive QSPI_RTCLK

edge

160

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QSPI_CSnj

QSPI_CLK

QSPI_RTCLK

Read Data

Command

Bit n-1

Command

Bit n-2

QSPI_D[3:0]

Bit 1

Bit 0

QSPI_Read_Clock mode 0

图 5-82. QSPI Read (Mode [3:0])

表 5-90. Switching Characteristics for QSPI

NO.

PARAMETER

MIN

10.42⁽¹⁾

0.48 × P⁽²⁾

5.00

MAX

UNIT

t_c(CLK)

Cycle time, QSPI_CLK

t_{w(CLK L)}

t_{w(CLK H)}

t_d(CSn-CLK)

Pulse duration, QSPI_CLK low

Pulse duration, QSPI_CLK high

Delay time, QSPI_CSn active edge to QSPI_CLK

transition

t_d(CLK-CSn)

t_d(CLK-D0)

Delay time, QSPI_CLK transition to QSPI_CSn inactive

edge

5.00

Delay time, QSPI_CLK active edge to QSPI_D[0]

transition

(1) Maximum supported frequency is 96 MHz (Mode 0 only).

(2) P = QSPI_CLK period.

PHA=0

QSPI_CSnj

POL=0

QSPI_CLK

QSPI_D[0]

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

QSPI_D[3:1]

QSPI_Write_Clock mode 0

图 5-83. QSPI Write (Mode [3:0])

For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the

Device TRM.

Specifications

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5.9.4.14 SPI

For more details about features and additional description information on the device Serial Port Interface,

see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the Device

TRM.

5.9.4.14.1 SPI—Slave Mode

表 5-91, 表 5-92, 图 5-84, and 图 5-85 present Timing Requirements for SPI - Slave Mode.

表 5-91. Timing Requirements for SPI Input Timings—Slave Mode

NO.

PARAMETER

Cycle time, SPI_CLK

MIN

MAX

UNIT

t_c(SPICLK)

(1)

t_w(SPICLKL)

t_w(SPICLKH)

Typical Pulse duration, SPI_CLK low

Typical Pulse duration, SPI_CLK high

0.45P

(1)

0.45P

Setup time, SPI_D[x] (SIMO) valid before SPI_CLK active

edge⁽²⁾⁽³⁾

t_{su(SIMO-SPICLK)}

t_{h(SPICLK-SIMO)}

Hold time, SPI_D[x] (SIMO) valid after SPI_CLK active

edge⁽²⁾⁽³⁾

t_{su(CS-SPICLK)}

t_h(SPICLK-CS)

Setup time, SPI_CS valid before SPI_CLK first edge⁽²⁾

Hold time, SPI_CS valid after SPI_CLK last edge⁽²⁾

Required delay from SPIx_CS asserted at slave to first

SPI_CLK edge at slave. Phase = 0

t_d(CS-SPICLK)

t_d(SPICLK-CS)

t_d(CSH-SPCN)

C + 5⁽⁴⁾

A + 5⁽⁴⁾

G + 5⁽⁴⁾

E + 5⁽⁴⁾

C + 5⁽⁴⁾

Required delay from SPIx_CS asserted at slave to first

SPI_CLK edge at slave. Phase = 1

Required delay from final SPI_CLK edge before SPI_CS is

deasserted at slave. Phase = 0

Required delay from final SPI_CLK edge before SPI_CS is

deasserted at slave. Phase = 1

Minimum delay from slave deselected (SPI_CS deasserted) to

SPI_CLK edge (for another slave on the bus)

(1) P = SPI_CLK period.

(2) This timing applies to all configurations regardless of SPIx_CLK polarity and which clock edges are used to drive output data and

capture input data.

(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

(4) A = (2 × P2) + (0.5 × SPI_CLK)

C = (2 × P2)

E = (1 × P2)

G = (1 × P2) + (0.5 × SPI_CLK)

P2 = 1 / (SYSCLK1 / 6)

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表 5-92. Switching Characteristics for SPI Output Timings—Slave Mode

NO.

PARAMETER

MIN

MAX

UNIT

Delay time, SPI_CLK active edge to SPI_D[x] (SOMI)

transition⁽¹⁾⁽²⁾

t_{d(SPICLK-SOMI)}

t_ena(CS-SOMI)

t_dis(CS-SOMI)

Delay from master asserting SPIx_CS to slave driving

SPIx_SOMI valid⁽²⁾

Delay from master deasserting SPIx_CS to slave 3-

stating SPIx_SOMI⁽²⁾

S10

1 x P2⁽³⁾

1 x P2⁽³⁾+ 5

(1) This timing applies to all configurations regardless of SPIx_CLK polarity and which clock edges are used to drive output data and

capture input data.

(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

(3) P2 = 1 / (SYSCLK1 / 6).

PHA=0

EPOL=1

SPI_CS[x] (In)

POL=0

POL=1

SPI_SCLK (In)

Bit n-2

SPI_D[x] (SIMO, In)

Bit n-1

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[x] (In)

SPI_SCLK (In)

POL=0

POL=1

SPI_SCLK (In)

SPI_D[x] (SIMO, In)

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

SPI_01

图 5-84. SPI Slave Mode Receive Timing

Specifications

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PHA=0

EPOL=1

SPI_CS[x] (In)

POL=0

SPI_SCLK (In)

POL=1

SPI_SCLK (In)

Bit n-1

SPI_D[x] (SOMI, Out)

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[x] (In)

POL=0

SPI_SCLK (In)

POL=1

SPI_SCLK (In)

SPI_D[x] (SOMI, Out)

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

SPI_02

图 5-85. SPI Slave Mode Transmit Timing

5.9.4.14.2 SPI—Master Mode

表 5-94, 表 5-95, 图 5-86 and 图 5-87 present Timing Requirements for SPI - Master Mode.

表 5-93. SPI Timing Conditions—Master Mode

PARAMETER

MIN

MAX

UNIT

Input Conditions

t_r

Input signal rise time

t_f

Input signal fall time

Output Condition

C_load

Output load capacitance

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表 5-94. Timing Requirements for SPI Input Timings—Master Mode

NO.

PARAMETER

MIN

MAX UNIT

(1)

t_{su(SOMI-SPICLK)}

Setup time, SPI_D[x] (SOMI) valid before SPI_CLK active edge⁽²⁾

Hold time, SPI_D[x] (SOMI) valid after SPI_CLK active edge⁽²⁾

(1)

t_{h(SPICLK-SOMI)}

(1) This timing applies to all configurations regardless of SPIx_CLK polarity and which clock edges are used to capture input data.

(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

表 5-95. Switching Characteristics for SPI Output Timings—Master Mode

NO.

PARAMETER

MIN

20⁽⁵⁾

MAX

UNIT

t_c(SPICLK)

Cycle time, SPI_CLK

t_w(SPICLKL)

t_w(SPICLKH)

t_r(SPICLK)

Typical Pulse duration, SPI_CLK low

Typical Pulse duration, SPI_CLK high

Rising time, SPI_CLK

0.45P⁽¹⁾

S3R

S3F

t_f(SPICLK)

Falling time, SPI_CLK

Delay time, SPI_CLK active edge to SPI_D[x] (SIMO) transition⁽²⁾

t_{d(SPICLK-SIMO)}

-2

A - 5⁽⁴⁾

C - 5⁽⁴⁾

E - 5⁽⁴⁾

G - 5⁽⁴⁾

Mode 1 and 3⁽³⁾

B + 5⁽⁴⁾

D + 5⁽⁴⁾

F + 5⁽⁴⁾

H + 5⁽⁴⁾

t_d(CS-SPICLK)

Delay time, SPI_CS active to SPI_CLK first edge

Delay time, SPI_CLK last edge to SPI_CS inactive

Mode 0 and 2⁽³⁾

Mode 1 and 3⁽³⁾

Mode 0 and 2⁽³⁾

t_d(SPICLK-CS)

(1) P = SPI_CLK period.

(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which spix_simo is driven and spix_somi is latched is all software

configurable:

–

PHASE = 1 Mode 3 and Mode 1.

PHASE = 0 Mode 2 and Mode 0.

(4) A = (2 × P2) + (0.5 × SPI_CLK)

B = (2 × P2) + (C2TDELAY +1) × P2) + (0.5 × SPI_CLK)

C = (2 × P2)

D = (2 × P2) + (C2TDELAY +1) × P2)

E = (1 × P2)

F = (1 × P2) + ((T2CDELAY+1) × P2)

G = (1 × P2) + (0.5 × SPI_CLK)

H = (1 × P2) + ((T2CDELAY+1) × P2) + (0.5 × SPI_CLK)

P2 = 1/(SYSCLK1 / 6)

(5) Minimum clock period is dependent on SYSCLK1 and SPI module prescaler settings and may be higher than shown in the table.

Specifications

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PHA=0

EPOL=1

SPI_CS[x] (Out)

S3F

S3R

POL=0

SPI_SCLK (Out)

POL=1

SPI_SCLK (Out)

SPI_D[x] (SOMI, In)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[x] (Out)

S3F

S3R

POL=0

SPI_SCLK (Out)

POL=1

SPI_SCLK (Out)

SPI_D[x] (SOMI, In)

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

SPI_03

图 5-86. SPI Master Mode Receive Timing

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PHA=0

EPOL=1

SPI_CS[x] (Out)

S3F

S3R

POL=0

POL=1

SPI_SCLK (Out)

S3F

S3R

SPI_SCLK (Out)

Bit n-1

SPI_D[x] (SIMO, Out)

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[x] (Out)

SPI_SCLK (Out)

S3F

S3R

POL=0

POL=1

S3F

S3R

SPI_SCLK (Out)

Bit n-1

SPI_D[x] (SIMO, Out)

Bit n-2

Bit n-3

Bit 1

Bit 0

SPI_04

图 5-87. SPI Master Mode Transmit Timing

5.9.4.15 Timers

For more details about features and additional description information on the device Timers, see the

corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed Description.

表 5-96. Timer Input Timing Requirements

NO.

PARAMETER

t_w(TINPH)

MIN

12C⁽¹⁾

MAX

UNIT

Pulse duration, high

Pulse duration, low

t_w(TINPL)

(1) C=1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL.

表 5-97. Timer Output Switching Characteristics

NO.

PARAMETER

t_w(TOUTH)

MIN

UNIT

Pulse duration, high

Pulse duration, low

12C⁽¹⁾- 3

t_w(TOUTL)

Specifications

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(1) C=1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL.

TIMIx

TIMOx

TIMER_01

图 5-88. Timer Timing

For more information, see section Timers in chapter Peripherals of the Device TRM.

5.9.4.16 UART

For more details about features and additional description information on the device Universal

Asynchronous Receiver Transmitter, see the corresponding sections within 节 4.3, Signal Descriptions and

节 6, Detailed Description.

表 5-98, 图 5-89, and 图 5-92 present Timing Requirements for UART interface.

表 5-98. Timing Requirements for UART

NO.

MIN

MAX UNIT

Receive Timing

t_w(RXSTART)

t_w(RXH)

Pulse width, receive start bit

0.96U⁽¹⁾

1.05U⁽¹⁾

Pulse width, receive data/parity bit high

Pulse width, receive data/parity bit low

Pulse width, receive stop bit

1.05U⁽¹⁾

t_w(RXL)

t_w(RXSTOP)

(1) U = UART baud time = 1 / programmed baud rate.

(2) P = 1/(SYSCLK1/6). SYSCLK1 clock is sourced from the main PLL.

RXD

Start

Bit 0

Bit 1

Bit N-1

Bit N

Parity

Stop

Idle

Start

Stop/Idle

图 5-89. UART Receive Timing Waveform

表 5-99, 图 5-90, and 图 5-91 present Switching Characteristics for UART interface.

表 5-99. Switching Characteristics Over Recommended Operating Conditions for UART

NO.

PARAMETER

MIN

MAX

UNIT

Transmit Timing

t_w(TXSTART)

t_w(TXH)

Pulse width, transmit start bit

U⁽¹⁾- 2

U⁽¹⁾+ 2

Pulse width, transmit data/parity bit high

Pulse width, transmit data/parity bit low

Pulse width, transmit stop bit 1

t_w(TXL)

t_w(TXSTOP1)

t_w(TXSTOP15)

t_w(TXSTOP2)

U⁽¹⁾- 2

U⁽¹⁾+ 2

Pulse width, transmit stop bit 1.5

Pulse width, transmit stop bit 2

1.5U⁽¹⁾- 2

2U⁽¹⁾- 2

1.5U⁽¹⁾+ 2

2U⁽¹⁾+ 2

Autoflow Timing Requirements

t_d(RX-RTSH)

t_d(CTSL-TX)

Delay time, STOP bit received to RTS deasserted

Delay time, CTS asserted to START bit transmit

P⁽²⁾

5P⁽²⁾

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(1) U = UART baud time = 1 / programmed baud rate.

(2) P = 1/(SYSCLK1/6). SYSCLK1 clock is sourced from the main PLL.

TXD

Start

Bit 0

Bit 1

Bit N-1

Bit N

Parity

Stop

Idle

Start

Stop/Idle

图 5-90. UART Transmit Timing Waveform

RXD

RTS

Bit N-1

Bit N

Stop

Start

图 5-91. UART RTS (RXD Stop to RTS Output) – Autoflow Timing Waveform

TXD

CTS

Bit N-1

Bit N

Stop

Start

Bit 0

图 5-92. UART CTS (CTS to TXD Start Output) — Autoflow Timing Waveform

For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter

Peripherals of the Device TRM.

5.9.4.17 USB

The USB 2.0 subsystem is fully-compliant with the Universal Serial Bus (USB) Specification, revision 2.0.

Refer to the specification for timing details.

For more details about features and additional description information on the device Universal Serial Bus

Subsystem (USB), see the corresponding sections within 节 4.3, Signal Descriptions and 节 6, Detailed

Description.

For more information, see section Universal Serial Bus Subsystem (USB) in chapter Peripherals of the

Device TRM.

5.9.5 Emulation and Debug Subsystem

5.9.5.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)

For more details about features and additional description information on the device IEEE 1149.1

Standard-Test-Access Port, see the corresponding sections within 节 4.3, Signal Descriptions and 节 6,

Detailed Description.

5.9.5.1.1 JTAG Electrical Data and Timing

表 5-100, 表 5-101, and 图 5-93 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Specifications

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表 5-100. Timing Requirements for IEEE 1149.1 JTAG

NO.

MIN

9.2

MAX UNIT

J1 t_c(TCK)

J1H t_w(TCKH)

J1L t_w(TCKL)

J3 t_su(TDI-TCK)

t_su(TMS-TCK)

J4 t_h(TCK-TDI)

t_h(TCK-TMS)

Cycle time, TCK

Pulse duration, TCK high (40% of t_c)

Pulse duration, TCK low(40% of t_c)

Input setup time, TDI valid to TCK high

Input setup time, TMS valid to TCK high

Input hold time, TDI valid from TCK high

Input hold time, TMS valid from TCK high

表 5-101. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

MAX UNIT

J2 t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

8.24 ns

J1H

J1L

TCK

TDO

TDI / TMS

图 5-93. JTAG Test-Port Timing

170

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6 Detailed Description

6.1 Overview

The SoC is a low-cost, low-power device based on TI KeyStone II (KS2) Multicore SoC architecture. It is

optimized to achieve better power efficiency at similar performance compared to the preceding devices in

the KS2 family. In addition to cost and power optimization, the device also integrates peripherals that

facilitate industrial communications, control automotive and performance audio applications. It

incorporates the performance-optimized Cortex-A15 and a C66x DSP core, built to meet the processing

and system-level integration needs of automotive amplifiers, enterprise media gateway, focused end

equipment (FEE), and broad-market applications (software-defined radio (SDR), ProAudio, emerging

equipment that requires a low-power A15 or C66-class SoC).

注

For more information on features, subsystems, and architecture of superset System on Chip

(SoC), see the Device TRM.

Detailed Description

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6.2 Functional Block Diagram

66AK2G1x

Memory Subsystem

1x Arm®

1x C66x DSP

MSMC

1MB RAM w/ ECC

Cortex®–A15

EMIF 36-bits

DDR3L w/ ECC

GPMC

512KB L2 w/ ECC

1MB L2 w/ ECC

Algorithm Accelerators and Application-specific Subsystems

7x Timers

64-bits

Network Subsystem

Industrial Subsystem

EMAC

2x PRU-ICSS

Message Manager

eAVB/1588v2

RGMII/RMII/MII

Display Subsystem

EDMA

NAVSS

1x Video Pipeline

Blend/Scale/CSC

PMMC

Queue Manager

PKTDMA

LCD

DPI

Crypto Engine

Semaphore

ASRC

TeraNet

High-Speed

Serial Interfaces

Automotive Interfaces

2x DCAN

Control Interfaces General Connectivity

PCIe®

Single Lane

6x ePWM

2x eCAP

3x eQEP

2x GPIO

3x UART

4x SPI

Gen 2

MediaLB®

MOST150

2x USB 2.0

Dual Role

+ PHY

Audio Peripherals

3x McASP

3x I2C

Media & Data Storage

QSPI

McBSP

2x MMC/SD

intro_001

图 6-1. Functional Block Diagram

172

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6.3 Arm A15

The Arm Subsystem (ARMSS) of the SoC integrates a single Cortex-A15 processor with additional logic

for bus protocol conversion, local power management, and various debug and trace enhancements.

The Cortex-A15 processor is an Armv7A-compatible, multi-issue out-of-order superscalar execution

engine with integrated L1 caches.

The implementation also supports advanced SIMDv2 (NEON™ technology) and VFPv4 (vector floating

point) architecture extensions, security, virtualization, LPAE (large physical address extension), and

multiprocessing extensions.

The Arm Subsystem includes a 512KB L2 cache and support for AMBA4 AXI and AXI coherence

extension (ACE) protocols.

注

The Arm Subsystem is also referred to as Arm CorePac.

The Arm subsystem supports the following key features:

•

Arm Cortex-A15 processor, full implementation of Armv7-A architecture instruction set

32KB L1 instruction (L1I) and data (L1D) caches

512KB L2 cache

Super scalar, variable-length, out-of-order pipeline (12 stage in-order, 3-12 stage out-of-order)

128-bit instruction fetch

3-wide instruction decode

3-wide instruction dispatch

8-wide instruction issue

Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return

stack, and an indirect predictor

•

Integrated Neon and VFP (Vector Floating Point unit)

Support for security and virtualization extensions

Error Correction Code (ECC) protection for L1 data cache and L2 cache, parity protection for L1

instruction cache

•

32-entry fully-associative L1 Translation Look-aside Buffers (TLBs), for instruction fetch, data loads,

and data stores

•

512-entry 4-way set-associative L2 TLB

AMBA 4.0 AXI Coherency Extension (ACE) master port which is directly connected to MSMC

(Multicore Shared Memory Controller) for low-latency access to shared MSMC SRAM

•

Dedicated Arm clocking (ARM_PLL) for full flexibility in performance trade-offs

Support for four integrated generic timers, in addition to 1 dedicated SoC-level watchdog timer

(TIMER_5)

•

Support for invasive (stop-mode) and non-invasive (tracing, performance monitoring) debug modes

and cross triggering for multiprocessor debugging

Support for processor instruction trace using Program Trace Macrocell (PTM) and data trace (printf

style debug) using System Trace Macrocell (STM)

Support for up to 480 interrupt requests via the Arm Interrupt Controller (AINTC) module

The Arm subsystem does not support the following features:

•

ACP (Accelarator Coherancy Port) Slave

Native AXI Master interface (only MSMC option is used)

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The Arm subsystem integrates the following major blocks:

•

Single-core Arm Cluster

AXI2VBUS_MASTER

Debug and Trace components

ARM_VBUSP registers

AINTC

Global Timebase Counter (GTC)

Various interfaces for interaction with other SoC subsystems and modules

For more information, see section Arm Cortex-A15 Subsystem in chapter Processors and Accelerators

of the Device TRM.

6.4 C66x DSP Subsystem

The C66x DSP is the next-generation fixed-point and floating-point DSP. The new DSP enhances the

C674x, which merged the C67x+ floating point and the C64x+ fixed-point instruction set architectures. The

C66x DSP is object-code compatible with the C64x+ and C674x DSP.

The DSP sybsystem (C66x CorePac) supports the following key features:

•

Fixed/Floating-point C66x CPU based on a superset of the C64x+ and C67x+ ISA

Program Memory Controller (PMC):

–

32KB Level 1 Program (L1P) Cache/SRAM

Data Memory Controller (DMC):

32KB L1 Data (L1D) Cache/SRAM

Unified Memory Controller (UMC):

1024KB L2 Cache/SRAM

External Memory Controller (EMC):

•

–

Internal DMA (IDMA) engine

One 128-bit VBUSM slave port from TeraNet_DMA

One 32-bit VBUSP master port to TeraNet_CFG

•

XMC (Extended Memory Controller):

One 256-bit port to MSMC controller

–

•

Multistream prefetch buffer

Address extension/translation (32-bit to 36-bit)

Memory protection for multiple segments

Memory protection for all internal L1/L2 RAM

Error Detection for L1P

Error Detection and Correction for L1D

Error Detection and Correction for all L2

Integrated C66x CorePac interrupt controller (INTC) that works in conjunction with Chip-level Interrupt

Controller (CIC) for distribution of system interrupts to the C66x core. Interrupts can be routed directly

to the C66x core or through the CIC module in a flexible manner

•

Integrated leakage and dynamic power management

Debug/emulation capabilities:

–

Support for halt mode, real time and monitor mode debug capabilities

Support for processor instruction trace and system trace (printf-style debug)

•

Dedicated timer module (TIMER_0) for the C66x CorePac, integrated at SoC level. TIMER_0 can be

used as either general-purpose timer or watchdog timer

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Fore more information about:

•

C66x CorePac, see the TMS320C66x DSP CorePac User's Guide (SPRUGW0).

C66x CPU core, see the TMS320C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7).

C66x cache memory system, see the TMS320C66x DSP Cache User's Guide (SPRUGY8).

C66x debug/trace support, see chapter On-chip Debug of the Device TRM.

6.5 C66x Cache Subsystem

The purpose of this section is to provide an overview of the C66x cache memory architecture and to

specify its configuration in this device. Details on the C66x cache functionality can be found in the

TMS320C66x DSP Cache User Guide (SPRUGY8).

The device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB

level-1 data memory (L1D). Each memory has a unique location in the memory map (see chapter Memory

Map of the Device TRM).

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache

can be reconfigured via software through the L1PMODE field of the L1P Configuration Register

(L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac.

L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

For more information, see section C66x Cache Subsystem in chapter Processors and Accelerators of

the Device TRM.

6.6 PRU-ICSS

The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

consists of:

•

Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)

Data RAMs per PRU core

Instruction RAMs per PRU core

Shared RAM

Peripheral modules

Interrupt controller (ICSS_INTC).

The programmable nature of the PRU cores, along with their access to pins, events and all device

resources, provides flexibility in implementing fast real-time responses, specialized data handling

operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the

device.

The device has integrated two identical PRU subsystems (PRU-ICSS_0 and PRU-ICSS_1).

The PRU cores within each PRU-ICSS have access to all resources on the SoC through the Interface

Master port, and the external host processors can access the PRU-ICSS resources through the Interface

Slave port. The 32-bit interconnect bus connects the various internal and external masters to the

resources inside the PRU-ICSS. The PRU cores within the subsystems also have access to all resources

on the SoC through the TeraNet DMA Interconnect. A subsystem local Interrupt Controller — ICSS_INTC

handles system input events and posts events back to the device-level host CPUs.

The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate

independently or in coordination with each other and can also work in coordination with the device-level

host CPU. This interaction between processors is determined by the nature of the firmware loaded into the

PRU’s instruction memory.

Detailed Description

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The PRU subsystem includes the following main features:

•

Two PRU CPUs:

–

20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO)

Asynchronous capture [Serial Capture Unit (SCU)] with EnDat 2.2 protocol and Sigma-Delta

demodulation support

NOTE: There is no Sigma-Delta modulator inside the PRU. However, Sigma-Delta support is

enabled through digital filtering hardware in the PRU to perform Sinc filtering.

–

Multiplier with accumulation (MAC)

CRC16 and CRC32 HW accelerator

16-KB program RAM per PRU CPU (signified IRAM0 for PRU0 and IRAM1 for PRU1) with ECC

8-KB data RAM per PRU CPU (signified RAM0 for PRU0 and RAM1 for PRU1) with ECC

Two high-performance master (initiator) ports on the TeraNet_DMA interconnect — one per PRU

•

64-KB general purpose memory RAM (signified RAM2) with ECC, shared between PRU0 and PRU1

One Scratch-Pad (SPAD) memory:

–

3 Banks of 30 × 32-bit registers

•

Broadside direct connect between PRU cores within subsystem. Optional address translation for PRU

transaction to External Host

•

16 software events generated by two PRUs

One Ethernet MII_RT module (ICSS_MII_RT_CFG) with two MII ports and configurable connections to

PRUs

•

One MDIO Port (ICSS_MII_MDIO) to control external Ethernet PHY

One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions:

–

One Industrial Ethernet 64-bit timer with 9 capture and 16 compare events with slow and fast

compensation

•

16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS

Enhanced Capture Module (eCAP_0)

Interrupt Controller (ICSS_INTC):

–

Up to 64 input events supported

Supports up to to 10 interrupt channels

Generation of 10 Host interrupts: 2 Host interrupts to PRU0 and PRU1, 1 Host interrupt to PRU-

ICSS_0 and PRU-ICSS_1, 7 Host interrupts exported from the ICSS for signaling the Arm interrupt

controllers (pulse and level provided)

–

Each system event can be enabled and disabled

Each host event can be enabled and disabled

Hardware prioritization of events

•

One 32-bit VBUSP slave (target) port for memory mapped register and internal memories access

Two (master and slave) 32-bit VBUSP ports for low-latency interface between PRU-ICSS subsystems

Flexible power management support

Integrated 32-bit interconnect

All memories support ECC

For more information, see section Programmable Real-Time Unit Subsystem and Industrial

Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the Device TRM.

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6.7 Memory Subsystem

6.7.1 MSMC

The Multicore Shared Memory Controller (MSMC) manages traffic among the device ARMSS, DSP, DMA,

other master peripherals, and the DDR EMIF controller. It also provides a shared on-chip SRAM that is

accessible by the ARMSS, DSP and the master peripherals in the device.

The MSMC module has the following features:

•

CPU/1 frequency of operation (that is, frequency same as that of the ARMSS/DSP)

One 256-bit master interface for connection to external SDRAM (through DDR EMIF controller)

One 256-bit master interface for connection to TeraNet_DMA

One 256-bit slave interface for the DSP

One 256-bit slave interface for the ARMSS

One 256-bit slave interface for accesses to the shared SRAM

One 256-bit slave interface for accesses to the external SDRAM

Memory protection for accesses to both the shared SRAM and external SDRAM spaces

Address extension from 32-bit to 36-bit for larger addressing space

Error Detection and Correction (EDC) and scrubbing support for the MSMC SRAM

Level 2 or Level 3 shared SRAM that is accessible by the device ARMSS, DSP and the master

peripherals

•

Coherency between ARMSS L1/L2 cache and EDMA/system master peripherals (through SES/SMS

ports) in the SRAM space and SDRAM space

For more information, see section Multicore Shared Memory Controller (MSMC) in chapter Memory

Subsystem of the Device TRM.

6.7.2 DDR EMIF

This section describes the DDR External Memory Interface (EMIF) for the device.

The DDR EMIF controller supports:

•

DDR3L Memory device compliant to JEDEC JESD79-3F and JESD79-3-1 (DDR3L addendum)

standards

•

16-bit and 32-bit SDRAM data bus without ECC

32-bit SDRAM data bus with 4-bit ECC

CAS latencies of 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16

CAS write latencies of 5, 6, 7, 8, 9, 10, 11, and 12

1, 2, 4, and 8 internal banks

Burst length of 8

Sequential burst type

4GB address space available over one chip select

33-bit system address for address space of 4GB

Page sizes with 256, 512, 1024, and 2048 words

Self-refresh mode

Power-down mode

Output impedance calibration

On-Die Termination (ODT)

Prioritized refresh scheduling

Programmable SDRAM refresh rate and backlog counter

Programmable SDRAM timing parameters

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•

Only little endian mode

ECC on SDRAM data bus:

–

8-bit ECC per 64-bit data quanta without additional cycle latency

1-bit correction and 2-bit detection

Statistics for 1-bit ECC and 2-bit ECC errors

Programmable address ranges to define ECC protected region

ECC calculated and stored on all writes to ECC protected address region

ECC verified on all reads to ECC protected address region

Two ECC modes supported:

•

Read-Modify-Write (RMW) ECC enabled to support sub quanta accesses to the ECC space.

RMW ECC disabled

•

Class of service

UDIMM address mirroring.

The DDR EMIF controller does not support:

•

Any memory types except DDR3L

RDIMMs

ECC for 16-bit mode

Single ended DQS

Mixed 8-bit and 16-bit SDRAM configurations

4-bit SDRAMs.

For more information, see section DDR External Memory Interface (EMIF) in chapter Memory Subsystem

of the Device TRM.

6.7.3 GPMC

The general-purpose memory controller (GPMC) is a unified memory controller dedicated for interfacing

with external memory devices like:

•

Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

Asynchronous, synchronous, and page mode (available only in nonmultiplexed mode) burst NOR flash

devices

•

Pseudo-SRAM devices

The main features of the GPMC are:

•

8- or 16-bit-wide data path to external memory device

Supports up to 4 chip select regions of programmable size and programmable base addresses in a

total address space of 1 GB

•

Fully pipelined operation for optimal memory bandwidth usage

The clock to the external memory is provided from GPMC_FCLK divided by 1, 2, 3, or 4

Supports programmable autoclock gating when no access is detected

Independent and programmable control signal timing parameters for setup and hold time on a per-chip

basis. Parameters are set according to the memory device timing parameters with a timing granularity

of one GPMC_FCLK clock cycle.

•

Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin

monitoring

•

Support bus keeping

Support bus turnaround

32-bit TeraNet slave interface which supports non-wrapping and wrapping burst of up to 16 x 32 bits.

The GPMC supports the following various access types:

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•

Asynchronous read/write access

Asynchronous read page access (4-, 8-, and 16- Word16)

Synchronous read/write access

Synchronous read/write burst access without wrap capability (4-, 8-, and 16- Word16)

Synchronous read/write burst access with wrap capability (4-, 8-, and 16- Word16)

Address-data-multiplexed (AD) access

Address-address-data (AAD) multiplexed access

Little-endian access only

The GPMC can communicate with a wide range of external devices:

•

External asynchronous or synchronous 8-bit wide memory or device (non burst device)

External asynchronous or synchronous 16-bit wide memory or device

External 16-bit nonmultiplexed NOR flash device

External 16-bit address and data multiplexed NOR Flash device

External 16-bit pseudo-SRAM (pSRAM) device

For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory

Subsystem of the Device TRM.

6.8 Interprocessor Communication

6.8.1 MSGMGR

The SoC implements a single instance of the Message Manager to provide inter-processor communication

between the various processing units:

•

Arm (Cortex-A15)

DSP (C66x)

PMMC (CPU)

PRU-ICSS (PRUs)

The Message Manager is a hardware engine used for queuing messages in a secure and self-contained

manner. There is no limitation on the message format or content. It is software responsibility to define the

message format.

The Message Manager provides a multi-core and multi-process safe message interface which allows

multiple users (message senders and receivers) to access the queues without the need for any mutual

exclusion. It also allows for secure and authorized access to the queues.

The general features of the Message Manager module include:

•

Provides hardware acceleration for pushing/popping messages to/from logical queues

Supports the following SoC configuration:

–

64 queues

Up to 128 pending messages

64-byte messages

32 proxies (single proxy per page)

•

Support for highly-pipelined push/pop operations

Support for self-contained mode with zero SW initialization

Provides a secure front-end for the queues

Provides flexible message allocation with ability to store the same message multiple times in different

queues or multiple times in the same queue

•

Queue depth limited only by the maximum number of messages

Support for little-endian (LE) operation only

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Monitoring and trace functions include:

•

Provides hardware signals to monitor the empty status for all transmit source queues

Provides ability to read Linking RAM contents for debug purposes

Provides ability to generate an interrupt when there are no free entries in the Linking RAM

Provides ability to generate an interrupt due to a proxy fault

For more information, see section Message Manager in chapter Interprocessor Communication of the

Device TRM.

6.8.2 SEM

This chapter describes the operation of the Semaphore hardware module. The Semaphore module is

accessible across all the cores on a multicore environment. The module supports up to 64 independent

semaphores that help the application to implement shared-resource protection mechanism across multiple

cores. Each of the semaphores can be accessed by the cores in direct, indirect, or combined modes.

In a multicore environment where system resources must be shared it is important to control simultaneous

accesses to the available resources. To ensure correct system operation, it is necessary to limit access to

a resource by one and only one core at a time; that is, it is necessary to provide mutual exclusion for

resources shared across multiple cores.

The Semaphore module provides a mechanism that applications can use to implement mutual exclusion

of shared resources across multiple cores. The following CPU cores can be semaphore masters on this

device:

•

DSP C66x

Arm Cortex-A15

PMMC CPU

ICSS0_PRU0

ICSS0_PRU1

ICSS1_PRU0

ICSS1_PRU1

The Semaphore module supports the following features:

•

Provides mutual exclusion for a shared resource

A maximum of 16 semaphore masters (device cores)

A maximum of 64 independent semaphores

Semaphore request methods:

–

Direct request

Indirect request

Combined request

•

Endian independent

Atomic semaphore access

Lock-out mechanism for used semaphores

Queued requests for used semaphores

Semaphores access grant interrupt for queued requests

Allows the application to check the status of any of the semaphores

Error detection and interrupts

For more information, see section Semaphore Module in chapter Interprocessor Communication of the

Device TRM.

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6.9 EDMA

The primary purpose of the Enhanced Direct Memory Access (EDMA) controller is to service user-

programmed data transfers between two memory-mapped slave endpoints on the device.

Typical usage of the EDMA controller includes:

•

Servicing software-driven paging transfers (for example, data movement between external memory

[such as SDRAM] and internal memory [such as DSP L2 SRAM])

•

Servicing event-driven peripherals, such as a serial port

Performing sorting or sub-frame extraction of various data structures

Offloading data transfers from the main device CPUs, such as the C66x DSP CorePac or the Arm

CorePac

The EDMA controller consists of two major principle blocks:

•

EDMA Channel Controller

EDMA Transfer Controller(s)

The EDMA Channel Controller (EDMACC) serves as the user interface for the EDMA controller. The

EDMACC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers.

The EDMACC serves to prioritize incoming software requests or events from peripherals and submits

transfer requests (TR) to the EDMA transfer controller.

The EDMA Transfer Controller (EDMATC) is responsible for data movement. The transfer request packets

(TRP) submitted by the EDMACC contain the transfer context, based on which the transfer controller

issues read/write commands to the source and destination addresses programmed for a given transfer.

There are two EDMA controllers present on this device:

•

EDMA_0, integrating:

–

1 Channel Controller, referenced as: EDMACC_0

2 Transfer Controllers, referenced as: EDMACC_0_TC_0 (or EDMATC_0) and EDMACC_0_TC_1

(or EDMATC_1)

•

EDMA_1, integrating:

–

1 Channel Controller, referenced as: EDMACC_1

2 Transfer Controllers, referenced as: EDMACC_1_TC_0 (or EDMATC_2) and EDMACC_1_TC_1

(or EDMATC_3)

The two EDMA channel controllers (EDMACC_0 and EDMACC_1) are functionally identical. For

simplification, the unified name EDMACC shall be regularly used throughout this chapter when referring to

EDMA Channel Controllers functionality and features.

The four EDMA transfer controllers (EDMACC_0_TC_0, EDMACC_0_TC_1, EDMACC_1_TC_0 and

EDMACC_1_TC_1) are functionally identical. For simplification, the unified name EDMATC shall be

regularly used throughout this chapter when referring to EDMA Transfer Controllers functionality and

features.

Each EDMACC has the following features:

•

Fully orthogonal transfer description:

–

3 transfer dimensions:

•

Array (multiple bytes)

Frame (multiple arrays)

Block (multiple frames)

–

Single event can trigger transfer of array, frame, or entire block

Independent indexes on source and destination

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•

Flexible transfer definition:

–

Increment or constant addressing modes

Linking mechanism allows automatic PaRAM set update

Chaining allows multiple transfers to execute with one event

64 DMA channels:

–

Channels triggered by either:

•

Event synchronization

Manual synchronization (CPU write to event set register)

Chain synchronization (completion of one transfer triggers another transfer)

–

Support for programmable DMA Channel to PaRAM mapping

•

8 Quick DMA (QDMA) channels:

–

QDMA channels are triggered automatically upon writing to PaRAM set entry

Support for programmable QDMA channel to PaRAM mapping

•

512 PaRAM sets:

Each PaRAM set can be used for a DMA channel, QDMA channel, or link set

2 transfer controllers/event queues:

16 event entries per event queue

Interrupt generation based on:

–

Transfer completion

Error conditions

•

Debug visibility:

–

Queue water marking/threshold

Error and status recording to facilitate debug

Memory protection support:

–

Proxied memory protection for TR submission

Active memory protection for accesses to PaRAM and registers

Each EDMATC has the following features:

•

Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC

manages the 3rd dimension)

•

Up to 4 in-flight transfer requests (TR)

Programmable priority levels

Support for increment or constant addressing mode transfers

Interrupt and error support

Supports only little-endian operation in this device

Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR

For more information chapter EDMA Controller of the Device TRM.

6.10 Peripherals

6.10.1 DCAN

Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed

real-time applications. CAN has high immunity to electrical interference and the ability to self-diagnose and

repair data errors. In a CAN network, many short messages are broadcast to the entire network, which

provides for data consistency in every node of the system.

The device supports two DCAN modules, referred to as DCAN_0 and DCAN_1, connecting to the CAN

network through external (for the device) transceivers. The DCAN modules support bit rates up to 1 Mbit/s

and are compliant to the CAN 2.0B Protocol Specification.

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The DCAN module implements the following features:

•

Support for CAN protocol version 2.0 part A, B

Bit rates up to 1 Mbit/s

Dual clock source

64 message objects in a dedicated message RAM

Individual identifier mask for each message object

Programmable FIFO mode for message objects

Programmable loop-back modes for self-test operation

Software module reset

Suspend mode for debug support

Automatic bus on after Bus-Off state by a programmable 32-bit timer

Message RAM single error correction and double error detection mechanism (SECDED)

Direct access to message RAM during test mode.

Support for three interrupt lines: Level 0 and Level 1, and a separate ECC interrupt line

Local power down and wakeup support

Automatic message RAM initialization

Support for DMA access

For more information, see section Dual Controller Area Network (DCAN) Interface in chapter Peripherals

of the Device TRM.

6.10.2 DSS

The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS includes a DMA

engine as part of the integrated Display Controller (DISPC) module, which allows direct access to the

frame buffer (system memory). Various pixel processing capabilities are supported, such as: color space

conversion, filtering, scaling, etc.

The supported display interfaces (connections to external panel) are:

•

One parallel interface, which can be used for MIPI® DPI 2.0, or BT-656 or BT-1120.

One RFBI interface, supporting MIPI DBI 2.0.

The modules integrated in DSS are:

Display Controller (DISPC), with the following main features

•

–

One Direct Memory Access (DMA) engine

One Video Pipeline (VID1) with color space conversion and in-loop up/down-scaling

One Overlay Manager (OVR1)

Active Matrix color support for 12/16/18/24-bit (truncated or dithered encoded pixel values)

One Video Port (VP1) with programmable timing generator to support up to 148.5 MHz pixel clock

video formats defined in CEA-861-E and VESA DMT standards

–

Supported maximum FrameBuffer width of 4096 for all pixel formats

Configurable output mode: progressive or interlaced

Selection between RGB and YUV422 output pixel formats (YUV4:2:2 only available when BT-656

or BT-1120 output mode is enabled on the DPI interface)

–

Stall Mode support for RFBI

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•

Remote Frame Buffer Interface (RFBI) module, with the following main features:

–

Access to RFB direct "ARMSS interface":

•

Sending commands and data to the RFB panel, received from DISPC or from ARMSS (through

the 32-bit interconnect slave port)

•

Reading data/status from the RFB through the 32-bit interconnect slave port

–

RFB interface:

•

8/9/12/16-bit data bus (for up to QVGA @30fps)

Two programmable configurations for two peripheral devices connected to the RFBI module

Tearing Effect control logic: Horizontal Synchronization (HSync) and Vertical Synchronization

(VSync) embedded in a single signal (TE) or using two signals (HS+VS)

•

Programmable pixel memory and output formats

DSS provides two interfaces to SoC interconnect:

•

One 128-bit master port (with MFLAG support). The DMA engine in DISPC uses this single master port

to read data from SoC system memory.

•

One 32-bit slave port. Used for configuration of the memory mapped registers inside DSS. It is further

connected internally to DISPC and RFBI modules.

For more information, see section Display Subsystem (DSS) in chapter Peripherals of the Device TRM.

6.10.3 eCAP

The enhanced Capture (eCAP) module can be used for:

•

Sample rate measurements of audio inputs

Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)

Elapsed time measurements between position sensor pulses

Period and duty cycle measurements of pulse train signals

Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.

The eCAP module includes the following features:

•

32-bit time base counter

4-event time-stamp registers (each 32 bits)

Edge polarity selection for up to four sequenced time-stamp capture events

Interrupt on either of the four events

Single shot capture of up to four event time-stamps

Continuous mode capture of time-stamps in a four-deep circular buffer

Absolute time-stamp capture

Difference (Delta) mode time-stamp capture

All above resources dedicated to a single input pin

When not used in capture mode, the eCAP module can be configured as a single channel PWM

output.

For more information, see section Enhanced Capture (eCAP) Module in chapter Peripherals of the Device

TRM.

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6.10.4 ePWM

An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU

overhead or intervention. It needs to be highly programmable and very flexible while being easy to

understand and use. The ePWM unit described here addresses these requirements by allocating all

needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources

has been avoided; instead, the ePWM is built up from smaller single channel modules with separate

resources and that can operate together as required to form a system. This modular approach results in

an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users

to understand its operation quickly.

In the further description the letter x within a signal or module name is used to indicate a generic ePWM

instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from

the ePWM_x instance. Thus, EPWM1A and EPWM1B belong to ePWM_1, EPWM2A and EPWM2B

belong to ePWM_2, and so forth.

The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA

and EPWMxB. A given ePWM module functionality can be extended with the so called High-Resolution

Pulse Width modulator.

Each ePWM module supports the following features:

•

Dedicated 16-bit time-base counter with period and frequency control

Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:

–

Two independent PWM outputs with single-edge operation

Two independent PWM outputs with dual-edge symmetric operation

One independent PWM output with dual-edge asymmetric operation

•

Asynchronous override control of PWM signals through software

Programmable phase-control support for lag or lead operation relative to other ePWM modules

Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis

Dead-band generation with independent rising and falling edge delay control

Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions

A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs

Allows events to trigger both CPU interrupts and ADC start of conversions

Programmable event prescaling minimizes CPU overhead on interrupts

PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.

For more information, see section Enhanced PWM (ePWM) Module in chapter Peripherals of the Device

TRM.

6.10.5 eQEP

A single track of slots patterns the periphery of an incremental encoder disk. These slots create an

alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs

that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that

occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position.

Encoder manufacturers identify the index pulse using different terms such as index, marker, home position

and zero reference.

To derive direction information, the lines on the disk are read out by two different photo-elements that

"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is

realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk

lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of

phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The

clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB

channel and vise versa.

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The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at

a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from

the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line

encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of

166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can

determine the velocity of the motor.

For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter

Peripherals of the Device TRM.

6.10.6 GPIO

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When configured as an output, user can write to an internal register

to control the state driven on the output pin. When configured as an input, user can obtain the state of the

input by reading the state of an internal register.

In addition, the GPIO peripheral can produce CPU interrupts and EDMA synchronization events in

different interrupt/event generation modes.

The device has two instances of GPIO144 modules (GPIO_0 and GPIO_1). The GPIO pins are grouped

into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated

general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to

288 (2 instances × (9 banks × 16 pins)) pins. Since GPIO1_[143:68] are reserved in this Device, general-

purpose interface supports up to 212 pins.

Each channel in the GPIO modules has the following features:

•

Supports 9 banks of 16 GPIO signals

Supports up to 9 banks of interrupt capable GPIOs

Interrupts:

–

Can enable interrupts for each bank of 16 GPIO signals

Interrupts can be triggered by rising and/or falling edge (or neither edge = disabled), specified for

each interrupt capable GPIO signal

•

Set/clear functionality:

–

Software writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows

multiple software processes to toggle GPIO output signals without critical section protection (disable

interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process

during GPIO programming).

Separate Input/Output registers:

–

Output register in addition to set/clear so that if preferred by software, some GPIO output signals

can be toggled by direct write to the output register(s).

–

Output register, when read in, reflects output drive status. This, in addition to the input register

reflecting pin status and open-drain I/O cell, allows wired logic be implemented.

For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the Device

TRM.

6.10.7 I2C

The multi-master inter-integrated circuit (I2C) peripheral provides an interface between the device and any

I²C-bus-compatible device that is connected via the I²C serial bus. External components attached to the

I²C bus can serially transmit/receive up to 8-bit data to/from the device through the two-wire I²C interface.

Each I2C module has the following features:

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•

Compliance with the Philips Semiconductors I²C-bus Specification (version 2.1):

–

Supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps)

Support for byte format transfer

7-bit addressing mode

General call

START byte mode

Support for multiple master-transmitters and slave-receivers mode

Support for multiple slave-transmitters and master-receivers mode

Combined master transmit/receive and receive/transmit mode

•

2 to 7 bit format transfer

Free data format mode

One read DMA event and one write DMA event that can be used by the DMA

Seven interrupts that can be used by the CPU

Module enable/disable capability

I2C module unsupported features:

•

GPIO mode

High-speed (HS) mode

10-bit device addressing mode

The I2C module is compliant with the Philips Semiconductors Inter-IC bus (I²C-bus) Specification version

2.1.

For more information, see section Inter-IC module (I2C) in chapter Peripherals of the Device TRM.

6.10.8 ASRC

The reception of many different audio sources and the transmission of these to different audio zones, may

require different audio clocks. The asynchronous Audio Sample Rate Converter (ASRC) module takes

samples from one clock zone and moves them to another, while maintaining a high signal to noise ratio to

ensure that the output quality is sufficient to meet the requirements for various high-end algorithms.

The ASRC module supports the following main features:

•

High performance Asynchronous Sample Rate Converter with 140 dB Signal-to-Noise (SNR)

Up to 8 stereo streams (16 audio channels)

Automatically sensing / detection of input sample frequencies

Attenuation of sampling clock jitter

16-, 18-, 20-, 24-bit data input/output

Audio sample rates from 8 kHz to 216 kHz

Input/output sampling ratios from 16:1 to 1:16

Group mode, where multiple ASRC blocks use the same timing loop for input or output

Linear phase FIR filter

Controllable soft mute

Independent Clock Generator, and Rate and Stamp generator, for each input and output clock zone

Separate DMA events for input and output, for each channel and group

For more information, see section Audio Sample Rate Converter (ASRC) in chapter Peripherals of the

Device TRM.

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6.10.9 McASP

The Multi-channel Audio Serial Port (McASP) module functions as a general-purpose audio serial port

optimized for the needs of multichannel audio applications. The McASP supports transmission and

reception of time-division multiplexed (TDM) and Inter-IC Sound (I²S) protocols. In addition, it supports

intercomponent digital audio interface transmission (DIT).

The McASP consists of transmit and receive sections that may operate synchronized, or completely

independently with separate master clocks, bit clocks, and frame syncs, and using different transmit

modes with different bit-stream formats. The McASP module also includes up to 16 serializers that can be

individually enabled to either transmit or receive.

The device integrates three McASP modules (McASP0, McASP1, and McASP2) with:

•

McASP0 supporting 16 serializers with independent TX/RX clock zones

McASP1 supporting 10 serializers with independent TX/RX clock zones

McASP2 supporting 6 serializers with independent TX/RX clock zones

Each McASP module includes the following main features:

•

Up to 16 individually assignable serializers, each with its own data pins (AXR)

A single 32-bit buffer per serializer for transmit and receive operations

2x interconnect slave interface ports:

–

A configuration (CFG) port

A slave DMA data port synchronized with functional clock

•

Two independent clock generator modules for transmit and receive:

–

Clocking flexibility allows the McASP to receive and transmit at different rates. For example, the

McASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz.

Configurable functional clocks:

–

May be generated internally (master mode)

May be supplied by an external device (slave mode)

May be divided down internally

•

Independent transmit and receive modules, each providing:

–

Programmable clock and frame sync generator

TDM streams from 2 to 32, and 384 time slots

Support for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits

Data formatter for bit manipulation

•

Glueless connection to audio analog-to-digital converters (ADC), digital-to-analog converters (DAC),

codec, digital audio interface receiver (DIR), and S/PDIF transmit physical layer components.

•

Support for wide variety of I²S and similar bit-stream formats

Integrated digital audio interface transmitter (DIT):

–

S/PDIF, IEC60958-1, AES-3 formats.

Enhanced channel status/user data RAM

•

384-slot TDM with external digital audio interface receiver (DIR) device:

–

For DIR reception, an external DIR receiver integrated circuit should be used with I²S output format

and connected to the McASP receive section

Support for 2x DMA requests (1 per direction) per each McASP module:

–

1 level-sensitive transmit direct memory access (DMA) request common for all of the McASP

serializers

–

1 level-sensitive receive direct memory access (DMA) request common for all of the McASP

serializers

•

One transmit interrupt request common for all serializers per McASP module

One receive interrupt request common for all serializers per McASP module

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•

Extensive error checking and recovery:

–

Transmit underruns and receiver overruns due to the system not meeting real-time requirements

Early or late frame sync in TDM mode

DMA error due to incorrect programming

McASP Audio FIFO (AFIFO):

–

Provides additional data buffering

Provides added tolerance to variations in host/DMA controller response times

May be used as a DMA event pacer

Independent Read FIFO and Write FIFO

256 bytes of RAM for each FIFO (read and write), where:

•

256 bytes = four 32-bit words per serializer in the case of 16 data pins

256 bytes = 64 32-bit words in the case of one data pin

–

Option to bypass Write FIFO and/or Read FIFO independently

For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the

Device TRM.

6.10.10 McBSP

The Multi-channel Buffered Serial Port (McBSP) provides a full-duplex serial communication interface

between the device and other devices in a system. The primary use for the McBSP is for audio interface

purposes. The main audio modes that are supported are the AC97 and I²S modes. In addition to the

primary audio modes, the McBSP can be programmed to support other serial formats but is not intended

to be used as a high-speed interface. The device communicates to the McBSP using 32-bit-wide control

registers accessible via the internal peripheral bus.

The McBSP provides the following functions:

•

Full-duplex communication

Double-buffered data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

•

External shift clock or an internal, programmable frequency shift clock for data transfer

In addition, the McBSP has the following capabilities:

•

Direct interface to:

–

T1/E1 framers

MVIP switching compatible and ST-BUS compliant devices including:

•

MVIP framers

H.100 framers

SCSA framers

–

IOM-2 compliant devices

AC97 compliant devices (the necessary multiphase frame synchronization capability is provided)

I²S compliant devices

•

Multi-channel transmit and receive of up to 128 channels

A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits

μ-Law and A-Law companding

8-bit data transfers with the option of LSB or MSB first

Programmable polarity for both frame synchronization and data clocks

Highly programmable internal clock and frame generation

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•

Additional McBSP Buffer FIFO (BFIFO):

–

Provides additional data buffering

Provides added tolerance to variations in host/DMA controller response times

May be used as a DMA event pacer

Independent Read FIFO and Write FIFO

256 bytes of RAM for each FIFO (read and write)

Option to bypass Write FIFO and/or Read FIFO, independently

McBSP module unsupported features:

•

The McBSP on this device does not support the SPI protocol.

512 Channel Mode

Individual enable/disable channel control

Timeslot buffering

Super frame synchronization

ABIS Mode

For more information, see section Multi-channel Buffered Serial Port (McBSP) in chapter Peripherals of

the Device TRM.

6.10.11 MLB

The Media Local Bus subsystem (MLB) is based on a module designed by SMSC. This module provides a

MediaLB/MediaLB+ controller and an interface to other MediaLB/MediaLB+ devices. The

MediaLB/MediaLB+ interface allows also connection to a MOST (Media Oriented Systems Transport)

network controller.

The MLB supports the following features:

•

3-pin MediaLB 3.3V LVCMOS I/Os compliant to MediaLB Physical Layer Specification v4.2

6-pin MediaLB+ low-voltage differential signaling (LVDS) I/Os (3 differential pairs) compliant to

MediaLB Physical Layer Specification v4.2

•

MediaLB core functionality compliant to MediaLB Physical Layer and Link Layer Specification v4.2

Supports 256/512/1024Fs in 3-pin mode and 2048Fs in 6-pin mode

Supports all types of transfer (synchronous stream data, asynchronous packet data, control message

data, and isochronous data) over 64 logical channels

•

Supports single 32-bit TeraNet_CFG slave interface for configuration

Supports single 32-bit TeraNet_DMA master interface with burst capability for DMA transfers into

system memory. The maximum burst size is 32 Bytes

•

Has 16 KB buffer for all types of transfers in the subsystem

Dedicated BOOT_CFG bits for controlling the MLB priority on the system interconnect

The MLB does not support:

•

5-pin mode

Digital Transmission Content Protection (DTCP) cipher accelerators

For more information, see section Media Local Bus (MLB) in chapter Peripherals of the Device TRM.

6.10.12 MMC/SD

The multimedia card (MMC), secure digital (SD), and secure digital I/O (SDIO) high-speed controller

(MMC/SD) provides an interface between a local host (LH) such as microprocessor unit (MPU) or digital

signal processor (DSP) and either MMC, SD memory card, or SDIO card and handles MMC, SD, and

SDIO transactions with minimal LH intervention. There are two MMC/SD host controllers inside the device.

Each controller has an 8-bit wide data bus.

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The MMC/SD host controllers support the following main features:

•

Full compliance with MMC/eMMC command/response sets as defined in the JC64 MMC/eMMC

Standard Specification, v4.5.

Full compliance with SD command/response sets as defined in the SD Physical Layer Specification

v3.01.

Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume

operations as defined in the SD part E1 Specification v3.00.

Full compliance with SD Host Controller Standard Specification sets as defined in the SD card

Specification Part A2 v3.00.

Main features of the MMC/SD host controllers:

•

Flexible architecture allowing support for new command structure

Designed for low power (Local Power Management)

Programmable clock generation

Card insertion/removal detection and write protect detection

The slave interface supports:

–

32-bit wide data bus

Streaming burst supported only with burst length up to 7

WNP supported

•

The master interface supports:

–

32-bit wide data bus

Burst supported

•

Built-in 1024-byte buffer for read or write

Two DMA channels, one interrupt line

Support JC 64 v4.4.1 boot mode operations

Support SDA 3.00 Part A2 programming model

Support SDA 3.00 Part A2 DMA feature (ADMA2)

Supported data transfer rates:

–

MMC0 supports the following data transfer rates (eMMC/SD):

•

SDR12 (3.3 V IOs): up to 12 MBps (24 MHz clock)

SDR25 (3.3 V IOs): up to 24 MBps (48 MHz clock)

HS mode (3.3 V IOs): up to 24 MBps (48 MHz clock)

DS mode (3.3 V IOs): up to 12 MBps (24 MHz clock)

Default SD mode 1-bit data transfer up to 24 Mbps (3 MBps)

–

MMC1 supports the following data transfer rates (eMMC):

•

SDR12 (1.8 V IOs): up to 12 MBps (24 MHz clock)

SDR25 (1.8 V IOs): up to 24 MBps (48 MHz clock)

DDR50 (1.8 V IOs): up to 48 MBps (48 MHz clock)

1.8 V legacy modes with 1/4/8-bit single data rate at up to 26 MHz bus clock

•

MMC0 Supports 3.3-V IO modes only

MMC1 Supports 1.8-V IO modes only

The differences between the MMC/SD host controller and a standard SD host controller defined by the SD

Card Specification, Part A2, SD Host Controller Standard Specification, v3.00 are:

•

The clock divider in the MMC/SD host controller supports a wider range of frequency than specified in

the SD Memory Card Specifications, v3.0. The MMC/SD host controller supports odd and even clock

ratio.

•

The MMC/SD host controller supports configurable busy time-out.

ADMA2 64-bit mode is not supported.

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•

There is no external LED control.

The following features are not supported:

•

Byte or half-word accesses. Only word accesses to the slave port are supported.

MMC Out-of-band interrupt.

Dual voltage I/O (MMC0 Supports 3.3-V only. MMC1 Supports 1.8-V only).

No built-in hardware support for error correction codes (ECC).

SPI transfers are not supported.

Module doesn’t support card insertion/removal sensing with pull up resistor on MMCi_DAT[3] data bus

line as specified in the SD Physical Layer Specification.

For more information, see section Multimedia Card High Speed Interface (MMC/SD) in chapter

Peripherals of the Device TRM.

6.10.13 NSS

Networking Subsystem (NSS) consists of DMA/Queue Management components – Navigator Subsystem

(NAVSS), an Ethernet MAC (EMAC) Subsystem, and a packet Security Accelerator (SA).

The NSS, presented by its general sub-components, supports the following features:

•

NAVSS:

–

High Performance CPPI DMA Controller, 32 Receive Flows, 4 Loopback threads for infrastructure

mode

–

CPPI Queue Manager (QM) features:

•

Single QM

Supports up to 128 queues – 21 QPEND signals for TX use, remaining 107 QPEND signals are

for host use

•

2048 buffers supported in Internal Linking RAM

Two Queue Proxies provided for host interaction (one per DSP and ARMSS):

–

Queue Proxy 0 assigned to DSP

Queue Proxy 1 assigned to ARMSS

–

Support for SER protection (SECDED)

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•

EMAC Subsystem:

–

One Gigabit Ethernet port: MII/RMII/RGMII interfaces:

•

Supports 10-, 100-, 1000-Mbps full duplex

Supports 10-, 100-Mbps half duplex

–

One Host Port 0 CPPI Streaming Packet Interface (PSI)

Support Ethernet Audio/Video Bridging (eAVB) (P802.1Qav/D6.0)

Maximum frame size 2016 bytes (2020 bytes with VLAN)

Eight priority level QOS support (802.1p)

IEEE 1588v2 (2008 annex D, annex E, and annex F) to facilitate Audio/Video bridge 802.1AS

Precision Time Protocol:

•

Timestamp module capable of time stamping external timesync events like Pulse Per Second

and also generating Pulse Per Second outputs

•

CPTS module that supports time stamping for IEEE 1588v2 with support for 8 hardware push

events and generation of compare output pulses

–

DSCP Priority Mapping (IPv4 and IPv6)

Maximum frame size 2016 bytes (2020 with VLAN)

Address Lookup Engine (ALE)

Castagnoli or Ethernet CRC selectable for Ethernet ingress and egress (Host Port0 CRC is

Ethernet only)

–

MDIO module for PHY management

EtherStats and 802.3Stats RMON statistics gathering

Support for SER protection (SECDED)

•

Security Accelerator (SA):

–

Support IPSec and SRTP protocol stack

Support various encryption modes and algorithms such as:

•

ECB, CBC, CFB, OFB, F8, CTR, CBC-MAC, CCM, GCM, GMAC and AES-CMAC

AES, DES, 3DES, SHA-1, SHA-2 (224, 256-bit operation) and MD5

–

Support for True random number generator (TRNG) and Public Key Accelerator (PKA)

Support for SER protection (SECDED)

The NSS does not support the following features:

•

No external queue RAM supported

Priority Based Flow Control is not supported.

No Castignoli CRC to Host CPPI port.

For more information, see section Networking Subsystem (NSS) in chapter Peripherals of the Device

TRM.

6.10.14 PCIESS

Peripheral Component Interconnect Express (PCIE) controllers provide a high-speed glueless serial

interconnect to peripherals utilizing high bandwidth applications.

PCIe module is a multi-lane I/O interconnect that provides low pin-count, high reliability, and high-speed

data transfer at rates of up to 5.0 Gbps per lane, per direction, for serial links on backplanes and printed

curcuit boards. It is a 2nd generation I/O interconnect technology succeeding PCI and ISA bus designed

to be used as a general-purpose serial I/O interconnect. It is also used as a bridge to other interconnects

such as SATA, USB2/3.0, GbE MAC, and so forth.

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The PCI Express standard's predecessor - PCI, is a parallel bus architecture that is increasingly difficult to

scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe

architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the

necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It

is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its

practical performance limits while simplifying the interface design.

PCIe module supports the following features:

•

Dual operation mode: Root Complex (RC) or End Point (EP)

Supports a single bidirectional link interface (a single input port and a single output port) with one lane

Operated at a raw speed of 2.5 Gbps or 5.0 Gbps per lane per direction

Maximum outbound payload size of 128 bytes

Maximum inbound payload size of 256 bytes

Maximum remote read request size of 256 bytes

Ultra-low transmit and receive latency

Support for dynamic-width conversion

Automatic lane reversal

Polarity inversion on receive

Single virtual channel (VC)

Single traffic class (TC)

Single function in End Point (EP) mode

Automatic credit management

ECRC generation and checking

PCI device power management with the exception of D3cold with Vaux

PCI Express active state power management (ASPM) state L0s and L1

PCI Express link power management states, except L2 state

PCI Express advanced error reporting

PCI Express messages for both transmit and receive

Filtering for posted, non-posted, and completion traffic

Configurable BAR filtering, I/O filtering, configuration filtering, and completion lookup/timeout

Access to configuration space registers and external application memory-mapped registers through

BAR0 and through configuration access

•

Legacy interrupts reception (in RC) and generation (in EP)

MSI generation and reception

PHY loopback in RC mode

PCIe module does not support the following features:

•

No support for multiple lanes

No support for multiple VCs

No support for multiple TCs

No support for function-level reset

No support for PCI Express beacon for in-band wake

No built-in hardware support for hot-plug

No support for vendor messaging

No support for I/O access in inbound direction in RC or EP mode

No support for addressing modes other than incremental for burst transactions. Thus, the PCIe

addresses cannot be in cacheable memory space

•

No auxiliary power to maintain controller context when rezuming from D3cold state

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•

No support for L2 link state

For more information, see section Peripheral Component Interconnect Express Subsystem (PCIe SS) in

chapter Peripherals of the Device TRM.

6.10.15 QSPI

The Quad Serial Peripheral Interface (QSPI™) module is a kind of Serial Peripheral Interface (SPI)

module which allows single, dual or quad read and write access to external flash devices. This module

has a memory mapped register interface, which provides a direct memory interface for accessing data

from external flash devices, simplifying software requirements.

The QSPI module has the following features:

•

Memory-Mapped Direct mode of operation for performing flash data transfers and executing code from

flash memory.

•

Software triggered 'indirect' mode of operation for performing low latency and non-processor intensive

flash data transfers.

•

Local SRAM to reduce bus overhead and buffer flash data during indirect transfers.

Set of software accessible flash control registers to perform any flash command, including data

transfers up to 8-bytes at a time.

•

Supports any device clock frequency, including frequencies of 96 MHz (QSPI mode 0 only).

Supports XIP (Execute in Place), also referred to as continuous mode.

Supports single, dual or quad I/O instructions.

Supports 16/32/64 byte cacheline wrap accesses.

Supports ECC for its internal SRAM buffer.

Programmable device sizes.

Programmable write protected regions to block system writes from taking effect.

Programmable delays between transactions.

Legacy mode allowing software direct access to low level transmit and receive FIFOs bypassing the

higher layer processes.

•

Independent reference clock to decouple bus clock from SPI clock – allows slow system clocks.

Serial clock with programmable polarity.

Programmable baud rate generator to generate QSPI clocks.

Features included to improve high speed read data capture mechanism.

Option to use adapted clocks to further improve read data capturing.

Programmable interrupt generation.

Up to four external chip selects.

Supports Little-endian operation only.

For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the

Device TRM.

6.10.16 SPI

The SPI module is a master/slave high-speed synchronous serial input/output interface that allows a serial

bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-

transfer rate. There are four separate SPI modules (SPI0, SPI1, SPI2, and SPI3) in the device. All these

four modules support up to two external devices (two chip selects) and are able to work as both master

and slave. The SPI module allows multiple programmable chip-selects. It is normally used for

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communication between the device and external peripherals. Typical applications include interface to

external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMS,

and analog-to-digital converters. The SPI module may be used to connect to serial flash memory devices

for booting. The SPI module supports EDMA events and can be used in conjunction with EDMA for data

transfer with minimal CPU overhead.

The SPI module has the following features:

•

16-bit Shift register

16-bit Receive buffer register and 16-bit Receive buffer emulation alias register

16-bit Transmit data register and 16-bit Transmit data and format selection register

8-bit Baud clock generator

Serial clock (SPIm_CLK) I/O pin

Slave in, master out (SPIm_SIMO) I/O pin

Slave out, master in (SPIm_SOMI) I/O pin

2 Chip select signals (SPIm_SCSn0 and SPIm_SCSn1)

Programmable SPI clock frequency range

Programmable character length (2 to 16 bits)

Programmable clock phase (delay or no delay)

Programmable clock polarity (high or low)

Interrupt capability

DMA support (read/write synchronization events)

Operates at up to 50 MHz in master mode and 25 MHz in slave mode (actual speed depends on SPI

functional clock and SPI clock divider)

The SPI module allows software to program the following options:

•

SPIm_CLK frequency (SPI functional clock / 2 through SPI functional clock / 256)

3-pin and 4-pin options

Character length (2 to 16 bits) and shift out direction (MSB/LSB first)

Clock phase (delay or no delay) and polarity (high or low)

Delay between transmissions in master mode

Chip select setup and hold times in master mode

Chip select hold in master mode

The SPI module does not support the following features:

•

Multibuffer mode

Parallel mode and parity

GPIO mode

For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the Device

TRM.

6.10.17 Timers

There are total of 7 chip-level timers.

The device includes several types of timers used by the system software, including general-purpose (GP)

timers, watchdog timers, and a wake-up timer, as it follows:

•

TIMER_0 is dedicated/tightly coupled for C66x CorePac. TIMER_0 can be used as general-purpose

timer or watchdog timer

•

TIMER_1 through TIMER_4 are general-purpose timers

TIMER_5 is dedicated/tightly coupled for the Arm core 0. TIMER_5 can be used as general-purpose

timer or watchdog timer

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•

TIMER_6 is dedicated as device wake-up timer by interrupting PMMC CPU. TIMER_6 cannot be used

by high-level software as a general-purpose timer or watchdog. TIMER_6 is neither connected to Timer

pin manager block nor to Timer IOs.

–

On-the-fly read/write register (while counting)

Each timer has two input pins (TINPL and TINPH) and two output pins (TOUTL and TOUTH).

At the chip level there are 4 timer pins — two input pins (TIMI[1:0]) and two output pins (TIMO[1:0]). Each

of TIMER_0 through TIMER_5 input can be configured to be driven by the timer input pins. Each of

TIMO[1:0] output pin can be driven by any of the timer outputs. The selection of timer inputs and outputs

is controlled by Timer pin manager. The Timer pin manager block is controlled by registers in BOOT_CFG

module.

For more information, see section Timers in chapter Peripherals of the Device TRM.

6.10.18 UART

The Universal Asynchronous Receiver/Transmitter peripheral is 16550 standard compatible asynchronous

communications element. The UART can be placed in an alternate FIFO mode. This relieves the CPU of

excessive software overhead by buffering received and transmitted characters. The receiver and

transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the

receiver FIFO.

There are 3 UART (UART_0, UART_1 and UART_2) modules in the device. Only UART_0 supports full

modem control functions. Each UART can be used for configuration and data exchange with a number of

external peripheral devices or interprocessor communication between devices.

The UART_i (where i = 0 to 2) include the following features:

•

16550 standard compatible

16-byte FIFO buffer for receiver and 16-byte FIFO for transmitter

Baud generation based on programmable divisors operating from a fixed functional clock of 192 MHz

Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two

options:

–

Baud rate = (functional clock / 16) / N

Baud rate = (functional clock / 13) / N

•

Break character detection and generation

Configurable data format:

–

Data bit: 5, 6, 7, or 8 bits

Parity bit: Even, odd, none

Stop-bit: 1, 1.5, 2 bit(s)

•

Flow control: Hardware (RTS/CTS)

The 192 MHz functional clock option allows baud rates up to 12Mbps

The UART performs serial-to-parallel conversions on data received from a peripheral device or modem

and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at

any time. The UART includes control capability and a processor interrupt system that can be tailored to

minimize software management of the communications link.

For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter

Peripherals of the Device TRM.

6.10.19 USB

Similar to earlier versions of USB bus, USB 2.0 is a general-purpose cable bus, supporting data exchange

between a host device and a wide range of simultaneously accessible peripherals.

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The device supports two USB 2.0 subsystems with High Speed Dual-Role-Device (DRD) ports with

integrated PHY.

The USB 2.0 subsystem, supports the following USB features:

•

Dual-role-device (DRD) capability:

–

Supports USB 2.0 Peripheral (or Device) mode at Highspeed (480 Mbps) and Fullspeed (12 Mbps)

Supports USB 2.0 Host mode at Highspeed (480 Mbps), Fullspeed (12 Mbps), and Lowspeed (1.5

Mbps)

–

USB 2.0 static peripheral operation

USB 2.0 static host operation

xHCI Debug Capability

External Buffer Control (EBC) mode for IN (Tx) Endpoint

•

Each controller instance contains single xHCI with the following features:

–

Compatible to the xHCI Specification (Revision 1.1) in Host mode

Supports 15 Transmit (TX), 15 Receive (RX) endpoints (EPs), and one EP0 endpoint which is

bidirectional

–

Internal DMA controller

Interrupt moderation and blocking

Supports for all USB transfer modes - Control, Bulk, Interrupt, and Isochronous

Supports high bandwidth ISO mode

Descriptor caching and data pre-fetching used to improve system performance

Dynamic FIFO memory allocation for all endpoints

•

Operation flexibility:

–

Uniform programming model for HS, FS, and LS operation

Multiple interrupt lines:

•

16 interrupts associated with 16 programmable Event Rings for multi-core support

A MISC interrupt line for all miscellaneous events

•

ECC RAM

External requirements:

–

An external charge pump for VBUS 5 V generation

An external reference clock input for USB PHY operation

An external high-precision resistor for internal PHY termination calibration

The following are USB features which are not supported:

•

USB 3.0 SuperSpeed (5 Gbps) or USB3.1 SuperSpeed+ (10 Gbps) operation in either host or device

modes

•

OTG Functionality

HSIC (High Speed inter-chip)

ULPI Interface for external PHY

Battery Charger Support

Accessory Charger Adaptor Support

xHCI Virtualization

Hibernation (separate power domain for wake up from USB and save/ restore on wakeup) mode

External Buffer Control (EBC) for OUT (Rx) Endpoint

For more information, see section Universal Serial Bus Subsystem (USB) in chapter Peripherals of the

Device TRM.

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7 Applications, Implementation, and Layout

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test design implementation to confirm system functionality.

7.1 DDR3L Board Design and Layout Guidelines

7.1.1 DDR3L General Board Layout Guidelines

To help ensure good signaling performance, consider the following board design guidelines:

•

Avoid crossing splits in the power plane.

Minimize Vref noise.

Use the widest trace that is practical between decoupling capacitors and memory module.

Maintain a single reference.

Minimize ISI by keeping impedances matched.

Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.

Use proper low-pass filtering on the Vref pins.

Keep the stub length as short as possible.

Add additional spacing for on-clock and strobe nets to eliminate crosstalk.

Maintain a common ground reference for all bypass and decoupling capacitors.

Take into account the differences in propagation delays between microstrip and stripline nets when

evaluating timing constraints.

7.1.2 DDR3L Board Design and Layout Guidelines

7.1.2.1 Board Designs

TI only supports board designs using DDR3L memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the DDR3L memory controller are shown in 表 7-1 and 图

7-1.

表 7-1. Switching Characteristics Over Recommended Operating Conditions for DDR3L Memory

Controller

NO.

PARAMETER

MIN

2.5

MAX

3.3⁽¹⁾

UNIT

Device Speed 60

Device Speed 100

t_{c(DDR3_CLKOUT_P/N)}

Cycle time, DDR3_CLKOUT_P/N

1.876

(1) This is the absolute maximum value of the clock period. Actual maximum clock period may be limited by DDR3L speed grade and

operating frequency (see the DDR3L memory device data sheet).

DDR3_CLKOUT_P/N

图 7-1. DDR3L Memory Controller Clock Timing

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7.1.2.2 DDR3L Device Combinations

Because there are several possible combinations of device counts and single- or dual-side mounting, 表

7-2 summarizes the supported device configurations.

表 7-2. Supported DDR3L Device Combinations

NUMBER OF DDR3L DEVICES DDR3L DEVICE WIDTH (BITS)

MIRRORED?

DDR EMIF WIDTH (BITS)

Y⁽¹⁾

Y⁽²⁾

(1) Two DDR3L devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(2) This is two mirrored pairs of DDR3L devices.

7.1.2.3 DDR3L Interface Schematic

7.1.2.3.1 32-Bit DDR3L Interface

The DDR EMIF schematic varies, depending upon the width of the DDR3L devices used and the width of

the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR devices

look like two 8-bit devices. 图 7-2 and 图 7-3 show the schematic connections for 32-bit interfaces using

×16 devices.

7.1.2.3.2 16-Bit DDR3L Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see 图 7-2 and

图 7-3); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

When not using all or part of the DDR EMIF, the proper method of handling the unused pins is to tie off

the DDR3_DQS*_Pi pins to ground via a 1k-Ω resistor and to tie off the DDR3_DQS*_Ni pins to the

corresponding DVDD_DDR supply via a 1k-Ω resistor. This needs to be done for each byte not used.

Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide

additional protection against external electrical noise causing activity on the signals.

The DVDD_DDR, DVDD_DDRDLL, and DDR3_VREFSSTL power supply pins need to be connected to

their respective power supplies even if the DDR EMIF is not being used. All other DDR EMIF pins can be

left unconnected.

Note: The only DDR EMIF configurations supported are 32-bits wide, 16-bits wide, or not used.

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32-bit DDR EMIF

16-Bit DDR3L

Devices

DDR3_D31

DDR3_D24

DQ15

DQ8

DDR3_DQM3

DDR3_DQS3_P

DDR3_DQS3_N

UDM

UDQS

DDR3_D23

DQ7

DDR3_D16

DQ0

DDR3_DQM2

DDR3_DQS2_P

DDR3_DQS2_N

LDM

LDQS

DDR3_D15

DQ15

DQ8

DDR3_D8

DDR3_DQM1

DDR3_DQS1_P

DDR3_DQS1_N

UDM

UDQS

DDR3_D7

DQ7

DDR3_D00

DQ0

DDR3_DQM0

DDR3_DQS0_P

DDR3_DQS0_N

LDM

LDQS

0.1 µF

DDR3_CLKOUT_P

DDR3_CLKOUT_N

DVDD_DDR

DDR3_ODT0

DDR3_CEn0

DDR3_BA0

DDR3_BA1

DDR3_BA2

ODT

BA0

BA1

BA2

BA0

BA1

BA2

DDR_VTT

DDR3_A00

DDR3_A15

A15

DDR3_CASn

DDR3_RASn

CAS

RAS

DDR3_WEn

DDR3_CKE0/1

DDR3_RESETn

CKE

RST

DDR_VREF

RST

VREFDQ

VREFCA

VREFDQ

VREFCA

DDR3_VREFSSTL

0.1 µF

Termination is required. See terminator comments.

Value determined according to the DDR memory device data sheet.

图 7-2. 32-Bit, One-Bank DDR EMIF Interface Schematic Using Two 16-Bit DDR3L Devices

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32-bit DDR EMIF

8-Bit DDR3L

Devices

8-Bit DDR3L

Devices

DDR3_D31

DQ7

DDR3_D24

DQ0

DDR3_DQM3

DM/TQS

TDQS

DQS

DDR3_DQS3_P

DDR3_DQS3_N

DQS

DDR3_D23

DQ7

DQ0

DDR3_D16

DDR3_DQM2

DM/TQS

TDQS

DQS

DDR3_DQS2_P

DDR3_DQS2_N

DQS

DDR3_D15

DQ7

DQ0

DDR3_D8

DDR3_DQM1

DM/TQS

TDQS

DQS

DDR3_DQS1_P

DDR3_DQS1_N

DQS

DDR3_D7

DQ7

DQ0

DDR3_D00

DDR3_DQM0

DM/TQS

TDQS

DQS

DDR3_DQS0_P

DDR3_DQS0_N

DQS

0.1 µF

DDR3_CLKOUT_P*

DDR3_CLKOUT_N*

DVDD_DDR

DDR3_ODT0

DDR3_CEn0

DDR3_BA0

DDR3_BA1

DDR3_BA2

ODT

BA0

BA1

BA2

BA0

BA1

BA2

BA0

BA1

BA2

BA0

BA1

BA2

DDR_VTT

DDR3_A00

DDR3_A15

A15

DDR3_CASn

DDR3_RASn

CAS

RAS

CAS

RAS

DDR3_WEn

DDR3_CKE0/1

DDR3_RESETn

CKE

RST

CKE

RST

DDR_VREF

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFDQ

VREFCA

DDR3_VREFSSTL

0.1 µF

Termination is required. See terminator comments.

Value determined according to the DDR memory device data sheet.

图 7-3. 32-Bit, One-Bank DDR EMIF Interface Schematic Using Four 8-Bit DDR3L Devices

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7.1.2.4 Compatible JEDEC DDR3L Devices

表 7-3 shows the parameters of the JEDEC DDR3L devices that are compatible with this interface.

表 7-3. Compatible JEDEC DDR3L Devices

NO.

PARAMETER

CONDITION

MIN

800

1066

MAX

1600

x16

UNIT

MT/s

JEDEC DDR3L device speed

grade⁽¹⁾

DDR clock rate ≤ 400 MHz

400 MHz < DDR clock rate ≤ 533 MHz

MT/s

JEDEC DDR3L device bit width

JEDEC DDR3L device count⁽²⁾

Bits

Devices

(1) Refer to 表 7-1 Switching Characteristics Over Recommended Operating Conditions for DDR3L Memory Controller for the range of

supported DDR clock rates.

(2) For valid DDR3L device configurations and device counts, see 节 7.1.2.2, 图 7-2, and 图 7-3.

7.1.2.5 PCB Stackup

The minimum stackup for routing the DDR EMIF interface is a six-layer stack up as shown in 表 7-4.

Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI

performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in

表 7-5.

表 7-4. Six-Layer PCB Stackup Suggestion

LAYER

TYPE

Signal

Plane

Signal

DESCRIPTION

Top routing mostly vertical

Ground

Split power plane

Split power plane or Internal routing

Ground

Bottom routing mostly horizontal

表 7-5. PCB Stackup Specifications

NO.

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing/plane layers

Signal routing layers

Full ground reference layers under DDR3L routing region⁽¹⁾

Full 1.5-V power reference layers under the DDR3L routing region⁽¹⁾

Number of reference plane cuts allowed within DDR3L routing region⁽²⁾

Number of layers between DDR3L routing layer and reference plane⁽³⁾

PCB routing feature size

Mils

Ω

PCB trace width, w

Single-ended impedance, Zo

Impedance control⁽⁵⁾

Z - 5

Z + 5

Ω

(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(2) No traces should cross reference plane cuts within the DDR3L routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.

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7.1.2.6 Placement

图 7-4 shows the required placement for the processor as well as the DDR3L devices. The dimensions for

this figure are defined in 表 7-6. The placement does not restrict the side of the PCB on which the devices

are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for

proper routing space. For a 16-bit DDR memory system, the high-word DDR3L devices are omitted from

the placement.

DDR3

Controller

PCB_DDR3_3

图 7-4. Placement Specifications

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表 7-6. Placement Specifications DDR3L

NO.

PARAMETER

MIN

MAX

500

UNIT

Mils

KOD31

KOD32

KOD33

KOD34

KOD35

KOD36

KOD37

600

1800

600

DDR3L keepout region⁽¹⁾

Clearance from non-DDR3L signal traces to DDR3L signal traces

(2)

(1) DDR3L keepout region to encompass entire DDR3L routing area.

(2) Non-DDR3L signals allowed within DDR3L keepout region provided they are separated from DDR3L routing layers by a ground plane.

7.1.2.7 DDR3L Keepout Region

The region of the PCB used for DDR3L circuitry must be isolated from other signals. The DDR3L keepout

region is defined for this purpose and is shown in 图 7-5. The size of this region varies with the placement

and DDR3L routing. Additional clearances required for the keepout region are shown in 表 7-6. Non-

DDR3L signals should not be routed on the DDR3L signal layers within the DDR3L keepout region. Non-

DDR3L signals may be routed in the region, provided they are routed on layers separated from the

DDR3L signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this

region. In addition, the DVDD_DDR power plane should cover the entire keepout region. Also note that

the two signals from the DDR3L controller should be separated from each other by the specification in 表

7-6 (see KOD37).

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DDR3L Keepout Region

DDR3

Controller

PCB_DDR3_3

图 7-5. DDR3L Keepout Region

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7.1.2.8 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3L and other circuitry. 表 7-

7 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this

table only covers the bypass needs of the DDR EMIF controller and DDR3L devices. Additional bulk

bypass capacitance may be needed for other circuitry.

表 7-7. Bulk Bypass Capacitors

NO.

PARAMETER

DVDD_DDR bulk bypass capacitor count⁽¹⁾

DVDD_DDR bulk bypass total capacitance

MIN

MAX

UNIT

Devices

μF

(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-

speed (HS) bypass capacitors and DDR3L signal routing.

7.1.2.9 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critcal for proper DDR3L interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,

and processor/DDR ground connections. 表 7-8 contains the specification for the HS bypass capacitors as

well as for the power connections on the PCB. Generally speaking, it is good to:

1. Fit as many HS bypass capacitors as possible.

2. Minimize the distance from the bypass cap to the pins/balls being bypassed.

3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.

4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest

hole size via possible.

5. Minimize via sharing. Note the limites on via sharing shown in 表 7-8.

表 7-8. High-Speed Bypass Capacitors

NO.

PARAMETER

HS bypass capacitor package size⁽¹⁾

MIN

TYP

MAX

0402

400

UNIT

10 Mils

Mils

0201

Distance, HS bypass capacitor to processor being bypassed^(2)(3)(4)

Processor HS bypass capacitor count per DVDD_DDR rail⁽¹²⁾

Processor HS bypass capacitor total capacitance per DVDD_DDR rail⁽¹²⁾

Number of connection vias for each device power/ground ball⁽⁵⁾

Trace length from device power/ground ball to connection via⁽²⁾

Distance, HS bypass capacitor to DDR3L device being bypassed⁽⁶⁾

DDR3L device HS bypass capacitor count⁽⁷⁾

See 节 7.3 and⁽¹¹⁾

Devices

μF

Vias

Mils

150

Mils

0.85

Devices

μF

DDR3L device HS bypass capacitor total capacitance⁽⁷⁾

10 Number of connection vias for each HS capacitor⁽⁸⁾⁽⁹⁾

11 Trace length from bypass capacitor connect to connection via⁽²⁾⁽⁹⁾

12 Number of connection vias for each DDR3L device power/ground ball⁽¹⁰⁾

13 Trace length from DDR3L device power/ground ball to connection via⁽²⁾⁽⁸⁾

(1) LxW, 10-mil units, that is, a 0402 is a 40×20-mil surface-mount capacitor.

(2) Closer/shorter is better.

Vias

100

Mils

Vias

Mils

(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.

(4) Three of these capacitors should be located underneath the processor, between the cluster of DVDD_DDR balls and ground balls,

between the DDR3L interfaces on the package.

(5) See the Via Channel™ escape for the processor package.

(6) Measured from the DDR3L device power/ground ball to the center of the capacitor package.

(7) Per DDR3L device.

(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of

vias is permitted on the same side of the board.

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(9) An HS bypass capacitor may share a via with a DDR3L device mounted on the same side of the PCB. A wide trace should be used for

the connection and the length from the capacitor pad to the DDR3L device pad should be less than 150 mils.

(10) Up to a total of two pairs of DDR power/ground balls may share a via.

(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s

guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.

(12) For more information, see 节 7.3, Power Distribution Network Implementation Guidance.

7.1.2.9.1 Return Current Bypass Capacitors

Use additional bypass capacitors if the return current reference plane changes due to DDR3L signals

hopping from one signal layer to another. The bypass capacitor here provides a path for the return current

to hop planes along with the signal. As many of these return current bypass capacitors should be used as

possible. Because these are returns for signal current, the signal via size may be used for these

capacitors.

7.1.2.10 Net Classes

表 7-9 lists the clock net classes for the DDR EMIF. 表 7-10 lists the signal net classes, and associated

clock net classes, for signals in the DDR EMIF. These net classes are used for the termination and routing

rules that follow.

表 7-9. Clock Net Class Definitions

CLOCK NET CLASS PROCESSOR PIN NAMES

DDR3_CLKOUT_N* / DDR3_CLKOUT_P*

DDR3_DQS0_P / ddrx_dqsn0

DQS0

DQS1

DDR3_DQS0_P / DDR3_DQS0_N

DDR3_DQS1_P / DDR3_DQS1_N

DDR3_DQS2_P / DDR3_DQS2_N

DQS2⁽¹⁾

DQS3⁽¹⁾

(1) Only used on 32-bit wide DDR3L memory systems.

表 7-10. Signal Net Class Definitions

ASSOCIATED CLOCK

SIGNAL NET CLASS

PROCESSOR PIN NAMES

NET CLASS

ADDR_CTRL

DDR3_BA[2:0], DDR3_A[14:0], DDR3_CEn0, DDR3_CASn, DDR3_RASn,

DDR3_WEn, DDR3_CKE0, DDR3_ODT0

DQ0

DQ1

DQ2⁽¹⁾

DQ3⁽¹⁾

DQS0

DQS1

DQS2

DQS3

DDR3_D[7:0], DDR3_DQM0

DDR3_D[15:8], DDR3_DQM1

DDR3_D[23:16], DDR3_DQM2

DDR3_D[31:24], DDR3_DQM3

(1) Only used on 32-bit wide DDR3L memory systems.

7.1.2.11 DDR3L Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

7.1.2.12 VREF_DDR Routing

DDR3_VREFSSTL (VREF) is used as a reference by the input buffers of the DDR3L memories as well as

the processor. VREF is intended to be half the DDR3L power supply voltage and is typically generated

with the DVDD_DDR and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1

µF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate

routing congestion.

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7.1.2.13 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3L supply voltage. Unlike VREF, VTT is

expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power

sub-plane. VTT should be bypassed near the terminator resistors.

7.1.2.14 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew

between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.

The following subsections show the topology and routing for various DDR3L configurations for CK and

ADDR_CTRL. The figures in the following subsections define the terms for the routing specification

detailed in 表 7-11.

7.1.2.14.1 Four DDR3L Devices

Four DDR3L devices are supported on the DDR EMIF consisting of four x8 DDR3L devices arranged as

one bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in

two pairs to save board space at a cost of increased routing complexity and parts on the backside of the

PCB.

7.1.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3L Devices

图 7-6 shows the topology of the CK net classes and 图 7-7 shows the topology for the corresponding

ADDR_CTRL net classes.

DDR Differential CK Input Buffers

–

Clock Parallel

Terminator

DVDD_DDR

Rcp

Cac

Processor

Differential Clock

Output Buffer

–

0.1 µF

Rcp

Routed as Differential Pair

图 7-6. CK Topology for Four x8 DDR3L Devices

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DDR Address and Control Input Buffers

Address and Control

Terminator

Rtt

Processor

Address and Control

Output Buffer

VTT

图 7-7. ADDR_CTRL Topology for Four x8 DDR3L Devices

7.1.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3L Devices

图 7-8 shows the CK routing for four DDR3L devices placed on the same side of the PCB. 图 7-9 shows

the corresponding ADDR_CTRL routing.

DVDD_DDR

Cac

Rcp

0.1 µF

图 7-8. CK Routing for Four Single-Side DDR3L Devices

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Rtt

VTT

图 7-9. ADDR_CTRL Routing for Four Single-Side DDR3L Devices

To save PCB space, the four DDR3L memories may be mounted as two mirrored pairs at a cost of

increased routing and assembly complexity. 图 7-10 and 图 7-11 show the routing for CK and

ADDR_CTRL, respectively, for four DDR3L devices mirrored in a two-pair configuration.

DVDD_DDR

Cac

Rcp

0.1 µF

图 7-10. CK Routing for Four Mirrored DDR3L Devices

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Rtt

VTT

图 7-11. ADDR_CTRL Routing for Four Mirrored DDR3L Devices

7.1.2.14.2 One DDR3L Device

A single DDR3L device is supported on the DDR EMIF consisting of one x16 DDR3L device arranged as

one bank (CS), 16 bits wide.

7.1.2.14.2.1 CK and ADDR_CTRL Topologies, One DDR3L Device

图 7-12 shows the topology of the CK net classes and 图 7-13 shows the topology for the corresponding

ADDR_CTRL net classes.

DDR Differential CK Input Buffer

–

Clock Parallel

Terminator

DVDD_DDR

Rcp

Cac

Processor

Differential Clock

Output Buffer

–

0.1 µF

Rcp

Routed as Differential Pair

图 7-12. CK Topology for One DDR3L Device

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DDR Address and Control Input Buffers

Address and Control

Terminator

Rtt

Processor

Address and Control

Output Buffer

VTT

图 7-13. ADDR_CTRL Topology for One DDR3L Device

7.1.2.14.2.2 CK and ADDR/CTRL Routing, One DDR3L Device

图 7-14 shows the CK routing for one DDR3L device placed on the same side of the PCB. 图 7-15 shows

the corresponding ADDR_CTRL routing.

DVDD_DDR

Cac

Rcp

0.1 µF

图 7-14. CK Routing for One DDR3L Device

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Rtt

VTT

图 7-15. ADDR_CTRL Routing for One DDR3L Device

7.1.2.15 Data Topologies and Routing Definition

No matter the number of DDR3L devices used, the data line topology is always point to point, so its

definition is simple.

Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is

better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure

there are nearby ground vias to allow the return currents to transition between reference planes if both

reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the

return currents to transition between reference planes if one of the reference planes is ground. The goal is

to minimize the size of the return current loops.

7.1.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. 图 7-16 and 图

7-17 show these topologies.

Processor

DQS

DDR

DQSn+

DQSn-

DQS

IO Buffer

Routed Differentially

n = 0, 1, 2, 3

图 7-16. DQS Topology

Processor

DQ and DM

IO Buffer

DDR

DQ and DM

IO Buffer

n = 0, 1, 2, 3

图 7-17. DQ/DM Topology

7.1.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices

图 7-18 and 图 7-19 show the DQS and DQ/DM routing.

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DQS

DQSn+

DQSn-

Routed Differentially

n = 0, 1, 2, 3

图 7-18. DQS Routing With Any Number of Allowed DDR3L Devices

DQ and DM

n = 0, 1, 2, 3

图 7-19. DQ/DM Routing With Any Number of Allowed DDR3L Devices

7.1.2.16 Routing Specification

7.1.2.16.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3L memories, the maximum

possible Manhattan distance can be determined given the placement. 图 7-20 and 图 7-21 show this

distance for four loads and two loads, respectively. It is from this distance that the specifications on the

lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for

other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class.

For CK and ADDR_CTRL routing, these specifications are contained in 表 7-11.

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A8^(A)

Rtt

VTT

图 7-20. Four Address Loads on One Side of PCB

A8^(A)

Rtt

VTT

图 7-21. Two Address Loads on One Side of PCB

表 7-11. CK and ADDR_CTRL Routing Specification⁽²⁾⁽³⁾

NO.

PARAMETER

MIN

TYP

MAX

UNIT

CARS31

CARS32

CARS33

CARS34

CARS35

CARS36

CARS37

CARS38

CARS39

A1+A2 length

A1+A2 skew

A3 length

A3 skew⁽⁴⁾

A3 skew⁽⁵⁾

A4 length

A4 skew

500⁽¹⁾

125

AS length

AS skew

5⁽¹⁾

1.3⁽¹⁾

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表 7-11. CK and ADDR_CTRL Routing Specification⁽²⁾⁽³⁾(continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

CARS310

CARS311

CARS312

CARS313

CARS314

CARS315

CARS316

CARS317

CARS318

CARS319

CARS320

AS+/AS- length

AS+/AS- skew

AT length⁽⁶⁾

AT skew⁽⁷⁾

AT skew⁽⁸⁾

1020

3⁽¹⁾

CK/ADDR_CTRL trace length

Vias per trace

vias

Via count difference

1⁽¹⁵⁾

Center-to-center CK to other DDR3L trace spacing⁽⁹⁾

Center-to-center ADDR_CTRL to other DDR3L trace spacing^(9)(10)

Center-to-center ADDR_CTRL to other ADDR_CTRL trace

spacing⁽⁹⁾

CARS321

CARS322

CARS323

CARS324

CK center-to-center spacing^(11)(12)

CK spacing to other net⁽⁹⁾

Rcp⁽¹³⁾

Zo-1

Zo-5

Zo+1

Zo+5

Rtt^(13)(14)

(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of

rise time and fall time confirms desired operation.

(2) The use of vias should be minimized.

(3) Additional bypass capacitors are required when using the DVDD_DDR plane as the reference plane to allow the return current to jump

between the DVDD_DDR plane and the ground plane when the net class switches layers at a via.

(4) Non-mirrored configuration (all DDR3L memories on same side of PCB).

(5) Mirrored configuration (one DDR3L device on top of the board and one DDR3L device on the bottom).

(6) While this length can be increased for convenience, its length should be minimized.

(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(8) CK net class only.

(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3L trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended

impedance, Zo.

(13) Source termination (series resistor at driver) is specifically not allowed.

(14) Termination values should be uniform across the net class.

(15) Via count difference may increase by 1 only if accurate 3D modeling of the signal flight times – including accurately modeled signal

propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.

7.1.2.16.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four

DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

Given the DQS and DQ/DM pin locations on the processor and the DDR3L memories, the maximum

possible Manhattan distance can be determined given the placement. 图 7-22 shows this distance for four

loads. It is from this distance that the specifications on the lengths of the transmission lines for the data

bus are determined. For DQS and DQ/DM routing, these specifications are contained in 表 7-12.

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DQ[0:7]/DM0/DQS0

DQ[8:15]/DM1/DQS1

DB0

DB1

DQ[16:23]/DM2/DQS2

DB2

DQ[24:31]/DM3/DQS3

DB3

DB0 - DB3 represent data bytes 0 - 3.

图 7-22. Any Number of Allowed DDR3L Devices

表 7-12. Data Routing Specification^(2)(11)

NO.

PARAMETER

MIN

TYP

MAX

340

UNIT

DRS31

DRS32

DRS33

DRS34

DRS35

DRS36

DRS37

DRS38

DRS39

DRS310

DRS311

DRS312

DRS313

DB0 length

DB1 length

DB2 length

DB3 length

DBn skew⁽³⁾

DQSn+ to DQSn- skew

DQSn to DBn skew⁽³⁾⁽⁴⁾

Vias per trace

Via count difference

5⁽¹⁰⁾

2⁽¹⁾

0⁽¹⁰⁾

vias

w⁽⁵⁾

Center-to-center DBn to other DDR3L trace spacing⁽⁶⁾

Center-to-center DBn to other DBn trace spacing⁽⁷⁾

DQSn center-to-center spacing⁽⁸⁾⁽⁹⁾

DQSn center-to-center spacing to other net

w⁽⁵⁾

(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of

rise time and fall time confirms desired operation.

(2) External termination disallowed. Data termination should use built-in ODT functionality.

(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.

(4) Each DQS pair is length matched to its associated byte.

(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.

(6) Other DDR3L trace spacing means other DDR3L net classes not within the byte.

(7) This applies to spacing within the net classes of a byte.

(8) DQS pair spacing is set to ensure proper differential impedance.

(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended

impedance, Zo.

(10) Via count difference may increase by 1 only if accurate 3D modeling of the signal flight times – including accurately modeled signal

propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.

(11) It is not required to match lengths across all bytes. Length matching is only required within the data bits of a given byte.

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7.2 High Speed Differential Signal Routing Guidance

The High-Speed Interface Layout Guidelines Application Report (SPRAAR7) available from

http://www.ti.com/lit/pdf/spraar7 provides guidance for successful routing of the high speed differential

signals. This includes PCB stackup and materials guidance as well as routing skew, length and spacing

limits. TI supports only designs that follow the board design guidelines contained in the application report.

7.3 Power Distribution Network (PDN) Implementation Guidance

66AK2G1x: EVMK2GX General Purpose EVM Power Distribution Network Analysis [literature number

SPRACE6] provides guidance for successful implementation of the PDN. This includes PCB stack-up

guidance as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI

supports only designs that follow the board design guidelines contained in the application report.

7.3.1 Decoupling/Filtering of Analog Power Supplies and Reference Inputs

7.3.1.1 PLL Power Supplies

The analog VDD pins with a prefix of AVDDA_ provide power to internal PLLs. Each of these analog VDD

pins shall be connected to DVDD18 through a dedicated low-pass filter. Each filter shall reduce power

supply noise of the respective analog VDD pin such that it has less than 250-mV peak-to-peak noise while

remaining within the voltage ranged defined in Section 5.4, Recommended Operating Conditions.

7.3.1.2 DDR EMIF PHY DLL Power Supplies

The DVDD_DDRDLL pins provide power to DDR EMIF PHY DLLs. These supply pins must be filtered

such that they have less than 36-mV peak-to-peak noise while remaining within the voltage ranged

defined in Section 5.4, Recommended Operating Conditions.

The recommended circuit topology for this filter is shown in 图 7-23.

DVDD18

Device

DVDD_DDRDLL

Ferrite Bead

100 MHz

75-100 Ω

10 µF

1.0 µF

0.1 µF

W10

Ferrite Bead

DVDD_DDRDLL

100 MHz

75-100 Ω

10 µF

1.0 µF

0.1 µF

W14

Ferrite Bead

100 MHz

75-100 Ω

10 µF

1.0 µF

0.1 µF

SPRSP07_DVDD_DDRDLL_01

图 7-23. Recommended DVDD_DDRDLL Filter Circuit

7.3.1.3 DDR EMIF PHY Voltage Reference Input

DDR3_VREFSSTL is a mid-supply voltage reference input which the DDR EMIF PHY uses as the

switching threshold for its input buffers. This pin must be filtered such that it has less than 13.5-mV peak-

to-peak noise while remaining within the voltage ranged defined in Section 5.4, Recommended Operating

Conditions.

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7.3.1.4 Internal LDO Outputs

There are two internal LDOs that require external decoupling capacitors.

The LDO_PCIE_CAP pins are connected to the output of an internal LDO that sources the PCIe PHY core

power rail. A single 1.0 µF, ±50% decoupling capacitor with ESR of 10–100 mΩ must be connected

between the LDO_PCIE_CAP pins and VSS with less than 0.5 nH of loop inductance.

The LDO_USB_CAP pins are connected to the output of an internal LDO that sources both USB PHY

core power rails. A single 1.0 µF, ±50% decoupling capacitor with ESR of 10–100 mΩ must be connected

between the LDO_USB_CAP pins and VSS with less than 0.5 nH of loop inductance.

7.3.1.5 PCIe PHY Power Supply

The VDDAHV pin provides power to the PCIe PHY. This supply pin must be filtered such that it has less

than 50-mV peak-to-peak noise while remaining within the voltage ranged defined in Section 5.4,

Recommended Operating Conditions.

7.3.1.6 USB PHY Power Supplies

The DVDD33_USB pins provide power to the USB PHYs. These supply pins must be filtered such that

they have less than 198-mV peak-to-peak noise while remaining within the voltage ranged defined in

Section 5.4, Recommended Operating Conditions.

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7.4 Single-Ended Interfaces

7.4.1 General Routing Guidelines

The following paragraphs detail the routing guidelines that must be observed when routing the various

functional LVCMOS interfaces.

•

Line spacing:

For a line width equal to W, the spacing between two lines must be 2 W, at least. This minimizes

–

the crosstalk between switching signals between the different lines. On the PCB, this is not

achievable everywhere (for example, when breaking signals out from the device package), but it is

recommended to follow this rule as much as possible. When violating this guideline, minimize the

length of the traces running parallel to each other (see 图 7-24).

D+

S = 2 W = 200 µm

SWPS040-185

图 7-24. Ground Guard Illustration

•

Length matching (unless otherwise specified):

–

For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length

difference between the longest and the shortest lines) must be less than 25 mm.

–

For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length

difference between the longest and the shortest lines) must be less than 2.5 mm.

•

Characteristic impedance

–

Unless otherwise specified, the characteristic impedance for single-ended interfaces is

recommended to be between 35-Ω and 65-Ω.

Multiple peripheral support

–

For interfaces where multiple peripherals have to be supported in the star topology, the length of

each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify

signal integrity based on simulations including actual PCB extraction.

7.5 Clock Routing Guidelines

7.5.1 Oscillator Routing

When designing the printed-circuit board:

•

Place the crystal circuit on the same side of the PCB as the 66AK2G1x device and as close as

possible to the respective device pins SYSOSC_IN

AUDOSC_OUT.

/ SYSOSC_OUT, or AUDOSC_IN /

The crystal circuit traces should be placed on the outer layer of the PCB when possible, with the

lengths being as short as possible to reduce parasitic capacitance and minimize crosstalk from other

signals.

•

Do not route any other signals under the crystal circuit traces if there is an adjacent signal layer on the

PCB.

Route all crystal circuit component ground connections to one common ground via. This via must

directly connect to the ground plane.

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•

Treat VSS_OSC_AUDIO and VSS_OSC_SYS pins the same way as other device VSS pins: connect

them to board ground as near to the ball as possible.

Device

SYSOSC_IN /

AUDOSC_IN

SYSOSC_OUT /

AUDOSC_OUT

Via to GND

SWPS040-196

图 7-25. SYSOSC and AUDIOOSC PCB requirements

7.5.2 Oscillator Ground Connection

Device

VSS_OSC_SYS /

VSS_OSC_AUDIO

SYSOSC_IN /

AUDOSC_IN

SYSOSC_OUT /

AUDOSC_OUT

Crystal

(Optional)

C_f2

C_f1

SPRS85v_PCB_CLK_OSC_2

图 7-26. Grounding Scheme for internal oscillators

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the

device, generate code, and develop solutions are listed below.

8.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)

(for example, 66AK2G12). Texas Instruments recommends two of three possible prefix designators for its

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development

from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

Experimental device that is not necessarily representative of the final device's electrical

specifications and may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications.

null

Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, ABY), the temperature range (for example, blank is the default commercial

temperature range), and the device speed range, in megahertz (for example, 60 is 600 MHz). 图 8-1

provides a legend for reading the complete device name for any 66AK2G1x device.

For orderable part numbers of 66AK2G1x devices in the ABY package type, see the Package Option

Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the Device Silicon Errata.

Device and Documentation Support

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BBBBBBbb

PPP

Zzz

SECURITY IDENTIFIER

DEVICE EVOLUTION STAGE

X = Prototype (TMX)

P = Preproduction (TMP - production test flow,

no reliability data)

BLANK = Production (TMS)

Blank = General purpose device (TMS)

D = HS device with TI developmental keys

S = HS device with production keys

IP SUPPORT DESIGNATOR

E = EtherCAT

OTHER = Alternate IP support

BASE PRODUCTION PART NUMBER

66AK2G1x = DSP + Arm KeyStone II G SoC

DEVICE SPEED

60 = 600 MHz

100 = 1 GHz

SILICON REVISION

Blank = Revision 1.0

(see Table 5-1. Supported Max Frequency)

OTHER = Alternate speed grade

TEMPERATURE⁽¹⁾

Blank = Commercial (see Recommended Operating Conditions)

Q = Automotive (see Recommended Operating Conditions)

A = Extended (see Recommended Operating Conditions)

PACKAGE DESIGNATOR

ABY = FCBGA-N625 Package

(see Mechanical Packaging and Orderable Information)

图 8-1. Device Nomenclature

(1) Applies to device max junction temperature.

8.2 Tools and Software

The following products support development for 66AK2G platforms:

Development Tools

66AK2G Clock Tree Tool is an interactive clock tree configuration software that allows the user to

visualize the device clock tree, interact with clock tree elements and view the effect on PRCM registers,

interact with the PRCM registers and view the effect on the device clock tree, and view a trace of all the

device registers affected by the user interaction with the clock tree.

66AK2G Pin Mux Utility is an interactive application that helps a system designer select the appropriate

pin-multiplexing configuration for their device-based product design. The Pin Mux Utility provides a way to

select valid IO Sets of specific peripheral interfaces to ensure the pinmultiplexing configuration selected for

a design only uses valid IO Sets supported by the device.

8.3 Documentation Support

The following documents describe the 66AK2G devices:

Technical Reference Manual

66AK2G1x Multicore DSP+Arm KeyStone II System-on-Chip (SoC) Technical Reference Manual

Details the integration, the environment, the functional description, and the programming

models for each peripheral and subsystem in the 66AK2G family of devices.

Errata

66AK2G1x Silicon Errata

Describes known exceptions to the functional specifications (advisories) with workarounds

and situations where the device's behavior may not match presumed or documented

behavior (usage notes).

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8.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates — including Silicon Errata — go to the product folder for

your device on ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you to

receive a weekly digest of product information that has changed (if any). For change details, check the

revision history of any revised document.

8.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki Established to help developers get started with Embedded Processors

from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

8.7 商标

E2E is a trademark of Texas Instruments.

Neon, CoreSight are trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.

Arm, Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.

EtherCAT is a trademark of Beckhoff Automation GmbH.

QSPI is a trademark of Cadence Design Systems, Inc.

MIPI is a registered trademark of MIPI Alliance, Inc.

MediaLB is a registered trademark of Microchip Technology Inc.

具有集成 PHY 的 PCI Express, PCIe are registered trademarks of PCI-SIG.

PROFIBUS is a registered trademark of PROFIBUS and PROFINET International.

All other trademarks are the property of their respective owners.

8.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Device and Documentation Support

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66AK2G12

ZHCSIL6E –JUNE 2017–REVISED MARCH 2019

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9 Mechanical Packaging and Orderable Information

9.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

226

Mechanical Packaging and Orderable Information

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PACKAGE OPTION ADDENDUM

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19-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

66AK2G12ABY100

66AK2G12ABY60

ACTIVE

FCCSP

ABY

625

RoHS & Green

Call TI

Level-3-260C-168 HR

0 to 90

66AK2G12ABY100

742 ABY

Samples

ACTIVE

ABY

Call TI

0 to 90

66AK2G12ABY60

742 ABY

66AK2G12ABYA100

66AK2G12ABYA100E

66AK2G12ABYA60

66AK2G12ABYA60E

66AK2G12ABYT100

ABY

-40 to 105

-40 to 125

66AK2G12ABYA100

742 ABY

ABY

66AK2G12ABYA100E

742 ABY

ABY

66AK2G12ABYA60

742 ABY

ABY

66AK2G12ABYA60E

742 ABY

ABY

66AK2G12ABYT100

742 ABY

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2022

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

ABY0625A

FCBGA - 1.56 mm max height

SCALE 0.700

BALL GRID ARRAY

21.1

20.9

BALL A1

CORNER

21.1

20.9

(

17)

4X (R1)

(0.4)

1.56 MAX

(0.55)

SEATING PLANE

0.2 C

BALL TYP

0.42

0.32

19.2

TYP

SYMM

(0.9) TYP

SYMM

19.2

TYP

0.57

625X

0.47

0.2

C A B

0.8

TYP

0.08

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

0.8 TYP

4223580/A 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

ABY0625A

FCBGA - 1.56 mm max height

BALL GRID ARRAY

(0.8) TYP

625X ( 0.4)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

(0.8) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 4X

METAL UNDER

SOLDER MASK

0.05 MIN

0.05 MAX

(

0.4)

METAL

(

0.4)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223580/A 04/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SPRU811 (www.ti.com/lit/spru811).

www.ti.com

EXAMPLE STENCIL DESIGN

ABY0625A

FCBGA - 1.56 mm max height

BALL GRID ARRAY

(0.8) TYP

625X ( 0.4)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

(0.8) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE: 4X

4223580/A 04/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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