74ABT16646DGGRG4 [TI]
ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56;
| 型号： | 74ABT16646DGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56 输入元件 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
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SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
SN54ABT16646 . . . WD PACKAGE
SN74ABT16646 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1OE
Latch-Up Performance Exceeds 500 mA Per
JESD 17
2
1CLKBA
1SBA
GND
1B1
3
4
Typical V
(Output Ground Bounce) < 1 V
OLP
5
1A1
1A2
at V
= 5 V, T = 25°C
CC
A
6
1B2
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
7
V
V
CC
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
Flow-Through Architecture Optimizes PCB
Layout
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The
’ABT16646
devices
consist
of
bus-transceiver circuits, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers.
V
V
CC
CC
2A7
2A8
GND
2B7
2B8
GND
2SBA
2CLKBA
2OE
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ’ABT16646 devices.
2SAB
2CLKAB
2DIR
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE
is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the
other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
description (continued)
The SN54ABT16646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
†
DATA I/O
INPUTS
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
B1–B8
↑
X
Input
Unspecified
Input
Store A, B unspecified
Store B, A unspecified
Store A and B data
X
X
↑
X
X
Unspecified
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the
bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
H or L
X
X
H
X
X
X
X
↑
X
X
X
↑
X
L
H
H or L
X
X
X
H
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
†
logic symbol
56
G3
1OE
1
1DIR
3 EN1 [BA]
3 EN2 [AB]
55
54
2
1CLKBA
1SBA
C4
G5
1CLKAB
1SAB
C6
3
G7
29
28
G10
2OE
2DIR
10 EN8 [BA]
10 EN9 [AB]
30
31
27
26
2CLKBA
2SBA
C11
G12
2CLKAB
2SAB
C13
G14
52
4D
2
1B1
≥1
5
5
1A1
1
5 1
≥1
6D
7
7
1
6
51
49
48
47
45
44
43
42
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
8
9
10
12
13
14
≥1
12 11D
12 1
15
2A1
8
13D 14
1 14
≥1
9
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
logic diagram (positive logic)
56
1OE
1
1DIR
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
2OE
28
2DIR
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54ABT16646 SN74ABT16646
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16646 SN74ABT16646
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
hys
Control
inputs
±1
±1
±1
I
V
= 5.5 V, V = V
or GND
µA
A or B ports
±20
10
±20
10
±20
10
‡
I
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 0,
V
V
= 2.7 V
= 0.5 V
µA
µA
µA
OZH
CC
CC
CC
CC
O
‡
–10
±100
–10
–10
±100
OZL
off
O
V or V ≤ 4.5 V
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
= 2.5 V
50
50
50
µA
CEX
O
§
I
O
V
CC
= 5.5 V,
V
O
–50
–100
–180
2
–50
–180
2
–50
–180
2
mA
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
Data inputs
32
2
32
2
32
2
mA
CC
V = V
I
or GND
CC
Outputs disabled
V
CC
= 5.5 V,
Outputs enabled
Outputs disabled
50
50
50
50
50
50
50
50
50
One input at 3.4 V,
Other inputs at
¶
µA
∆I
CC
V
CC
or GND
Control
inputs
V
CC
= 5.5 V, One input at 3.4 V,
or GND
Other inputs at V
CC
Control
inputs
C
C
V = 2.5 V or 0.5 V
4
8
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
and I
The parameters I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT16646
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
125
125
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
4.3
3.5
0.5
4.3
4
w
ns
su
h
0.5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT16646
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
125
125
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
4.3
3
4.3
3
w
ns
su
h
0
0
ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
SN54ABT16646
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
125
1.5
1.5
1
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
125
1
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
3.1
3.2
2.3
3
4
4.1
3.2
4.1
4.3
4.3
4.6
5.3
5.6
4.4
4.5
5.1
5.9
5.1
5
5
CLKBA or CLKAB
A or B
A or B
B or A
B or A
A or B
A or B
A or B
A or B
1
0.6
0.6
0.6
0.6
0.6
1
4
ns
ns
ns
ns
ns
ns
1
4.9
5.3
5.3
5.9
6
1
2.9
3.1
3.4
3.5
3.9
3.1
3.2
3.4
4.2
3.6
†
SAB or SBA
1
1
OE
1.5
1.5
1.5
1
1
6.4
4.7
5.8
6.7
7.1
6.2
OE
DIR
DIR
1
0.6
1
1.5
2
1.2
1
1.5
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
SN74ABT16646
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
125
1.5
1.5
1
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
125
1.5
1.5
1
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
3.1
3.2
2.3
3
4
4.1
3.2
4.1
4.3
4.3
4.6
4.9
4.9
4.1
4.5
4.8
5.7
5.1
4.9
4.7
3.9
4.6
5
CLKBA or CLKAB
A or B
A or B
B or A
B or A
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
1
1
1
2.9
3.1
3.4
3.5
3.9
3.1
3.2
3.4
4.2
3.6
1
†
SAB or SBA
1
1
5
1
1
5.5
5.7
5.4
4.5
5.4
5.6
6.7
5.9
OE
1.5
1.5
1.5
1
1.5
1.5
1.5
1
OE
DIR
DIR
1.5
2
1.5
2
1.5
1.5
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
PLZ
PLH
PHL
PHL
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PHZ
PLH
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9450201QXA
ACTIVE
CFP
WD
56
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9450201QX
A
SNJ54ABT16646W
D
74ABT16646DGGRE4
74ABT16646DGGRG4
SN74ABT16646DGGR
SN74ABT16646DL
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
SSOP
SSOP
SSOP
SSOP
CFP
DGG
DGG
DGG
DL
56
56
56
56
56
56
56
56
2000
2000
2000
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
A42
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
ABT16646
ABT16646
ABT16646
ABT16646
ABT16646
ABT16646
ABT16646
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74ABT16646DLG4
SN74ABT16646DLR
SN74ABT16646DLRG4
SNJ54ABT16646WD
DL
20
Green (RoHS
& no Sb/Br)
DL
1000
1000
1
Green (RoHS
& no Sb/Br)
DL
Green (RoHS
& no Sb/Br)
WD
TBD
5962-9450201QX
A
SNJ54ABT16646W
D
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT16646, SN74ABT16646 :
Catalog: SN74ABT16646
•
Military: SN54ABT16646
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ABT16646DGGR
SN74ABT16646DLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
330.0
330.0
24.4
32.4
8.6
15.6
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35 18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ABT16646DGGR
SN74ABT16646DLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
367.0
367.0
367.0
367.0
45.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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