74AC11378_10 [TI]
HEX D-TYPE FLIP FLOP WITH ENABLE, POSITIVE EDGE TRIGGER;型号: | 74AC11378_10 |
厂家: | TEXAS INSTRUMENTS |
描述: | HEX D-TYPE FLIP FLOP WITH ENABLE, POSITIVE EDGE TRIGGER |
文件: | 总8页 (文件大小:108K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢇꢈꢉ ꢊꢋ ꢌꢍꢎ ꢏꢈꢊ ꢐ ꢑ ꢒꢏ ꢌ ꢐꢑ ꢓ
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SCAS150 − APRIL 1991 − REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
• Contains Six D-Type Flip-Flops
• Clock Enable Latched to Avoid False
Clocking
1Q
2Q
3Q
GND
GND
GND
GND
4Q
CLKEN
1D
2D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
• Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
3D
• Flow-Through Architecture Optimizes PCB
V
CC
Layout
V
CC
• Center-Pin V
and GND Pin Configurations
Minimize High-Speed Switching Noise
CC
4D
13 5D
12 6D
• EPIC (Enhanced-Performance Implanted
5Q
6Q
CMOS) 1-µm Process
11
CLK
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages, and Standard
Plastic 300-mil DIPs
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input. Information at the D inputs
meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse
if the clock-enable input (CLKEN) is low.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going pulse. When the clock inputs are at either the high or low level, the data (D) input signal has no
effect at the output. The circuits are designed to prevent false clocking by transitions at the clock-enable
(CLKEN) input.
The 74AC11378 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLKEN
CLK
D
Q
H
X
X
Q
O
L
L
↑
↑
L
H
L
H
L
X
X
Q
O
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1993, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅꢀ ꢆ
ꢇ ꢈꢉꢊ ꢋ ꢌ ꢍ ꢎꢏꢈ ꢊ ꢐꢑ ꢒ ꢏꢌ ꢐ ꢑ ꢓꢏ
ꢔꢒ ꢍ ꢇ ꢊꢃ ꢑ ꢓꢃ ꢕꢊ ꢈ ꢖꢂ ꢗꢑ ꢈ
SCAS150 − APRIL 1991 − REVISED APRIL 1993
†
logic symbol
20
11
G1
1C2
CLKEN
CLK
19
18
17
14
13
12
1
2
1D
2D
3D
4D
5D
6D
2D
1Q
2Q
3Q
4Q
5Q
6Q
3
8
9
10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
20
CLKEN
11
CLK
C1
1D
1
2
3
19
1Q
1D
C1
18
2Q
3Q
4Q
1D
1D
2D
C1
17
3D
C1
1D
8
9
14
4D
C1
1D
13
5Q
6Q
5D
C1
1D
10
12
6D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS150 − APRIL 1991 − REVISED APRIL 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
High-level input voltage
V
V
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
−4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
−24
−24
12
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
I
OL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
−40
85
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢔꢒ ꢍ ꢇ ꢊꢃ ꢑ ꢓꢃ ꢕꢊ ꢈ ꢖꢂ ꢗꢑ ꢈ
SCAS150 − APRIL 1991 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
2.9
4.4
4.5 V
5.5 V
3 V
4.4
I
I
= − 50 µA
OH
5.4
5.4
= − 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= − 24 mA
= −75 mA
OL
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
4.5 V
5.5 V
3 V
I
I
= 50 µA
OL
0.1
0.1
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
1
V
OL
V
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
I
I
OL
†
= 75 mA
OL
I
I
V = V
or GND
or GND,
or GND
0.1
8
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
80
CC
I
C
V = V
4
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
90
0
5.5
8
90
MHz
ns
clock
CLK high or low
Data
5.5
8
w
t
Setup time, before CLK↑
Hold time, after CLK↑
ns
ns
su
h
CLKEN high or low
Data
6.5
0
6.5
0
t
CLKEN high or low
0
0
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
110
0
4
110
MHz
ns
clock
CLK high or low
Data
4
w
5
5
t
Setup time, before CLK↑
Hold time, after CLK↑
ns
ns
su
h
CLKEN high or low
Data
4.5
0
4.5
0
t
CLKEN high or low
0
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS150 − APRIL 1991 − REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
90
3
TYP
115
7.6
MAX
f
90
3
MHz
max
PLH
PHL
t
t
9.5
10.9
14
CLK
Any Q
ns
3.6
9.8
12.8
3.6
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
140
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
110
2.4
3
MAX
f
110
2.4
3
MHz
max
PLH
PHL
t
t
4.3
7
7.7
9.7
CLK
Any Q
ns
6.2
8.8
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
30
UNIT
C
C
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅꢀ ꢆ
ꢇ ꢈꢉꢊ ꢋ ꢌ ꢍ ꢎꢏꢈ ꢊ ꢐꢑ ꢒ ꢏꢌ ꢐ ꢑ ꢓꢏ
ꢔꢒ ꢍ ꢇ ꢊꢃ ꢑ ꢓꢃ ꢕꢊ ꢈ ꢖꢂ ꢗꢑ ꢈ
SCAS150 − APRIL 1991 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50% V
50% V
CC
CC
Input
0 V
From Output
Under Test
t
w
C
= 50 pF
L
V
500 Ω
CC
(see Note A)
Low-Level
Input
50% V
CC
50% V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
LOAD CIRCUIT
V
CC
Input
(see Note B)
50% V
CC
50% V
CC
0 V
V
CC
Timing
Input
t
PHL
t
50%
PLH
(see Note B)
0 V
V
OH
CC
In-Phase
Output
50% V
50% V
CC
t
su
t
h
V
OL
V
CC
Data
Input
t
PLH
50%
50%
t
PHL
0 V
V
OH
Out-Of-Phase
Output
50% V
50% V
CC
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
PDIP
Drawing
74AC11378DW
74AC11378N
74AC11378N
OBSOLETE
OBSOLETE
OBSOLETE
DW
N
20
20
20
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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Addendum-Page 1
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