74AC16543 [TI]
16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS; 16位寄存收发器，三态输出
| 型号： | 74AC16543 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
54AC16543 . . . WD PACKAGE
74AC16543 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
3-State True Outputs
1OEAB
1LEAB
1CEAB
GND
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
Flow-Through Architecture Optimizes
PCB Layout
1
56
55
54
53
52
51
50
49
48
2
3
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
4
1A1
1A2
5
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
6
V
V
7
CC
CC
500-mA Typical Latch-Up Immunity at
125°C
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
8
9
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
Spacings
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47 1B5
GND
1B6
46
45
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
description
The ’AC16543 are 16-bit registered transceivers
that contain two sets of D-type latches for
temporary storage of data flowing in either
direction.
They can be used as two 8-bit
V
35
V
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB or LEBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
CC
CC
2A7
2A8
GND
34 2B7
33 2B8
32 GND
31 2CEBA
30 2LEBA
29 2OEBA
2CEAB
2LEAB
2OEAB
The A-to-B enable (CEAB) input must be low to
enter data from A or to output data to B. Having
CEAB low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition at LEAB
puts the A latches in the storage mode. Data flow from B to A is similar, but requires using the CEBA, LEBA,
and OEBA inputs.
The 74AC16543 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16543 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16543 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
†
FUNCTION TABLE
(each 8-bit section)
INPUTS
LEAB OEAB
OUTPUT
B
CEAB
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Z
Z
‡
B
0
L
L
L
L
H
H
†
‡
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state input
conditions were established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
†
logic symbol
56
54
55
1
1EN3
G1
1OEBA
1CEBA
1LEBA
1OEAB
1C5
2EN4
G2
3
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2
2C6
29
31
30
28
26
27
7EN9
G7
7C11
8EN10
G8
8C12
5
52
1A1
5D
1B1
3
6D
4
6
51
49
48
47
45
44
1A2
1A3
1A4
1A5
1B2
1B3
1B4
1B5
1B6
1B7
8
9
10
12
1A6
1A7
1A8
2A1
13
14
15
43
42
1B8
2B1
11D
10
9
12D
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
56
1OEBA
54
1CEBA
55
1LEBA
1
1OEAB
3
1CEAB
2
1LEAB
C1
1D
5
1A1
52
1B1
C1
1D
To Seven Other Channels
29
2OEBA
31
2CEBA
30
2LEBA
28
2OEAB
26
2CEAB
27
2LEAB
C1
1D
15
2A1
42
2B1
C1
1D
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power package dissipation at T = 55°C (in still air)(see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, T
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54AC16543
MIN NOM
74AC16543
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
3
2.1
5
5.5
3
2.1
5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
–4
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
0
10
ns/V
T
A
–55
125
–40
85
°C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
54AC16543
74AC16543
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
I
I
= –50 µA
4.4
4.4
4.4
OH
5.4
5.4
5.4
V
OH
= –4 mA
2.58
3.94
4.94
2.48
3.8
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= –24 mA
= –75 mA
OL
4.8
4.8
†
3.85
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
I
Control inputs V = V
or GND
±0.1
±0.5
8
µA
µA
µA
pF
pF
I
I
CC
A or B ports
V
= V or GND
CC
±5
±5
OZ
CC
O
V = V
or GND,
or GND
I = 0
O
80
80
I
CC
CC
C
C
Control inputs V = V
3
i
I
A or B ports
V
= V or GND
CC
5 V
11.5
io
O
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
= 25°C
54AC16543
74AC16543
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, LEAB or LEBA low
Setup time, data before LEAB or LEBA ↑
Hold time, data after LEAB or LEBA ↑
ns
ns
ns
1
1
1
3.5
3.5
3.5
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
= 25°C
54AC16543
74AC16543
A
UNIT
MIN
4
MAX
MIN
4
MAX
MIN
4
MAX
t
w
t
su
t
h
Pulse duration, LEAB or LEBA low
Setup time, data before LEAB or LEBA ↑
Hold time, data after LEAB or LEBA ↑
ns
ns
ns
1
1
1
3
3
3
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
8.6
54AC16543
74AC16543
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
3.2
4.6
4.6
3.7
4.6
4.7
4.3
3.5
4.5
4.8
4.1
MAX
12.5
16
MIN
3.2
4.6
4.6
3.7
4.6
4.7
4.3
3.5
4.5
4.8
4.1
MAX
MIN
3.2
4.6
4.6
3.7
4.6
4.7
4.3
3.5
4.5
4.8
4.1
MAX
t
t
t
t
t
t
t
t
t
t
t
A or B
B or A
A or B
13.9
18
13.9
18
PLH
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
11.8
11.3
10
ns
LEBA or LEAB
15.4
14
16.8
15.8
19.8
10.8
10.4
15.7
19.7
10.2
9.8
16.8
15.8
19.8
10.8
10.4
15.7
19.7
10.2
9.8
A or B
A or B
A or B
A or B
ns
ns
ns
ns
CEBA or CEAB
CEBA or CEAB
OEBA or OEAB
OEBA or OEAB
12.7
7.8
17.7
10.1
9.7
7.3
9.7
13.9
17.6
9.6
12.5
7.5
6.8
9.2
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5.2
5.5
7
54AC16543
74AC16543
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2.7
2.9
3.9
3.7
3
MAX
7.8
MIN
2.7
2.9
3.9
3.7
3
MAX
MIN
2.7
2.9
3.9
3.7
3
MAX
8.8
t
t
t
t
t
t
t
t
t
t
t
t
8.8
9.2
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
A or B
B or A
A or B
A or B
A or B
A or B
A or B
ns
8.3
9.2
10.2
9.9
11.5
10.9
9.8
11.5
10.9
9.8
ns
ns
ns
ns
ns
LEBA or LEAB
CEBA or CEAB
CEBA or CEAB
OEBA or OEAB
OEBA or OEAB
6.7
5.8
6.7
6.5
5.9
5.6
6.6
6.3
5.6
8.7
3.6
4.2
4
10.3
8.7
3.6
4.2
4
11.5
9.3
3.6
4.2
4
11.5
9.3
8.2
8.8
8.8
2.9
3.5
4.2
3.7
8.5
2.9
3.5
4.2
3.7
9.6
2.9
3.5
4.2
3.7
9.6
10.2
8.4
11.3
8.9
11.3
8.9
7.9
8.4
8.4
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
53
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
11
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16543, 74AC16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS125B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
V
CC
Timing Input
Data Input
50%
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50%
50%
50%
50%
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
74AC16623DL
AC SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 0.300 INCH, PLASTIC, SSOP-48
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