74AC16646DLR [TI]
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS;
| 型号： | 74AC16646DLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总10页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS241A − MARCH 1990 − REVISED APRIL 1996
54AC16646 . . . WD PACKAGE
74AC16646 . . . DL PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebust Family
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
1DIR
1OE
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
1CLKAB
1SAB
GND
1A1
1CLKBA
1SBA
GND
1B1
Flow-Through Architecture Optimizes
PCB Layout
Distributed V
Minimize High-Speed Switching Noise
and GND Pin Configurations
CC
1A2
1B2
EPICt (Enhanced-Performance Implanted
V
V
CC
CC
CMOS) 1-mm Process
1A3
1A4
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
500-mA Typical Latch-Up Immunity at
125°C
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16646 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry,
with 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The devices
can be used as two 8-bit transceivers or one 16-bit
transceiver. Data on the A or B bus is clocked into
the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the bus transceivers and
registers.
21
22
23
36
35
34
2A6
2B6
V
V
CC
CC
2A7
2B7
2A8 24
33 2B8
25
26
27
28
32
31
30
29
GND
2SAB
2CLKAB
2DIR
GND
2SBA
2CLKBA
2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. DIR determines which bus receives data when OE is active (low). In the isolation
mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74AC16646 is packaged in the TI shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54AC16646 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC16646 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
ꢌ ꢏ ꢙꢐꢍꢍ ꢗ ꢋꢕ ꢐꢎꢔ ꢊꢍ ꢐ ꢏ ꢗꢋꢐꢒ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢘꢎ ꢗ ꢒ ꢌ ꢃꢋ ꢊꢗ ꢏ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢅ ꢁ ꢅ ꢆ ꢇ ꢁꢂꢃ ꢄ ꢅ ꢅ ꢁꢅ
ꢄꢅ ꢈꢉꢊ ꢋ ꢉ ꢌ ꢍ ꢋ ꢎ ꢂꢏ ꢍꢃ ꢐꢊ ꢑ ꢐꢎ ꢍ ꢂꢏ ꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎꢍ
ꢔꢊ ꢋ ꢕ ꢖ ꢈꢍꢋꢂꢋ ꢐ ꢗꢌꢋ ꢘꢌ ꢋꢍ
SCAS241A − MARCH 1990 − REVISED APRIL 1996
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
H or L
X
X
H
X
X
X
X
↑
↑
X
X
X
↑
X
L
H
H or L
X
X
X
H
X
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS241A − MARCH 1990 − REVISED APRIL 1996
FUNCTION TABLE
DATA I/O
A1−A8
†
INPUTS
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
B1−B8
{
↑
X
Input
Unspecified
Input
Store A, B unspecified
{
X
X
↑
X
X
Unspecified
Input
Store B, A unspecified
X
↑
H or L
X
↑
H or L
X
X
X
Input
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
X
X
X
Input
Input
L
X
L
Output
Input
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
Output
L
H or L
X
H
X
Input
†
The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢐ
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ꢎꢐ
ꢓ
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ꢋꢐ
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SCAS241A − MARCH 1990 − REVISED APRIL 1996
†
logic symbol
56
1
G3
1OE
1DIR
3 EN1 [BA]
3 EN2 [AB]
55
54
2
1CLKBA
1SBA
C4
G5
1CLKAB
1SAB
C6
3
G7
29
28
G10
2OE
2DIR
10 EN8 [BA]
10 EN9 [AB]
30
31
27
26
2CLKBA
2SBA
C11
G12
2CLKAB
2SAB
C13
G14
52
4D
2
1B1
≥1
5
5
1A1
1
5 1
6D
7
7
≥1
1
6
51
49
48
47
45
44
43
42
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
8
9
10
12
13
14
≥1
12 11D
12 1
15
2A1
8
13D 14
1 14
≥1
9
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢄ ꢅ ꢈꢉꢊ ꢋ ꢉꢌꢍ ꢋ ꢎꢂꢏꢍ ꢃꢐꢊ ꢑꢐꢎꢍ ꢂꢏꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎ
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SCAS241A − MARCH 1990 − REVISED APRIL 1996
logic diagram (positive logic)
56
1OE
1
1DIR
1CLKBA
55
54
1SBA
2
1CLKAB
3
1SAB
C1
1D
TG
TG
5
1A1
C1
1D
TG
TG
52
B1
6
1A2
8
51
49
48
47
45
44
43
B2
B3
B4
B5
B6
B7
B8
1A3
9
1A4
10
Seven Channels Identical
to Channel One Above
1A5
12
1A6
13
1A7
14
1A8
29
2OE
28
2DIR
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
C1
1D
TG
15
2A1
TG
C1
1D
TG
42
B1
TG
41
40
38
37
36
34
33
16
17
19
20
21
23
24
B2
B3
B4
B5
B6
B7
B8
2A2
2A3
2A4
2A5
2A6
2A7
2A8
Seven Channels Identical
to Channel One Above
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢅ ꢁ ꢅ ꢆ ꢇ ꢁꢂꢃ ꢄ ꢅ ꢅ ꢁꢅ
ꢄꢅ ꢈꢉꢊ ꢋ ꢉ ꢌ ꢍ ꢋ ꢎ ꢂꢏ ꢍꢃ ꢐꢊ ꢑ ꢐꢎ ꢍ ꢂꢏ ꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎꢍ
ꢔꢊ ꢋ ꢕ ꢖ ꢈꢍꢋꢂꢋ ꢐ ꢗꢌꢋ ꢘꢌ ꢋꢍ
SCAS241A − MARCH 1990 − REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V
Continuous current through V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
CC
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.4 W
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions
54AC16646
MIN NOM
74AC16646
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage (see Note 3)
High-level input voltage
3
2.1
5
5.5
3
2.1
5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
−4
V
CC
−4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
−24
−24
12
−24
−24
12
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
24
I
OL
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
0
10
ns/V
T
A
−55
125
−40
85
°C
NOTE 3: All V
CC
and GND pins must be connected to the proper voltage power supply.
ꢘ ꢎꢗꢒ ꢌ ꢃꢋ ꢘꢎ ꢐꢑꢊ ꢐꢔ ꢜꢤ ꢦ ꢟꢧ ꢢ ꢥ ꢚꢜ ꢟꢤ ꢠꢟ ꢤꢠꢣ ꢧ ꢤꢝ ꢨꢧ ꢟꢞ ꢡꢠꢚ ꢝ ꢜꢤ ꢚꢛ ꢣ ꢦꢟ ꢧꢢ ꢥꢚ ꢜꢰꢣ ꢟꢧ
ꢞ ꢣ ꢝ ꢜ ꢯ ꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢰ ꢣ ꢪ ꢟꢨ ꢢꢣ ꢤ ꢚꢫ ꢃ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ ꢝꢨ ꢣꢠ ꢜꢦꢜꢠ ꢥ ꢚꢜꢟꢤ ꢝ
ꢥ ꢧ ꢣ ꢞ ꢣ ꢝ ꢜꢯ ꢤ ꢯꢟ ꢥ ꢪꢝ ꢫ ꢋꢣ ꢬ ꢥ ꢝ ꢊꢤ ꢝ ꢚ ꢧꢡ ꢢꢣ ꢤꢚꢝ ꢧ ꢣꢝ ꢣꢧ ꢰ ꢣꢝ ꢚꢛ ꢣ ꢧ ꢜꢯꢛ ꢚ ꢚꢟ ꢠꢛ ꢥꢤꢯ ꢣ ꢟꢧ
ꢜ ꢝ ꢠ ꢟ ꢤꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟ ꢞꢡꢠ ꢚꢝ ꢭ ꢜꢚ ꢛꢟ ꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢃ
ꢄ ꢅ ꢈꢉꢊ ꢋ ꢉꢌꢍ ꢋ ꢎꢂꢏꢍ ꢃꢐꢊ ꢑꢐꢎꢍ ꢂꢏꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎ
ꢄ
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ꢁ
ꢅ
ꢍ
ꢍ
ꢔ
ꢊ
ꢋ
ꢕ
ꢖ
ꢈ
ꢍ
ꢋ
ꢂ
ꢋ
ꢐ
ꢗ
ꢌ
ꢋ
ꢘ
ꢌ
ꢋ
SCAS241A − MARCH 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54AC16646
74AC16646
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
4.4
4.4
I
I
= −50 µA
OH
5.4
5.4
= −4 mA
2.58
3.94
4.94
2.48
3.8
OH
V
OH
V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
4.8
†
†
I
I
= −50 mA
OH
= −75 mA
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
5.5 V
3 V
I
I
= 50 µA
OL
0.1
0.1
0.1
= 12 mA
0.36
0.36
0.36
0.5
0.44
0.44
0.44
OL
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
0.5
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
1
OL
I
I
I
V = V
or GND
or GND
or GND,
or GND
or GND
0.1
0.5
8
1
10
µA
µA
µA
pF
pF
I
I
CC
CC
CC
CC
CC
‡
V = V
5
OZ
CC
I
V = V
I
O
= 0
160
80
I
C
C
V = V
4.5
16
i
I
V = V
5 V
o
I
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
timing requirements over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 2)
V
CC
T
= 25°C
54AC16646
74AC16646
A
UNIT
MIN
0
MAX
MIN
0
MAX
65
MIN
0
MAX
65
f
t
t
t
Clock frequency
65
MHz
ns
clock
Pulse duration, CLKAB or CLKBA high or low
Setup time, A before CLKAB↑ or B before CLKBA↑
Hold time, A after CLKAB↑ or B after CLKBA↑
7
7
7
w
6.5
1
6.5
1
6.5
1
ns
su
h
ns
timing requirements over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
T
= 25°C
54AC16646
74AC16646
A
UNIT
MIN
0
MAX
MIN
0
MAX
75
MIN
0
MAX
75
f
t
t
t
Clock frequency
75
MHz
ns
clock
Pulse duration, CLKAB or CLKBA high or low
Setup time, A before CLKAB↑ or B before CLKBA↑
Hold time, A after CLKAB↑ or B after CLKBA↑
6.5
5
6.5
5
6.5
5
w
ns
su
h
1
1
1
ns
ꢘꢎ ꢗ ꢒꢌ ꢃ ꢋ ꢘꢎ ꢐꢑꢊ ꢐꢔ ꢜꢤ ꢦ ꢟꢧ ꢢꢥ ꢚꢜꢟ ꢤ ꢠꢟ ꢤꢠꢣ ꢧ ꢤꢝ ꢨꢧ ꢟꢞ ꢡꢠꢚ ꢝ ꢜꢤ ꢚꢛ ꢣ ꢦꢟ ꢧꢢ ꢥꢚ ꢜꢰꢣ ꢟꢧ
ꢞꢣ ꢝ ꢜ ꢯꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢰ ꢣ ꢪ ꢟꢨ ꢢꢣ ꢤꢚꢫ ꢃ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ ꢝꢨ ꢣꢠ ꢜꢦꢜꢠ ꢥ ꢚꢜꢟꢤ ꢝ
ꢥ ꢧ ꢣ ꢞꢣ ꢝ ꢜ ꢯꢤ ꢯꢟ ꢥ ꢪꢝ ꢫ ꢋꢣ ꢬ ꢥ ꢝ ꢊꢤꢝ ꢚꢧ ꢡꢢ ꢣꢤꢚ ꢝ ꢧ ꢣꢝ ꢣꢧ ꢰ ꢣꢝ ꢚꢛ ꢣ ꢧ ꢜꢯꢛ ꢚ ꢚꢟ ꢠꢛ ꢥꢤꢯ ꢣ ꢟꢧ
ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟ ꢞꢡꢠ ꢚꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢅ ꢁ ꢅ ꢆ ꢇ ꢁꢂꢃ ꢄ ꢅ ꢅ ꢁꢅ
ꢄꢅ ꢈꢉꢊ ꢋ ꢉ ꢌ ꢍ ꢋ ꢎ ꢂꢏ ꢍꢃ ꢐꢊ ꢑ ꢐꢎ ꢍ ꢂꢏ ꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎꢍ
ꢔꢊ ꢋ ꢕ ꢖ ꢈꢍꢋꢂꢋ ꢐ ꢗꢌꢋ ꢘꢌ ꢋꢍ
SCAS241A − MARCH 1990 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
54AC16646
74AC16646
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
65
TYP
MAX
MIN
65
MAX
MIN
65
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
max
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
3.4
3.6
3.8
4.8
4.4
4
9.3
10
13.2
13.4
3.4
3.6
3.8
4.8
4.4
4
15.7
15.1
17.6
22.1
11
3.4
3.6
3.8
4.8
4.4
4
14.8
4.5
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
ns
ns
10.5
13.9
7.6
16.4
20.9
10.7
10.1
18.7
18
OE
OE
7
10.4
19.9
18.8
19.9
17.2
17.3
20.3
17.9
22.1
11.6
11
4.7
4.8
4.7
4.5
4
12.1
12.2
12
4.7
4.8
4.7
4.5
4
4.7
4.8
4.7
4.5
4
CLKBA or CLKAB
18.5
16.4
16.3
19.3
16.8
20.8
11.2
10.6
†
SAB or SBA
(with A or B high)
11.4
10.5
13.3
10.3
13.5
7.8
†
SBA or SAB
(with A or B low)
5.2
3.6
4.7
4.6
3.9
5.2
3.6
4.7
4.6
3.9
5.2
3.6
4.7
4.6
3.9
DIR
DIR
7
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
54AC16646
74AC16646
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
75
2.9
2.9
3.1
4.1
4
TYP
MAX
MIN
75
2.9
2.9
3.1
4.1
4
MAX
MIN
75
2.9
2.9
3.1
4.1
4
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
max
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
5.5
5.7
6.1
7.3
6.1
5.7
7
8.5
8.9
10.1
10.1
11.1
12.9
9.1
9.5
9.7
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
ns
ns
9.4
10.5
12.2
8.9
OE
OE
11
8.4
3.8
3.9
3.9
4
8
3.8
3.9
3.9
4
8.9
3.8
3.9
3.9
4
8.6
10.8
10.8
11.1
10.2
9.5
12.8
12.5
13.4
11.8
11.2
13.9
11.6
12.9
9.6
12.1
11.9
12.5
11.2
10.6
13.1
10.9
12.2
9.4
CLKBA or CLKAB
7.1
7.4
6.7
6.1
8
†
SAB or SBA
(with A or B high)
3.6
3.3
4.3
3
3.6
3.3
4.3
3
3.6
3.3
4.3
3
†
SBA or SAB
(with A or B low)
11.7
9.6
5.9
7
DIR
3.6
4
11.1
8.8
3.6
4
3.6
3
6.2
5.7
DIR
3.7
8.2
3.7
9
3.7
8.8
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
ꢘ
ꢎ
ꢗ
ꢒ
ꢌ
ꢃ
ꢋ
ꢘ
ꢎ
ꢐ
ꢑ
ꢊ
ꢐ
ꢔ
ꢜ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢧ
ꢤ
ꢝ
ꢨ
ꢧ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢝ
ꢞ ꢣ ꢝ ꢜ ꢯ ꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢰ ꢣ ꢪ ꢟꢨ ꢢꢣ ꢤ ꢚꢫ ꢃ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢰ
ꢣ
ꢟ
ꢧ
ꢝ
ꢠ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢧ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢯ
ꢤ
ꢯ
ꢟ
ꢥ
ꢪ
ꢝ
ꢫ
ꢋ
ꢣ
ꢬ
ꢥ
ꢝ
ꢊ
ꢤ
ꢝ
ꢚ
ꢧ
ꢡ
ꢢ
ꢣ
ꢤ
ꢚ
ꢝ
ꢧ
ꢛ ꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟ ꢞꢡꢠ ꢚꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢣ
ꢝ
ꢣ
ꢧ
ꢰ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢧ
ꢜ
ꢯ
ꢛ
ꢚ
ꢚ
ꢟ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢁ
ꢅ
ꢆ
ꢇ
ꢁ
ꢂ
ꢃ
ꢄ ꢅ ꢈꢉꢊ ꢋ ꢉꢌꢍ ꢋ ꢎꢂꢏꢍ ꢃꢐꢊ ꢑꢐꢎꢍ ꢂꢏꢒ ꢎꢐ ꢓ ꢊꢍ ꢋꢐ ꢎ
ꢄ
ꢅ
ꢅ
ꢁ
ꢅ
ꢍ
ꢍ
ꢔ
ꢊ
ꢋ
ꢕ
ꢖ
ꢈ
ꢍ
ꢋ
ꢂ
ꢋ
ꢐ
ꢗ
ꢌ
ꢋ
ꢘ
ꢌ
ꢋ
SCAS241A − MARCH 1990 − REVISED APRIL 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
62
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance
C
pF
pd
14
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
Open
GND
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
V
CC
50%
Timing Input
Data Input
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
50%
50%
50%
50%
Input
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
[ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
V
OL
OL
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
80% V
CC
50% V
50% V
CC
CC
CC
[ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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