74ACT11373DBR [TI]
具有三态输出的八路透明 D 型锁存器 | DB | 24 | -40 to 85;
| 型号： | 74ACT11373DBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的八路透明 D 型锁存器 | DB | 24 | -40 to 85 锁存器 |
| 文件： | 总6页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
DB, DW, OR NT PACKAGE
(TOP VIEW)
Eight Latches in a Single Package
3-State Bus Driving True Outputs
Full Parallel Access for Loading
Buffered Input and Output-Enable Pins
Inputs Are TTL-Voltage Compatible
1Q
2Q
OE
1D
2D
3D
4D
V
1
24
23
22
21
20
19
18
17
16
15
14
13
2
3Q
3
4Q
4
Flow-Through Architecture Optimizes
PCB Layout
GND
GND
GND
GND
5Q
5
6
CC
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
7
V
CC
8
5D
6D
7D
8D
LE
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
9
10
11
12
6Q
500-mA Typical Latch-Up Immunity at
125°C
7Q
8Q
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
description
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels
that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The 74ACT11373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
LE
H
H
L
OE
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
†
logic symbol
24
OE
EN
C1
13
LE
23
1D
1
2
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
22
2D
21
3
3D
20
4
4D
17
9
5D
16
10
11
12
6D
15
7D
14
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
13
OE
LE
C1
1D
1
2
23
22
21
20
17
16
15
14
1Q
1D
2D
3D
4D
5D
6D
7D
8D
C1
1D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
1D
3
C1
1D
4
C1
1D
9
C1
1D
10
11
12
C1
1D
C1
1D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
DW package . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
recommended operating conditions
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
0
0
V
V
V
I
CC
Output voltage
V
O
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
mA
mA
ns/V
°C
OH
OL
t/ v
0
10
T
–40
85
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
4.4
TYP
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
4.4
5.4
I
I
= –50 A
OH
5.4
3.94
4.94
3.8
V
V
OH
OL
= –24 mA
= –75 mA
OH
4.8
3.85
I
I
OH
0.1
0.1
0.1
0.1
0.44
0.44
1.65
±5
= 50
A
OL
0.36
0.36
V
V
I
I
= 24 mA
= 75 mA
OL
OL
I
I
I
V
= V or GND
CC
±0.5
±0.1
8
A
A
OZ
O
V = V
or GND
or GND,
±1
I
I
CC
CC
V = V
I = 0
O
80
A
CC
I
I
One input at 3.4 V,
V = V or GND
Other inputs at GND or V
CC
0.9
1
mA
pF
pF
CC
C
C
4
i
I
CC
= V or GND
CC
V
5 V
10
o
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
A
MIN
MAX
UNIT
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data LE↓
5
3.5
3.5
ns
ns
ns
3.5
3.5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
7.5
6.5
8.5
8.5
7
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
10.3
9.3
t
t
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
11.8
10
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
11.3
10.9
10.7
10.9
12.1
9.5
13
LE
Any Q
Any Q
Any Q
ns
12.2
12.5
12
ns
OE
OE
7.5
10
12.2
10.1
ns
7.5
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
65
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per latch
C
= 50 pF,
L
f = 1 MHz
pF
pd
54
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
t
t
/t
Open
PLH PHL
/t
C
= 50 pF
t
2 × V
L
PLZ PZL
CC
500 Ω
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT
3 V
Timing Input
Data Input
1.5 V
0 V
3 V
0 V
t
w
t
h
t
3 V
su
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
74ACT11373NSR
IC ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24, Bus Driver/Transceiver
TI
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