74ACT11651NT [TI]

OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS;


型号：	74ACT11651NT
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 输出元件
文件：	总9页 (文件大小：145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢇꢅ

ꢈ ꢃꢄꢂꢉꢊꢋ ꢌꢍꢊ ꢄꢎꢂ ꢏꢍꢃꢐ ꢑꢒꢐ ꢎꢊꢂꢏꢓ ꢊꢎꢐ ꢔ ꢑꢍ ꢄꢐ ꢎ

ꢕ ꢑꢄ ꢖꢊ ꢗ ꢘꢍꢄꢂꢄ ꢐꢊ ꢈꢌ ꢄꢙ ꢌꢄ ꢍ

ꢚ

SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

DW OR NT PACKAGE

(TOP VIEW)

• Inputs Are TTL-Voltage Compatible

• Bus Transceivers/Registers

• Independent Registers and Enables for A

GAB

28 CAB

and B Buses

SAB

• Multiplexed Real-Time and Stored Data

• Inverting Data Paths

• Flow-Through Architecture to Optimize

GND

GBA

PCB Layout

• Center-Pin V

and GND Configurations to

Minimize High-Speed Switching Noise

CBA

SBA

• EPICt (Enhanced-Performance Implanted

CMOS) 1-mm Process

• 500-mA Typical Latch-Up Immunity

at 125°C

• Package Options Include Plastic Small

Outline Packages and Standard Plastic

300-mil DIPs

description

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed

transmission of data directly from the data bus or from the internal storage registers. Enables GAB and GBA

are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether

real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch

that occurs in a multiplexer during the transition between stored and real-time data.

A low input level selects real-time data and a high selects stored data. Figure 1 illustrates the four fundamental

bus-management functions that can be performed with the octal bus transceivers and registers. Data on the

A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock

pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time

transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously

enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all other data sources

to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

The 74ACT11651 is characterized for operation from − 40°C to 85°C.

EPIC is a trademark of Texas Instruments Incorporated.

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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆꢇ ꢅ

ꢈꢃ ꢄꢂ ꢉꢊ ꢋ ꢌꢍ ꢊ ꢄꢎꢂ ꢏꢍ ꢃꢐ ꢑ ꢒꢐ ꢎꢊꢂꢏ ꢓꢊ ꢎꢐꢔ ꢑ ꢍꢄ ꢐꢎ

ꢕꢑ ꢄ ꢖ ꢊꢗ ꢘꢍ ꢄꢂꢄꢐ ꢊ ꢈ ꢌꢄ ꢙꢌꢄ ꢍ

ꢚ

SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

GAB

GBA

CAB

CBA

SAB

SBA

GAB

GBA

CAB

CBA

SAB

SBA

REAL-TIME TRANSFER BUS B TO BUS A

REAL-TIME TRANSFER BUS A TO BUS B

GAB

GBA

CAB

↑

CBA

SAB

SBA

GAB

GBA

CAB

CBA

SAB

SBA

H or L

↑

STORAGE FROM A AND/OR B

TRANSFER STORED DATA TO A AND/OR B

Figure 1. Bus Transfer Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢇꢅ

ꢈ ꢃꢄꢂꢉꢊꢋ ꢌꢍꢊ ꢄꢎꢂ ꢏꢍꢃꢐ ꢑꢒꢐ ꢎꢊꢂꢏꢓ ꢊꢎꢐ ꢔ ꢑꢍ ꢄꢐ ꢎ

ꢕ ꢑꢄ ꢖꢊ ꢗ ꢘꢍꢄꢂꢄ ꢐꢊ ꢈ ꢌꢄ ꢙꢌ ꢄꢍ

ꢚ

SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

FUNCTION TABLE

DATA I/O

INPUTS

OPERATION OR FUNCTION

GAB

GBA

CAB

CBA

SAB

SBA

A1 THRU A8

Input

B1 THRU B8

Input

H or L

Isolation

↑

Input

Store A and B Data

†

↑

H or L

Input

Unspecified

Store A, Hold B

‡

↑

H or L

↑

Input

Output

Input

Store A in both registers

Hold A, Store B

†

↑

Unspecified

‡

↑

Output

Input

Store B in both registers

Real-Time B data to A Bus

Stored B Data to A Bus

Real-Time A Data to B Bus

Stored A Data to B Bus

Stored A Data to B Bus and

Stored B Data to A Bus

Input

H or L

Input

Output

H or L

Input

H or L

Output

†

‡

The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled,

i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.

Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers.

logic symbol

GBA

GAB

CBA

SBA

CAB

SAB

EN1 [BA]

EN2 [AB]

≥1

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆꢇ ꢅ

ꢈꢃ ꢄꢂ ꢉꢊ ꢋ ꢌꢍ ꢊ ꢄꢎꢂ ꢏꢍ ꢃꢐ ꢑ ꢒꢐ ꢎꢊꢂꢏ ꢓꢊ ꢎꢐꢔ ꢑ ꢍꢄ ꢐꢎ

ꢕꢑ ꢄ ꢖ ꢊꢗ ꢘꢍ ꢄꢂꢄꢐ ꢊ ꢈ ꢌꢄ ꢙꢌꢄ ꢍ

ꢚ

SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

logic diagram (positive logic)

GBA

GAB

CBA

SBA

CAB

SAB

7 Channels Identical

To Channel 1 Above

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to V

+ 0.5 V

Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to V

Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Output clamp current, I

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Continuous current through V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢇꢅ

ꢈ ꢃꢄꢂꢉꢊꢋ ꢌꢍꢊ ꢄꢎꢂ ꢏꢍꢃꢐ ꢑꢒꢐ ꢎꢊꢂꢏꢓ ꢊꢎꢐ ꢔ ꢑꢍ ꢄꢐ ꢎ

ꢕ ꢑꢄ ꢖꢊ ꢗ ꢘꢍꢄꢂꢄ ꢐꢊ ꢈ ꢌꢄ ꢙꢌ ꢄꢍ

ꢚ

SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage

4.5

5.5

High-level input voltage

Low-level input voltage

Input voltage

0.8

Output voltage

High-level output current

Low-level output current

−24

ns/V

°C

Dt/Dv Input transition rise or fall rate

Operating free-air temperature

−40

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

= 25°C

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

MIN

4.4

TYP

MAX

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

5 V

4.4

5.4

= − 50 mA

5.4

3.94

4.94

3.8

= − 24 mA

= − 75 mA

= 50 mA

4.8

{

3.85

0.1

0.44

1.65

0.36

= 24 mA

{

= 75 mA

A or B ports

V = V

or GND

or GND,

or GND

0.5

0.1

Control Inputs

V = V

I = 0

‡

V = V

0.9

Control Inputs

A or B ports

V = V

4.5

V = V

5 V

†

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V

For I/O ports, the parameter I

includes the input leakage current.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 2)

= 25°C

MIN

MAX

UNIT

MIN

MAX

Clock frequency

100

MHz

clock

Pulse duration, CAB or CBA high or low

Setup time, A before CAB↑ or B before CBA↑

Hold time, A after CAB↑ or B after CBA↑

5.5

4.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆꢇ ꢅ

ꢈꢃ ꢄꢂ ꢉꢊ ꢋ ꢌꢍ ꢊ ꢄꢎꢂ ꢏꢍ ꢃꢐ ꢑ ꢒꢐ ꢎꢊꢂꢏ ꢓꢊ ꢎꢐꢔ ꢑ ꢍꢄ ꢐꢎ

ꢕꢑ ꢄ ꢖ ꢊꢗ ꢘꢍ ꢄꢂꢄꢐ ꢊ ꢈ ꢌꢄ ꢙꢌꢄ ꢍ

ꢚ

SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 2)

T = 25°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

MIN

TYP

MAX

max

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PZH

2.6

4.7

5.5

6.3

4.8

4.1

5.6

7.7

8.4

9.5

7.6

7.7

6.2

8.7

7.4

8.2

7.7

6.9

8.9

10.7

11.2

12.7

10.4

11.2

9.3

2.6

4.7

5.5

6.3

4.8

4.1

9.9

11.9

12.7

14.1

11.8

12.4

10.4

A or B

B or A

A or B

CBA or CAB

†

SBA or SAB

with A or B high

†

SBA or SAB

with A or B low

5.6

11.7

10.7

11.9

9.5

5.6

11.9

13.3

GBA

4.3

5.9

5.1

5.9

6.4

4.7

3.8

4.3

5.9

5.1

5.9

6.4

4.7

3.8

PZL

PHZ

GBA

8.7

9.2

PLZ

PZH

12.1

13.2

9.5

13.7

14.9

GAB

9.8

7.1

6.1

PZL

PHZ

8.4

8.8

PLZ

†

These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

operating characteristics, V

= 5 V, T = 25°C

PARAMETER

TEST CONDITIONS

= 50 pF, f = 1 MHz

TYP

UNIT

Outputs enabled

Outputs disabled

Power dissipation capacitance per gate

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢇꢅ

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SCAS134 − D3445, MARCH 1990 − REVISED APRIL 1993

PARAMETER MEASUREMENT INFORMATION

2 × V

TEST

Open

500 Ω

Open

GND

PLH PHL

From Output

Under Test

2 × V

PLZ PZL

GND

PHZ PZH

= 50 pF

500 Ω

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

3 V

0 V

Input

1.5 V

3 V

0 V

Timing Input

Data Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

3 V

0 V

3 V

0 V

1.5 V

Output

Control

(low-level

enabling)

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

≈ V

3 V

0 V

Input

(see Note B)

Output

Waveform 1

1.5 V

50% V

20% V

80% V

S1 at 2 × V

(see Note C)

PLH

PHZ

PHL

PZH

Output

Waveform 2

S1 at GND

Output

(see Note D)

50% V

(see Note C)

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.

For testing pulse duration: t = t = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jun-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SOIC

PDIP

Drawing

74ACT11651DW

74ACT11651NT

OBSOLETE

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

no Sb/Br)

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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