74ALVCH16543DGGRG4 [TI]
16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS;
| 型号： | 74ALVCH16543DGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
•
•
•
•
Member of the Texas Instruments Widebus™
Family
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1OEBA
1LEBA
1CEBA
GND
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
2
3
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
4
5
1A1
1B1
ESD Protection Exceeds 2000 V Per
6
1A2
1B2
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
7
V
CC
V
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16543 can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB or LEBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
V
CC
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The A-to-B enable (CEAB) input must be low to enter
data from A or to output data from B. If CEAB is low
and LEAB is low, the A-to-B latches are transparent;
a subsequent low-to-high transition of LEAB puts the
A latches in the storage mode. With CEAB and OEAB
both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data
flow from B to A is similar, but requires using CEBA,
LEBA, and OEBA.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16543 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
LOGIC SYMBOL (1)
56
1EN3
G1
1OEBA
54
1CEBA
55
1LEBA
1
1C5
2EN4
G2
1OEAB
3
1CEAB
2
2C6
1LEAB
29
7EN9
G7
2OEBA
31
2CEBA
30
7C11
8EN10
G8
2LEBA
28
2OEAB
26
2CEAB
27
8C12
2LEAB
5
52
1A1
5D
4
1B1
3
6D
6
1A2
8
51
49
48
47
45
44
1B2
1B3
1B4
1B5
1B6
1B7
1A3
9
1A4
10
1A5
12
1A6
13
1A7
14
1A8
43
42
1B8
2B1
15
2A1
11D
10
9
12D
16
2A2
17
41
40
38
37
36
34
33
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2A3
19
2A4
20
2A5
21
2A6
23
2A7
24
2A8
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
56
54
1OEBA
1CEBA
55
1
1LEBA
1OEAB
3
2
1CEAB
1LEAB
C1
1D
5
1A1
52
1B1
C1
1D
To Seven Other Channels
29
31
2OEBA
2CEBA
30
28
2LEBA
2OEAB
26
27
2CEAB
2LEAB
C1
1D
15
2A1
42
2B1
C1
1D
To Seven Other Channels
3
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
FUNCTION TABLE(1)
(each 8-bit section)
INPUTS
OUTPUT
B
CEAB
LEAB
OEAB
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Z
Z
(2)
B0
L
L
L
L
H
H
(1) A-to-B data flow is shown; B-to-A flow control is the same, except
that it uses CEBA, LEBA, and OEBA.
(2) Output level before the indicated steady-state input conditions were
established
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
-0.5
-0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range
4.6
4.6
V
Except I/O ports(2)
I/O ports(2)(3)
V
VCC + 0.5
VCC + 0.5
-50
VO
IIK
Output voltage range(2)(3)
Input clamp current
V
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
-50
Continuous output current
Continuous current through each VCC or GND
±50
±100
81
DGG package
DL package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
74
Tstg
-65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.
4
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
0.35 × VCC
0.7
0.8
VCC
VCC
-4
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
-40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1)
VCC - 0.2
MAX
UNIT
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = -12 mA
2.7 V
3 V
IOH = -24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
VOL
V
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.55
±5
II
3.6 V
µA
1.65 V
1.65 V
2.3 V
25
-25
45
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
2.3 V
-45
75
µA
VI = 0.8 V
3 V
VI = 2 V
3 V
-75
VI = 0 to 3.6 V(2)
VO = VCC or GND
VI = VCC or GND,
3.6 V
±500
±10
40
(3)
IOZ
3.6 V
µA
µA
µA
pF
pF
ICC
∆ICC
Ci
IO = 0
3.6 V
One input at VCC - 0.6 V, Other inputs at VCC or GND
Control inputs VI = VCC or GND
A or B ports VO = VCC or GND
3 V to 3.6 V
3.3 V
750
3.5
8.5
Cio
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN MAX
MIN MAX
MIN MAX
(1)
tw
tsu
th
Pulse duration, LE or CE low
Setup time
3.3
1.2
1.2
3.3
1.5
0.8
3.3
1.2
1.3
ns
ns
ns
(1)
(1)
Data before LE↑ or CE↑
Data after LE↑ or CE↑
Hold time
(1) This information was not available at the time of publication.
6
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN
1
MAX
MIN
MAX
MIN
1
MAX
(1)
A or B
LE
B or A
A or B
A or B
A or B
A or B
A or B
5.1
6.5
7.2
6.1
6.8
5.7
4.8
6.2
6.9
6.2
6.3
4.8
4.3
5
tpd
ns
(1)
(1)
(1)
(1)
(1)
1
1.1
1
ten
tdis
ten
tdis
CE
1
5.6
5.1
5.3
4.6
ns
ns
ns
ns
CE
1.3
1
1.5
1
OE
OE
1
1.1
(1) This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
54
6
TYP
64
7
(1)
Outputs enabled
Outputs disabled
Power dissipation
capacitance
Cpd
CL = 50 pF, f = 10 MHz
pF
(1)
(1) This information was not available at the time of publication.
7
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × V
CC
S1
Open
1 kΩ
From Output
Under Test
TEST
S1
GND
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
1 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V /2
CC
V
/2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
8
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V /2
CC
V
/2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
9
SN74ALVCH16543
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES025E–JULY 1995–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6 V
S1
Open
TEST
S1
500 Ω
From Output
Under Test
t
pd
Open
6 V
GND
GND
t
t
/t
PLZ PZL
/t
C = 50 pF
L
500 Ω
PHZ PZH
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
0 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
Data
Input
Output
Control
(low-level
enabling)
1.5 V
1.5 V
2.7 V
0 V
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
(see Note B)
0 V
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74ALVCH16543DGGRE4
74ALVCH16543DGGRG4
74ALVCH16543DLG4
74ALVCH16543DLRG4
SN74ALVCH16543DGGR
SN74ALVCH16543DL
SN74ALVCH16543DLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
TSSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ALVCH16543DGGR TSSOP
SN74ALVCH16543DLR SSOP
DGG
DL
56
56
2000
1000
330.0
330.0
24.4
32.4
8.6
15.6
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35
18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALVCH16543DGGR
SN74ALVCH16543DLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
346.0
346.0
346.0
346.0
41.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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