74ALVCH16601DGVRG4 [TI]

ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56;


型号：	74ALVCH16601DGVRG4
厂家：	TEXAS INSTRUMENTS
描述：	ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56 光电二极管输出元件逻辑集成电路电视
文件：	总15页 (文件大小：358K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

FEATURES

DGG OR DL PACKAGE

(TOP VIEW)

•

Member of the Texas Instruments Widebus™

Family

OEAB

LEAB

GND

CLKENAB

CLKAB

GND

•

UBT™ (Universal Bus Transceiver) Combines

D-Type Latches and D-Type Flip-Flops for

Operation in Transparent, Latched, Clocked,

or Clock-Enabled Modes

•

EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

GND

•

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

A10

A11

A12

GND

A13

A14

A15

B10

B11

B12

GND

B13

B14

B15

DESCRIPTION

This 18-bit universal bus transceiver is designed for

1.65-V to 3.6-V V_CCoperation.

The SN74ALVCH16601 combines D-type latches and

D-type flip-flops to allow data flow in transparent,

latched, and clocked modes.

A16

A17

B16

B17

GND

A18

OEBA

LEBA

GND

B18

CLKBA

CLKENBA

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and CLKBA)

inputs. The clock can be controlled by the

clock-enable (CLKENAB and CLKENBA) inputs. For

A-to-B data flow, the device operates in the

transparent mode when LEAB is high. When LEAB is

low, the A data is latched if CLKAB is held at a high

or low logic level. If LEAB is low, the A data is stored

in the latch/flip-flop on the low-to-high transition of

CLKAB. Output enable OEAB is active low. When

OEAB is low, the outputs are active. When OEAB is

high, the outputs are in the high-impedance state.

<br/>

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CCthrough a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16601 is characterized for operation from -40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBT, EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

FUNCTION TABLE⁽¹⁾

INPUTS

OUTPUT

CLKENAB

OEAB

LEAB

CLKAB

↑

(2)

B₀

(2)

B₀

↑

(2)

B₀

(3)

B₀

(1) A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA,

LEBA, and CLKBA.

(2) Output level before the indicated steady-state input conditions were

established, provided that CLKAB was high before LEAB went low

(3) Output level before the indicated steady-state input conditions were

established

LOGIC DIAGRAM (POSITIVE LOGIC)

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

CLK

To 17 Other Channels

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

-0.5

MAX

4.6

UNIT

V_CC

V_I

Supply voltage range

Input voltage range

Except I/O ports⁽²⁾

I/O ports⁽²⁾⁽³⁾

4.6

-0.5 V_CC+ 0.5

V_O

I_IK

Output voltage range⁽²⁾⁽³⁾

Input clamp current

-0.5 V_CC+ 0.5

V_I< 0

-50

I_OK

I_O

Output clamp current

V_O< 0

Continuous output current

Continuous current through each V_CCor GND

±50

±100

DGG package

DL package

θ_JA

Package thermal impedance⁽⁴⁾

Storage temperature range

°C/W

°C

T_stg

-65

150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) This value is limited to 4.6 V maximum.

(4) The package thermal impedance is calculated in accordance with JESD 51.

RECOMMENDED OPERATING CONDITIONS⁽¹⁾

MIN

MAX UNIT

V_CC

Supply voltage

1.65

3.6

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0.65 × V_CC

V_IH

High-level input voltage

1.7

0.35 × V_CC

0.7

V_IL

Low-level input voltage

0.8

V_I

Input voltage

V_CC

-4

V_O

Output voltage

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 2.7 V

V_CC= 3 V

-12

-24

I_OH

High-level output current

Low-level output current

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 2.7 V

V_CC= 3 V

I_OL

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

10 ns/V

85 °C

T_A

-40

(1) All unused control inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

1.65 V to 3.6 V

1.65 V

2.3 V

MIN TYP⁽¹⁾

V_CC- 0.2

MAX UNIT

I_OH= -100 µA

I_OH= -4 mA

I_OH= -6 mA

1.2

V_OH

2.3 V

1.7

2.2

2.4

I_OH= -12 mA

2.7 V

3 V

I_OH= -24 mA

I_OL= 100 µA

I_OL= 4 mA

I_OL= 6 mA

3 V

1.65 V to 3.6 V

1.65 V

2.3 V

0.2

0.45

0.4

V_OL

2.3 V

0.7

I_OL= 12 mA

2.7 V

0.4

I_OL= 24 mA

V_I= V_CCor GND

V_I= 0.58 V

3 V

0.55

I_I

3.6 V

±5

µA

1.65 V

2.3 V

-25

V_I= 1.07 V

V_I= 0.7 V

I_I(hold)

V_I= 1.7 V

2.3 V

-45

V_I= 0.8 V

3 V

V_I= 2 V

3 V

-75

V_I= 0 to 3.6 V⁽²⁾

V_O= V_CCor GND

V_I= V_CCor GND,

3.6 V

±500

±10

(3)

I_OZ

3.6 V

µA

I_CC

∆I_CC

C_i

I_O= 0

3.6 V

One input at V_CC- 0.6 V, Other inputs at V_CCor GND

Control inputs V_I= V_CCor GND

A or B ports V_O= V_CCor GND

3 V to 3.6 V

3.3 V

750

C_io

3.3 V

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to

another.

(3) For I/O ports, the parameter I_OZincludes the input leakage current.

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

TIMING REQUIREMENTS

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)

V_CC= 2.5 V

± 0.2 V

V_CC= 3.3 V

± 0.3 V

V_CC= 1.8 V

V_CC= 2.7 V

UNIT

MIN

MAX

MIN

MAX

150

MIN

MAX

150

MIN

MAX

150

(1)

f_clockClock frequency

MHz

(1)

LE high

3.3

2.3

3.3

2.4

1.6

1.2

3.3

2.1

1.6

1.1

1.7

0.8

1.4

1.7

0.6

t_w

Pulse duration

CLK high or low

Data before CLK↑

CLK high

CLK low

t_su

Setup time

Data before LE↓

1.3

CLKEN before CLK↑

Data after CLK↑

0.7

1.3

1.7

0.3

0.7

1.6

CLK high

CLK low

t_h

Hold time

Data after LE↓

CLKEN after CLK↑

0.5

(1) This information was not available at the time of publication.

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)

V_CC= 2.5 V

± 0.2 V

V_CC= 3.3 V

± 0.3 V

V_CC= 1.8 V

V_CC= 2.7 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN TYP MIN MAX MIN MAX MIN MAX

(1)

f_max

150

MHz

(1)

A or B

B or A

A or B

4.6

5.2

5.3

4.9

4.6

5.3

5.8

6.1

4.8

4.1

4.7

t_pd

LEAB or LEBA

CLKAB or CLKBA

OEAB or OEBA

1.2

1.1

1.4

t_en

A or B

5.2

4.4

t_dis

(1) This information was not available at the time of publication.

OPERATING CHARACTERISTICS

T_A= 25°C

V_CC= 1.8 V V_CC= 2.5 V V_CC= 3.3 V

PARAMETER

TEST CONDITIONS

UNIT

TYP

(1)

Outputs enabled

C_pdPower dissipation capacitance

C_L= 50 pF, f = 10 MHz

(1)

Outputs disabled

(1) This information was not available at the time of publication.

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

PARAMETER MEASUREMENT INFORMATION

V_CC= 1.8 V

2 × V

Open

1 kΩ

From Output

Under Test

TEST

GND

Open

C = 30 pF

(see Note A)

2 × V

GND

PLZ PZL

1 kΩ

PHZ PZH

LOAD CIRCUIT

Input

V /2

Timing

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Output

Control

(low-level

enabling)

Data

Input

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

Input

+ 0.15 V

S1 at 2 × V

(see Note B)

0 V

PZH

PHZ

PHL

PLH

Output

Waveform 2

S1 at GND

− 0.15 V

V /2

Output

V /2

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time, with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

are the same as t

PZH

are the same as t .

PHL pd

Figure 1. Load Circuit and Voltage Waveforms

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

PARAMETER MEASUREMENT INFORMATION

V_CC= 2.5 V ± 0.2 V

2 × V

Open

GND

500 Ω

From Output

Under Test

TEST

Open

C = 30 pF

(see Note A)

2 × V

GND

PLZ PZL

500 Ω

PHZ PZH

LOAD CIRCUIT

Input

V /2

Timing

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Output

Control

(low-level

enabling)

Data

Input

V /2

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

V /2

Input

V /2

S1 at 2 × V

+ 0.15 V

(see Note B)

0 V

PZH

PHZ

PHL

PLH

Output

Waveform 2

S1 at GND

− 0.15 V

V /2

Output

V /2

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time, with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

are the same as t

PZH

are the same as t .

PHL pd

Figure 2. Load Circuit and Voltage Waveforms

SN74ALVCH16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES027F–JULY 1995–REVISED OCTOBER 2004

PARAMETER MEASUREMENT INFORMATION

V_CC= 2.7 V AND 3.3 V ± 0.3 V

6 V

Open

GND

500 Ω

TEST

From Output

Under Test

Open

6 V

PLZ PZL

C = 50 pF

(see Note A)

500 Ω

GND

PHZ PZH

LOAD CIRCUIT

2.7 V

0 V

Input

1.5 V

2.7 V

Timing

Input

1.5 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

2.7 V

0 V

Data

Input

Output

1.5 V

2.7 V

0 V

Control

(low-level

enabling)

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

S1 at 6 V

3 V

2.7 V

0 V

1.5 V

Input

1.5 V

+ 0.3 V

(see Note B)

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

− 0.3 V

1.5 V

Output

1.5 V

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

are the same as t

PZH

are the same as t .

PHL pd

Figure 3. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2007

PACKAGING INFORMATION

Orderable Device

74ALVCH16601DGGRE4

74ALVCH16601DGGRG4

74ALVCH16601DGVRG4

74ALVCH16601DLG4

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

DGG

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

TVSOP

SSOP

DGG

DGV

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

74ALVCH16601DLRG4

SN74ALVCH16601DGGR

SN74ALVCH16601DGVR

SN74ALVCH16601DL

SN74ALVCH16601DLR

SSOP

1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

TVSOP

SSOP

DGG

DGV

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SSOP

1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

SN74ALVCH16601DGGR TSSOP

SN74ALVCH16601DGVR TVSOP

DGG

DGV

2000

1000

330.0

24.4

32.4

8.6

6.8

15.6

11.7

1.8

1.6

3.1

12.0

16.0

24.0

32.0

SN74ALVCH16601DLR

SSOP

11.35

18.67

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74ALVCH16601DGGR

SN74ALVCH16601DGVR

SN74ALVCH16601DLR

TSSOP

TVSOP

SSOP

DGG

DGV

2000

1000

346.0

41.0

49.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

0,08

0,50

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

0.0135 (0,343)

0.008 (0,203)

0.005 (0,13)

0.010 (0,25)

0.005 (0,13)

0.299 (7,59)

0.291 (7,39)

0.420 (10,67)

0.395 (10,03)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

Seating Plane

0.004 (0,10)

0.008 (0,20) MIN

PINS **

0.110 (2,79) MAX

0.630

DIM

0.380

(9,65)

0.730

A MAX

A MIN

(16,00) (18,54)

0.370

(9,40)

0.620

0.720

(15,75) (18,29)

4040048/E 12/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

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