74CB3Q3125DBQRE4 [TI]
3.3V、1:1 (SPST)、4 通道 FET 总线开关 | DBQ | 16 | -40 to 85;
| 型号： | 74CB3Q3125DBQRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V、1:1 (SPST)、4 通道 FET 总线开关 | DBQ | 16 | -40 to 85 开关 驱动 光电二极管 逻辑集成电路 总线驱动器 总线收发器 |
| 文件： | 总12页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
www.ti.com
SCDS143B–OCTOBER 2003–REVISED MARCH 2005
FEATURES
•
•
Data and Control Inputs Provide Undershoot
Clamp Diodes
(1)
•
High-Bandwidth Data Path (up to 500 MHz
)
Low Power Consumption
(ICC = 0.3 mA Typ)
•
5-V Tolerant I/Os With Device Powered Up or
Powered Down
•
•
VCC Operating Range From 2.3 V to 3.6 V
•
•
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 3 Ω Typ)
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Rail-to-Rail Switching on Data I/O Ports
– 0- to 5-V Switching With 3.3-V VCC
– 0- to 3.3-V Switching With 2.5-V VCC
•
•
•
•
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
•
•
Bidirectional Data Flow With Near-Zero
Propagation Delay
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 4 pF Typ)
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
•
Fast Switching Frequency (fOE = 20 MHz Max)
– 1000-V Charged-Device Model (C101)
•
Supports Both Digital and Analog
Applications: USB Interface, Differential
Signal Interface, Bus Isolation, Low-Distortion
Signal Gating
(1) For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,
literature number SCDA008.
DGV OR PW PACKAGE
(TOP VIEW)
DBQ PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
4OE
4A
4B
3OE
3A
1OE
1A
V
4OE
4A
4B
3OE
3A
NC
1OE
1A
1B
2OE
2A
CC
CC
1
14
1B
2OE
2A
2B
GND
1A
1B
13 4OE
2
3
4
5
6
12
11
10
9
4A
2OE
2A
4B
3OE
3A
8
3B
3B
2B
2B
NC
GND
7
8
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q3125 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3125 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
www.ti.com
SCDS143B–OCTOBER 2003–REVISED MARCH 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74CB3Q3125 is organized as four 1-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE)
inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated 1-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74CB3Q3125RGYR
SN74CB3Q3125DBQR
SN74CB3Q3125PW
TOP-SIDE MARKING
BU125
QFN – RGY
Tape and reel
Tape and reel
Tube
SSOP (QSOP) – DBQ
BU125
–40°C to 85°C
TSSOP – PW
BU125
BU125
Tape and reel
Tape and reel
SN74CB3Q3125PWR
TVSOP – DGV
SN74CB3Q3125DGVR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH BUS SWITCH)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
Z
A port = B port
Disconnect
H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
1
3
5
4
6
1A
1B
3B
SW
2A
2B
4B
SW
SW
1OE
2OE
12
13
11
9
8
3A
4A
SW
10
4OE
3OE
Pin numbers shown are for the DGV, PW, and RGY packages.
2
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
www.ti.com
SCDS143B–OCTOBER 2003–REVISED MARCH 2005
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
B
V
CC
Charge
Pump
(1)
EN
(1) EN is the internal enable signal applied to the switch.
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
7
UNIT
V
VCC
VIN
VI/O
II/K
Supply voltage range
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
V
7
V
VIN < 0
VI/O < 0
–50
–50
±64
±100
90
mA
mA
mA
mA
II/OK
IIO
ON-state switch current(5)
Continuous current through VCC or GND
DBQ package(6)
DGV package(6)
PW package(6)
RGY package(7)
127
113
47
θJA
Package thermal impedance
Storage temperature range
°C/W
°C
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
.
.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
(7) The package thermal impedance is calculated in accordance with JESD 51-5.
3
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
www.ti.com
SCDS143B–OCTOBER 2003–REVISED MARCH 2005
Recommended Operating Conditions(1)
MIN MAX UNIT
VCC
VIH
Supply voltage
2.3
1.7
2
3.6
5.5
5.5
0.7
0.8
5.5
85
V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High-level control input voltage
V
0
VIL
Low-level control input voltage
V
0
VI/O
TA
Data input/output voltage
0
V
Operating free-air temperature
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
MIN
TYP(2) MAX UNIT
VIK
IIN
VCC = 3.6 V,
–1.8
±1
V
Control inputs VCC = 3.6 V,
VIN = 0 to 5.5 V
µA
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
(3)
IOZ
Ioff
VCC = 3.6 V,
±1
1
µA
µA
mA
µA
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
II/O = 0,
Switch ON or OFF,
ICC
VCC = 3.6 V,
VIN = VCC or GND
Other inputs at VCC or GND
0.3
1
(4)
(5)
∆ICC
ICCD
Cin
Control inputs VCC = 3.6 V,
One input at 3 V,
30
VCC = 3.6 V,
A and B ports open,
Per control
input
mA/
MHz
0.04
0.2
Control input switching at 50% duty cycle
Control inputs VCC = 3.3 V,
VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0
2.5
4
3.5
5
pF
pF
Switch OFF,
VIN = VCC or GND,
Cio(OFF)
Cio(ON)
VI/O = 5.5 V, 3.3 V, or 0
VI/O = 5.5 V, 3.3 V, or 0
Switch ON,
VIN = VCC or GND,
VCC = 3.3 V,
VCC = 2.3 V,
8
10
pF
VI = 0,
IO = 30 mA
IO = –15 mA
IO = 30 mA
IO = –15 mA
4
4
4
4
8
9
6
8
TYP at VCC = 2.5 V
VI = 1.7 V,
VI = 0,
(6)
ron
Ω
VCC = 3 V
VI = 2.4 V,
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
4
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
www.ti.com
SCDS143B–OCTOBER 2003–REVISED MARCH 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
(1)
fOE
OE
A or B
OE
A or B
B or A
A or B
A or B
10
0.12
6.7
20
0.2
6.6
5.3
MHz
ns
(2)
tpd
ten
1.5
1
1.5
1
ns
tdis
OE
4.6
ns
(1) Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
TYPICAL r
vs
on
V
I
16
14
12
10
8
V
= 3.3 V
= 25°C
= -15 mA
CC
T
A
I
O
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
V - V
3.0
3.5
4.0
4.5
5.0
I
Figure 1. Typical ron vs VI
TYPICAL I
vs
CC
OE SWITCHING FREQUENCY
12
10
8
V
= 3.3 V
= 25°C
CC
T
A
A and B Ports Open
6
4
2
One OE Switch
16
0
0
2
4
6
8
10
12
14
OE Switching Frequency − MHz
Figure 2. Typical ICC vs OE Switching Frequency
5
SN74CB3Q3125
QUADRUPLE FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
www.ti.com
SCDS143B–OCTOBER 2003–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Input Generator
50 Ω
S1
Open
R
L
V
I
V
O
GND
50 Ω
V
G2
C
L
R
L
(see Note A)
S1
V
I
C
L
V
∆
R
L
V
CC
TEST
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
V
V
or GND
or GND
30 pF
50 pF
CC
t
pd(s)
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PLZ PZL
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
V
V
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PHZ PZH
CC
Output
Control
(V
V
CC
V /2
CC
V /2
CC
)
IN
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
V
CC
V /2
CC
S1 at 2 × V
V + V
∆
OL
V /2
CC
V /2
CC
CC
(V )
IN
(see Note B)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V /2
CC
Output
V /2
CC
V /2
CC
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
en
are the same as t
. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
pd(s)
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2005
PACKAGING INFORMATION
Orderable Device
SN74CB3Q3125DBQR
SN74CB3Q3125DGVR
SN74CB3Q3125PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
16
14
14
14
14
14
14
2500
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TVSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
DGV
PW
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
Pb-Free
(RoHS)
SN74CB3Q3125PWE4
SN74CB3Q3125PWR
SN74CB3Q3125PWRE4
SN74CB3Q3125RGYR
PW
90
Pb-Free
(RoHS)
PW
2000
2000
Pb-Free
(RoHS)
PW
Pb-Free
(RoHS)
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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