74CB3Q3244DGVRG4 [TI]

CB3Q/3VH/3C/2B SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TVSOP-20;


型号：	74CB3Q3244DGVRG4
厂家：	TEXAS INSTRUMENTS
描述：	CB3Q/3VH/3C/2B SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TVSOP-20 驱动光电二极管输出元件逻辑集成电路电视
文件：	总21页 (文件大小：1175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢉ ꢊꢅꢋ ꢌ ꢍ ꢎꢌ ꢅꢏ ꢀ ꢀ ꢐꢋ ꢌꢄ ꢑ

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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

High-Bandwidth Data Path

(Up To 500 MHz )

Data and Control Inputs Provide

Undershoot Clamp Diodes

†

5-V-Tolerant I/Os with Device Powered Up

or Powered Down

Low Power Consumption

= 0.7 mA Typical)

Low and Flat ON-State Resistance (r

)

Operating Range From 2.3 V to 3.6 V

Characteristics Over Operating Range

(r = 4 Ω Typical)

Data I/Os Support 0- to 5-V Signaling

Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,

5 V)

Rail-to-Rail Switching on Data I/O Ports

− 0- to 5-V Switching With 3.3-V V

− 0- to 3.3-V Switching With 2.5-V V

Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

Bidirectional Data Flow, With Near-Zero

Propagation Delay

Supports Partial-Power-Down Mode

off

Operation

Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

= 3.5 pF Typical)

io(OFF)

ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

Fast Switching Frequency

(f = 20 MHz Max)

†

For additional information regarding the performance

characteristics of the CB3Q family, refer to the TI

application report, CBT-C, CB3T, and CB3Q

Signal-Switch Families, literature number SCDA008.

− 1000-V Charged-Device Model (C101)

Supports Both Digital and Analog

Applications: Differential Signal Interface,

Memory Interleaving, Bus Isolation,

Low-Distortion Signal Gating

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

RGY PACKAGE

(TOP VIEW)

1OE

1A1

2B4

1A2

2B3

1A3

2B2

1A4

2B1

GND

19 2OE

18 1B1

1A1

2B4

1A2

2B3

1A3

2B2

1A4

2B1

2OE

1B1

2A4

1B2

2A3

1B3

2A2

1B4

2A4

1B2

2A3

1B3

2A2

1B4

2A1

description/ordering information

The SN74CB3Q3244 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage

of the pass transistor, providing a low and flat ON-state resistance (r ). The low and flat ON-state resistance

allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The

device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data

bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3244 provides an optimized

interface solution ideally suited for broadband communications, networking, and data-intensive computing

systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢤ ꢨ ꢥ ꢤꢝ ꢞꢱ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢒ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈꢃ ꢃ

ꢉꢊ ꢅꢋ ꢌ ꢍ ꢎꢌ ꢅ ꢏ ꢀ ꢀ ꢐꢋ ꢌ ꢄꢑ

ꢈꢒ ꢓꢊꢔ ꢕꢆ ꢒ ꢆ ꢊꢔ ꢖ ꢗꢐꢊꢔ ꢗꢖꢌꢘꢙ ꢎ ꢑꢋ ꢙ ꢑꢊꢅ ꢘꢁꢚ ꢐ ꢋꢚꢌ ꢑ ꢅꢏꢀ ꢀꢐ ꢋ ꢌꢄ ꢑ

SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

description/ordering information (continued)

The SN74CB3Q3244 is organized as two 4-bit bus switches with separate output-enable (1OE, 2OE) inputs.

It can be used as two 4-bit bus switches or as one 8-bit bus switch. When OE is low, the associated 4-bit bus

switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When

OE is high, the associated 4-bit bus switch is OFF, and the high-impedance state exists between the A and B

ports.

This device is fully specified for partial-power-down applications using I . The I circuitry prevents damaging

off

current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

QFN − RGY

Tape and reel

SN74CB3Q3244RGYR

SN74CB3Q3244DW

SN74CB3Q3244DWR

SN74CB3Q3244DBR

SN74CB3Q3244DBQR

SN74CB3Q3244PW

SN74CB3Q3244PWR

SN74CB3Q3244DGVR

SN74CB3Q3244GQNR

BU244

Tube

SOIC − DW

SSOP − DB

CB3Q3244

Tape and reel

BU244

SSOP (QSOP) − DBQ Tape and reel

Tube

CB3Q3244

−40°C to 85°C

TSSOP − PW

BU244

Tape and reel

TVSOP − DGV

VFBGA − GQN

Tape and reel

BU244

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

GQN PACKAGE

(TOP VIEW)

terminal assignments

1A1

1A2

1A3

1A4

GND

1OE

2A4

2B3

2A2

2B1

2OE

1B1

1B2

1B3

1B4

2B4

2A3

2B2

2A1

FUNCTION TABLE

(each 4-bit bus switch)

INPUT INPUT/OUTPUT

FUNCTION

A port = B port

Disconnect

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

logic diagram (positive logic)

1A1

1B1

1A4

1OE

1B4

2A1

2B1

2A4

2OE

2B4

simplified schematic, each FET switch (SW)

Charge

Pump

†

EN is the internal enable signal applied to the switch.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/O

IK IN

I/O port clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/OK I/O

ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA

Continuous current through V

I/O

or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Package thermal impedance, θ (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W

(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W

(see Note 5): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

(see Note 5): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W

(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W

(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. V and V are used to denote specific conditions for V

I/O

4. I and I are used to denote specific conditions for I .

I/O

5. The package thermal impedance is calculated in accordance with JESD 51-7.

6. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 7)

MIN

2.3

1.7

MAX

3.6

5.5

0.7

0.8

5.5

UNIT

Supply voltage

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

High-level control input voltage

Low-level control input voltage

Data input/output voltage

I/O

Operating free-air temperature

−40

°C

NOTE 7: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

−1.8

UNIT

= 3.6 V,

I = −18 mA

Control inputs

= 0 to 5.5 V

µA

= 0 to 5.5 V,

Switch OFF,

‡

= 3.6 V,

= 0,

µA

V = 0,

= V

or GND

V = 0

= 0 to 5.5 V,

= 0,

off

I/O

= 3.6 V,

= V

or GND

0.7

Switch ON or OFF,

∆I

Control inputs

= 3.6 V,

One input at 3 V,

Other inputs at V

or GND

0.15

3.5

A and B ports open,

Control input switching at 50% duty cycle

Per control

input

mA/

MHz

0.14

2.5

CCD

Control inputs

= 3.3 V,

= 5.5 V, 3.3 V, or 0

Switch OFF,

= V

= 3.3 V,

= 5.5 V, 3.3 V, or 0

3.5

io(OFF)

I/O

or GND,

Switch ON,

= V

= 3.3 V,

= 2.3 V,

io(ON)

I/O

V = 0,

= 30 mA

TYP at V

= 2.5 V

V = 1.7 V,

= −15 mA

= 30 mA

= −15 mA

Ω

V = 0,

= 3 V

V = 2.4 V,

†

‡

and I refer to control inputs. V , V , I , and I refer to data pins.

All typical values are at V

= 3.3 V (unless otherwise noted), T = 25°C.

For I/O ports, the parameter I

includes the input leakage current.

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2).

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 3)

= 2.5 V

= 3.3 V

0.2 V

0.3 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN MAX

A or B

B or A

A or B

0.12

7.1

0.2

5.9

5.8

MHz

dis

2.8

2.5

1.5

5.8

Maximum switching frequency for control input (V > V , V = 5 V, R ≥ 1 MΩ, C = 0)

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,

when driven by an ideal voltage source (zero output impedance).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

TYPICAL r

= 3.3 V

= 25°C

= −15 mA

0.0

0.5

1.0

1.5

2.0

2.5

V − V

3.0

3.5

4.0

4.5

5.0

Figure 1. Typical r vs V , V

= 3.3 V and I = −15 mA

TYPICAL I

OE SWITCHING FREQUENCY

= 3.3 V

= 25°C

A and B ports Open

One OE Switching

OE Switching Frequency − MHz

Figure 2. Typical I

vs OE Switching Frequency, V

= 3.3 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004

PARAMETER MEASUREMENT INFORMATION

Input Generator

50 Ω

TEST CIRCUIT

DUT

2 × V

Open

Input Generator

50 Ω

GND

50 Ω

(see Note A)

∆

TEST

2.5 V 0.2 V

3.3 V 0.3 V

Open

500 Ω

or GND

30 pF

50 pF

pd(s)

2.5 V 0.2 V

3.3 V 0.3 V

2 × V

500 Ω

GND

30 pF

50 pF

0.15 V

0.3 V

PLZ PZL

2.5 V 0.2 V

3.3 V 0.3 V

GND

500 Ω

30 pF

50 pF

0.15 V

0.3 V

PHZ PZH

Output

Control

)

0 V

PLZ

PZL

Output

Waveform 1

Output

Control

S1 at 2 × V

(see Note B)

+ V

∆

)

0 V

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at GND

− V

∆

Output

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

)

pd(s)

C includes probe and jig capacitance.

NOTES: A.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

. The tpd propagation delay is the calculated RC time constant of the typical ON-state

pd(s)

resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

Figure 3. Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

25-Jul-2013

PACKAGING INFORMATION

Orderable Device

74CB3Q3244DBQRE4

74CB3Q3244DBQRG4

74CB3Q3244DGVRE4

74CB3Q3244DGVRG4

74CB3Q3244RGYRG4

SN74CB3Q3244DBQR

SN74CB3Q3244DGVR

SN74CB3Q3244PW

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ACTIVE

SSOP

DBQ

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

SNAGCU

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

CB3Q3244

ACTIVE

DBQ

DGV

RGY

DBQ

DGV

2500

2000

3000

2500

2000

Green (RoHS

& no Sb/Br)

CB3Q3244

BU244

CB3Q3244

BU244

TVSOP

VQFN

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SSOP

Green (RoHS

& no Sb/Br)

TVSOP

TSSOP

VQFN

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SN74CB3Q3244PWE4

SN74CB3Q3244PWG4

SN74CB3Q3244PWR

SN74CB3Q3244PWRE4

SN74CB3Q3244PWRG4

SN74CB3Q3244RGYR

SN74CB3Q3244ZQNR

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

3000

1000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

RGY

ZQN

Green (RoHS

& no Sb/Br)

BGA

Green (RoHS

& no Sb/Br)

MICROSTAR

JUNIOR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Jul-2013

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74CB3Q3244DBQR

SSOP

DBQ

DGV

2500

2000

3000

1000

330.0

16.4

12.4

16.4

12.4

6.5

6.9

9.0

5.6

7.1

4.8

4.3

2.1

1.6

8.0

16.0

12.0

16.0

12.0

SN74CB3Q3244DGVR TVSOP

SN74CB3Q3244PWR

SN74CB3Q3244RGYR

TSSOP

VQFN

6.95

3.8

RGY

ZQN

SN74CB3Q3244ZQNR BGA MI

3.3

CROSTA

R JUNI

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74CB3Q3244DBQR

SN74CB3Q3244DGVR

SN74CB3Q3244PWR

SN74CB3Q3244RGYR

SSOP

TVSOP

TSSOP

VQFN

DBQ

DGV

2500

2000

3000

1000

367.0

338.1

367.0

338.1

38.0

35.0

38.0

35.0

20.6

RGY

ZQN

SN74CB3Q3244ZQNR BGA MICROSTAR

JUNIOR

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

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