74F299SC [TI]
F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, 0.300 INCH, PLASTIC, SOIC-20;
| 型号： | 74F299SC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, 0.300 INCH, PLASTIC, SOIC-20 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54F299,74F299
54F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins
Literature Number: SNOS185A
May 1995
54F/74F299 Octal Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The ’F299 is an 8-bit universal shift/storage register with
Features
Y
Common parallel I/O for reduced pin count
Y
TRI-STATE outputs. Four modes of operation are possi-
Additional serial inputs and outputs for expansion
Four operating modes: shift left, shift right, load and
store
É
Y
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to re-
duce the total number of package pins. Additional outputs,
Y
Y
TRI-STATE outputs for bus-oriented applications
Guaranteed 4000V minimum ESD protection
Q –Q , are provided to allow easy serial cascading. A sep-
0
7
arate active LOW Master Reset is used to reset the register.
Package
Commercial
74F299PC
Military
Package Detion
Number
N20A
J20A
20-Lead (0.300 Wide) Molded DuIn-Line
×
54F299DM (Note 2)
20-Lead Ceramic Du
74F299SC (Note 1)
74F299SJ (Note 1)
M20B
M20D
W20A
E20A
20-Lead (0.300 d Small Outline, JEDEC
×
20-Lea0.300 Wolded Sll Outline, EIAJ
×
54F299FM (Note 2)
54F299LM (Note 2)
20-Lead Cack
20-Lead CeramLeadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Us
QB and LMQB.
Logic Symbols
IEEE/IEC
TL/F/9515–1
TL/F/9515–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9515
RRD-B30M75/Printed in U. S. A.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9515–3
TL/F/9515–2
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I
HIGH/LOW
20 mA
20 m
20 mAmA
0 mA/ 2 mA
CP
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
1.0/1.0
1.0/1.0
DS
DS
0
7
1.0/1.0
S , S
0
1.0/2.0
1
b
2A/ 0.
b
20 m0.6 mA
MR
Asynchronous Master Reset Input (Active LOW)
TRI-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
1.0/1.0
OE , OE
1
1.0/1.0
2
I/O –I/O
0
3.5/1
150/
50
0 mA/ .65 mA
7
TRI-STATE Parallel Outputs
Serial Outputs
A/24 mA (20 mA)
Q , Q
0
mA/20 mA
7
Functional Description
The ’F299 contains eight edge-triggered D-type flip-flo
and the interstage logic necessary to perform synchrono
shift left, shift right, parallel load and hold operations. The
H signal on either OE or OE disables the TRI-
1 2
STATbuffers and puts the I/O pins in the high impedance
state. this condition the shift, hold, load and reset opera-
tioncan still occur. The TRI-STATE outputs are also dis-
type of operation is determined by S and S , in
1
the Mode Select Table. All flip-flop outs a
through TRI-STATE buffers to separate
serve as data inputs in the parallel load m
are also brought out on or expan
shifting of longer words
bled by HIGH signals on both S and S in preparation for
0 1
a parallel load operation.
Mode Select Table
Inputs
MR S
Response
A LOW signal on MR and CP puts
and resets the flip-flos are initiated
by the rising edge of tnge when the
clock is in either state ecommended
setup and hold times, redge of CP, are
observed.
S
CP
1
0
e
LOW
L
H
H
H
H
X
X
X
Asynchronous Reset; Q –Q
7
H
H
H
L
L Parallel Load; I/On x0
Q
n
L
H
L
L Shift Right; DS0 x Q , Q0 x Q , etc.
0
1
L Shift Left; DS7 x Q , Q7 x Q , etc.
7
6
L
X
Hold
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
L
LOW-to-HIGH Clock Transition
2
Logic Diagram
TL/F/9515–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage Applied to Output
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
b
b
a
65 C to 150 C
Storage Temperature
§
§
Current Applied to Output
in LOW State (Max)
a
55 C to 125 C
Ambient Temperature under Bias
§
§
§
§
§
§
twice the rated I (mA)
OL
b
b
a
55 C to 175 C
Junction Temperature under Bias
Plastic
a
55 C to 150 C
Recommended Operating
Conditions
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Free Air Ambient Temperature
Military
Commercial
Input Voltage (Note 2)
b
a
55 C to 125 C
§
0 C to 70 C
§
b
a
Input Current (Note 2)
30 mA to 5.0 mA
4000V
a
§
§
ESD Last Passing Voltage (Min)
Supply Voltage
Military
Commercial
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
a
a
a
4.5V to 5.5V
a
4.5V to 5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Codition
Min Typ Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HISignal
Recognia LOW nal
IH
Input LOW Voltage
0.8
IL
b
e
Input Clamp Diode Voltage
1.2
Min
Min
I
CD
OH
IN
e
e b
e b
b
Output HIGH
Voltage
54F 10% V
2.5
2.4
2.5
2.4
2.7
2.7
I
I
I
I
I
A (Q , , I/O )
0 7 n
CC
CC
CC
CC
OH
OH
OH
O
OH
54F 10% V
74F 10% V
74F 10% V
mA (I/O
1 mA (Q Q , I/O )
7
n
V
3 /O )
n
74F 5% V
74F 5% V
1 mA (Q , Q , I/O )
0 7 n
3 mA (I/O )
CC
CC
n
e
e
e
V
OL
Output LOW
Voltage
54 10% V
74 10% V
74 10% V
0.5
0.5
0.5
20 mA
20 mA (Q , Q )
24 mA (I/O )
CC
CC
CC
L
L
OL
0
7
n
e
e
e
I
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
V
2.7V (CP, DS , DS , S , S ,
0 7 0 1
MR, OE , OE )
IH
IN
IN
IN
mA
mA
mA
V
x
Max
Max
Max
0.0
1
2
Input HIGH Current
Breakdown Test
54F
74F
0
7.0
7.0V (CP, DS , DS , S , S ,
0 7 0 1
MR, OE , OE )
BVI
1
2
Input HIGH Current 54F
Breakdown Test (I/O) 74F
0
0.5
5.5V (I/O )
n
BVIT
CEX
e
V
CC
Output HIGH
Leakage Current
54F
250
50
OUT
e
All Other Pins Grounded
V
Input Leakage
Test
I
ID
1.9 mA
ID
OD
IL
4.
e
All Other Pins Grounded
I
I
Output Leak
Circuit Curren
V
150 mV
IOD
3.75
mA
mA
mA
mA
0.0
b
b
e
e
Input LOW Cur
0.6
1.2
V
V
0.5V (CP, DS , DS , MR, OE , OE )
0 7 1 2
0.5V (S , S )
IN
IN
Max
Max
Max
0
1
a
e
I
I
Output Leakage Current
Output Leakage Current
V
2.7V (I/O )
n
IH
I/O
70
OZH
a
e
I
I
V
0.5V (I/O )
n
IL
I/O
b
b
650
150
OZL
b
e
0V
I
I
I
I
I
Output Short-Circuit Current
Bus Drainage Test
60
mA
mA
mA
mA
mA
Max
0.0V
Max
Max
Max
V
V
V
V
V
OS
OUT
e
500
5.25V
ZZ
OUT
e
Power Supply Current
Power Supply Current
Power Supply Current
68
68
68
95
95
95
HIGH
LOW
CCH
CCL
CCZ
O
e
O
e
HIGH Z
O
4
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Input Frequency
Propagation Delay
70
100
85
70
MHz
ns
max
t
t
4.0
4.5
7.0
6.5
8.0
8.0
4.0
4.5
9.0
9.5
4.0
4.5
8.5
8.5
PLH
CP to Q or Q
0
PHL
7
t
t
Propagation Delay
CP to I/O
3.5
4.0
7.0
8.5
9.0
9.0
3.5
4.0
10.0
11.0
3.5
4.0
10.0
10.0
PLH
PHL
n
t
Propagation Delay
MR to Q or Q
PHL
5.5
5.5
7.5
9.5
5.5
5.5
12.5
12.0
5.5
5.5
10.5
5
0
7
ns
ns
t
Propagation Delay
MR to I/O
PHL
11.0
10.0
n
t
t
Output Enable Time
OE to I/O
3.5
4.0
6.0
7.0
8.0
3.0
4.0
9.5
4
9.0
PZH
10.0
10
11.0
PZL
n
t
t
Output Disable Time
OE to I/O
2.0
1.0
4.5
4.0
6.0
5.5
1.5
1.0
7.
6.5
2.0
1.0
7.
6.5
PHZ
PLZ
n
t
t
Output Enable Time
to I/O
3.5
4.0
9.0
3.0
4.0
4.0
10.0
11.0
PZH
ns
ns
S
n
10.0
PZL
n
t
t
Output Disable Time
to I/O
2.5
1.5
6.
5.5
1.
1.0
7.0
6.5
2.5
1.5
7.0
6.5
PHZ
S
n
PLZ
n
AC Operating Requirements
74F
54F
74F
e a
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
C
Mil
Max
T
, V
A CC
Com
Max
Units
V
CC
Min
Max
Min
t (H)
s
Setup Time, HIGH or LOW
8.
8.
10.0
7.5
8.5
8.5
t (L)
s
S or S to CP
0 1
ns
t (H)
h
Hold Time, HIGH or LOW
S or S to CP
0
0
0
0
0
0
t (L)
h
1
t (H)
s
Setup Time, HIGH o
I/O , DS DS to CP
5.0
5.0
5.0
5.0
t (L)
s
n
7
ns
ns
t (H)
h
HLOW
2.0
2.0
2.0
2.0
2.0
t (L)
h
t
t
(H)
(L)
5.0
5.0
5.0
5.0
5.0
5.0
w
w
t
t
(L)
M
5.0
7.0
6.0
5.0
7.0
ns
ns
w
RecovR to CP
12.0
rec
5
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 299
S
C
X
Temperature Range Family
Special Variations
e
e
e
74F
54F
Commercial
Military
QB
Military grade device with
environmental and burn-in
processing
Device Type
e
X
Devices shipped in 13 reel
×
Package Code
Temperature Range
e
e
e
e
e
e
P
D
S
SJ
F
L
Plastic DIP
Ceramic DIP
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
Flatpak
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
Leadless Chip Carrier (LCC)
Physical Dimensions inches (millimeters)
-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Linackage
NS Package Number J2
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
7
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Small Outline Page, EIA
×
NS Package Number MD20D
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
8
9
Physical Dimensions inches (millimeters) (Continued)
20-Lead Cerpack
NS Package Number W20A
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DEVICES OR THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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be reasonably expected to cause the failure of the life
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