74FCT162652ETPVCT [TI]
16-Bit Registered Transceivers; 16位寄存收发器
| 型号： | 74FCT162652ETPVCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Registered Transceivers |
| 文件： | 总10页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY74FCT162652T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16652T
CY74FCT162652T
SCCS061 - July 1994 - Revised March 2000
16-Bit Registered Transceivers
Features
Functional Description
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
These 16-bit, high-speed, low-power, registered transceivers
that are organized as two independent 8-bit bus transceivers
with three-state D-type registers and control circuitry arranged
for multiplexed transmission of data directly from the input bus
or from the internal storage registers. OEAB and OEBA control
pins are provided to control the transceiver functions. SAB and
SBA control pins are provided to select either real-time or
stored data transfer.
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CLKAB or CLKBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration, each output reinforces
its input. Thus, when all other data sources to the two sets of
bus lines are at high impedance, each set of bus lines will
remain at its last state. The output buffers are designed with a
power-off disable feature that allows live insertion of boards.
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16652T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
CY74FCT162652T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
The CY74FCT16652T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162652T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.
Logic Block Diagrams
OEAB
1
OEAB
2
OEBA
1
OEBA
2
CLKBA
1
1
CLKBA
2
SBA
2
SBA
1
CLKAB
CLKAB
2
SAB
2
SAB
1
B REG
D
B REG
D
C
C
A
1
2
A
1
1
A REG
A REG
D
C
D
C
B
B
1
1
1
2
TO 7 OTHER CHANNELS
FCT16652-1
FCT16652-2
TO 7 OTHER CHANNELS
Copyright © 2000, Texas Instruments Incorporated
CY74FCT16652T
CY74FCT162652T
Pin Configuration
SSOP/TSSOP
Top View
OEAB
OEBA
1
1
2
56
55
1
CLKBA
CLKAB
1
1
SAB
1
SBA
3
4
54
53
1
GND
A
GND
B
B
5
6
7
52
51
50
1
1
1
2
1
1
1
2
A
V
CC
V
CC
A
3
B
3
1
1
1
8
9
49
48
1
1
1
A
4
B
4
A
B
5
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
GND
GND
A
A
A
B
B
B
B
B
B
1
1
1
6
7
8
1
1
1
2
2
2
6
7
8
1
2
3
A
A
2
2
1
2
A
3
2
GND
GND
B
B
B
A
2
2
2
4
5
6
2
4
A
A
2
2
5
6
V
2
V
CC
CC
B
7
A
2
2
7
8
A
B
8
2
24
25
26
33
32
31
30
29
GND
SBA
GND
SAB
2
2
CLKAB
OEAB
27
28
CLKBA
OEBA
2
2
2
2
FCT16652-3
Pin Description
Name
Description
A
Data Register A Inputs
Data Register B Outputs
B
Data Register B Inputs
Data Register A Outputs
CLKAB, CLKBA
SAB, SBA
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
OEAB, OEBA
2
CY74FCT16652T
CY74FCT162652T
Function Table[1]
Inputs
Data I/O[2]
OEAB
OEBA
CLKAB CLKBA
SAB
SBA
A
B
Operation or Function
L
L
H
H
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
X
H
H
H
H or L
X
X
X
Input
Input
Unspecified[2] Store A, Hold B
X[3]
Output
Store A in Both Registers
L
L
X
L
H or L
X
X
X
X
Unspecified[2]
Input
Input
Hold A, Store B
Store B in both Registers
X[3]
L
L
X
X
L
Output
Input
Output
Output
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
X
X
H or L
X
X
L
H
X
H
H
Input
Real Time A Data to B Bus
Stored A Data to B Bus
H
H
H
L
H or L
H or L
X
H
H
X
H
H or L
Output
Stored A Data to B Bus and
Stored B Data to A Bus
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
=LOW-to-HIGH Transition
2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
3. Select control=L; clocks can occur simultaneously.
Select control=H; clocks must be staggered to load both registers.
3
CY74FCT16652T
CY74FCT162652T
BUS A
BUS B
BUS A
BUS B
OEAB
L
OEBA
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
OEAB
H
OEBA
L
CLKAB
X
CLKBA
X
SAB
L
SBA
X
Real-Time Transfer
BusB to BusA
Real-Time Transfer
BusA to BusB
BUS A
BUS B
BUS A
BUS A
OEAB
OEBA
SAB
SBA
X
X
OEAB
H
OEBA
L
SAB
H
SBA
H
CLKAB
X
CLKBA
X
CLKAB
H or L
CLKBA
H or L
X
L
L
H
X
H
X
X
X
X
Storage from
A and/or B
Transfer Stored Data
to A and/or B
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .....................Com’l −55°C to +125°C
Ambient Temperature with
Power Applied.................................Com’l −55°C to +125°C
Operating Range
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
Ambient
Range
Industrial
Temperature
VCC
−40°C to +85°C
5V ± 10%
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
Note:
4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
CY74FCT16652T
CY74FCT162652T
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Input Hysteresis
Test Conditions[5]
Min.
Typ.[6]
Max.
Unit
V
VIH
VIL
VH
VIK
IIH
Logic HIGH Level
2.0
Logic LOW Level
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
VCC=Min., IIN=−18 mA
VCC=Max., VI=VCC
−0.7
−1.2
±1
µA
µA
µA
IIL
VCC=Max., VI=GND
VCC=Max., VOUT=2.7V
±1
IOZH
High Impedance Output
Current
±1
(Three-State Output pins)
IOZL
High Impedance Output
Current
VCC=Max., VOUT=0.5V
±1
µA
(Three-State Output pins)
IOS
IO
Short Circuit Current[8]
Output Drive Current[8]
Power-Off Disable
VCC=Max., VOUT=GND
VCC=Max., VOUT=2.5V
VCC=0V, VOUT≤4.5V[7]
−80
−50
−140
−200
−180
±1
mA
mA
µA
IOFF
Output Drive Characteristics for CY74FCT16652T
Parameter
Description
Test Conditions[5]
Min.
2.5
Typ.[6]
3.5
Max.
Unit
VOH
Output HIGH Voltage
VCC=Min., IOH=−3 mA
V
VCC=Min., IOH=−15 mA
VCC=Min., IOH=−32 mA
VCC=Min., IOL=64 mA
2.4
3.5
2.0
3.0
VOL
Output LOW Voltage
0.2
0.55
V
Output Drive Characteristics for CY74FCT162652T
Parameter
IODL
Description
Output LOW Current[8]
Output HIGH Current[8]
Output HIGH Voltage
Output LOW Voltage
Test Conditions[5]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
VCC=Min., IOH=−24 mA
Min.
60
Typ.[6]
115
Max.
150
Unit
mA
mA
V
IODH
−60
2.4
−115
3.3
−150
VOH
VOL
VCC=Min., IOL=24 mA
0.3
0.55
V
Capacitance (TA = +25˚C, f = 1.0 MHz)
Parameter
Description[10]
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V
Typ.
4.5
Max.
6.0
Unit
pF
CIN
COUT
VOUT = 0V
5.5
8.0
pF
Notes:
5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
6. Typical values are at VCC=5.0V, +25°C ambient.
7. Tested at TA= +25°C.
8. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
9. Duration of the condition cannot exceed one second.
10. This parameter is measured at characterization but not tested.
5
CY74FCT16652T
CY74FCT162652T
Power Supply Characteristics
Param.
Description
Test Conditions[11]
VIN<0.2V
Min. Typ.[12]
Max.
Unit
ICC
Quiescent Power Supply
Current
VCC=Max.
—
5
500
µA
VIN>VCC−0.2V
∆ICC
Quiescent Power Supply
Current
VCC = Max. VIN=3.4V[13]
—
0.5
1.5
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply
Current[14]
VCC=Max.
Outputs Open
VIN=VCC or
VIN=GND
—
75
120
µA/
MHz
OEAB=OEAB=GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current[15] VCC=Max.
Outputs Open
VIN=VCC or
VIN=GND
—
—
0.8
1.3
1.7
3.2
mA
mA
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
One-Bit Toggling
f1=5 MHz
VIN=3.4V or
VIN=GND
50% Duty Cycle
VCC=Max.
Outputs Open
VIN=VCC or
VIN=GND
—
—
3.8
8.3
6.5[16]
mA
mA
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
Sixteen Bits Toggling
f1=2.5 MHz
VIN=3.4V or
VIN=GND
20.0[16]
50% Duty Cycle
Notes:
11. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
12. Typical values are at VCC=5.0V +25° ambient.
13. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
15. IC
IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
f1
N1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
16. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
6
CY74FCT16652T
CY74FCT162652T
Switching Characteristics Over the Operating Range[17]
CY74FCT16652AT
CY74FCT162652AT
Parameter
tPLH
Description
Min.
Max.
Unit
Fig. No.[18]
Propagation Delay Bus to Bus
1.5
6.3
ns
1, 3
tPHL
tPZH
tPHL
Output Enable Time OEAB or OEBA to Bus
Output Disable Time OEAB or OEBA to Bus
Propagation Delay Clock to Bus
1.5
1.5
1.5
1.5
9.8
6.3
6.3
7.7
ns
ns
ns
ns
1, 7, 8
1, 7, 8
1, 5
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
Propagation Delay SBA or SAB to Bus
1, 5
tSU
tH
Set-Up time HIGH or LOW Bus to Clock
Hold Time HIGH or LOW Bus to Clock
Clock Pulse Width HIGH or LOW
Output Skew[19]
2.0
1.5
5.0
—
—
—
ns
ns
ns
ns
4
4
5
tW
—
tSK(O)
0.5
CY74FCT16652CT
CY74FCT162652CT
CY74FCT16652ET
CY74FCT162652ET
Parameter
tPLH
Description
Min.
Max.
Min.
Max.
Unit
Fig. No.[18]
Propagation Delay
Bus to Bus
1.5
5.4
1.5
3.8
ns
ns
ns
ns
ns
ns
1, 3
tPHL
tPZH
Output Enable Time
OEAB or OEBA to Bus
1.5
1.5
1.5
1.5
2.0
7.8
6.3
5.7
6.2
—
1.5
1.5
1.5
1.5
2.0
4.8
4.0
3.8
4.2
—
1, 7, 8
1, 7, 8
1, 5
tPHL
tPHZ
Output Disable Time
OEAB or OEBA to Bus
tPLZ
tPLH
Propagation Delay
Clock to Bus
tPHL
tPLH
Propagation Delay
SBA or SAB to Bus
1, 5
tPHL
tSU
Set-Up Time
HIGH or LOW
Bus to Clock
4
tH
Hold Time
HIGH or LOW
Bus to Clock
1.5
—
0.0
—
ns
4
5
tW
Clock Pulse Width
HIGH or LOW
5.0
—
—
3.0
—
—
ns
ns
tSK(O)
Output Skew[19]
0.5
0.5
Notes:
17. Minimum limits are specified, but not tested, on propagation delays.
18. See “Parameter Measurement Information” in the General Information section.
19. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
7
CY74FCT16652T
CY74FCT162652T
Ordering Information CY74FCT16652
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
56-Lead (240-Mil) TSSOP
3.8
CY74FCT16652ETPACT
Z56
O56
O56
O56
Industrial
CY74FCT16652ETPVC/PVCT
CY74FCT16652CTPVC/PVCT
CY74FCT16652ATPVC/PVCT
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
5.4
6.3
Industrial
Industrial
Ordering Information CY74FCT162652
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
74FCT162652ETPACT
CY74FCT162652ETPVC
74FCT162652ETPVCT
74FCT162652CTPACT
CY74FCT162652CTPVC
74FCT162652CTPVCT
CY74FCT162652ATPVC
74FCT162652ATPVCT
Package Type
3.8
Z56
O56
O56
Z56
O56
O56
O56
O56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
Industrial
Industrial
Industrial
5.4
6.3
8
CY74FCT16652T
CY74FCT162652T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
9
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Copyright 2000, Texas Instruments Incorporated
相关型号：
74FCT162827BTPVCG4
FCT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, 0.635 MM PITCH, PLASTIC, SSOP-56
TI
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