74LV8T245QWRKSRQ1 [TI]

Automotive single-supply octal-translating transceiver with tri-state outputs

| RKS | 20 | -40 to 125;


型号：	74LV8T245QWRKSRQ1
厂家：	TEXAS INSTRUMENTS
描述：	Automotive single-supply octal-translating transceiver with tri-state outputs \| RKS \| 20 \| -40 to 125
文件：	总22页 (文件大小：1099K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LV8T245-Q1

ZHCSQX7A –DECEMBER 2022 –REVISED APRIL 2023

SN74LV8T245-Q1 具有三态输出和逻辑电平转换器的汽车类1.65V 至5V、八路

总线收发器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

SN74LV8T245-Q1 是一款具有三态输出的八路总线收

发器。所有八个通道均由方向 (DIR) 引脚和输出使能

(OE) 引脚控制。输出电平以电源电压 (V_CC) 为基准，

并且支持1.8V、2.5V、3.3V 和5V CMOS 电平。

– 器件温度等级1：

–40°C 至+125°C，T_A

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C6

• 1.8V 至5.5V 的宽工作电压范围

• 采用具有可湿性侧面的QFN (WRKS) 封装

• 单电源电压转换器（参阅LVxT 增强输入电压）：

该输入经设计，具有较低阈值电路，支持较低电压

CMOS 输入的上行转换（例如 1.2V 输入转换为 1.8V

输出或 1.8V 输入转换为 3.3V 输出）。此外，5V 容限

输入引脚可实现下行转换（例如 3.3V 至 2.5V 输

出）。

– 上行转换：

封装信息⁽¹⁾

• 1.2V 至1.8V

• 1.5V 至2.5V

• 1.8V 至3.3V

• 3.3V 至5.0V

– 下行转换：

器件型号

封装

封装尺寸（标称值）

RKS（VQFN，20） 4.50mm × 2.50mm

DGS（VSSOP，

20）

5.10mm × 3.00mm

SN74LV8T245-Q1

PW（TSSOP，20） 6.50mm × 4.40mm

• 5.0V、3.3V、2.5V 至1.8V

• 5.0V、3.3V 至2.5V

• 5.0 V 至3.3 V

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 5.5V 容限输入引脚

• 支持标准引脚排列

• 速率高达150 Mbps，具有5V 或3.3V V_CC

• 闩锁性能超过250mA，符合

JESD 17 规范

2 应用

• 启用或禁用数字信号

• 消除缓慢或嘈杂输入信号

• 在控制器复位期间保持信号

• 对开关进行去抖

Shared Control Logic

DIR

One of Eight Transceiver Channels

简化逻辑图（正逻辑）

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCLS908

SN74LV8T245-Q1

ZHCSQX7A –DECEMBER 2022 –REVISED APRIL 2023

www.ti.com.cn

Table of Contents

8.3 Feature Description...................................................11

8.4 Device Functional Modes..........................................14

9 Application and Implementation..................................15

9.1 Application Information............................................. 15

9.2 Typical Application.................................................... 15

9.3 Design Requirements............................................... 15

9.4 Application Curves....................................................17

10 Power Supply Recommendations..............................17

11 Layout...........................................................................18

11.1 Layout Guidelines................................................... 18

11.2 Layout Example...................................................... 18

12 Device and Documentation Support..........................19

12.1 Documentation Support.......................................... 19

12.2 接收文档更新通知................................................... 19

12.3 支持资源..................................................................19

12.4 Trademarks.............................................................19

12.5 静电放电警告.......................................................... 19

12.6 术语表..................................................................... 19

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics - 1.8-V V_CC........................6

6.7 Switching Characteristics - 2.5-V V_CC........................7

6.8 Switching Characteristics - 3.3-V V_CC........................7

6.9 Switching Characteristics - 5-V V_CC...........................7

6.10 Noise Characteristics................................................7

6.11 Typical Characteristics.............................................. 8

7 Parameter Measurement Information..........................10

8 Detailed Description......................................................11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram......................................... 11

Information.................................................................... 19

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (December 2022) to Revision A (April 2023)

Page

• 将数据表的状态从预告信息更改为量产数据 .....................................................................................................1

English Data Sheet: SCLS908

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5 Pin Configuration and Functions

DIR VCC

DIR

V_CC

PAD

14 B5

GND

12 B7

图5-2. DGS or PW Package, 20-Pin VSSOP or

TSSOP (Top View)

GND

图5-1. RKS Package, 20-Pin VQFN (Transparent

Top View)

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

DIR

Direction control input (L = B →A, H = A →B)

I/O

Channel 1 output/input A

Channel 2 output/input A

Channel 3 output/input A

Channel 4 output/input A

Channel 5 output/input A

Channel 6 output/input A

Channel 7 output/input A

Channel 8 output/input A

Ground

GND

I/O

Channel 8 input/output B

Channel 7 input/output B

Channel 6 input/output B

Channel 5 input/output B

Channel 4 input/output B

Channel 3 input/output B

Channel 2 input/output B

Channel 1 input/output B

Output enable, active low

Positive supply

V_CC

The thermal pad can be connected to GND or left floating. Do not connect to any other

signal or supply.

Thermal Pad⁽²⁾

—

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power

(2) RKS package only

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English Data Sheet: SCLS908

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.5

MAX

UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾

V_CC+ 0.5

4.6

V_O

Voltage range applied to any output in the high-impedance or power-off state⁽²⁾

I_IK

I_OK

I_O

Input clamp current

V_I< -0.5 V

-20

°C

Output clamp current

Continuous output current

V_O< -0.5 V or V_O> V_{CC +}0.5 V

V_O= 0 to V_CC

±20

±25

Continuous output current through V_CCor GND

Storage temperature

±50

T_stg

-65

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,

performance, and shorten the device lifetime.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2⁽¹⁾

±4000

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level

C4B

±2000

(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

English Data Sheet: SCLS908

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

Spec

Description

Condition

MIN

1.6

MAX

5.5

UNIT

V_CC

V_I

Supply voltage

Input Voltage

5.5

V_O

Output Voltage

V_CC

V_CC= 1.65 V to 2 V

1.1

1.28

1.45

V_CC= 2.25 V to 2.75 V

V_CC= 3 V to 3.6 V

V_IH

High-level input voltage

V_CC= 4.5 V to 5.5 V

V_CC= 1.65 V to 2 V

V_CC= 2.25 V to 2.75 V

V_CC= 3 V to 3.6 V

0.51

0.65

0.75

0.80

±3

V_IL

Low-Level input voltage

Output Current

V_CC= 4.5 V to 5.5 V

V_CC= 1.65 V to 2.0 V

V_CC= 2.25 V to 2.75 V

V_CC= 3.3 V to 5.0 V

V_CC= 1.6 V to 5.5 V

I_O

±7

±15

Input transition rise or fall rate

Operating free-air temperature

ns/V

°C

Δt/Δv

T_A

125

–40

(1) All unused inputs of the device must be held at V_CCor GND for proper device operation. Refer to the TI application report, Implications

of Slow or FLoating CMOS Inputs.

6.4 Thermal Information

SN74LV8T245-Q1

THERMAL METRIC⁽¹⁾

RKS (VQFN)

20 PINS

67.7

DGS (VSSOP)

20 PINS

118.4

PW (TSSOP)

20 PINS

122.3

64.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

72.4

57.7

R_θJB

Ψ_JT

Y_JB

Junction-to-board thermal resistance

40.4

73.1

73.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

10.3

5.7

19.0

40.4

72.7

73.0

R_θJC(bot)Junction-to-case (bottom) thermal resistance

24.1

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

T_A= 25°C

-40°C to 125°C

PARAMETER

TEST CONDITIONS

V_CC

UNIT

MAX

MIN

TYP

MAX

MIN

V_CC-0.1

1.21

TYP

I_OH= -50 µA

1.65 V to 5.5 V

1.65 V

V_CC-0.1

1.28

I_OH= -2 mA

I_OH= -3 mA

I_OH= -5.5 mA

I_OH= -8 mA

I_OL= 50 µA

1.6⁽¹⁾

2.3⁽¹⁾

V_OH

2.25 V

1.93

3.0 V

2.6 3.08⁽¹⁾

4.1 4.65⁽¹⁾

2.49

4.5 V

3.95

1.65 V to 5.5 V

1.65 V

0.1

0.2

0.17

0.23

0.3

0.1

I_OL= 2 mA

0.15⁽¹⁾

0.20⁽¹⁾

0.30⁽¹⁾

0.25

V_OL

I_OL= 3 mA

2.25 V

0.2

0.25

0.35

I_OL= 5.5 mA

I_OH= 8 mA

3.0 V

4.5 V

I_CC

V_I= V_CCor GND, I_O= 0

1.65 V to 5.5 V

µA

One input at 0.3 V or 3.4 V,

other inputs at V_CCor GND

5.5 V

1.8 V

1.35

1.5

Δ_ICC

One input at 0.3 V or 1.1 V,

other inputs at V_CCor GND

µA

I_I

V_I= 0 V to V_CC

5.5 V

±0.1

±0.25

±1

±2.5

µA

I_OZ

C_i

V_O= V_CCor GND

V_I= V_CCor GND

Vo = V_CCor GND

CL = 50 pF, F = 10 MHz

3.3 V

C_O

3.3 V

(2) (3)

C_PD

1.65 V to 5.5 V

(1) Typical value at nearest nominal voltage (1.8 V; 2.5 V; 3.3 V; 5 V)

(2) C_PDis used to determine the dynamic power consumption, per channel

(3) P_D= V_CC²xF_Ix(C_PD+ C_L) where F_I= input frequency, C_L= output load capacitance, V_CC= supply voltage

6.6 Switching Characteristics - 1.8-V V_CC

over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information

T_A= 25°C

-40°C to 125°C

PARAME

TER

LOAD

CAPACITANCE

FROM (INPUT)

TO (OUTPUT)

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

25.1

32.6

t_Pd

t_en

A or B

B or A

C_L= 15 pF

C_L= 50 pF

11.8

A or B

B or A

A or B

16.4

27.2

24.8

t_dis

t_Pd

t_en

16.4

A or B

15.6

19.5

30.9

31.4

2.5

t_dis

t_sk(o)

24.1

36.6

2.5

English Data Sheet: SCLS908

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6.7 Switching Characteristics - 2.5-V V_CC

over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information

T_A= 25°C

-40°C to 125°C

PARAME

TER

LOAD

CAPACITANCE

FROM (INPUT)

TO (OUTPUT)

UNIT

MIN

TYP

MAX

13.5

20.4

18.6

16.4

23.2

23.6

MIN TYP

MAX

17.5

24.5

22.5

21.5

28.5

27.5

t_Pd

t_en

A or B

B or A

C_L= 15 pF

C_L= 50 pF

8.8

A or B

B or A

A or B

12.3

t_dis

t_Pd

t_en

12.3

A or B

11.7

14.6

t_dis

t_sk(o)

18.1

6.8 Switching Characteristics - 3.3-V V_CC

over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information

T_A= 25°C

TYP

6.4

-40°C to 125°C

PARAME

TER

LOAD

CAPACITANCE

FROM (INPUT)

TO (OUTPUT)

UNIT

MIN

MAX

8.9

MIN TYP

MAX

11.5

t_Pd

t_en

A or B

B or A

C_L= 15 pF

C_L= 50 pF

A or B

B or A

A or B

13.7

t_dis

t_Pd

t_en

10.1

8.8

A or B

12.4

17.2

20.3

1.5

11.5

14.4

20.5

23.5

1.5

t_dis

t_sk(o)

6.9 Switching Characteristics - 5-V V_CC

over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information

T_A= 25°C

TYP

4.5

-40°C to 125°C

PARAME

TER

LOAD

CAPACITANCE

FROM (INPUT)

TO (OUTPUT)

UNIT

MIN

MAX

7.7

MIN TYP

MAX

t_Pd

t_en

A or B

B or A

C_L= 15 pF

C_L= 50 pF

A or B

B or A

A or B

8.9

13.8

14.4

8.7

t_dis

t_Pd

t_en

9.2

16.5

A or B

5.3

9.7

14.8

15.4

t_dis

t_sk(o)

17.5

6.10 Noise Characteristics

V_CC= 5 V, C_L= 50 pF, T_A= 25°C⁽¹⁾

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

V_OL(P)

Quiet output, maximum dynamic V_OL

Quiet output, minimum dynamic V_OL

Quiet output, minimum dynamic V_OH

High-level dynamic input voltage

Low-level dynamic input voltage

V_OL(V)

V_OH(V)

V_IH(D)

V_IL(D)

-0.6

0.8

(1) Characteristics are for surface-mount packages only

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6.11 Typical Characteristics

100

700

630

560

490

420

350

280

210

140

25°C

125°C

25°C

125°C

-40°C

0.5

1.5

2.5

3.5

4.5

5.5

0.5

1.5

2.5

V_IN(V)

3.5

4.5

V_CC(V)

图6-1. Supply Current Across Operating Voltage

图6-2. Supply Current Across Input Voltage, 5-V Supply

250

16.5

16.25

25°C

125°C

-40°C

225

200

175

150

125

100

15.75

15.5

15.25

14.75

14.5

1.8 V

3.3 V

5 V

14.25

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

V_IN(V)

3.3

图6-4. Power Dissipation Capacitance per Gate Across

图6-3. Supply Current Across Input Voltage, 3.3-V Supply

Temperature, 1.8-V, 3.3-V, and 5-V Supply

4.95

4.9

0.36

0.32

0.28

0.24

0.2

4.85

4.8

4.75

4.7

0.16

0.12

4.65

0.08

4.6

25°C

125°C

-40°C

125°C

-40°C

0.04

4.55

4.5

-16

-14

-12

-10

-8

-6

-4

-2

I_OL(mA)

I_OH(mA)

图6-6. Output Voltage vs Current in LOW State; 5-V Supply

图6-5. Output Voltage vs Current in HIGH State; 5-V Supply

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6.11 Typical Characteristics (continued)

3.3

3.27

3.24

3.21

3.18

3.15

3.12

3.09

3.06

3.03

0.2

0.175

0.15

0.125

0.1

0.075

0.05

0.025

25°C

125°C

-40°C

25°C

125°C

-40°C

-8

-7

-6

-5

-4

-3

-2

-1

I_OL(mA)

I_OH(mA)

图6-8. Output Voltage vs Current in LOW State; 3.3-V Supply

图6-7. Output Voltage vs Current in HIGH State; 3.3-V Supply

2.5

2.45

2.4

0.27

0.24

0.21

0.18

0.15

0.12

0.09

2.35

2.3

2.25

2.2

0.06

25°C

125°C

-40°C

2.15

2.1

125°C

-40°C

0.03

-8

-7

-6

-5

-4

-3

-2

-1

I_OH(mA)

I_OL(mA)

图6-9. Output Voltage vs Current in HIGH State; 2.5-V Supply

图6-10. Output Voltage vs Current in LOW State; 2.5-V Supply

1.8

1.75

1.7

0.36

0.32

0.28

0.24

0.2

1.65

1.6

1.55

1.5

0.16

0.12

1.45

0.08

25°C

125°C

-40°C

125°C

-40°C

1.4

0.04

1.35

-8

-7

-6

-5

-4

-3

-2

-1

I_OH(mA)

I_OL(mA)

图6-11. Output Voltage vs Current in HIGH State; 1.8-V Supply

图6-12. Output Voltage vs Current in LOW State; 1.8-V Supply

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators

having the following characteristics: PRR ≤1 MHz, Z_O= 50 Ω.

For clock inputs, f_maxis measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

V_CC

0 V

V_OH

V_OL

V_OH

V_OL

Test

Point

Input

Output

50%

S₁

S₂

R_L

(1)

From Output

Under Test

t_PLH

t_PHL

(1)

C_L

50%

(1)

(1) C_Lincludes probe and test-fixture capacitance.

t_PHL

t_PLH

图7-1. Load Circuit for 3-State Outputs

50%

(1) The greater between t_PLHand t_PHLis the same as t_pd

图7-2. Voltage Waveforms Propagation Delays

V_CC

90%

10%

90%

Output

Control

50%

Input

10%

t_f⁽¹⁾

0 V

V_OH

V_OL

t_r⁽¹⁾

(3)

(4)

t_PZL

t_PLZ

≈ V_CC

90%

10%

90%

Output

Waveform 1

(1)

S1 at V_LOAD

50%

Output

10%

t_f⁽¹⁾

V_OL

t_r⁽¹⁾

(3)

(4)

t_PZH

t_PHZ

(1) The greater between t_rand t_fis the same as t_t.

V_OH

Output

Waveform 2

S1 at GND⁽²⁾

图7-4. Voltage Waveforms, Input and Output

90%

50%

Transition Times

≈ 0 V

(1) S1 = CLOSED, S2 = OPEN.

(2) S1 = OPEN, S2 = CLOSED.

(3) The greater between t_PZLand t_PZHis the same as t_en

(4) The greater between t_PLZand t_PHZis the same as t_dis

图7-3. Voltage Waveforms Propagation Delays

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8 Detailed Description

8.1 Overview

The SN74LV8T245-Q1 is an octal bus transceiver with 3-state outputs. All eight channels are controlled by the

direction (DIR) pin and output enable (OE) pin. Each transceiver includes one buffer oriented from Ax to Bx and

one from Bx to Ax, with at least one output disabled at all times. The direction (DIR) pin controls which buffer is

active. The buffer that is not active has the output placed into the high-impedance state.

The output enable (OE) controls all outputs in the device. When the OE pin is in the low state, the appropriate

outputs as determined by the direction (DIR) pin are enabled. When the OE pin is in the high state, all outputs of

the device are disabled. All disabled outputs are placed into the high-impedance state.

To ensure the high-impedance state during power up or power down, the OE pin should be tied to V_CCthrough a

pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver and

the leakage of the pin as defined in the Electrical Characteristics table. Typically a 10-kΩ resistor will be

sufficient.

The output level is referenced to the supply voltage (V_CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS

levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for

example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable

down translation (for example 3.3 V to 2.5 V output).

8.2 Functional Block Diagram

Shared Control Logic

DIR

One of Eight Transceiver Channels

8.3 Feature Description

8.3.1 Balanced CMOS 3-State Outputs

This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the

three states that these outputs can be in. The term balanced indicates that the device can sink and source

similar currents. The drive capability of this device may create fast edges into light loads, so routing and load

conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger

currents than the device can sustain without being damaged. It is important for the output power of the device to

be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute

Maximum Ratings must be followed at all times.

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When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of

minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output

voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to

the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can

be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The

value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption

limitations. Typically, a 10-kΩresistor can be used to meet these requirements.

Unused 3-state CMOS outputs should be left disconnected.

8.3.2 Clamp Diode Structure

The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have

negative clamping diodes only as depicted in 图8-1.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to

the device. The input and output voltage ratings may be exceeded if the input and output clamp-

current ratings are observed.

V_CC

Device

+I_OK

Input

Output

Logic

-I_IK

-I_OK

GND

图8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.3 LVxT Enhanced Input Voltage

The SN74LV8T245-Q1 belongs to TIs LVxT family of Logic devices with integrated voltage level translation. This

family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs

tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be

referenced to the supply voltage (V_CC), as described in the Electrical Characteristics table. For proper

functionality, input signals must remain at or below the specified V_IH(MIN)level for a HIGH input state, and at or

below the specified V_IL(MAX)for a LOW input state. 图8-2 shows the typical V_IHand V_ILlevels for the LVxT family

of devices, as well as the voltage levels for standard CMOS devices for comparison.

The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance

given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage,

given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical

Characteristics, using Ohm's law (R = V ÷ I).

The inputs require that input signals transition between valid logic states quickly, as defined by the input

transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will

result in excessive power consumption and could cause oscillations. More details can be found in the

Implications of Slow or Floating CMOS Inputs application report.

Do not leave inputs floating at any time during operation. Unused inputs must be terminated at V_CCor GND. If a

system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a

valid input voltage during these times. The resistor value will depend on multiple factors; a 10-kΩ resistor,

however, is recommended and will typically meet all requirements.

English Data Sheet: SCLS908

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3.6

3.4

3.2

3.3-V CMOS

V_IH

V_IL

HIGH Input

LOW Input

2.8

2.6

2.4

2.2

2.5-V CMOS

2.4 V (V_OH

)

2 V (V_OH

)

1.8-V CMOS

1.8

1.6

1.4

1.2

1.45 V (V_OH

)

1.2-V CMOS

1.1 V (V_OH

)

0.8

0.6

0.4

0.2

0.45 V (V_OL

)

0.4 V (V_OL

)

0.4 V (V_OL

)

0.3 V (V_OL

)

1.6 1.8

2.2 2.4 2.6 2.8

3.2 3.4 3.6 3.8

4.2 4.4 4.6 4.8

5.2

5.5

V_CC- Supply Voltage (V)

图8-2. LVxT Input Voltage Levels

8.3.3.1 Down Translation

Signals can be translated down using the SN74LV8T245-Q1. The voltage applied at the V_CCwill determine the

output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical

Characteristics tables.

When connected to a high-impedance input, the output voltage will be approximately V_CCin the HIGH state, and

0 V in the LOW state. Ensure that the input signals in the HIGH state are between V_IH(MIN)and 5.5 V, and input

signals in the LOW state are lower than V_IL(MAX)as shown in 图8-2.

For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V, or 2.5 V can be down-translated to

match 1.8 V CMOS signals when operating from 1.8-V V_CC. See 图8-3.

Down Translation Combinations:

• 1.8-V V_CC–Inputs from 2.5 V, 3.3 V, and 5.0 V

• 2.5-V V_CC–Inputs from 3.3 V and 5.0 V

• 3.3-V V_CC–Inputs from 5.0 V

8.3.3.2 Up Translation

Input signals can be up translated using the SN74LV8T245-Q1. The voltage applied at V_CCwill determine the

output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical

Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately V_CC

in the HIGH state, and 0 V in the LOW state.

The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard

values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a V_IH(MIN)of 3.5 V.

For the SN74LV8T245-Q1, V_IH(MIN)with a 5-V supply is only 2 V, which would allow for up-translation from

typical 2.5-V to 5-V signals.

Ensure that the input signals in the HIGH state are above V_IH(MIN)and input signals in the LOW state are lower

than V_IL(MAX)as shown in 图8-3.

Up Translation Combinations:

• 1.8-V V_CC–Inputs from 1.2 V

• 2.5-V V_CC–Inputs from 1.8 V

• 3.3-V V_CC–Inputs from 1.8 V and 2.5 V

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• 5.0-V V_CC–Inputs from 2.5 V and 3.3 V

VIH = 2.0 V

VIL = 0.8 V

VIH = 0.99 V

VIL = 0.5 V

Vcc = 5.0 V

Vcc = 1.8 V

5.0 V, 3.3 V

2.5 V, 1.8 V

1.5 V, 1.2 V

System

5.0 V

3.3 V

System

5.0 V

System

1.8 V

System

LV1Txx Logic

图8-3. LVxT Up and Down Translation Example

8.3.4 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the

data sheet for which packages include this feature.

Package

Solder

Standard Lead

We able Flank Lead

Pad

PCB

图8-4. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After

Soldering

Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with

automatic optical inspection (AOI). As shown in 图 8-4, a wettable flank can be dimpled or step-cut to provide

additional surface area for solder adhesion which assists in reliably creating a side fillet. See the mechanical

drawing for additional details.

8.4 Device Functional Modes

表8-1 lists the functional modes of the SN74LV8T245-Q1.

表8-1. Function Table

INPUTS⁽¹⁾

OUTPUTS⁽²⁾

DIR

(1) H = High voltage level, L = Low voltage level, X = Do not care

(2) A = Logic value at 'A' input, B = Logic value at 'B' input, Z = High

impedance

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The SN74LV8T245-Q1 can be used to drive signals over relatively long traces or transmission lines. To reduce

ringing caused by impedance mismatches between the driver, transmission line, and receiver, a series damping

resistor placed in series with the transmitter’s output can be used. The figure in the Application Curve section

shows the received signal with three separate resistor values. Just a small amount of resistance can make a

significant impact on signal integrity in this type of application.

9.2 Typical Application

R_d

System

Controller

Z₀

Peripheral

L > 12 cm

Transceiver 1

Transceiver 2

图9-1. Application Block Diagram

9.3 Design Requirements

9.3.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The

supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.

The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all

outputs of the SN74LV8T245-Q1 plus the maximum static supply current, I_CC, listed in the Electrical

Characteristics and any transient current required for switching. The logic device can only source as much

current as is provided by the positive supply source. Be sure not to exceed the maximum total current through

V_CClisted in the Absolute Maximum Ratings.

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The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the

SN74LV8T245-Q1 plus the maximum supply current, I_CC, listed in the Electrical Characteristics, and any

transient current required for switching. The logic device can only sink as much current as can be sunk into its

ground connection. Be sure not to exceed the maximum total current through GND listed in the Absolute

Maximum Ratings.

The SN74LV8T245-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all

of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to

exceed 50 pF.

The SN74LV8T245-Q1 can drive a load with total resistance described by R_L≥ V_O/ I_O, with the output voltage

and current defined in the Electrical Characteristics table with V_OHand V_OL. When outputting in the high state,

the output voltage in the equation is defined as the difference between the measured output voltage and the

supply voltage at the V_CCpin.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.

CAUTION

The maximum junction temperature, T_J(max)listed in the Absolute Maximum Ratings, is an additional

limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum

Ratings. These limits are provided to prevent damage to the device.

9.3.2 Input Considerations

Input signals must cross V_IL(max)to be considered a logic LOW, and V_IH(min)to be considered a logic HIGH. Do

not exceed the maximum input voltage range found in the Absolute Maximum Ratings.

Unused inputs must be terminated to either V_CCor ground. These can be directly terminated if the input is

completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used

for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

SN74LV8T245-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ

resistor value is often used due to these factors.

The SN74LV8T245-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined

in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power

consumption, and reduction in device reliability.

Refer to the Feature Description section for additional information regarding the inputs for this device.

9.3.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

decrease the output voltage as specified by the V_OHspecification in the Electrical Characteristics. The ground

voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output

voltage as specified by the V_OLspecification in the Electrical Characteristics.

Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected

directly together. This can cause excessive current and damage to the device.

Two channels within the same device with the same input signals can be connected in parallel for additional

output drive strength.

Unused outputs can be left floating. Do not connect outputs directly to V_CCor ground.

Refer to Feature Description section for additional information regarding the outputs for this device.

English Data Sheet: SCLS908

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9.3.4 Detailed Design Procedure

1. Add a decoupling capacitor from V_CCto GND. The capacitor needs to be placed physically close to the

device and electrically close to both the V_CCand GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit; it will, however, ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the

SN74LV8T245-Q1 to one or more of the receiving devices.

3. Ensure the resistive load at the output is larger than (V_CC/ I_O(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in MΩ; much larger than the minimum calculated previously.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.4 Application Curves

0 ꢀ

22 ꢀ

50 ꢀ

3.3

-1

-2

Time (ns)

90 100

图9-2. Simulated Signal Integrity at the Receiver With Different Damping Resistor (R_d) Values

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Recommended Operating Conditions. Each V_CCterminal should have a good bypass capacitor to prevent power

disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass

capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in

parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as

shown in the following layout example.

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11 Layout

11.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many

cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a

triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left

unconnected because the undefined voltages at the outside connections result in undefined operational states.

All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the

input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular

unused input depends on the function of the device. Generally, the inputs are tied to GND or V_CC, whichever

makes more sense for the logic function or is more convenient.

11.2 Layout Example

V_CC

GND

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Bypass capacitor

placed close to the

device

0.1 ꢀF

DIR

VCC

GND

Avoid 90°

corners for

signal lines

GND

图11-1. Example Layout for the SN74LV8T245-Q1 in RKS

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, CMOS Power Consumption and C_pdCalculation application report

• Texas Instruments, Designing With Logic application report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

74LV8T245QWRKSRQ1

SN74LV8T245QDGSRQ1

SN74LV8T245QPWRQ1

ACTIVE

VQFN

VSSOP

TSSOP

RKS

DGS

3000 RoHS & Green

5000 RoHS & Green

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LV8245Q

Samples

NIPDAU

8245Q

LV8T245Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LV8T245-Q1 :

Catalog : SN74LV8T245

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

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