74SSTUB32868_15 [TI]
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST;
| 型号： | 74SSTUB32868_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST 双倍数据速率 |
| 文件： | 总23页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74SSTUB32868
www.ti.com ......................................................................................................................................................... SCAS835C–JUNE 2007–REVISED MARCH 2009
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
1
FEATURES
•
Supports LVCMOS Switching Levels on the
Chip-Select Gate-Enable, Control, and RESET
Inputs
2
•
Member of the Texas Instruments
Widebus+ ™Family
•
•
•
Checks Parity on DIMM-Independent Data
Inputs
•
•
•
•
Pinout Optimizes DDR2 DIMM PCB Layout
1-to-2 Outputs Supports Stacked DDR2 DIMMs
One Device Per DIMM Required
Supports Industrial Temperature Range
(-40°C to 85°C)
Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low, Except QERR
•
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
APPLICATIONS
•
•
•
Supports SSTL_18 Data Inputs
DDR2 registered DIMM
Differential Clock (CLK and CLK) Inputs
DESCRIPTION
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM
is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM
loads.
All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs,
which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error (QERR) output.
The 74SSTUB32868 operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The 74SSTUB32868 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it
with the data received on the DIMM-independent D-inputs (D1−D5, D7, D9−D12, D17−D28 when C = 0; or
D1−D12, D17−D20, D22, D24−D28 when C = 1) and indicates whether a parity error has occurred on the
open-drain QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number
of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all
DIMM-independent D-inputs must be tied to a known logic state.
The 74SSTUB32868 includes a parity checking function. Parity, which arrives one cycle after the data input to
which it applies, is checked on the PAR_IN input of the device. Two clock cycles after the data are registered,
the corresponding QERR signal is generated.
ORDERING INFORMATION
ORDERABLE PART
TA
PACKAGE(1)
Tape and Reel
TOP-SIDE MARKING
NUMBER
-40°C to 85°C
TFBGA-ZRH
74SSTUB32868ZRHR
SB868
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
74SSTUB32868
SCAS835C–JUNE 2007–REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and
latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error
occurs on the clock cycle before the device enters the low−power mode (LPM) and the QERR output is driven
low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity
check computation.
The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration
(when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low
or high level to configure the register in the desired mode.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers.
However, when coming out of reset, the register becomes active quickly, relative to the time to enable the
differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the
low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32868 must
ensure that the outputs remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C
inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1)
and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs
are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs function normally. Also, if both DCS0 and DCS1
inputs are high, the device will gate the QERR output from changing states. If either DCS0 or DCS1 is low, the
QERR output functions normally. The RESET input has priority over the DCS0 and DCS1 control and when
driven low forces the Qn outputs low, and the QERR output high. If the chip-select control functionality is not
desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0
and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and
DCS1 only, then the CSGEN input should be pulled up to VCC through a pullup resistor.
The two VREF pins (A5 and AB5) are connected together internally by approximately 150 Ω. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
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Product Folder Link(s): 74SSTUB32868
74SSTUB32868
www.ti.com ......................................................................................................................................................... SCAS835C–JUNE 2007–REVISED MARCH 2009
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.5 to 2.5
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
±50
UNIT
V
VCC
VI
Supply voltage range
Input voltage range (see notes (2) and
Output voltage range (see notes (2) and
(3)
)
V
(3)
VO
IIK
)
V
Input clamp current (VI < 0, VI > VCC
Output clamp current (VI < 0, VO > VCC
Continuous output current (VO = 0 to VCC
)
mA
mA
mA
mA
IOK
IO
)
±50
)
±50
ICC
Continuous current through each VCC or GND
±100
No airflow
Airflow 200 ft/min
No airflow
46.8
(4)
RθJA
Thermal resistance, junction−to−ambient (see note
)
42.9
k/W
°C
(4)
RθJC
Tstg
Thermal resistance, junction−to−case (see note
)
17.9
Storage temperature range
-65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 2.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGES, CURRENTS AND TEMPERATURE RANGE
VCC
VREF
VTT
VI
Supply voltage
1.7
0.49 x VCC
VREF - 40 mV
0
1.9
V
V
V
V
V
V
V
V
V
V
Reference voltage
0.5 x VCC
0.51 x VCC
Termination voltage
VREF VREF + 40 mV
VCC
Input voltage
VIH
VIL
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs, DCSn, PAR_IN
Data inputs, DCSn, PAR_IN
Data inputs, DCSn, PAR_IN
Data inputs, DCSn, PAR_IN
RESET, CSGEN, C
VREF + 250 mV
VREF - 250 mV
VREF - 125 mV
VIH
VIL
VREF + 125 mV
0.65 x VCC
VIH
VIL
RESET, CSGEN, C
0.35 x VCC
1.125
Common-mode input voltage
range
VICR
CLK, CLK
0.675
0.6
V
VI(PP)
IOH
Peak-to-peak input voltage
High-level output current
CLK, CLK
Q outputs
Q outputs
QERR output
V
-8
8
mA
IOL
TA
Low-level output current
mA
°C
30
Operating free-air temperature
-40
85
(1) The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. See the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
Copyright © 2007–2009, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
IOH = -100 µA
VCC
1.7 V to 1.9 V
1.7 V
MIN
VCC - 0.2
1.2
TYP(1)
MAX
UNIT
VOH
Q outputs
V
IOH = -6 mA
IOL = 100 µA
IOL = 6 mA
1.7 V to 1.9 V
1.7 V
0.2
0.5
0.5
-5
Q outputs
QERR
VOL
V
IOL = 25 mA
VI = GND
1.7 V
PAR_IN
II
VI = VCC
1.9 V
25
±5
µA
All other inputs(2)
QERR outputs
Static standby(3)
VI = VCC or GND
VO = VCC or GND
RESET = GND
IOZ
ICC
1.9 V
1.9 V
±10
µA
µA
(3)
200
IO = 0
RESET = VCC, VI = VIH(AC) or
VIL(AC)
Static operating
80
mA
RESET = VCC, VI = VIH(AC) or
VIL(AC),CLK and CLK switching
50% duty cycle
Dynamic operating −
clock only
64
37
µA/MHz
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
50% duty cycle, One data input
switching at one half clock
frequency, 50% duty cycle
ICC(D)
IO = 0
1.8 V
µA/clock
MHz/
D inputs
Dynamic operating −
per each data input
Chip-select-enabled RESET = VCC, VI = VIH(AC) or
low-power active
mode − clock only
VIL(AC),CLK and CLK switching
50% duty cycle
68
µA/MHz
RESET = VCC, VI = VIH(AC) or
Chip-select-enabled VIL(AC), CLK and CLK switching
ICC(DLP)
IO = 0
1.8 V
1.8 V
µA/clock
MHz/
low-power active
mode
50% duty cycle, One data input
switching at one half clock
frequency, 50% duty cycle
2.7
D inputs
Data inputs, DCSn,
PAR_IN, CSGEN
VI = VREF ±250 mV
2
2
2.5
4
3
3
CI
pF
CLK, CLK
RESET
VICR = 0.9 V, VI(PP) = 600 mV
VI = VCC or GND
(1) All typical values are at VCC = 1.8 V, TA = 25°C.
(2) Each VREF pin (A5 or AB5) should be tested independently, with the other (untested) pin open.
(3) The maximum static standby current ICC is 100 µA if the device is exposed to commercial temperature range (0°C to 70°C) only. For
industrial temperature range (-40°C to 85°C), the static ICC is 200 µA.
4
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Product Folder Link(s): 74SSTUB32868
74SSTUB32868
www.ti.com ......................................................................................................................................................... SCAS835C–JUNE 2007–REVISED MARCH 2009
PACKAGE
(TOP VIEW)
Terminal Assignment for Register-A (C = 0)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
V
Q1A
Q2A
Q1B
Q2B
A
B
D2
D4
D1
D3
C
GND
GND
REF
A
B
C
D
V
V
V
V
CC
CC
CC
CC
D6
(DCKE1)
Q3A
Q4A
Q5A
Q3B
Q4B
Q5B
C
D
E
D5
D7
GND
GND
GND
GND
D8
(DCKE0)
V
V
V
V
CC
CC
CC
CC
E
F
G
H
J
Q6A
(QCKE1A)
D9
GND
GND
GND
GND
Q8A
(QCKE0A)
Q6B
(QCKE1B)
V
V
V
V
Q7A
F
G
H
D10
D11
D12
CC
CC
CC
CC
Q10A
Q12A
Q9A
Q7B
GND
GND
GND
GND
Q8B
(QCKE0B)
K
L
V
V
V
V
Q11A
CC
CC
CC
CC
D13
(DCS1)
Q13A
(QCS1A)
Q10B
Q9B
J
GND
GND
GND
GND
M
N
P
R
T
D14
(DCS0)
Q14A
(QCS0A)
V
V
V
V
Q12B
Q14B
(QCS0B) (QCS1B)
Q15B Q16B
(QODT0B) (QODT1B)
Q11B
Q13B
K
L
CC
CC
CC
CC
PAR_IN
QERR
GND
CLK
CSGEN
GND
GND
GND
V
V
V
M
CLK
D15
RESET
Q15A
CC
CC
CC
U
V
Q17B
Q19B
Q18B
Q20B
N
P
GND
GND
GND
(DODT0) (QODT0A)
W
Y
D16 Q16A
(DODT1) (QODT1A)
V
V
V
V
CC
CC
CC
CC
Q17A
Q19A
Q21A
Q18A
Q20A
Q22A
Q21B
Q22B
Q23B
R
T
D17
D18
D19
GND
GND
GND
GND
AA
AB
V
V
V
V
CC
CC
CC
CC
U
GND
GND
GND
GND
V
V
V
V
Q23A
D22
Q24A
Q25A
Q24B
Q25B
V
D20
D21
CC
CC
CC
CC
W
GND
GND
GND
GND
V
V
V
V
Q26A
Q27A
Q28A
Q26B
Q27B
Y
D23
D25
D24
D26
CC
CC
CC
CC
AA
GND
NC
GND
GND
GND
V
V
V
Q28B
AB
D27
D28
CC
REF
CC
A. Each pin name in parentheses indicates the DDR2 DIMM signal name.
B. NC - No internal connection.
Copyright © 2007–2009, Texas Instruments Incorporated
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SCAS835C–JUNE 2007–REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com
Logic Diagram for Register-A Configuration (Positive Logic); C = 0
M2
RESET
L1
CLK
M1
CLK
A5, AB5
V
REF
D1, C1
F2, E2
H8, F8
DCKE0,
DCKE1
2
QCKE0A,
QCKE1A
2
D
R
2
2
2
CLK
Q
QCKE0B,
QCKE1B
N1, P1
N2, P2
M7, M8
DODT0,
DODT1
2
QODT0A,
QODT1A
2
D
R
2
2
2
CLK
Q
QODT0B,
QODT1B
K1
K2
L7
DCS0
QCS0A
QCS0B
D
R
CLK
Q
L2
J1
CSGEN
DCS1
J2
L8
QCS1A
QCS1B
D
R
CLK
Q
One of 22 Channels
A2
D1
A7
A8
CE
Q1A
Q1B
D
R
Q
CLK
To 21 Other Channels
(D2−D5, D7, D9−D12, D17−D28)
6
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Product Folder Link(s): 74SSTUB32868
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www.ti.com ......................................................................................................................................................... SCAS835C–JUNE 2007–REVISED MARCH 2009
Parity Logic Diagram for Register-A Configuration (Positive Logic); C = 0
M2
RESET
L1
CLK
M1
CLK
D1−D5,
Q1A−Q5A,
Q7A,
D1−D5, D7,
D9−D12,
D17−D28
D7,
D9−D12,
D17−D28
D1−D5, D7,
D9−D12,
D17−D28
22
22
22
Q9A−Q12A,
Q17A−Q28A
A5, AB5
D
R
V
22
REF
Q
CLK
CE
22
Q1B−Q5B,
Q7B,
D1−D5, D7,
D9−D12,
D17−D28
Q9B−Q12B,
Q17B−Q28B
22
L3
PAR_IN
D
R
Parity Generator
and
Error Check
M3
Q
QERR
CLK
CE
K1
K2
L7
DCS0
QCS0A
QCS0B
D
CLK
Q
R
L2
J1
CSGEN
DCS1
J2
L8
QCS1A
QCS1B
D
R
CLK
Q
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PACKAGE
(TOP VIEW)
Terminal Assignment for Register-B (C = 1)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
V
Q1A
Q2A
Q1B
Q2B
A
B
C
D2
D4
D1
D3
C
GND
GND
REF
A
B
C
D
V
V
V
V
CC
CC
CC
CC
Q3A
Q4A
Q5A
Q7A
Q3B
Q4B
Q5B
Q6B
D6
D5
GND
GND
GND
GND
V
V
V
V
D8
D7
D
E
F
CC
CC
CC
CC
Q6A
Q8A
D9
GND
GND
GND
GND
E
F
G
H
J
V
V
V
V
D10
CC
CC
CC
CC
Q10A
Q12A
Q13A
Q9A
Q7B
Q8B
G
H
D11
D12
D13
GND
GND
GND
GND
V
V
V
V
Q11A
CC
CC
CC
CC
Q10B
Q9B
J
K
L
GND
GND
GND
GND
K
L
(DODT1) (DODT1A)
D14
Q14A
(DODT0) (QODT0A)
V
V
V
V
Q12B
Q14B
Q11B
Q13B
CC
CC
CC
CC
M
N
P
R
T
PAR_IN
QERR
GND
CLK
CLK
CSGEN
RESET
GND
GND
GND
(QODT0B) (QODT1B)
Q15B Q16B
(QCS0B) (QCS1B)
V
V
V
M
N
P
CC
CC
CC
D15
(DCS0)
Q15A
(QCS0A)
Q17B
Q19B
Q18A
Q18B
Q20B
GND
GND
GND
U
V
D16
(DCS1)
Q16A
(QCS1A)
V
V
V
V
CC
CC
CC
CC
W
Y
Q21B
(QCKE0B)
Q17A
R
D17
GND
GND
GND
GND
V
V
V
V
Q19A
Q20A
Q22A
Q22B
T
D18
D19
AA
AB
CC
CC
CC
CC
Q21A
(QCKE0A)
Q23B
(QCKE1B)
U
GND
GND
GND
GND
Q23A
(QCKE1A)
V
V
V
V
Q24A
Q25A
Q26A
Q24B
Q25B
Q26B
V
W
Y
D20
CC
CC
CC
CC
D21
(DCKE0)
D22
D24
GND
GND
GND
GND
D23
(DCKE1)
V
V
V
V
CC
CC
CC
CC
Q27A
Q28A
Q27B
Q28B
AA
AB
D25
D27
D26
D28
GND
NC
GND
GND
GND
V
V
V
CC
REF
CC
8
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Logic Diagram for Register-B Configuration (Positive Logic); C = 1
M2
RESET
L1
CLK
M1
CLK
A5, AB5
V
REF
W1, Y1
U2, V2
R8, U8
DCKE0,
DCKE1
2
QCKE0A,
QCKE1A
2
D
R
2
2
2
CLK
Q
QCKE0B,
QCKE1B
K1, J1
K2, J2
L7, L8
DODT0,
DODT1
2
QODT0A,
QODT1A
2
D
R
2
2
2
CLK
Q
QODT0B,
QODT1B
N1
N2
M7
DCS0
QCS0A
QCS0B
D
R
CLK
Q
L2
P1
CSGEN
DCS1
P2
QCS1A
QCS1B
D
R
CLK
Q
M8
One of 22 Channels
A2
D1
A7
A8
CE
Q1A
Q1B
D
R
Q
CLK
To 21 Other Channels
(D2−D12, D17−D20, D22, D24−D28)
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Parity Logic Diagram for Register-B Configuration (Positive Logic); C = 1
M2
RESET
L1
CLK
M1
CLK
D1−D12,
Q1A−Q12A,
Q17A−Q20A,
Q22A,
D1−D12,
D17−D20,
D22,
D17−D20, D22,
D24−D28
D1−D12,
22
22
22
D24−D28
D17−D20, D22,
D24−D28
Q24A−Q28A
A5, AB5
D
R
V
22
REF
Q
CLK
CE
22
Q1B−Q12B,
Q17B−Q20B,
Q22B,
D1−D12,
22
D17−D20, D22,
D24−D28
Q24B−Q28B
L3
PAR_IN
D
R
Parity Generator
and
Error Check
M3
Q
CLK
CE
QERR
N1
N2
M7
DCS0
QCS0A
QCS0B
D
CLK
Q
R
L2
P1
CSGEN
DCS1
P2
QCS1A
QCS1B
D
R
CLK
Q
M8
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Timing Diagram for 74SSTUB32868 During Start-Up (RESET Switches From L to H)
RESET
CSGEN
DCS0
DCS1
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
t
act
su
h
Dn, DODTn,
DCKEn
(see Note A)
t
t
pdm, pdmss
CLK to Q
Qn, QODTn,
QCKEn
t
t
su
h
PAR_IN
(see Note A)
t
t
t
PHL, PLH
PHL
CLK to QERR
CLK to QERR
QERR
(see Note B)
Data to QERR Latency
H, L, or X
H or L
A. After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum
time of tact max, to avoid a false error.
B. If the data is clocked in on the n-clock pulse, the QERR output signal is generated on the n + 2 clock pulse, and it is
valid on the n + 3 clock pulse.
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Timing Diagram for 74SSTUB32868 During Normal Operation (RESET = H)
RESET
CSGEN
DCS0
DCS1
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
su
h
Dn, DODTn,
DCKEn
t
t
pdm’ pdmss
CLK to Q
Qn, QODTn,
QCKEn
t
t
su
h
PAR_IN
t
t
PHL’ PLH
CLK to QERR
QERR
(see Note A)
Data to QERR Latency
Output signal is dependent on
the prior unknown input event
Unknown input
event
H or L
A. If the data is clocked in on the n-clock pulse, the QERR output signal is generated on the n + 2 clock pulse, and it is
valid on the n + 3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a
minimum of two clock cycles or until RESET is driven low.
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Timing Diagram for 74SSTUB32868 During Shut-Down (RESET Switches From H to L)
RESET
t
inact
CSGEN
(see Note A)
DCS0
(see Note A)
DCS1
(see Note A)
CLK
(see Note A)
CLK
(see Note A)
Dn, DODTn,
DCKEn
(see Note A)
t
RPHL
RESET to Q
Qn, QODTn,
QCKEn
PAR_IN
(see Note A)
QERR
t
RPHL
RESET to QERR
H, L, or X
H or L
A. After RESET is switched from high to low, all data and clock input signals must be held at logic levels (not floating) for
a minimum time of tinact max, to avoid a false error.
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TERMINAL FUNCTIONS
ELECTRICAL
CHARACTERISTICS
TERMINAL NAME
GND
DESCRIPTION
Ground
Ground input
VCC
VREF
CLK
CLK
C
Power supply voltage
Input reference voltage
Positive master clock input
Negative master clock input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS input
Configuration control input - Register A or Register B
Asynchronous reset input − resets registers and disables VREF, data and clock
differential-input receivers. When RESET is low, all the Q outputs are forced low and
the QERR output is forced high.
RESET
LVCMOS input
Chip select gate enable − When high, D1−D28(1) inputs are latched only when at least
one chip select input is low during the rising edge of the clock. When low, the
D1−D28(1) inputs are latched and redriven on every rising edge of the clock.
CSGEN
D1-D28
LVCMOS input
SSTL_18 input
Data input − clocked in on the crossing of the rising edge of CLK and the falling edge
of CLK
Chip select inputs − These pins initiate DRAM address/command decodes, and as
such at least one will be low when a valid address/command is present. The Register
can be programmed to redrive all D inputs (CSGEN high) only when at least one chip
select input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1−D28(2) inputs will
be disabled.
DCS0, DCS1
SSTL_18 input
DODT0, DODT1
DCKE0, DEKE1
The outputs of this register bit will not be suspended by the DCS0 and DCS1 control.
The outputs of this register bit will not be suspended by the DCS0 and DCS1 control.
SSTL_18 input
SSTL_18 input
Parity input − arrives one clock cycle after the corresponding data input. Pulldown
resistor of typical 150kΩ to GND.
SSTL_18 input with
pulldown
PAR_IN
Q1-Q28(3)
Data outputs that are suspended by the DCS0 and DCS1 control.
Data output that will not be suspended by the DCS0 and DCS1 control.
Data output that will not be suspended by the DCS0 and DCS1 control.
Data output that will not be suspended by the DCS0 and DCS1 control.
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
QCS0, QCS1
QODT0, QODT1
QCKE0, QEKE1
Output error bit − generated two clock cycles after the corresponding data is
registered.
QERR
NC
Open-drain output
No internal connection
(1) Data inputs = D1−D5, D7, D9−D12, D17−D28 when C = 0.
Data inputs = D1−D12, D17−D20, D22, D24−D28 when C = 1.
(2) Data inputs = D1−D5, D7, D9−D12, D17−D28 when C = 0.
Data inputs = D1−D12, D17−D20, D22, D24−D28 when C = 1.
(3) Data outputs = Q1−Q5, Q7, Q9−Q12, Q17−Q28 when C = 0.
Data outputs = Q1−Q12, Q17−Q20, Q22, Q24−Q28 when C = 1.
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FUNCTION TABLE
INPUTS
CSGEN
OUTPUTS
RESET
DCS0
DCS1
CLK
CLK
dn,
DODTn,
DCKEn
Qn
QCS0
QCS1
QODT,
QCKE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
↑
↓
L
H
X
L
L
H
L
L
L
L
L
H
↑
↓
L
L
L or H
L or H
Q0
L
Q0
L
Q0
H
Q0
L
L
H
H
H
L
↑
↓
L
↑
↓
H
X
L
H
L
H
H
L
L or H
L or H
Q0
L
Q0
H
Q0
L
Q0
L
H
H
H
H
H
H
H
H
H
↑
↓
L
↑
↓
H
X
L
H
H
L
H
L
L or H
L or H
Q0
L
Q0
H
Q0
H
Q0
L
H
H
H
H
H
H
↑
↓
L
↑
L or H
↑
↓
L or H
↓
H
X
L
H
H
H
H
L
Q0
Q0
Q0
Q0
L
Q0
H
Q0
H
Q0
L
H
H
H
↑
↓
H
X
L
H
H
H
L or H
L or H
Q0
L
Q0
L
Q0
L
X or
X or
X or
X or
X or
floating
floating
floating
floating
floating
PARITY AND STANDBY FUNCTION
INPUTS
OUTPUTS
(2)
RESET
CLK
CLK
DCS0
DCS1
Σ OF INPUTS = H
PAR_IN(1)
QERR
D1 - D22
H
H
H
H
H
H
H
H
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↓
L
X
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
L
L
H
L
L
X
↓
L
X
H
H
L
L
↓
L
X
H
H
L
↓
X
L
↓
X
L
L
↓
X
L
H
H
X
X
L
↓
↓
X
L
H
(3)
H
X
H
X
QERR 0
L or H
X or floating
L or H
X or floating
X
QERR 0
H
X or floating
X or floating
X
X or floating
(1) PAR_IN arrives one clock cycle after the data to which it applies.
(2) This transition assumes that QERR is high at the crossing of CLK going high and CLK going low. If QERR goes low, it stays latched low
for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive errors occur, the QERR output is driven low
and latched low for a clock duration equal to the parity error duration or until RESET is driven low. For QERR computation, CSGEN is a
“don’t care”.
(3) If DCS0, DCS1 and CSGEN are driven high, the device is placed in a low−power mode (LPM). If a parity error occurs on the clock cycle
before the device enters the LPM and the QERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or
until RESET is driven low.
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TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating free-air temperature (see Figure 1 and Note
(1)
)
VCC = 1.8 V ±0.1 V
MIN
MAX
UNIT
MHz
ns
f(clock)
tw
Clock frequency
410
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note
Differential inputs inactive time (see Note
1
(2)
tact
)
10
15
ns
(3)
tinact
)
ns
DCSn before CLK↑, CLK↓, CSGEN high
DCSn before CLK↑, CLK↓, CSGEN low
DODTn, DCKEn, and Data before CLK↑, CLK↓
PAR_IN before CLK↑, CLK↓
600
500
500
500
400
400
tsu
Setup time
Hold time
ps
ps
DCSn, DODTn, DCKEn, and Data after CLK↑, CLK↓
PAR_IN after CLK↑, CLK↓
th
(1) All inputs slew rate is 1 V/ns ±20%
(2) VREF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
(3) VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low.
SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage, load, and operating free-air temperature (unless otherwise noted)
VCC = 1.8 V ±0.1 V
PARAMETER
fmax (see Figure 2)
tpdm (1) (production test, see Figure 1)
FROM (INPUT)
TO (OUTPUT)
MIN
410
0.5
1.2
1
MAX
UNIT
MHz
ns
CLK and CLK
CLK and CLK
Q
1.0
3
tPLH (see Figure 4)
ns
QERR
tPHL (see Figure 4)
tRPHL(2) (see Figure 2)
2.4
3
RESET
RESET
Q
ns
ns
tRPLH (see Figure 4)
QERR
3
(1) The typical difference between min and max does not exceed 400 ps.
(2) Includes 350-ps test-load transmission line delay.
OUTPUT SLEW RATES
over operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V ±0.1 V
PARAMETER
dV/dt_r
FROM
20%
TO (OUTPUT)
80%
MIN
1
MAX
UNIT
V/ns
V/ns
V/ns
5
5
1
dV/dt_f
dV/dt_Δ(1)
80%
20%
1
20% to 80%
20% to 80%
(1) The difference between dV/dr_r (rising edge rate) and dV/dt_f (falling edge).
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PARAMETER MEASUREMENT INFORMATION
V
/2
CC
Test
DUT
CLK
Z
= 50 W
O
Point
R
= 50 W
L
Test
Point
Clock Inputs
Out
Z
= 50 W
O
CLK
Test
Z
= 50 W
O
Point
LOAD CIRCUIT
V
I(PP)
Timing
Inputs
V
/2
V
/2
CC
CC
t
t
PLH
PHL
/2
V
V
OH
OL
Output
V
/2
V
CC
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Figure 1. Output Load Circuit for Production Test
Propagation Delay (Design Goal as per JEDEC Specification)
VCC = 1.8 V ±0.1 V
PARAMETER
FROM (INPUT)
CLK and CLK
CLK and CLK
TO (OUTPUT)
MIN
MAX
1.5
UNIT
ns
(1)
tpdm
Q
Q
1.1
(1)
tpdmss
1.6
ns
(1) Includes 350-ps test-load transmission line delay.
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V
CC
Z
t
= 50 W,
O
Test
DUT
CLK
= 350 ps
R
= 1 kW
Point
D
L
Output
Out
Clock Inputs
R
= 100 W
L
Test Point
C
= 30 pF
Z
t
= 50 W,
L
(see Note A)
O
CLK
R
= 1 kW
L
= 350 ps
Test
D
Z
t
= 50 W,
O
Point
= 350 ps
D
LOAD CIRCUIT
t
w
V
V
IH
IL
V
V
REF
Input
REF
V
CC
LVCMOS
V
/2
V
/2
CC
CC
RESET
Input
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
V
I(PP)
t
t
act
inact
Timing
Inputs
V
V
ICR
I
ICR
CC
(see Note B)
I
I
(operating)
CC
90%
10%
(standby)
CC
t
t
PLH
PHL
/2
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
OH
V
/2
V
Output
CC
CC
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
Timing
Inputs
IH
LVCMOS
RESET
Input
V
V
/2
ICR
CC
IL
t
PHL
t
su
t
h
V
V
V
OH
IH
V
/2
Output
Input
V
V
REF
CC
REF
V
OL
IL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
PROPAGATION DELAY TIMES
A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew
rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E. VREF = VCC/2
F. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. VI(PP) = 600 mV.
I.
tPLH and tPHL are the same as tpd.
Figure 2. Data Output Load Circuit and Voltage Waveforms
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V
CC
DUT
R
= 50 W
L
V
V
Output
OH
Out
Test Point
80%
C
= 10 pF
20%
L
(see Note A)
OL
dV_f
dt_f
LOAD CIRCUIT
VOLTAGE WAVEFORMS
HIGH-TO-LOW SLEW-RATE MEASUREMENT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
dt_r
dV_r
Out
Test Point
V
OH
OL
80%
C
= 10 pF
R
= 50 W
L
(see Note A)
L
20%
V
Output
LOAD CIRCUIT
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
LOW-TO-HIGH SLEW-RATE MEASUREMENT
A. CL includes probe and jig capacitance.
B. All
input
pulses
are
supplied
by
generators
having
the
following
characteristics:
PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
Figure 3. Data Output Slew-Rate Measurement Information
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V
V
CC
I(PP)
Timing
Inputs
DUT
V
V
ICR
ICR
R = 1 kW
L
t
PHL
Out
Test Point
Output
V
CC
C
= 10 pF
Waveform 1
L
(see Note A)
V
/2
CC
V
OL
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(HIGH-TO-LOW)
LOAD CIRCUIT
V
I(PP)
LVCMOS
RESET
Input
V
CC
Timing
Inputs
V
/2
V
V
ICR
CC
ICR
0 V
t
PLH
t
PHL
V
OH
V
OH
Output
Output
0.15 V
Waveform 2
0.15 V
Waveform 2
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(LOW-TO-HIGH)
OPEN-DRAIN OUTPUT TRANSITION TIME
(LOW-TO-HIGH)
A. CL includes probe and jig capacitance.
B. All input pulses are supplied
PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
C. tPLH and tPHL are the same as tpd
by
generators
having
the
following
characteristics:
.
Figure 4. Error Output Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74SSTUB32868ZRHR
ACTIVE
NFBGA
ZRH
176
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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相关型号：
74SSTV16859NL
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, PLASTIC, VFPQFN-56
IDT
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