8302501EA [TI]
同步 4 位加/减二进制计数器 | J | 16 | -55 to 125;
| 型号： | 8302501EA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 同步 4 位加/减二进制计数器 | J | 16 | -55 to 125 逻辑集成电路 触发器 计数器 |
| 文件： | 总9页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
SN54ALS169B, SN54AS169A . . . J PACKAGE
SN74ALS169B, SN74AS169A . . . D OR N PACKAGE
(TOP VIEW)
• Fully Synchronous Operation for Counting
and Programming
• Internal Carry Look-Ahead Circuitry for
Fast Counting
U/D
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
• Carry Output for n-Bit Cascading
• Fully Independent Clock Circuit
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT
ENP
GND
LOAD
description
SN54ALS169B, SN54AS169A . . . FK PACKAGE
(TOP VIEW)
These synchronous 4-bit up/down binary
presettable counters feature an internal carry
look-ahead circuitry for cascading in high-speed
counting applications. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when so instructed by
the count-enable (ENP, ENT) inputs and internal
gating. This mode of operation eliminates the
output counting spikes normally associated with
asynchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the four flip-flops on the
rising(positive-going)edgeoftheclockwaveform.
3
2
1
20 19
18
A
B
Q
Q
4
5
6
7
8
A
B
17
16
15
14
NC
C
NC
Q
C
D
Q
D
9 10 11 12 13
These counters are fully programmable; that is,
they may be preset to either level. The load-input
circuitry allows loading with the carry-enable
output of cascaded counters. Because loading is
synchronous, setting up a low level at the load
(LOAD) input disables the counter and causes the
outputs to agree with the data inputs after the next
clock pulse.
NC – No internal connection
The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without
additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this
function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the
up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward
to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting
down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enablesuccessive
cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs
are diode clamped to minimize transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)
that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
†
logic symbol
CTRDIV16
9
M1 [LOAD]
M2 [COUNT]
LOAD
U/D
1
M3 [UP]
M4 [DOWN]
15
10
RCO
3,5CT=15
4,5CT=0
G5
ENT
ENP
CLK
7
2
G6
2,3,5,6+/C7
2,4,5,6 –
3
4
5
6
14
13
12
11
Q
A
1
2
4
8
A
B
C
D
1, 7D
Q
B
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
logic diagram (positive logic)
9
LOAD
1
15
U/D
RCO
10
ENT
7
ENP
C1
1D
2
14
CLK
Q
Q
Q
A
B
C
3
A
C1
1D
13
12
11
4
B
C1
1D
5
C
C1
1D
Q
D
6
D
Pin numbers shown are for the D, J, and N packages.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
typical load, count, and inhibit sequences
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD
A
B
Data
Inputs
C
D
CLK
U/D
ENP and ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
13
14
15
0
1
2
2
2
1
0
15
14
13
Count Up
Inhibit
Count Down
Load
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
recommended operating conditions
SN54ALS169B
MIN NOM MAX
SN74ALS169B
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
f
t
mA
mA
MHz
ns
OH
OL
clock
w
0
14
20
25
20
28
0
22
0
12.5
15
15
15
15
0
40
Pulse duration, CLK high or low
A, B, C, or D
ENP or ENT
LOAD
t
su
Setup time before CLK↑
ns
U/D
t
h
Hold time, data after CLK↑
ns
T
A
Operating free-air temperature
–55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS169B
SN74ALS169B
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
V = 7 V
0.1
20
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.2
–112
25
–0.2
–112
25
mA
mA
mA
‡
V
O
= 2.25 V
–20
–30
O
15
15
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
T
A
= MIN to MAX
SN54ALS169B SN74ALS169B
MIN
22
3
MAX
MIN
40
3
MAX
f
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
20
25
20
23
16
24
22
26
20
20
15
20
13
16
19
19
CLK
CLK
RCO
6
6
2
2
Any Q
ns
ns
ns
5
5
2
2
ENT
U/D
RCO
RCO
3
3
4
5
5
5
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS169A
MIN NOM MAX
SN74AS169A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
–2
20
60
0.8
–2
20
75
V
IL
I
I
f
mA
mA
MHz
ns
OH
OL
clock
*
0
7.7
10
0
6.7
8
t *
w
Pulse duration, CLK high or low
A, B, C, or D
ENP or ENT
LOAD
10
8
t
su
*
Setup time before CLK↑
ns
10
8
U/D
14
11
0
t *
h
Hold time, data after CLK↑
2
ns
T
A
Operating free-air temperature
–55
125
0
70
°C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS169A
SN74AS169A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
V
V
IK
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
= –2 mA
= 20 mA
V
CC
–2
V
CC
–2
OH
OL
OH
OL
I
0.25
0.5
0.2
0.25
0.5
0.2
LOAD, ENT, U/D
All others
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
I
mA
µA
I
0.1
0.1
LOAD, ENT, U/D
All others
40
40
V = 2.7 V
I
IH
IL
20
20
LOAD, ENT, U/D
All others
–1
–1
V = 0.4 V
I
mA
–0.5
–112
63
–0.5
–112
63
‡
I
I
V
V
= 5.5 V,
= 5.5 V
V = 2.25 V
O
–30
–30
mA
mA
O
CC
41
41
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
§
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS169A SN74AS169A
MIN
60
3
MAX
MIN
75
3
MAX
f
t
t
t
t
t
t
t
t
*
MHz
ns
max
17.5
14
16.5
13
7
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
RCO
(LOAD high or low)
CLK
CLK
2
2
1
7.5
14
1
Any Q
ns
ns
ns
2
2
13
9
1.5
1.5
2
10
1.5
1.5
2
ENT
U/D
RCO
RCO
10
9
14
12
13
2
14.5
2
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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