AD7524MFKB [TI]

Advanced LinCMOSE 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER; 高级LinCMOSE 8位乘法数位类比转换器


型号：	AD7524MFKB
厂家：	TEXAS INSTRUMENTS
描述：	Advanced LinCMOSE 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER 高级LinCMOSE 8位乘法数位类比转换器转换器
文件：	总13页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

Advanced LinCMOS Silicon-Gate

Technology

J PACKAGE

(TOP VIEW)

Easily interfaced to Microprocessors

On-Chip Data Latches

OUT1

OUT2

GND

DB7

DB6

DB5

Monotonicity Over Entire A/D Conversion

Range

REF

DB0

DB1

DB2

Segmented High-Order Bits Ensure

Low-Glitch Output

Designed to Be interchangeable With

Analog Devices AD7524, PMI PM-7524, and

Micro Power Systems MP7524

DB4

DB3

Fast Control Signaling for Digital Signal

Processor Applications Including Interface

With SMJ320

FK PACKAGE

(TOP VIEW)

KEY PERFORMANCE SPECIFICATIONS

Resolution

8 Bits

Linearity error

1/2 LSB Max

5 mW Max

100 ns Max

80 ns Max

20 19

Power dissipation at V

Settling time

= 5 V

GND

DB7

Propagation delay

DB6

DB5

DB0

9 10 11 12 13

description

The AD7524M is an Advanced LinCMOS 8-bit

digital-to-analog converter (DAC) designed for

easy interface to most popular microprocessors.

NC–No internal connection

The AD7524M is an 8-bit multiplying DAC with input latches and with a load cycle similar to the write cycle of

a random access memory. Segmenting the high-order bits minimizes glitches during changes in the

most-significant bits, which produce the highest glitch impulse. The AD7524M provides accuracy to 1/2 LSB

without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically.

Featuring operation from a 5-V to 15-V single supply, the AD7524M interfaces easily to most microprocessor

buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524M an ideal choice for many

microprocessor-controlled gain-setting and signal-control applications.

The AD7524M is characterized for operation from –55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

CERAMIC CHIP

CERAMIC DIP

(J)

CARRIER

(FK)

–55°C to 125°C

AD7524MFK

AD7524MJ

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

functional block diagram

REF

S-1

S-2

S-3

S-8

OUT1

OUT2

Data Latches

GND

DB7

(MSB)

DB6

DB5

DB0

(LSB)

Data Inputs

operating sequence

t (CS)

10%

(WR)

10%

t (D)

DB0–DB7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 17 V

Voltage between R and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V +0.3 V

Reference voltage range, V

Peak digital input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA

Operating free-air temperature range, T

Storage temperature range, T

Case temperature for 60 seconds, T : FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

ref

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

= 5 V

= 15 V

MIN NOM

UNIT

MAX

Supply voltage, V

4.75

2.4

5.25

14.5

13.5

15.5

Reference voltage, V

ref

High-level input voltage, V

±10

Low-level input volage, V

0.8

1.5

CS setup time, t

°C

su(CS)

CS hold time, t

h(CS)

Data bus input setup time, t

su(D)

Data bus input hold time, t

h(D)

Pulse duration, WR low, t

w(WR)

Operating free-air temperature, T

–55

125

–55

125

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range, V = 10 V,

ref

OUT1 and OUT2 at GND (unless otherwise noted)

= 5 V

TYP

= 15 V

TYP

PARAMETER

TEST CONDITIONS

UNIT

µA

MIN

MAX

MIN

MAX

Full-range

High-level input current

Low-level input current

V = V

25°C

Full-range

25°C

–10

–1

–10

–1

V = 0

µA

DB0–DB7 at 0,

WR and CS at 0 V

Full-range

25°C

±400

±50

±200

±50

OUT1

ref

= ±10 V

Output leakage

current

pkg

DB0–DB7 at V

DD,

WR and CS at 0

Full-range

25°C

±400

±200

OUT2

ref

= ±10 V

±50

Quiescent DB0–DB7 at V min or V max

Supply current

Full-range

25°C

500

100

0.16

0.02

500

100

0.04

0.02

Standby

DB0–DB7 at 0 V or V

µA

Full-range

25°C

%/%

Supply voltage sensitivity,

∆V = 10%

SVS

∆gain/∆V

0.002

0.001

Input capacitance, DB0–DB7,

WR, CS

V = 0

kΩ

OUT1

120

DB0–DB7 at 0, WR and CS at 0 V

OUT2

OUT1

OUT2

Output

capacitance

DB0–DB7 at V , WR and CS at 0 V

Reference input impedance

(REF to GND)

operating characteristics over recommended operating free-air temperature range, V = 10 V,

ref

OUT1 and OUT2 at GND (unless otherwise noted)

= 5 V

MIN

= 15 V

MIN

PARAMETER

TEST CONDITIONS

UNIT

MAX

Linearity error

Gain error

±0.2

±1.4

±1

±0.2 %FSR

Full range

±0.6

See Note 1

%FSR

±0.5

25°C

Settling time (to 1/2 LSB)

See Note 2

100

Propagation delay from digital input to

90% of final analog output current

Full range

0.5

= ±10 V (100 kHz sinewave),

ref

WR and CS at 0, DB0–DB7 at 0

Feedthrough at OUT1 or OUT2

Temperature coefficient of gain

%FSR

25°C

0.25

%FSR/

°C

= 25°C to t

min

or t

±0.004

±0.001

max

NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = V – 1 LSB.

ref

2. OUT1 load = 100 Ω, C

ext

= 13 pF, WR at 0 V, CS at 0 V, DB0–DB7 at 0 V to V

or V

to 0 V.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

PRINCIPLES OF OPERATION

The AD7524M is an 8-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches, and

data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus

maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are

decoded and these decoded bits, through a modification in the R-2R ladder, control three equally weighted

current sources. Most applications only require the addition of an external operational amplifier and a voltage

reference.

The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire reference

current, I , is switched to OUT2. The current source 1/256 represents the constant current flowing through the

ref

termination resistor of the R-2R ladder, while the current source I

represents leakage currents to the

Ikg

substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all

digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch

capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown

in Figure 1. Analysis of the circuit for all digital inputs high is similar to Figure 1; however, in this case, I would

ref

be switched to OUT1.

Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS and

WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data activity

on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects

the analog output. When either the CS signal or WR signal goes high, the data on the DB0–DB7 inputs are

latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless

of the state of the WR signal.

The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for

2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar

operation are summarized in Tables 1 and 2, respectively.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

PRINCIPLES OF OPERATION

OUT1

30 pF

1kg

REF

OUT2

120 pF

1/256

Figure 1. AD7524M Equivalent Circuit With All Digital Inputs Low

ref

= 2 kΩ

(see Note A)

C (see Note B)

DB0–DB7

OUT1

OUT2

–

Output

GND

Figure 2. Unipolar Operation (2-Quadrant Multiplication)

ref

20 kΩ

= 2 kΩ

20 kΩ

(see Note A)

–

C (see Note B)

OUT1

Output

10 kΩ

DB0–DB7

–

OUT2

5 kΩ

GND

Figure 3. Bipolar Operation (4-Quadrant Operation)

NOTES: A.

R and R used only if gain adjustment is required.

A B

B. C phase compensation (10 – 15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

PRINCIPLES OF OPERATION

Table 1. Unipolar Binary Code

DIGITAL INPUT

(see NOTE 3)

ANALOG OUTPUT

MSB LSB

11111111

10000001

10000000

01111111

00000001

00000000

–V (255/256)

ref

–V (129/256)

ref

–V (128/256) = –V /2

ref ref

–V (127/256)

ref

–V (1/256)

ref

NOTES: 3. LSB = 1/256 (V ).

ref

Table 2. Bipolar (Offset Binary) Code

DIGITAL INPUT

(see NOTE 4)

ANALOG OUTPUT

MSB LSB

11111111

10000001

10000000

01111111

00000001

00000000

(127/128)

(128)

ref

–V (128)

ref

–V (127/128)

–V

ref

NOTES: 4. LSB = 1/128 (V ).

ref

microprocessor interfaces

Data Bus

D0–D7

Z-80A

DB0–DB7

AD7524M

OUT1

OUT2

Decode

Logic

IORQ

A0–A15

Address Bus

Figure 4. AD7524M–Z-80A Interface

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

Advanced LinCMOS 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER

SGLS028A – SEPTEMBER 1989 – REVISED MARCH 1995

PRINCIPLES OF OPERATION

Data Bus

D0–D7

6800

DB0–DB7

AD7524M

Φ2

OUT1

OUT2

Decode

Logic

VMA

A0–A15

Address Bus

Figure 5. AD7524M–6800 Interface

A8–A15

Address Bus

Decode

Logic

8-Bit

Latch

8051

AD7524M

OUT1

OUT2

ALE

DB0–DB7

Address/Data Bus

AD0–AD7

Figure 6. AD7524M–8051 Interface

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

1-Dec-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

LCCC

CDIP

Drawing

5962-87700012A

5962-8770001EA

AD7524MFKB

AD7524MJ

OBSOLETE

TBD

Call TI

AD7524MJB

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

no Sb/Br)

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF

TERMINALS

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

B SQ

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

A SQ

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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AD7524MFKB [TI]

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