ADC08B200CIVS/NOPB_技术文档

ADC08B200

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ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture Buffer

Check for Samples: ADC08B200

1

FEATURES

DESCRIPTION

The ADC08B200 is a high speed analog-to-digital

converter (ADC) with an integrated capture buffer.

The 8-bit, 200 MSPS A/D core is based upon the

proven ADC08200 with integrated track-and-hold and

is optimized for low power consumption. This device

contains a selectable size capture buffer of up to

1,024 bytes that allows fast capture of an input signal

with a slower readout rate. An on-chip clock PLL

circuit provides the option of on-chip clock rate

multiplication to provide the high speed sampling

clock.

2

•

Single-Ended Input

•

Selectable Capture Buffer Size

PLL for Clock Multiplication

Reference Ladder Top and Bottom Accessible

Linear Power Scaling with Sample Rate

FPGA Training Pattern

AEC-Q100 Grade 2 Qualified

Power-Down Feature

The ADC08B200 is resistant to latch-up and the

outputs are short-circuit proof. The top and bottom of

the ADC08B200's reference ladder are available for

APPLICATIONS

•

Laser Ranging

RADAR

connections, enabling

a

wide range of input

possibilities. The digital outputs are TTL/CMOS

compatible with a separate output power supply pin

to support interfacing with 2.7V to 3.3V logic. The

digital inputs and outputs are low voltage TTL/CMOS

compatible and the output data format is straight

binary.

Pulse Capturing

KEY SPECIFICATIONS

(PLL Bypassed)

•

Resolution 8 Bits

Maximum Sampling Frequency 200 MSPS

(min)

The ADC08B200Q runs on an Automotive Grade

Flow and is AEC-Q100 Grade 2 Qualified.

•

DNL ±0.4 LSB (typ)

The ADC08B200 is offered in a 48-pin plastic

package (TQFP) and is specified over the extended

industrial temperature range of −40°C to +105°C. An

evaluation board is available to assist in the easy

evaluation of the ADC08B200.

ENOB (f_IN= 49 MHz) 7.2 bits (typ)

THD (f_IN= 49 MHz) −53 dBc (typ)

Power Consumption

–

Operating (50 MHz) Input 2 mW / Msps (typ)

Power Down 2.15 mW (typ)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC08B200

SNAS388F –MARCH 2007–REVISED APRIL 2013

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PIN CONFIGURATION

V

A

1

36

35

34

33

32

31

30

29

28

27

26

25

D0

D1

D2

D3

VDR

DRDY

DR GND

D4

D5

D6

2

GND

VRT

V

A

3

4

5

GND

V

IN

6

ADC08B200

7

SIG GND

GND

8

V

RM

9

V

RB

10

11

12

GND

D7

ASW

V

A

Figure 1. TQFP Package

See Package Number PFB0048A

Block Diagram

V_A

V_P

V_D

V_DR

REN

READ

CONTROL

V

RCLK

RT

17

8

Read Pointer

ENCODER

& ERROR

CORRECTION

COARSE/FINE

COMPARATORS

1

8

OUTPUT

DRIVERS

DATA

OUT

MUX

17

8

CAPTURE

BUFFER

SWITCHES

MUX

V

RM

8

ENCODER

& ERROR

CORRECTION

Write

Pointer

COARSE/FINE

COMPARATORS

EF

FF

FLAG

LOGIC

256

WRITE

CONTROL

V

RB

CLOCK

GEN

MULT(1:0)

D

Q

WENSYNC

Sampling Clock

DR

BSIZE(1:0)

V_IN

CLK

V_IN

RESET WEN

PDADC PDGND ASW

GND

(pin 30)

GND

2

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Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

V

A

6

V_IN

Analog signal input. Conversion range is V_RBto V_RT

.

6

GND

Analog Input that is the high (top) side of the reference ladder

of the ADC. Voltage on V_RTand V_RBinputs define the V_IN

V

A

3

9

V_RT

9

conversion range. V_RTshould be more positive than V_RB

.

Bypass well.

Analog input that is the mid-point of the reference ladder. This

pin should be bypassed to a quiet point in the ground plane

with a 0.1 µF capacitor. DO NOT LOAD this pin.

3

10

V_RM

Analog Input that is the low side (bottom) of the reference

ladder of the ADC. The voltages on V_RTand V_RBinputs define

the V_INconversion range. Bypass well.

10

V_RB

GND

Chip Power Down input. When this pin is high, the entire chip

is in the Power Down mode. Any data in the capture buffer is

lost and the output pins hold the last byte that was output.

13

41

PD

ADC Power Down Input. When this pin is high, the ADC is

powered down. The capture buffer is active and the data

within it may be clocked out.

PDADC

CMOS/TTL compatible digital clock Input. When the PLL is

bypassed, the clock signal at this pin is the ADC sampling

clock and V_INis sampled on the rising edge of this clock input.

When the PLL is enabled, the signal at this input is the

reference clock, which is multiplied to provide a higher

frequency sample clock.

46

CLK

V

D

Buffer Read Clock input. When the capture buffer is enabled,

this input signal is used to read the data from the internal

buffer. The data output and the buffer empty flag (EF)

transition with the rise of this clock.

19

17

RCLK

WEN

Write Enable input. A high level at this input causes a byte of

data to be written into the capture buffer with the rise of each

sample clock.

GND

Read Enable input. A high level at this input causes a byte of

data to be read from the capture buffer with the rise of each

RCLK input. This rise of the REN input should be synchronous

with the RCLK input and should not be high while the WEN

input is high.

20

REN

Device Reset Input. A high level at this input resets all control

logic on the chip.

22

37

RESET

OE

Output Enable input. A high level at this input enables the

output buffers. A low level at this input puts the digital data

output pins into a high impedance state.

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Pin No.

Symbol

Equivalent Circuit

Description

V

D

Output Edge Select or Test Mode Enable input. If this input is

high, the data outputs transition with the rising edge of the

DRDY output. If this input is low, the data outputs transition

with the falling edge of the DRDY output. Forcing a potential

of V_A/2 at this input enables the Test Mode.

50k

14

OEDGE/TEN

GND

Synchronized WEN output. The WEN control input is

synchronized on-chip with the internal sample clock and is

provided at this output.

18

31

WENSYNC

DRDY

V

D

Data Ready output. This signal transitions with the transition of

the digital data outputs and indicates that the output data is

ready.

26 thru 29

and

D0–D7

Digital data digital Outputs. D0 is the LSB, D7 is the MSB.

33 thru 36

Buffer Full Flag. This output is high when the capture buffer is

full.

16

15

FF

EF

GND

Buffer Empty Flag. This output is high when the capture buffer

is empty.

Auto-Stop Write input. This pin has a dual function. With the

buffer enabled, this pin acts as the ASW input. When this

input is high, writing to the buffer is halted when the capture

buffer is full (FF high). When the buffer is disabled, this pin is

ignored. When the device is in Test Mode, this pin acts as the

Output Edge Select signal, functioning in accordance with the

description of the OEDGE/TEN pin.

V

D

25

ASW

Buffer Size input. These inputs determine the size of the

buffer, as described in the Functional Description.

23,24

38, 39

1, 4, 12

BSIZE(1:0)

MULT(1:0)

V_A

Clock Multiply Factor input. These inputs determine the

internal clock PLL's multiplication factor.

GND

Positive analog supply pin. Connect to a voltage source of

+3.3V.

43, 44, 48

40

V_P

V_D

PLL supply pin. Connect to a voltage source of +3.3V.

Digital core supply pin. Connect to a voltage source of +3.3V.

Power supply for the output drivers. Connect to a voltage

source of 2.7V to V_D.

32

V_DR

2, 5, 8, 11, 21,

42, 45, 47

GND

The ground return for the chip core.

7

SIG GND

DR GND

Analog input signal ground.

30

The ground return for the output drivers.

4

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

(1)(2)(3)

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V_A, V_P, V_D, V_DR

Driver Supply Voltage (V_DR

Voltage on Any Input or Output Pin

)

-0.3V to 3.8V

-0.3V to V_A+0.3V

−0.3V to V_A

GND to V_A

±1 mA

)

Reference Voltage (V_RT, V_RB

)

Input Current, Data Outputs

(4)

Input Current all other pins

±25 mA

(4)

Package Input Current

±50 mA

(5)

Power Dissipation at T_A= 25°C

See

(6)

ESD Susceptibility

Human Body Model

Machine Model

2500V

200V

Charged Device Model

1000V

Soldering Temperature, Infrared, 10 seconds

Storage Temperature

235°C

−65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical

Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the

device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

(4) When the input voltage at any pin exceeds the power supplies (that is, less than GND or DR GND, or greater than V_A, V_P, V_Dor V_DR),

the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can

safely exceed the power supplies with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax − T_A) / θ_JA

.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO

Ohms.

(1)(2)

OPERATING RATINGS

Operating Temperature Range

−40°C ≤ T_A≤ +105°C

Supply Voltage (V_A)

+3.0V to +3.6V

+2.7V to (V_A+ 0.3V)

V_A+ 0.3V

Driver Supply Voltage (V_DR

)

Maximum Supply Voltage V_D, V_P

CLK Frequency

PLL Bypassed

PLL used

1 to 210 MHz

15 to 105 MHz

2 - 210 MHz

(3)

RCLK Frequency

RCLK Duty Cycle

35% to 65%

Ground Difference |GND - DR GND|

0V to 300 mV

0.5V to (V_A− 0.3V)

0V to (V_RT− 0.5V)

0.5V to 2.3V

Upper Reference Voltage (V_RT

)

Lower Reference Voltage (V_RB

)

Reference Delta (V_RT− V_RB

)

V_INVoltage Range

V_RBto V_RT

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical

Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the

device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

(3) RCLK should be stopped with the buffer is not being read.

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PACKAGE THERMAL RESISTANCE

Package

θ_JA

48-Lead TQFP

76 °C/W

CONVERTER ELECTRICAL CHARACTERISTICS

The following specifications apply for V_A= V_D= V_P= V_DR= +3.3V_DC, V_RT= +1.9V, V_RB= 0.3V, C_L= 10 pF, f_CLK= 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J=

(1)(2)

25°C

Units

(Limits)

(3)

Parameter

Test Conditions

Typ⁽³⁾Limits

DC ACCURACY

INL

Integral Non-Linearity

Differential Non-Linearity

Missing Codes

±0.55

±0.40

±1.3

±0.9

0

LSB (max)

(max)

DNL

−80

0

mV (min)

mV (max)

FSE

Full Scale Error

−39

V_OFF

Zero Scale Offset Error

55

70

mV (max)

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V_RB

V_RT

V (min)

V (max)

pF

V_IN

C_IN

Input Voltage

1.6

(CLK LOW)

(CLK HIGH)

3

4

V_INInput Capacitance

V_IN= 0.75V +0.5 Vrms

pF

R_IN

Analog Input Resistance

Full Power Bandwidth

>1

500

MΩ

FPBW

MHz

V_A

0.5

V (max)

V (min)

V (max)

V (min)

V (max)

Ω (min)

Ω (max)

V_RT

Top Reference Voltage

Bottom Reference Voltage

Reference Voltage Delta

1.9

0.3

1.6

160

V

_RT− 0.5

V_RB

0

0.5

V_RT

V_RB

-

2.3

145

200

R_REF

Reference Ladder Resistance V_RTto V_RB

DIGITAL INPUT CHARACTERISTICS

OEDGE/TEN

Others

2.2

1.6

0.9

1.3

2.7

2.1

0.5

0.7

V (min)

V (max)

V_IH

V_IL

Logic High Input Voltage

Logic Low Input Voltage

OEDGE/TEN

Others

(1) The analog inputs are protected as shown below. Input voltage magnitudes up to V_A+ 300 mV or to 300 mV below GND will not

damage this device. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV.

For example, if V_Ais 3.3V_DCthe input voltage must be ≤3.4V_DCto ensure accurate conversions.

V

A

TO INTERNAL

CIRCUITRY

V

IN

GND

(2) To ensure accuracy, it is required that V_A, V_D, V_Pand V_DRbe well bypassed. Each supply pin should be decoupled with separate

bypass capacitors.

(3) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL

(Average Outgoing Quality Level).

6

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for V_A= V_D= V_P= V_DR= +3.3V_DC, V_RT= +1.9V, V_RB= 0.3V, C_L= 10 pF, f_CLK= 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J=

25°C ⁽¹⁾⁽²⁾

Units

(Limits)

(3)

Parameter

Test Conditions

Typ⁽³⁾Limits

Operational

Test Mode

10

70

µA

OEDGE/TEN

Others

I_IH

Logic High Input Current

V_IH= V_DR= V_A= 3.6V

10

nA

Operational

Test Mode

−10

−600

µA

OEDGE/TEN

I_IL

Logic Low Input Current

Logic Input Capacitance

V_IL= 0V, V_DR= V_A= 3.0V

Others

−50

nA

pF

C_IN

3

DIGITAL OUTPUT CHARACTERISTICS

V_OH

V_OL

High Level Output Voltage

Low Level Output Voltage

Digital Output Capacitance

V_A= V_DR= 3.0V, I_OH= −5 mA

3.0

0.25

2

2.4

0.5

V (min)

V (max)

pF

V_A= V_DR= 3.0V, I_OL= 5 mA

C_OUT

DYNAMIC PERFORMANCE

f_IN= 10 MHz, V_IN= FS − 0.25 dB

7.4

7.2

Bits

Bits (min)

Bits

f_IN= 49 MHz, V_IN= FS − 0.25 dB

6.8

ENOB

Effective Number of Bits

f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

f_IN= 10 MHz, V_IN= FS − 0.25 dB

7.2

7.0

Bits

6.9

Bits

46

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB

45

42.7

43.7

dBc (min)

dBc

SINAD Signal-to-Noise & Distortion

f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

f_IN= 10 MHz, V_IN= FS − 0.25 dB

45

44

dBc

43.4

47

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB

46.3

45.8

45.6

56

dBc (min)

dBc

SNR

SFDR

THD

HD2

Signal-to-Noise Ratio

f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

f_IN= 10 MHz, V_IN= FS − 0.25 dB

dBc

\dBc

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB

56

dBc

Spurious Free Dynamic Range f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

56

dBc

50

dBc

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

f_IN= 10 MHz, V_IN= FS − 0.25 dB

49.7

−55

−53

−49

-47.5

−57

−55

−50

−49.9

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB

dBc

Total Harmonic Distortion

2nd Harmonic Distortion

f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

dBc

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

f_IN= 10 MHz, V_IN= FS − 0.25 dB

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

dBc

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

dBc

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for V_A= V_D= V_P= V_DR= +3.3V_DC, V_RT= +1.9V, V_RB= 0.3V, C_L= 10 pF, f_CLK= 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J=

25°C ⁽¹⁾⁽²⁾

Units

(Limits)

(3)

Parameter

Test Conditions

Typ⁽³⁾Limits

f_IN= 10 MHz, V_IN= FS − 0.25 dB

−62

−63

dBc

f_IN= 49 MHz, V_IN= FS − 0.25 dB

dBc

HD3

IMD

3rd Harmonic Distortion

Intermodulation Distortion

f_IN= 49 MHz, V_IN= FS − 0.25 dB, PLL x8

f_IN= 100 MHz, V_IN= FS − 0.25 dB

−62

dBc

−56

dBc

f_IN= 100 MHz, V_IN= FS − 0.25 dB, PLL x4

−54.6

dBc

f₁= 11 MHz, V_IN= FS − 6.25 dB

f₂= 12 MHz, V_IN= FS − 6.25 dB

-50

dBc

POWER SUPPLY CHARACTERISTICS

DC Input

72.5

mA

mA (max)

mA

I_A

Analog Supply Current

f_IN= 50 MHz

76.8

0.3

1.2

1.6

38

88.3

PD High

DC Input, Buffer bypassed

f_IN= 50 MHz, Buffer bypassed

mA

2.1

mA (max)

mA

(4)

I_D

Digital Core Supply Current

f_IN= 50 MHz, 1k writing to Buffer

42.4

(4)

PDADC High, reading Buffer

1.1

0.3

8.8

3.6

60

mA

PD High

mA

PLL x2

10.1

4.3

mA (max)

µA

I_P

PLL Supply Current

PLL disabled

PD High

DC Input

f_IN= 50 MHz

PD High

7

mA

I_DR

Output Driver Supply Current

41

57

mA (max)

µA

25

DC Input, Buffer bypassed, PLL x2

97.5

164.6

20

mA

mA (max)

mA

(5)

50 MHz Input, writing to Buffer, PLL X2

I_A+ I_D

198

(5)

+ I_P

I_DR

+

Total Operating Current

PDADC = Hi, reading Buffer,

RCLK = 200 MHz, D.C. input

PD High

0.65

306

mA

DC Input, Buffer & PLL bypassed

mW

50 MHz Input, writing to Buffer, PLL X2

543

653

mW (max)

(5)

PC

Power Consumption

(5)

PDADC High, reading Buffer, PLL disabled

PD High

66

mW

2.15

D.C. Power Supply Rejection

Ratio

PSRR₁

PSRR₂

FSE change with 3.0V to 3.6V change in V_A

48

dB

A.C. Power Supply Rejection

Ratio

SNR reduction with 200 mV at 10MHz on supply

TBD

(4) This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.

(5) This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.

8

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CONVERTER TIMING CHARACTERISTICS

The following specifications apply for V_A= V_DR= +3.3V_DC, V_RT= +1.9V, V_RB= 0.3V, C_L= 50 pF, f_CLK= 200 MHz at 50% duty

cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C

(1)(2)

Units

(3)

Parameter

Test Conditions

PLL Disabled

Typ

Limits

(Limits)

MHz (min)

MHz

210

200

105

f_C1

Maximum Input Clock Rate

Using PLL

15

1

PLL Disabled

f_C2

Minimum Input Clock Rate

Using PLL

15

MHz

(4)

t_CL

Minimum CLK Low Time

Minimum CLK High Time

Maximum RCLK Rate

1.7

200

ns (min)

MHz (min)

MHz

(4)

(5)

(4)

t_CH

f_RC1

f_RC2

t_RCL

t_RCH

ΔDC

210

2

Minimum RCLK Rate

Minimum RCLK Low Time

Minimum RCLK High Time

DRDY to RCLK Duty Cycle Delta

2.0

±3

ns (min)

%

0.3

−0.8

4.0

ns (min)

ns (max)

t_SU

t_RR

REN to RCLK Set-Up Time

−0.4

RCLK Rising Edge to DRDY Rising

Edge

2.4

5.9

ns (min)

ns (max)

3.8

RCLK Falling Edge to DRDY Falling

Edge

t_RF

3.5

160

2.3

ns

ps

t_SKDR

t_SKR

t_SKEF

t_CFF

Skew of DRDY Rising Edge to DATA

RCLK Falling Edge to First DATA

Byte

1.8

7.4

ns (min)

ns (max)

Skew of DRDY Rising Edge to EF

Rising Edge

36

4.2

ps

ns

CLK Rising Edge to FF Rising Edge

FF Rising Edge to WENSYNC Falling

Edge

t_FFW

ASW pin high

CLK Rising Edge to WENSYNC

Rising Edge

2.4

5.5

ns (min)

ns (max)

t_CW

PLL Disabled

3.5

Write Clock

Cycles (min)

(4)

t_RST

RESET Pulse Width

4

C_L= 10 pF

C_L= 20 pF

0.9

2

ns

Output Data Rise Time

(0.4V to 2.5V)

t_r

(1) The analog inputs are protected as shown below. Input voltage magnitudes up to V_A+ 300 mV or to 300 mV below GND will not

damage this device. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV.

For example, if V_Ais 3.3V_DCthe input voltage must be ≤3.4V_DCto ensure accurate conversions.

V

A

TO INTERNAL

CIRCUITRY

V

IN

GND

(2) To ensure accuracy, it is required that V_A, V_D, V_Pand V_DRbe well bypassed. Each supply pin should be decoupled with separate

bypass capacitors.

(3) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL

(Average Outgoing Quality Level).

(4) This parameter is specified by design and/or characterization and is not production tested.

(5) RCLK should be stopped with the buffer is not being read.

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CONVERTER TIMING CHARACTERISTICS (continued)

The following specifications apply for V_A= V_DR= +3.3V_DC, V_RT= +1.9V, V_RB= 0.3V, C_L= 50 pF, f_CLK= 200 MHz at 50% duty

cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C ⁽¹⁾⁽²⁾

Units

(Limits)

(3)

Parameter

Test Conditions

Typ

Limits

C_L= 10 pF

C_L= 20 pF

1.4

ns

Output Data Fall Time

(2.4V to 0.4V)

t_f

3.2

7.0

5.5

6.5

5.5

3.8

ns

4.0

11.7

ns (min)

ns (max)

Reading Buffer

RCLK Rising Edge to Data Output

Fall to 0.4V

t_ODF

Buffer bypassed, PLL disabled

Reading Buffer

ns

2.3

13.1

ns (min)

ns (max)

RCLK Rising Edge to Data Output

Rise to 2.5V

t_ODR

Buffer bypassed, PLL disabled

Reading Buffer

ns

RCLK Rising Edge to Data Output

Fall to 2.5V

2.4

5.5

ns (min)

ns (max)

t_OHF

t_OHR

RCLK Rising Edge to Data Output

Rise to 0.4V

2.6

6.9

ns (min)

ns (max)

Reading Buffer

4.5

Output Falling (2.4V to 0.4V)

Output Rising (0.4V to 2.5V)

PLL Enabled

1.5

2.3

20

2

V / ns

t_SLEW

Output Slew Rate

V / ns

µs

t_DRDY1

t_DRDY2

PD Low to Device Active

PLL Bypassed

µs

PDADC Low to Device Active

Pipeline Delay (Latency)

2

6

Clock Cycles

ns

PLL on

PLL off

3.4

3.9

2

CLK Rise to

Acquisition of Data

t_AD

Sampling (Aperture) Delay

Aperture Jitter

ns

PLL Bypassed

ps rms

t_AJ

(6)

PLL Enabled in x8 mode

7

(6) Jitter with the PLL enabled is measured with 32k samples and the PLL in the x8 multiplication mode.

SPECIFICATION DEFINITIONS

APERTURE (SAMPLING) DELAY is that time delay after the rise of the sample clock until the input signal is

sampled within the ADC.

APERTURE JITTERis the variation in aperture delay from sample to sample. Aperture jitter shows up as input

noise.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one

clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. Measured at 200 MSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below V_RTand

is defined as:

FSE = V_max+ 1.5 LSB – V_RT

where

•

V_maxis the voltage at which the transition to the maximum (full scale) code occurs

(1)

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

10

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zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code

value. The end point test method is used. Measured at 200 MSPS with a ramp input.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the

power in the second and third order intermodulation products to the power in one of the original

frequencies. IMD is usually expressed in dBFS.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These

codes cannot be reached with any input value.

OFFSET ERRORis the error in the input voltage required to cause the first code transition. It is defined as the

difference between the voltage required to cause the first code transition and the ideal voltage (1/2 LSB)

to cause that transition.

V_OFF= V_ZT− 1/2 LSB = V_ZT- (V_RT− V_RB) / 512

where

•

V_ZTis the first code transition input voltage

(2)

OUTPUT DELAY is the time delay after the rising edge of the RCLK input before the data update is present at

the output pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of CLK or RCLK output.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that

data is presented to the output driver stage. New data is available at every clock cycle, but the data lags

the conversion by the Pipeline Delay plus the Output Delay.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC08B200, PSRR1 is the ratio of the change in Full-Scale Error that results from

a change in the DC power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c.

signal riding upon the power supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output

to the rms value of the sum of all other spectral components below one-half the sampling frequency, not

including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of

the input signal at the output to the rms value of all of the other spectral components below half the clock

frequency, including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR)is the difference, expressed in dB, between the rms values of the

input signal at the output and the peak spurious signal, where a spurious signal is any signal present in

the output spectrum that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

2

f10

A

+ . . . + A

f2

THD = 20 x log

2

A

f1

where

•

A_f1is the RMS power of the fundamental (output) frequency

A_f2through A_f10are the RMS power of the first 9 harmonic frequencies in the output spectrum

(3)

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TIMING DIAGRAMS (PLL BYPASSED)

Sampling

Clock

WEN

FF asserted

EF cleared

Buffer Full

FF cleared

EF asserted

Buffer

Contents

Buffer Empty

RCLK

REN

Figure 2. ADC08B200 Data Capture and Read Operation

t

AD

Vin

Actual Sample Point

Input

CLK

4 Clock Rises

WEN

WENSYNC

FF

t

CW

t

FFW

t

CFF

Figure 3. ADC08B200 Capture and Write Enable Timing

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#1

#2

#3

#4

CLK

WEN

t

CL

CH

Asynchronous Assertiopn

t

FFW

t

CW

WENSYNC

t

CFF

FF

Figure 4. ADC08B200 Buffer Write Timing

RCLK

t

RCH RCL

t

SU

REN

DRDY

DATA

t

RF

RR

OEDGE = 1

t

ODF

t

SKDR

t

OHF

ODR

SKR

2.5V

SAMPLE 1 SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5

0.4V

t

OHR

Figure 5. ADC08B200 Buffer Read Timing (OEDGE/TEN = 1)

#1

#2

#3

#4

RCLK

REN

t

RR

t

RCH RCL

t

RR

t

RF

OEDGE = 0

DRDY

DATA

t

SKDR

SKR

SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5 SAMPLE 6

SAMPLE 1

Figure 6. ADC08B200 Buffer Read Timing (OEDGE/TEN = 0)

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CLK

t

RR

t

RL

RH

DRDY

t

ODF

OHF

ODR

OHR

t

SKDR

2.5V

0.4V

2.5V

DATA

0.4V

Figure 7. ADC08B200 Buffer Bypassed Timing

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TYPICAL PERFORMANCE CHARACTERISTICS

V_A= V_D= V_P= V_DR= 3.3V, f_CLK= 200 MHz, f_IN= 50 MHz, PLL & Buffer bypassed, T_A= 25°C, unless otherwise stated

INL

INL vs. Supply Voltage

Figure 8.

Figure 9.

INL vs. Temperature

INL vs. Sample Rate

Figure 10.

DNL

Figure 11.

DNL vs. Supply Voltage

Figure 12.

Figure 13.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_P= V_DR= 3.3V, f_CLK= 200 MHz, f_IN= 50 MHz, PLL & Buffer bypassed, T_A= 25°C, unless otherwise stated

DNL vs. Temperature

DNL vs. Sample Rate

Figure 14.

Figure 15.

Offset Error vs. Temperature

Full Scale Error vs. Temperature

Figure 16.

Figure 17.

SNR vs. Supply Voltage

SNR vs. Input Frequency

Figure 18.

Figure 19.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_P= V_DR= 3.3V, f_CLK= 200 MHz, f_IN= 50 MHz, PLL & Buffer bypassed, T_A= 25°C, unless otherwise stated

SNR vs. Temperature

SNR vs. Sample Rate

Figure 20.

Figure 21.

SNR vs. Clock Duty Cycle

Distortion vs. Supply Voltage

Figure 22.

Figure 23.

Distortion vs. Input Frequency

Distortion vs. Temperature

Figure 24.

Figure 25.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_P= V_DR= 3.3V, f_CLK= 200 MHz, f_IN= 50 MHz, PLL & Buffer bypassed, T_A= 25°C, unless otherwise stated

Distortion vs. Sample Rate

Distortion vs. Clock Duty Cycle

Figure 26.

Figure 27.

SINAD vs. Supply Voltage

SINAD vs. Input Frequency

Figure 28.

Figure 29.

SINAD vs. Temperature

SINAD vs. Sample Rate

Figure 30.

Figure 31.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_P= V_DR= 3.3V, f_CLK= 200 MHz, f_IN= 50 MHz, PLL & Buffer bypassed, T_A= 25°C, unless otherwise stated

SINAD vs. CLK Duty Cycle

SFDR vs. Supply Voltage

Figure 32.

Figure 33.

SFDR vs. Input Frequency

SFDR vs. Temperature

Figure 34.

Figure 35.

SFDR vs. Sample Rate

SFDR vs. Clock Duty Cycle

Figure 36.

Figure 37.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_A= V_D= V_P= V_DR= 3.3V, f_CLK= 200 MHz, f_IN= 50 MHz, PLL & Buffer bypassed, T_A= 25°C, unless otherwise stated

Power Consumption vs. Sample Rate

Power Consumption vs. Temperature

Figure 38.

Figure 39.

Spectral Response @ f_IN= 49 MHz

Spectral Response @ f_IN= 76 MHz

Figure 40.

Figure 41.

Spectral Response @ f_IN= 99 MHz

Intermodulation Distortion

Figure 42.

Figure 43.

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FUNCTIONAL DESCRIPTION

The ADC08B200 integrates an 8-bit, high speed ADC and a configurable capture buffer of up to 1 kilobyte,

allowing the sampling and processing tasks to be independent of each other. This functionality is intended for

those applications that need to sample an input signal at a high rate and then read the collected samples at a

slower rate. The Timing Diagrams illustrate the operation of the ADC08B200.

The analog input signal that is within the voltage range set by V_RTand V_RBis digitized to eight bits. Input voltages

below V_RBwill cause the output word to consist of all zeroes. Input voltages above V_RTwill cause the output word

to consist of all ones.

The ADC08B200 exhibits a power consumption that is proportional to frequency, limiting power consumption to

what is needed at the clock rate that is used. This, its excellent performance over a wide range of clock

frequencies and the incorporation of a capture buffer make ADC08B200 an ideal choice for many 8-bit ADC

applications.

Data is acquired at the rising edge of the sample clock and, in the buffer bypass mode, the digital equivalent of

that data is available at the digital outputs 6 clock cycles plus t_ODlater. When the Buffer is enabled, the

converted data is written to the buffer with each internal conversion clock cycle and can be read out with the

RCLK signal. The ADC08B200 will convert as long as a CLK signal is present, but when using the buffer no

writing to the buffer will occur when that buffer is full. The output coding is straight binary.

The entire device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the entire

device is in the power down mode, consuming very little power. Holding the clock input low after raising the

Power Down pin will further reduce the power consumption in the power down mode.

When the PDADC pin is high, only the A/D converter itself is in the power down mode. The rest of the chip is left

powered up so that the capture buffer may be read. If both the PD and PDADC pins are high, the PD pin

dominates and the entire device is powered down.

The A/D converter sample clock can be either the clock signal at the CLK input pin or a multiplied version of that

clock. The clock multiplier can be 2, 4 or 8. In any case, the sample clock is also used to write the converter data

into the capture buffer when that buffer is used.

As long as the chip is not in a power down state and there is a clock signal present, the A/D converter is

converting the input signal. However, the data is stored into the capture buffer, when the buffer is used, only

while the Write Enable (WEN) input is high. The data is read from the capture buffer with the RCLK signal, which

can be a free running clock, while the Read Enable (REN) signal is high.

Note that the capture buffer on this chip must be entirely filled to its configured size before reading its contents

can begin. It is not possible to write to and read from the buffer at the same time and the WEN and REN inputs

should not be high at the same time. If they are high at the same time, the REN input is ignored. This is true

even if the REN input is high first and a read operation is progressing normally when the WEN input goes high.

Asserting the WEN input while REN is high will cause the read operation to be aborted, an internal buffer reset to

be issued (resetting the pointers) and a capture operation to begin. Although this device is intended for fast

capture and slower read out applications, it is possible for the RCLK to operate at the same rate or faster than

the sample clock.

Two status flags are provided to manage the capture buffer. As the name suggests, the Full Flag (FF) goes high

when the buffer is full. The next sample clock rise after the assertion of FF will begin writing over the oldest data

because the write pointer will "wrap around". This is called an "over run" condition. Similarly, the Empty Flag (EF)

indicates that the last of the data has been read and the buffer is empty. When EF goes high, the DRDY and

Data outputs stop switching and both DRDY and the Data lines remain low if OEDGE=1. Both remain high if

OEDGE=0.

The user has the option to stop writing to the buffer automatically upon a buffer full condition with the use of the

ASW (Auto Stop Write) input. If the ASW input is low, the buffer will be continually written to, resulting in the

possibility of the write pointer "wrapping around" and the data continually being overwritten as long as there is a

clock and the WEN input is high. If the ASW input is high, the write operation stops upon reaching the "full"

condition.

FF goes low upon device reset and when the "full" condition is removed by starting a transfer operation with the

assertion of REN. The EF output goes low when the "empty" condition is removed by starting a capture operation

with the raising of WEN. The EF output goes high upon device reset because resetting empties the buffer.

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The RESET signal resets the read and write pointers and the EF and FF flags. The RESET signal also stops the

read operation early (before the EF flag goes high). Consequently, only a partial read is performed if the RESET

input goes high while a buffer read out is under way. This allows the buffer pointers to be reset so a new capture

operation can begin. The RESET signal has no effect upon the A/D converter, which has its own internal Power-

On Reset circuit.

Note that the RCLK input does not need to be as noise (jitter) free as does the CLK signal. The reason for this is

that RCLK is only used to read the Capture Buffer, while the CLK signal is either the ADC sample clock or is the

reference for the internal PLL that generates the sample clock for the ADC. Consequently, CLK jitter directly

affects the ADC's SNR performance. There is no requirement for the RCLK to have any fixed relationship with

CLK in terms of phase or frequency.

Applications Information

REFERENCE INPUTS

The reference inputs V_RTand V_RBare the top and bottom of the reference ladder, respectively. Input signals

between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should

be within the range specified in OPERATING RATINGS and ELECTRICAL CHARACTERISTICS. Any device

used to drive the reference pins should be able to source sufficient current into the V_RTpin and sink sufficient

current from the V_RBpin to maintain the desired voltages.

Choke

+3.3V

+

10 mF

0.1 mF

1

4

32

12 43 44 48

V_P

40

V_A

V_DR

V_D

6

7

26

27

28

29

33

34

35

36

V

IN

D7

D6

D5

D4

D3

D2

D1

D0

+3.3V

V

GND

RT

IN

V

110

1

1.9V

nomina

%

3

9

l

+

0.1 mF

301

1

10 mF

31

37

V

RM

DRDY

OE

%

0.1 mF

ADC08B200

10

V

RB

19

RCLK

39

38

MUL1

MUL0

18

14

WENsync

OEDGE

23

24

15

16

BSIZE1

BSIZE0

EF

FF

20

17

25

REN

WEN

ASW

22

RESET

41

13

PDADC

PD

DR GND

AGND

CLK

46

5

2

8

11

30

21 42 45 47

Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for

some applications.

Figure 44. Simple, Low Component Count Reference Biasing

The reference bias circuit of Figure 44 is very simple and the performance is adequate for many applications.

However, circuit tolerances will lead to a wide reference voltage range. Better reference tolerance can be

achieved by driving the reference pins with low impedance sources.

The circuit of Figure 45 will allow a more accurate setting of the reference voltages, with upper and lower

reference accuracies of about 16 mV, or about 2 1/2 LSB. The upper amplifier must be able to source the

reference current as determined by the value of the reference resistor and the value of (V_RT− V_RB). The lower

amplifier must be able to sink this reference current. Both amplifiers should be stable with a capacitive load.

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The LM8272 was chosen because of its rail-to-rail input and output capability, its high output current capability

and its ability to drive large capacitive loads.

The divider resistors at the inputs to the amplifiers could be changed to suit the application reference voltage

needs, or the divider can be replaced with potentiometers or DACs for precise settings. The bottom of the ladder

(V_RB) may be returned to ground if the minimum input signal excursion is 0V.

V_RTshould always be at least 0.5V more positive than V_RB. While V_RTmay be as high as the V_Asupply voltage

and V_RBmay be as low as ground, the difference between these two voltages (V_RT− V_RBshould not exceed 2.3V

to prevent a slight waveform distortion.

The V_RMpin is the center of the reference ladder and should be bypassed to a quiet point in the ground plane

with a 0.1 µF capacitor. DO NOT leave this pin open and DO NOT load this pin with more than 10µA.

+3.3V

Choke

+

10 mF

+

10 mF

470W

0.1 mF

+3.3V

+

1 mF

10 mF

0.1 mF

1

4

32

12 43 44 48

40

D

604W

LM4040-2.5

1/2

LM8272

V

3

V

P

V

8

+

A

DR

6

7

3

9

26

27

28

29

33

34

35

36

V

IN

V

IN

1

D7

2

-

D6

D5

D4

D3

D2

D1

D0

4

V

IN

GND

0.1 mF

0.01 mF

V

RT

1 mF

4.7k

1.62k

31

37

V

DRDY

OE

RM

0.1 mF

4.7k

ADC08B200

10

V

19

RB

RCLK

1 mF

39

38

0.01 mF

MUL1

MUL0

18

14

0.1 mF

WENsync

OEDGE

6

-

7

23

24

15

16

5

+

BSIZE1

BSIZE0

EF

FF

1/2

LM8272

20

17

25

22

REN

WEN

ASW

309W

RESET

41

13

PDADC

PD

CLK

DR GND

GND

11

5

8

30 46

21 42 45 47

2

Figure 45. Driving the Reference to Force Desired Values Requires Driving with a Low Impedance

Source

THE ANALOG INPUT

The analog input of the ADC08B200 is a switch followed by an integrator. The input capacitance changes with

the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature

of the analog input causes current spikes at the input that result in voltage spikes there. These spikes are normal

and need not be eliminated. However, any amplifier used to drive the analog input must be able to settle within

the clock high time. Using a single pole RC filter between the amplifier and the ADC input will minimize the

effects of these transients on the driving amplifier. The cutoff frequency of this filter should be approximately the

same as the ADC sample rate for Nyquist applications. Choose a capacitor value of 33 pF to 51 pF and a

resistor value according to the formula

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1

R =

2 p (C + 6 pF) f_S

where

•

f_Sis the converter sample rate

(4)

The added 6 pF in the formula above allows for the ADC input capacitance and a small board capacitance. For

undersampling applications, eliminate the capacitor and chose a pole frequency of about 2 to 3 times the

maximum input frequency, using the ADC input capacitance when the clock is high, plus trace capacitance, for

the filter capacitor. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but

also upon the circuit layout and board material. The LMH6702 and the LMH6628 have been found to be good

amplifiers to drive the ADC08B200.

Figure 46 shows an example of an input circuit using the LMH6702 at the ADC08B200 input. The input amplifier

should incorporate some gain as most operational amplifiers exhibit better phase margin and transient response

with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and

operate the amplifier at a higher gain, as indicated in Figure 46.

This will provide optimum SNR performance for Nyquist applications. Best THD performance is realized when the

capacitor and resistor values are both zero, but this would compromise SNR and SINAD performance. Generally,

the capacitor should not be added for undersampling applications.

The circuit of Figure 46 has both gain and offset adjustments. If you eliminate these adjustments normal circuit

tolerances may result in signal clipping unless care is exercised in the worst case analysis of component

tolerances and the input signal excursion is appropriately limited to account for the worst case conditions.

Full scale and offset adjustments may also be made by adjusting V_RTand V_RB, perhaps with the aid of a pair of a

DACs or a dual DAC. Of course, this circuit may be implemented without provision for offset and gain

adjustments, but component tolerances would require the planned use of less than the full dynamic range of the

ADC.

One advantage of having access to the bottom of the reference ladder (V_RB) is that the voltage at the analog

input does not have to come to 0V to cause an output code of zero. If V_RBis set high enough, the negative

supply on the amplifier driving the analog input may be at ground. How high V_RBneeds to be set to allow this will

depend upon the amplifier type and how close to its negative supply (or ground) the output can go while

maintaining linearity. This might be 100mV to 150mV for a rail-to-rail output amplifier or 1 Volt for other

amplifiers.

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Choke

www.ti.com

+3.3V

+

10 µF

+

+5V

10 µF

0.1µF

200

0.1 µF

Gain Adjust

0.1 µF

1

4

32

12 43 44 48

V_P

40

12

-

22

V_A

V_D

V_DR

*

6

7

3

9

10

LMH6702

+

V_IN

26

27

28

29

33

34

35

36

D7

D6

D5

D4

D3

D2

D1

D0

240

Signal

Input

10 pF

V_INGND

V_RT

*

100

47

0.1 µF

0.33 µF

*

4.7k

31

37

V_RM

DRDY

OE

+3.3V

1k

Offset

Adjust

ADC08B200

10

-5V

19

V_RB

RCLK

39

38

MUL1

MUL0

18

14

WENsync

OEDGE

Ground connections marked

with "*" should enter the

ground

23

24

15

16

BSIZE1

BSIZE0

EF

FF

plane at a common point.

20

17

25

REN

WEN

ASW

22

RESET

41

13

PDADC

PD

DR GND

AGND

CLK

46

5

8

11

30

21 42 45 47

2

Figure 46. The Input Amplifier Should Incorporate Some Gain for Best Performance (see text)

POWER SUPPLY CONSIDERATIONS

A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed.

Generally, a 10 µF tantalum or aluminum electrolytic capacitor should be provided for each of the four supplies

and a 0.1 µF ceramic chip capacitor placed within one centimeter of each converter power supply pin.

To further lower the inductance in series with the capacitors, mount the 0.1 µF capacitors on the same side of

the board as the ADC and use 2 to 4 closely spaced through holes to connect the ground side of the capacitors

to the ground plane. The through holes used to ground one side of these capacitors should not be used to

connect anything else to ground. Leadless chip capacitors are preferred because they have low lead inductance.

While a single voltage source is recommended for the V_A, V_Dand V_Psupplies of the ADC08B200, the V_Asupply

pins should be well isolated from the other supply pins to prevent any digital noise from being coupled into the

analog portions of the ADC. A choke is recommended between the V_DRsupply pin and the other supply pins with

adequate bypass capacitors close to each supply pin, as shown in Figure 44, Figure 45 and Figure 46.

As is the case with all high speed converters, the ADC08B200 should be assumed to have little power supply

rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any

system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other

analog circuitry.

No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300

mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be

sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than

does the voltage at the ADC08B200 power pins.

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THE DIGITAL INPUT PINS

The ADC08B200 has 14 digital input pins, 6 of which are used for buffer control and 2 of which are used for PLL

control.

The PD Pin

The Power Down (PD) pin, when high, puts the ADC08B200 into a low power mode where power consumption is

significantly reduced below its operating power. Stopping the clock after raising the PD input will reduce power

consumption even more. The ADC is active and will perform normally about 2 microseconds after the PD pin is

brought low. However, the PLL, if used, requires 20 microseconds to stabilize after the PD pin is brought low.

The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is

high. The buffer contents are lost when PD is brought high.

The PDADC Pin

When the PDADC pin is high the ADC is powered down. The capture buffer is active and the data within it may

be clocked out.

This is helpful for reduction of average power consumption as the ADC can be powered down while data is being

read from the buffer. As with the PD pin, the ADC is active and will perform normally about 2 microseconds after

the PDADC pin is brought low. Again the PLL, if used, requires 20 microseconds to stabilize after the PD pin is

brought low.

The PLL remains active when the PDADC input is high to allow for faster initiation of data capture after PDADC

is lowered. Stopping the input clock when PDADC is invoked can result in a loss of PLL lock and a longer than

normal recovery time from PDADC.

The Master CLK Pin

Although the ADC08B200 is tested and its performance is ensured with a 200 MHz clock, it typically will function

well with clock frequencies as indicated in the Electrical Characteristics table.

The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving

a precise duty cycle is difficult, the ADC08B200 is designed to maintain performance over a range of duty cycles.

While it is specified and performance is ensured with a 50% clock duty cycle and 200 Msps, ADC08B200

performance is typically maintained with clock high and low times and a clock frequency range as indicated in the

electrical table. Note that clock minimum low and high times may not be simultaneously imposed.

The ADC Clock input line should be series terminated at the clock source in the characteristic impedance of that

line if the clock line is longer than

where

•

t_ris the clock rise time

t_propis the propagation rate of the signal along the trace

(5)

Typical t_propis about 150 ps/inch (59 ps/cm) on FR-4 board material.

It is always best and advisable that one clock source pin drive a single destination pin for best signal integrity.

However, if the clock source is used to drive more than just one destination, the CLK pin should be a.c.

terminated with a series RC to ground such that the resistor value is equal to the characteristic impedance of the

clock line and the capacitor value is

where

•

t_PROPis the signal propagation rate down the clock line

"L" is the line length

Z_Ois the characteristic impedance of the clock line

(6)

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The units of "L" must be compatible with the units of t_PROP. This termination should be located as close as

possible to, but within one centimeter of, the ADC08B200 clock pin. Furthermore, this termination should be

beyond the receiving pin as seen from the clock source. For FR-4 board material, the value of C becomes

where

•

L is the length of the clock line in inches

(7)

The RESET Pin

A high level at this Reset input resets all control logic on the chip, including the buffer's read and write counters.

The FF output is reset low and the EF flag is reset high upon a device reset. Invoking a reset during the WRITE

phase can cause buffer data to be corrupted. A reset during the READ phase will stop the READ phase before it

is completed.

The RESET signal is asynchronous and should be at least 4 sample clock cycles wide. If no RESET is provided,

the chip generates its own internal reset signal at the beginning of the buffer write phase.

The OEDGE/TEN Pin

If this Output Edge Select input is high, the data outputs transition with the rising edge of the DRDY output. If this

input is low, the data outputs transition with the falling edge of the DRDY. Forcing a potential of V_A/2 at this input

enables the Test Mode. There is an on-chip pull-up resistor at this pin, so the device interprets a floating input at

this pin to be a logic high. See TEST PATTERN OUTPUT for the output test pattern.

The OE Pin

A high level at this Output Enable input enables the output buffers. A low level at this input puts the digital data

output pins, including the DRDY output, into a high impedance state. The only exception is in the Test Pattern

Mode, where the OE input is ignored and the DRDY and data output pins are active regardless of the OE pin

status.

CAUTION

Although this device has a TRI-STATE output, maintaining optimum noise performance

requires keeping the capacitance on the data output pins as low as possible.

Therefore, it is never a good idea to connect the output pins to a bus. Each output pin

should be connected to a single input with lines as short as possible.

Buffer-Associated Pins

The on-chip buffer is 1 kilobyte (1,024 bytes) in size and is controlled through six (6) TTL-CMOS compatible

digital input pins.

THE RCLK PIN

When the capture buffer is enabled, the RCLK input is used to read the data from the buffer. The data output and

the EF flag transition with the rise of RCLK.

It is best to halt the RCLK when not reading the buffer to minimize its impact upon noise performance. RCLK

may be stopped in either the high or the low state.

THE WEN PIN

A high level at this Write Enable input causes data to be written into the capture buffer. One byte is written with

the rise of each sample clock. This input may go high asynchronously.

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THE REN PIN

A high level at this Read Enable input causes data to be read from the capture buffer. One byte is read with the

rise of each RCLK input. This signal should go high synchronous with the RCLK input and should not be high

while the WEN input is high. If this input is high while the WEN input is high, the WEN input has priority and the

REN input is ignored, regardless of which of these two inputs is high first. It is not possible to read from the buffer

while a write to the buffer is in progress.

THE ASW PIN

This Auto-Stop Write input has a dual function. With writing to the buffer enabled and this ASW high, this pin acts

as the ASW (Auto-Stop Write) input, which causes writing to the buffer to halt once the buffer is full (FF high).

This prevents write "wrap around" and the over-writing of older data. When writing to the buffer is disabled, this

pin is ignored. When the device is in Test Mode, this pin acts as the Output Edge Select input and functions as

described for the OEDGE/TEN input.

THE BSIZE PINS

The two Buffer Size input pins (BSIZE0 and BSIZE1) are used to select the required buffer size for the

application or to bypass the buffer altogether. Refer to USING THE DATA BUFFER for use of these pins

PLL CONTROL: THE MULT PINS

The two MULT input pins (MULT0 and MULT1) are used to select the CLK Multiplier for the internal PLL, or to

bypass the PLL. Refer to CLOCK OPTIONS for more information.

DIGITAL OUTPUT PINS

The ADC08B200 has 12 digital output pins: 8 Digital Data Output pins, DRDY, WENSYNC, EF and FF

Digital Data Outputs

This 8-bit bus is LVTTL/LVCMOS compatible, with a Straight Binary output format. Data is clocked out on this

bus in one of two ways. When the internal buffer is bypassed, data is clocked out at the sample clock rate. When

the internal buffer is used, data is clocked out at the RCLK rate. In either case, data is clocked out on the rising

edge of the appropriate clock. Refer to CLOCK OPTIONS for information on sample rate determination.

When the Capture Buffer is bypassed, data is read directly from the converter at the sample clock rate.

When the capture buffer is used, data is read from the capture buffer and presented at these pins when the REN

input is high. If OEDGE/TEN is high, the digital data output and DRDY are held low when no valid data is being

sent out. If OEDGE/TEN is low, the digital data and DRDY are held high when no valid data is being sent out.

These pins source data at the converter sample rate when the buffer is disabled.

Whether the buffer is enabled or not, the output data is provided synchronous with DRDY. That is, the data

transition occurs with the edge of DRDY defined by OEDGE/TEN such that the data transitions on the rise of

DRDY if OEDGE/TEN is high or on the fall of DRDY if OEDGE/TEN is low.

The data output drivers are capable of sourcing and sinking a relatively high current to enable rapid charging and

discharging of the output capacitance, thereby allowing fast output rise and fall times. The data outputs should

be as lightly loaded as possible to minimize on-chip noise and the resulting loss of SNR performance. Note the

specified load capacitance at the heading of the Electrical Characteristics Tables.

The DRDY Pin

This output is intended for use to latch output data into a receiving device and transitions with the transition of

the digital data outputs. The synchronizing edge of the DRDY signal can be selected with the OEDGE input.

When the buffer is not used, DRDY is active as long as the ADC is functioning. When the buffer is enabled,

DRDY is active only while data is being sent out. When no valid data is being sent out, the DRDY output sense is

the opposite of the OEDGE input. When OE is low and the device is NOT in the Test Pattern Mode (OEDGE

floating or at V_A/ 2), the DRDY output is in the high impedance state, as are the data outputs. However, in Test

Pattern Mode the OE input is ignored and all output drivers (data and DRDY) are in the active state. When the

buffer is used, DRDY is held low at all times except during the buffer read phase, where it switches in

synchronism with the data output pins.

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The DRDY output should be have a load that is identical to the load of the digital data outputs to ensure that the

DRDY output edge transitions at the same time as does the data.

The WENSYNC Pin

This output is synchronous with the internal sample clock and is provided as an indication as to when sampling

takes place. The actual point in time when sampling takes place is as indicated in Figure 3.

The EF Pin

This Empty Flag goes high, synchronous with the internal sample clock, when the Capture Buffer is empty, either

by the buffer having been completely read or upon RESET of the device. This output goes low when one or more

bytes is written to the buffer. When EF goes high, the DRDY and Data outputs stop switching and both DRDY

and the Data lines remain low if OEDGE=1, or high if OEDGE=0.

The FF Pin

The Full Flag output indicates that the buffer is full and goes high, synchronous with the internal sample clock,

when the capture buffer is full. If the WEN input remains high, the rise of the next sample clock after the FF

output goes high will cause the buffer pointer to "wrap around" and start writing over the previous data unless the

ASW input is high. The FF signal goes low when the REN signal goes high and the full condition no longer

exists. This signal also goes low upon a RESET of the device.

CLOCK OPTIONS

The ADC08B200 incorporates a PLL to facilitate clocking. The PLL, like any PLL or DLL, can add phase noise to

the clock signal and so to the conversion process. The effect of this phase noise increases with higher analog

signal input frequencies. If a stable clock source at the desired sample rate is available, it is preferable to use

that clock as the sample clock for the ADC08B200, bypassing the PLL. If such a source is not available, the

internal PLL may be used to multiply the input clock frequency by 2, 4 or 8 to obtain the desired sample rate from

a lower frequency clock source.

Bypassing the PLL or setting the CLK frequency multiplier is accomplished through the use of the two MULT pins

as indicated in Table 1. Expected noise performance with and without the use of the PLL is indicated in TYPICAL

PERFORMANCE CHARACTERISTICS.

Table 1. MULT Pin Function

MULT1

MULT0

CLK Frequency Multiplier

CLK Frequency Range (MHz)

0

1

0

1

0

1

2

4

8

1 - 210

15 - 105

15 - 50

15 - 25

The internal sampling clock frequency is the input clock frequency at the CLK pin multiplied by the multiplier in

Table 1. When the PLL is bypassed, the input clock at the CLK pin is used as the sample clock and the PLL is

disabled.

USING THE DATA BUFFER

The Data Buffer has read and write pointers and the first word written to it is the first word read from it. The Data

Buffer is configurable to 256-, 512-, or 1024- bytes, and must be completely filled to the configured number of

bytes before it can be read. The "FF" flag goes high once the configured number of bytes is in the buffer are

read. Once the data buffer contents are completely read, indicated by the "EF" flag going high, the same data

cannot be read again. It is possible to read back only part of the buffer contents. Asserting the WEN high input,

even while a valid read operation is under way, will cause a resetting of the read and write pointers and initiation

of a write operation.

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The WEN (Write Enable) input is used to enable writing to the buffer, while the REN (Read Enable) input is used

to enable reading from the buffer. If both of these are high, the WEN input dominates and the REN input is

ineffective until WEN goes low. If the WEN pin remains high after the buffer is full, the previous contents are

over-written. The ASW (Auto-Stop Write) pin may be used to automatically stop writing to the buffer when it is full

to the configured number of bytes. See THE WEN PIN, THE REN PIN, and THE ASW PIN for information on

these inputs.

The BSIZE inputs are used to configure the Data Buffer size (described in Table 2). The user has a choice of

using the buffer or bypassing it.

When the buffer is used and its contents have been read, the DRDY and the Data Outputs maintain the opposite

sense of the OEDGE input. When the buffer is bypassed, it is not used and the data is presented at the ADC

data output pins at the same rate as the sample clock. Table 2 indicates the choices available and the BSIZE pin

settings to achieve each.

When the buffer is bypassed (both BSIZE pins low), the ADC output is sent directly to the output port at the

sample clock rate without going through the buffer. In this mode all buffer control inputs (WEN, REN, ASW and

RCLK) are ignored and the EF and FF outputs are held low. The DRDY output may be used to capture the data

at the output port.

Table 2. BSIZE Pin Function

BSIZE1

BSIZE0

Buffer Size

Buffer is bypassed

256 bytes

0

1

0

1

0

1

512 bytes

1024 bytes

Reading the Buffer

There are two options for reading the contents of the ADC08B200 buffer. Since the DRDY output is source-

synchronous with the data output, it may be used to read the buffer data into the receiving device. This buffer

read method works well at any read rate for which the device is capable and is the preferred method of reading

the buffer at read rates greater than about 70 to 80 MHz. When using this method it is important that the DRDY

line electrical length and load are matched with those of the data lines in order to minimize DRDY to data output

skew.

The other read option is to ignore the DRDY signal and use the RCLK signal to read the ADC08B200 buffer. This

method may be easier to implement than is the use of DRDY when using a DSP or processor to read the buffer.

However, because RCLK is not source-synchronous with the data lines, this method is not recommenced for

buffer read (RCLK) rates above about 60 to 70 MHz. Specifications for t_OHF+ t_F/ 2and t_OHR+ t_R/ 2 provide the

necessary timing information of output data relative to RCLK. Keep in mind that the device timing specifications

apply at the device pins. Additional system delays must be taken into account to determine the RCLK to Data

timing relationship at the receiving device.

Regardless of which method is used, RCLK is needed to clock the captured data from the buffer. The buffer can

not be read without RCLK. Likewise reading the test pattern also requires the use of RCLK.

RCLK may be stopped when not reading the buffer and may be stopped in either the high state or the low state.

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MODES OF OPERATION

The ADC08B200 has several modes of operation. These modes are detailed in Table 3.

The buffer function is controlled by the BSIZE pins, BSIZE0 and BSIZE1, as indicated in Table 4. The buffer can

be bypassed and data read directly from the ADC by setting both of the BSIZE pins low.

Table 3. Modes of Operation

PD

PDADC

WEN

REN

Power State

Operational State

1

x

Shutdown

Shutdown, non-operational

Buffer Active, ADC

Shutdown

0

1

x

0

1

0

ADC powered down, no data can be captured. Buffer may be read.

Data is being read from buffer with RCLK

Active

If buffer is bypassed, data is present at output bus. If buffer is used, the chip is

ready to capture data to the buffer.

Active

The ADC's digital output is being captured to the buffer. The REN input is

ignored.

0

1

x

Active

Buffer Active, ADC

Shutdown

PROHIBITED. WEN input is ignored.

Table 4. Buffer Write/Read

BSIZE1

BSIZE0

WEN

REN

Buffer Function

0

1

0

1

0

1

0

1

0

1

x

1

0

x

1

Buffer bypassed

Write to 256 byte buffer

Write to 512 byte buffer

Write to 1k byte buffer

Read from 256 byte buffer

Read from 512 byte buffer

Read from 1k byte buffer

TEST PATTERN OUTPUT

The ADC08B200 has a test mode whereby the data outputs have a test pattern which may be used to "train" a

receiving device, such as a PLD. The Test Mode is invoked by forcing a potential of V_A/2 at the OEDGE/TEN

input. There is an on-chip pull-up resistor at this pin, so the device interprets a floating input at this pin to be a

logic high. This pattern is used to test the integrity of the buffer, so the RCLK (Read Clock) input must be used to

get the output pattern.

The test pattern that is put out is a continuously repeated pattern of output codes 00h - FFh - 00h - FFh - 00h.

Note that this pattern repeats as long as the test mode is invoked and RCLK is running, so that every second

time a logic low appears it will be present for two bit times.

APPLICATION EXAMPLE

Figure 47 shows an example of a typical application. The analog input and reference circuits are as described in

Figure 45 and Figure 46, except the input amplifier is shown without any gain and offset adjustments. The overall

nominal gain of the input amplifier circuit is 1.98 and the nominal −3 dB input bandwidth is about 195 MHz. Note

that this circuit does not show an anti-aliasing filter.

A 50 MHz clock oscillator is used for the input clock source. The MULT0 input grounded and the MULT1 input

high means (from Table 1) that this 50 MHz input clock is multiplied by the internal PLL by 4 to provide a 200

Msps capture rate.

Since the BSIZE0 and BSIZE1 pins are both high, the internal capture buffer size is set to 1,024 bytes (see

Table 2). Data writing to the internal buffer will automatically stop when the buffer is full because the ASW input

is high. The FF (Full Flag) will go high when the buffer is full and data is ready to be read.

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The OEDGE pin is high, meaning the output data will transition at the rise of the DRDY output. Since the PD pin

is grounded and the OE pin is high, the device will never be completely powered down and the outputs are

always enabled. Since the PDADC pin is driven from the controlling device, the ADC may be powered down,

leaving the output buffer active, when the device buffer is being read, or when the device is not in use.

The digital lines between the ADC08B200 and the receiving device have 33 Ohms at the signal source end as

source terminators, assuming output impedances of about 20 Ohms and 50-Ohm lines. The RESET and PDADC

lines are not terminated because these are basically d.c. lines and it is assumed that they do not toggle

frequently.

+3.3V

Choke

10 µF

+

10 µF

470W

0.1 µF

+3.3V

+

1 µF

10 mF

0.1 µF

4

1

12 43 44 48

V_P

40

32

604W

3

LM4040-2.5

1/2

LM8272

8

+

V_A

V_D

V_DR

D7

1

33

26

27

28

29

33

2

-

D6

D5

D4

D3

D2

D1

D0

4

0.1 µF

0.01 µF

4.7k

3

9

34

35

V_RT

1 µF

36

31

1.62k

V_RM

33

DRDY

OE

0.1 µF

37

19

+3.3V

Processor / PLD /

FPGA / DSP

4.7k

ADC08B200

10

V_RB

33

39

38

RCLK

1 µF

MULT1

MULT0

33

0.01 µF

18

17

0.1 µF

WENsync

WEN

33

6

-

23

24

7

BSIZE1

BSIZE0

REN 20

5

+

+3.3V

33

15

1/2

LM8272

EF

309W

16

FF

14

OEDGE

V_IN

22

RESET

41

PDADC

ASW

6

7

25

13

+3.3V

V_INGND

PD

CLK

+5V

GND

DR GND

30

18

200

0.1 µF

2

5

8

11

46

21 42 45 47

-

22

LMH6702

+

+3.3V

240

Signal

Input

33 pF

0.1µF

100

47

CLK

OSC

(50MHz)

33

Figure 47. Example of a Typical Application

The average power consumption of the ADC08B200 (assuming a new capture is taken as soon as the buffer

contents is read) may be calculated by taking power consumed while capturing and writing to the buffer and

multiplying it by the capture time divided by the throughput time (interval between the successive rises of the

WEN signal), added to the power while reading the buffer with PDADC high (assuming the PDADC input is taken

high whenever data is not being captured) multiplied by the time that PDADC is high (Buffer read time plus any

idle time) divided by the throughput rate.

Assuming a Capture Power of 543 mW, a 200 Msps capture rate and a 66mW Read Power with PDADC high, a

50 MHz data read rate and no completely idle time, the average power consumption would be 161.4 mW.

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POWER SUPPLY CONSIDERATIONS

It is important to note that capacitors have an equivalent series inductance associated with them such that,

beyond a certain frequency, the capacitor behaves more like an inductance than a capacitance and adequate

bypassing may be infective, resulting in the power distribution system having a high impedance, which could

further result in excessive noise on the power supply. The frequency beyond which adequate bypassing may be

effective depends primarily upon the chemistry of the capacitor dielectric, but can also vary a little from one

manufacturer to another. Even so, this frequency is in the hundreds of Megahertz. Note, however, that a 200

MHz clock will have significant harmonic energy far beyond this. The result could be high frequency noise on the

supply lines that could effect the SNR performance of the converter.

The use of adjacent power and ground planes will go a long way toward reducing the impedance of the power

distribution system and is encouraged. Furthermore, we suggest placing the lowest value of bypass capacitor

close to the supply pin on the same side of the board as the ADC and connect the ground end of the bypass

capacitor to the ground plane with at least two through holes. The through holes have an inductance associated

with them and using two or more such holes puts these inductances in parallel, lowering the effective inductance

to ground.

Supply Voltages

The ADC8D200 will perform well with power supply voltages in the range specified in the Operating Ratings, just

before the Electrical Table. Many individual devices may perform well down to supply voltages of 2.7V, but this

should not be relied upon because part of the product distribution, depending upon normal fabrication process

tolerances, could result in the majority of some production runs not functioning well below 3.0V.

While all supplies may be of the same voltage, the digital supply (V_D), the PLL supply (V_P) and the output driver

supply (V_DR) ADC08B200 should never be higher than 300 mV above the analog supply (V_A). Furthermore, the

output driver supply, V_DRmay be as low as 2.7V only when using the buffer and when the buffer read clock

(RCLK) frequency is no higher than 50 MHz because the output slew rate decreases at low V_DRvoltages and the

output eye may not be open enough to allow reliable data capture.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A single, unified

ground plane should be used. Do not split the ground plane.

Coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance that may seem impossible to isolate and remedy. The solution is to keep all lines separated from

each other by at least six times the height above the reference plane, and to keep the analog circuitry well

separated from the digital circuitry.

The DR GND connection to the ground plane should not use the same through holes used by other ground

connections. High power digital components should not be located near any analog components.

Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog

path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should

be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be

avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies

is obtained with a straight signal path.

The reference and analog inputs should be isolated from noisy signal traces to avoid coupling of spurious signals

into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and

ground should be connected to a very clean point in the ground plane and preferably with 2 to 4 closely spaced

through holes.

DYNAMIC PERFORMANCE

The ADC08B200 is a.c. tested and its dynamic performance is ensured. To meet the published specifications,

the clock source driving the CLK input must exhibit as little jitter as possible. For best a.c. performance, each

clock destination should be driven by a separate source, such as with a clock distribution chip or with a clock tree

such as seen in Figure 48.

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Figure 48. Isolating the ADC Clock from Digital Circuitry

It is good practice to keep the ADC clock line as short as possible and to keep it well away from other signals,

which can introduce jitter into the clock signal. The clock signal can also introduce noise into a nearby signal

path.

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on

even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits

(e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 47Ω resistor in

series with the offending digital input, close to the driving source, will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the ADC08B200. Such practice may lead to conversion

inaccuracies and even to device damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current is required from V_DRand DR GND. These

large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the

digital data outputs may be necessary if the data bus capacitance exceeds 10 pF. Dynamic performance can

also be improved by adding 12Ω to 27Ω series resistors at each digital output, reducing the energy coupled back

into the converter input pins.

Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, there are

voltage spikes at the ADC analog input. These voltage spikes can cause instability in a feedback type amplifier

used to drive the analog input. These spikes need not be filtered out, but should settle quickly. The amplifier

should be fast enough to handle the frequencies presented to it, but not so fast that it would readily oscillate. A

single-pole RC filter, as explained in THE ANALOG INPUT will help ensure amplifier stability and accurate data

capture.

Driving the V_RTpin or the V_RBpin with devices that can not source or sink the current required by the

ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source

sufficient current into the V_RTpin and sink sufficient current from the V_RBpin. If these pins are not driven with

devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of

dynamic performance.

Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally

inadequate as a clock source.

Busing the data outputs. SNR performance of all ADCs, especially high speed ADCs, is sensitive to the

amount of capacitance at the data outputs because the currents required of the ADC data outputs to charge and

discharge these capacitances cause voltage spikes (noise) on the die. Minimizing the output capacitance will

help maintain noise performance of the converter. Busing the outputs adds undesired capacitive loading to the

ADC. Similarly, it is important to keep trace capacitance to a minimum by using short traces at the ADC outputs.

34

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SNAS388F –MARCH 2007–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision E (April 2013) to Revision F

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 34

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PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADC08B200CIVS/NOPB

PFB

TQFP

48

250

10 x 25

150

315 135.9 7620 12.2

11.1 11.25

ADC08B200QCIVS/NOP

B

Pack Materials-Page 1

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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型号：	ADC08B200CIVS/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	缓冲区容量为 1K 的 8 位、200MSPS 模数转换器 (ADC) \| PFB \| 48 \| -40 to 105 转换器模数转换器
文件：	总41页 (文件大小：1065K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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