ADC11C125 [TI]

11 位、125MSPS、1.1GHz 输入带宽模数转换器 (ADC);


型号：	ADC11C125
厂家：	TEXAS INSTRUMENTS
描述：	11 位、125MSPS、1.1GHz 输入带宽模数转换器 (ADC) 转换器模数转换器
文件：	总29页 (文件大小：715K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC11C125

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SNAS387C –MAY 2007–REVISED APRIL 2013

ADC11C125 11-Bit, 125 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs

Check for Samples: ADC11C125

FEATURES

DESCRIPTION

The ADC11C125 is

a high-performance CMOS

•

1.1 GHz Full Power Bandwidth

Internal Sample-and-Hold Circuit

Low Power Consumption

analog-to-digital converter capable of converting

analog input signals into 11-Bit digital words at rates

up to 125 Mega Samples Per Second (MSPS). This

converter uses a differential, pipelined architecture

with digital error correction and an on-chip sample-

and-hold circuit to minimize power consumption and

the external component count, while providing

excellent dynamic performance. A unique sample-

and-hold stage yields a full-power bandwidth of 1.1

GHz. The ADC11C125 operates from dual +3.3V and

+1.8V power supplies and consumes 608 mW of

power at 125 MSPS.

•

Internal Precision 1.0V Reference

Single-Ended or Differential Clock Modes

Clock Duty Cycle Stabilizer

Dual +3.3V and +1.8V Supply Operation

Power-Down and Sleep Modes

Offset Binary or 2's Complement Output Data

Format

•

Pin-Compatible: ADC14155, ADC12C170,

ADC11C170

The separate +1.8V supply for the digital output

interface allows lower power operation with reduced

noise. A power-down feature reduces the power

consumption to 5 mW while still allowing fast wake-up

time to full operation. In addition there is a sleep

feature which consumes 50 mW of power and has a

faster wake-up time.

48-pin WQFN Package, (7x7x0.8mm, 0.5mm

Pin-Pitch)

APPLICATIONS

•

High IF Sampling Receivers

Wireless Base Station Receivers

Power Amplifier Linearization

Multi-Carrier, Multi-Mode Receivers

Test and Measurement Equipment

Communications Instrumentation

Radar Systems

The differential inputs provide a full scale differential

input swing equal to 2 times the reference voltage. A

stable 1.0V internal voltage reference is provided, or

the ADC11C125 can be operated with an external

reference.

Clock mode (differential versus single-ended) and

output data format (offset binary versus 2's

complement) are pin-selectable.

duty cycle

stabilizer maintains performance over a wide range of

input clock duty cycles.

KEY SPECIFICATIONS

•

Resolution 11 Bits

The ADC11C125 is pin compatible with the

ADC12C170 and the ADC14155.

Conversion Rate 125 MSPS

SNR (f_IN= 70 MHz) 65.5 dBFS (typ)

SFDR (f_IN= 70 MHz) 88.2 dBFS (typ)

ENOB (f_IN= 70 MHz) 10.5 bits (typ)

Full Power Bandwidth 1.1 GHz (typ)

Power Consumption 608 mW (typ)

It is available in a 48-lead WQFN package and

operates over the industrial temperature range of

−40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC11C125

SNAS387C –MAY 2007–REVISED APRIL 2013

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Block Diagram

INTERNAL

REFERENCE

REF

D0 - D10

OVR

11BIT HIGH SPEED

PIPELINE ADC

DIGITAL

CORRECTION

SHA

DRDY

CLK+

CLK-

CLOCK/DUTY CYCLE

STABILIZER

Connection Diagram

AGND

DRGND

DRDY

OVR

AGND

D10 (MSB)

V_A

ADC11C125

(Top View)

PD/Sleep

CLK_SEL/DF

AGND

CLK+

CLK-

* Exposed pad must be soldered to ground

plane to ensure rated performance.

DRGND

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Pin Descriptions and Equivalent Circuits

Pin No.

ANALOG I/O

Symbol

Equivalent Circuit

Description

V_IN−

Differential analog input pins. The differential full-scale input signal

level is two times the reference voltage with each input pin signal

V_IN+

centered on a common mode voltage, V_CM

AGND

V_RP

V_RM

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very close to

the pin to minimize stray inductance. A 0.1 µF capacitor should be

placed between V_RPand V_RNas close to the pins as possible, and a

10 µF capacitor should be placed in parallel.

REF

V_RPand V_RNshould not be loaded. V_RMmay be loaded to 1mA for

use as a temperature stable 1.5V reference.

V_RN

It is recommended to use V_RMto provide the common mode voltage,

V_CM, for the differential analog inputs, V_IN+ and V_IN−.

AGND

This pin can be used as either the +1.0V internal reference voltage

output (internal reference operation) or as the external reference

voltage input (external reference operation).

To use the internal reference, V_REFshould be decoupled to AGND

with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In

this mode, V_REFdefaults as the output for the internal 1.0V

reference.

V_REF

To use an external reference, overdrive this pin with a low noise

external reference voltage. The input impedance looking into this pin

is 9kΩ. Therefore, to overdrive this pin, the output impedance of the

external reference source should be << 9kΩ.

This pin should not be used to source or sink current.

The full scale differential input voltage range is 2 * V_REF

AGND

This is a four-state pin controlling the input clock mode and output

data format.

CLK_SEL/DF = V_A, CLK+ and CLK− are configured as a differential

clock input. The output data format is 2's complement.

CLK_SEL/DF = (2/3)*V_A, CLK+ and CLK− are configured as a

differential clock input. The output data format is offset binary.

CLK_SEL/DF = (1/3)*V_A, CLK+ is configured as a single-ended clock

input and CLK− should be tied to AGND. The output data format is

2's complement.

CLK_SEL/DF

CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock

input and CLK− should be tied to AGND. The output data format is

offset binary.

This is a three-state input controlling Power Down and Sleep modes.

PD = V_A, Power Down is enabled. In the Power Down state only the

reference voltage circuitry remains active and power dissipation is

reduced.

AGND

PD/Sleep

PD = V_A/2, Sleep mode is enabled. Sleep mode consumes more

power than Power Down mode but has a faster recovery time.

PD = AGND, Normal operation.

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Pin Descriptions and Equivalent Circuits (continued)

Pin No.

Symbol

Equivalent Circuit

Description

CLK+

The clock input pins can be configured to accept either a single-

ended or a differential clock input signal.

When the single-ended clock mode is selected through CLK_SEL/DF

(pin 8), connect the clock input signal to the CLK+ pin and connect

the CLK− pin to AGND.

When the differential clock mode is selected through CLK_SEL/DF

(pin 8), connect the positive and negative clock inputs to the CLK+

and CLK− pins, respectively.

CLK−

The analog input is sampled on the falling edge of the clock input.

AGND

DIGITAL I/O

Digital data output pins that make up the 10-Bit conversion result. D0

(pin 20) is the LSB, while D10 (pin 32) is the MSB of the output

word. Output levels are CMOS compatible.

20-24,

27-32

D0–D10

OVR

Over-Range Indicator. This output is set HIGH when the input

amplitude exceeds the 11-Bit conversion range (0 to 2047).

Data Ready Strobe. This pin is used to clock the output data. It has

the same frequency as the sampling clock. One word of data is

output in each cycle of this signal. The rising edge of this signal

should be used to capture the output data.

DRDY

OGND

DRGND

DGND

Output GND, internally tied to GND through 5k ohm resistor to

provide pin compatibility with 14 and 12 bit ADCs.

17-19

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet +3.3V source and be bypassed to AGND with 0.01 µF and 0.1

µF capacitors located close to the power pins.

1, 6, 9, 37,

40, 41, 48

V_A

2, 5, 10, 38,

39, 42, 47,

Exposed Pad

The ground return for the analog supply.

Note: Exposed pad on bottom of package must be soldered to

ground plane to ensure rated performance.

AGND

DIGITAL POWER

Positive digital supply pin. This pin should be connected to a quiet

+3.3V source and be bypassed to DGND with a 0.01 µF and 0.1 µF

capacitor located close to the power pin.

V_D

DGND

The ground return for the digital supply.

Positive driver supply pin for the output drivers. This pin should be

connected to a quiet voltage source of +1.8V and be bypassed to

DRGND with 0.01 µF and 0.1 µF capacitors located close to the

power pins.

15, 25, 36

16, 26, 35

V_DR

The ground return for the digital output driver supply. These pins

should be connected to the system digital ground, but not be

connected in close proximity to the ADC's DGND or AGND pins. See

Layout and Grounding for more details.

DRGND

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings⁽¹⁾⁽²⁾

Supply Voltage (V_A, V_D)

−0.3V to 4.2V

−0.3V to 2.35V

≤ 100 mV

Supply Voltage (V_DR

)

|V_A–V_D|

Voltage on Any Input Pin

(Not to exceed 4.2V)

−0.3V to (V_A+0.3V)

Voltage on Any Output Pin

(Not to exceed 2.35V)

−0.3V to (V_DR+0.2V)

Input Current at Any Pin other than Supply Pins⁽³⁾

Package Input Current⁽³⁾

±5 mA

±50 mA

Max Junction Temp (T_J)

+150°C

Thermal Resistance (θ_JA

)

24°C/W

Package Dissipation at T_A= 25°C⁽⁴⁾

5.2W

Human Body Model⁽⁵⁾

Machine Model⁽⁵⁾

2000 V

ESD Rating

200 V

Charge Device Model

1000 V

Storage Temperature

−65°C to +150°C

Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.⁽⁶⁾

(1) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(3) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of ±5 mA to 10.

(4) The maximum allowable power dissipation is dictated by T_J,max, the junction-to-ambient thermal resistance, (θ_JA), and the ambient

temperature, (T_A), and can be calculated using the formula P_D,max= (T_J,max- T_A)/θ_JA. The values for maximum power dissipation listed

above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the

power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

(5) Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω

(6) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Operating Ratings⁽¹⁾⁽²⁾

Operating Temperature

Supply Voltage (V_A, V_D)

Output Driver Supply (V_DR

CLK

−40°C ≤ T_A≤ +85°C

+3.0V to +3.6V

+1.6V to +2.0V

−0.05V to (V_A+ 0.05V)

30/70 %

)

Clock Duty Cycle

Analog Input Pins

V_CM

0V to 2.6V

1.4V to 1.6V

|AGND-DGND|

≤100mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.

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Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A=

(1)(2)(3)

25°C

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(4)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

0.83

-0.83

0.50

-0.55

4.0

Bits (min)

LSB (max)

LSB (min)

LSB (max)

LSB (min)

%FS (max)

%FS (min)

%FS (max)

%FS (min)

ppm/°C

(5)

INL

Integral Non Linearity

Differential Non Linearity

Positive Gain Error

Full Scale Input

±0.25

±0.20

+1.1

DNL

PGE

-1.8

2.2

NGE

Negative Gain Error

Gain Error Tempco

-0.77

TBD

-3.7

TC GE

V_OFF

−40°C ≤ T_A≤ +85°C

0.78

%FS (max)

%FS (min)

ppm/°C

Offset Error (V_IN+ = V_IN−)

−0.11

-1.03

TC V_OFFOffset Error Tempco

Under Range Output Code

Over Range Output Code

TBD

2047

REFERENCE AND ANALOG INPUT CHARACTERISTICS

V_CM

Common Mode Input Voltage

1.5

Reference Ladder Midpoint Output

Voltage

V_RM

Output load = 1 mA

(CLK HIGH)

(CLK LOW)

V_INInput Capacitance (each pin to GND) V_IN= 1.5 Vdc ± 0.5

C_IN

(6)

(7)

V_REF

Reference Voltage

1.00

Reference Input Resistance

kΩ

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per Note 3 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at T_A= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(5) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through

positive and negative full-scale.

(6) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

(7) Optimum performance will be obtained by keeping the reference input in the 0.9V to 1.1V range. The LM4051CIM3-ADJ (SOT-23

package) is recommended for external reference applications.

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Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A=

25°C^(1)(2)(3)

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(4)

DYNAMIC CONVERTER CHARACTERISTICS, A_IN= -1dBFS

FPBW

SNR

Full Power Bandwidth

Signal-to-Noise Ratio

-1 dBFS Input, −3 dB Corner

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

1.1

65.7

65.5

65.4

64.9

64.5

87.1

88.2

83.4

84.9

75.7

10.6

10.5

10.4

10.3

-83.3

−85.7

-79.5

-81.8

-74.1

-97.7

−92.3

-83.4

-98.0

-82.2

-90.8

−88.2

-85.8

-84.9

-75.7

GHz

dBFS

Bits

64.5

76.0

10.4

SFDR

ENOB

THD

Spurious Free Dynamic Range

Bits

Effective Number of Bits

Bits

dBFS

-76.4

-78.3

-76.0

Total Harmonic Disortion

Second Harmonic Distortion

Third Harmonic Distortion

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per Note 3 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at T_A= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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Dynamic Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A=

25°C^(1)(2)(3)

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(4)

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 146 MHz

f_IN= 220 MHz

f_IN= 398 MHz

65.6

65.5

65.2

64.8

64.1

dBFS

64.6

SINAD

Signal-to-Noise and Distortion Ratio

Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_IN= -1 dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A=

(3)

25°C⁽¹⁾⁽²⁾

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(4)

CLK INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Input Capacitance

V_D= 3.6V

V_D= 3.0V

V_IN= 3.3V

V_IN= 0V

2.0

0.8

V (min)

V (max)

µA

−10

µA

DIGITAL OUTPUT CHARACTERISTICS (D0–D10, DRDY, OVR)

V_OUT(1)

V_OUT(0)

+I_SC

Logical “1” Output Voltage

I_OUT= −0.5 mA , V_DR= 1.8V

I_OUT= 1.6 mA, V_DR= 1.8V

V_OUT= 0V

1.2

0.4

V (min)

V (max)

Logical “0” Output Voltage

Output Short Circuit Source Current

Output Short Circuit Sink Current

Digital Output Capacitance

−10

−I_SC

V_OUT= V_DR

C_OUT

POWER SUPPLY CHARACTERISTICS

I_A

Analog Supply Current

Digital Supply Current

Full Operation

Full Operation⁽⁵⁾

177.0

7.0

208

7.8

mA (max)

I_D

I_DR

Digital Output Supply Current

TBD

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per Note 3 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at T_A= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(5) I_DRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR=V_DR(C₀x f₀+ C₁x f₁+....C₁₁

f₁₁) where V_DRis the output driver power supply voltage, C_nis total capacitance on the output pin, and f_nis the average frequency at

which that pin is toggling.

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Logic and Power Supply Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply: V_IN= -1 dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A=

25°C^{(1)(2) (3)}

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(4)

(5)

Power Consumption

Excludes I_DR

608

Power Down Power Consumption

Sleep Power Consumption

Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

Binary Format. Typical values are for T_A= 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface

limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A= 25°C^(1)(2)(3)

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(4)

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

125

MHz (max)

MHz (min)

t_CH

t_CL

3.8

Clock Low Time

Clock Cycles

Conversion Latency

t_OD

t_DV

t_DNV

t_AD

Output Delay of CLK to DATA

Relative to falling edge of CLK

2.0

3.0

Time output data is valid before the

Data Output Setup Time

Data Output Hold Time

2.45

ns (min)

(5)

output edge of DRDY

Time till output data is not valid after

3.0

(5)

the output edge of DRDY

Aperture Delay

Aperture Jitter

0.5

0.08

ps rms

0.1 µF on pins 43, 44; 10 µF and 0.1

µF between pins 43, 44; 0.1 µF and

10 µF on pins 45, 46

Power Down Recovery Time

Sleep Recovery Time

3.0

µs

0.1 µF on pins 43, 44; 10 µF and 0.1

µF between pins 43, 44; 0.1 µF and

10 µF on pins 45, 46

100

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per Note 3 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 11-Bit LSB is 976.6 µV.

(4) Typical figures are at T_A= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(5) This test parameter is specified by design and characterization.

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Specification Definitions

APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V_CM) is the common DC voltage applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is

presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay

plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full Scale Error

(1)

(2)

It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is V_FS/2ⁿ,

where “V_FS” is the full scale input voltage and “n” is the ADC resolution in bits.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC11C125 is

ensured not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages [(V_IN+) – (V_IN-)] required to cause a transition

from code 2047 to 2048.

OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply

limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.

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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

(3)

where f₁is the RMS power of the fundamental (output) frequency and f₂through f₁₀are the RMS power of the

first 9 harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in

the input frequency at the output and the power in its 2nd harmonic level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in

the input frequency at the output and the power in its 3rd harmonic level at the output.

Timing Diagram

Sample N + 8

Sample N + 7

Sample N + 6

Sample N

Sample N + 9

Sample N + 10

Clock N

Clock N + 7

CLK

90%

10%

90%

10%

CLK

Latency

DRDY

DNV

D0 - D10

Data N + 1

Data N + 2

Data N - 1

Data N

Figure 1. Output Timing

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Transfer Characteristic

Figure 2. Transfer Characteristic (Offset Binary Format)

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Typical Performance Characteristics, DNL, INL

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock Mode, Offset

(1) (2) (3)

Binary Format. Typical values are for T_A= 25°C.

DNL

INL

Figure 3.

Figure 4.

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per Note 3 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 11-Bit LSB is 976.6 µV.

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Typical Performance Characteristics, Dynamic Performance

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, f_IN= 70 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock

Mode, Offset Binary Format. Typical values are for T_A= 25°C.

SNR, SINAD, SFDR

DISTORTION

vs.

f_IN

vs.

f_IN

Figure 5.

Figure 6.

SNR, SINAD, SFDR

DISTORTION

vs.

V_A

vs.

V_A

Figure 7.

Figure 8.

SNR, SINAD, SFDR

DISTORTION

vs.

V_DR

Figure 9.

Figure 10.

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Typical Performance Characteristics, Dynamic Performance

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, f_IN= 70 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock

Mode, Offset Binary Format. Typical values are for T_A= 25°C.

SNR, SINAD, SFDR

DISTORTION

vs.

V_REF

Figure 11.

Figure 12.

SNR, SINAD, SFDR

vs.

DISTORTION

vs.

Temperature

Figure 13.

Figure 14.

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Typical Performance Characteristics, Dynamic Performance

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DGND = DRGND = 0V, V_A= V_D=

+3.3V, V_DR= +1.8V, Internal V_REF= +1.0V, f_CLK= 125 MHz, f_IN= 70 MHz, V_CM= V_RM, C_L= 5 pF/pin, Single-Ended Clock

Mode, Offset Binary Format. Typical values are for T_A= 25°C.

Spectral Response @ 70 MHz Input

Spectral Response @ 146 MHz Input

Figure 15.

Figure 16.

Spectral Response @ 220 MHz Input

Spectral Response @ 278 MHz Input

Figure 17.

Figure 18.

Spectral Response @ 332 MHz Input

Spectral Response @ 398 MHz Input

Figure 19.

Figure 20.

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FUNCTIONAL DESCRIPTION

Operating on dual +3.3V and +1.8V supplies, the ADC11C125 digitizes a differential analog input signal to 11

bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold

circuit to ensure maximum performance.

The user has the choice of using an internal 1.0V stable reference, or using an external reference. The

ADC11C125 will accept an external reference between 0.9V and 1.1V (1.0V recommended) which is buffered

on-chip to ease the task of driving that pin. The +1.8V output driver supply reduces power consumption and

decreases the noise at the output of the converter.

The quad state function pin CLK_SEL/DF (pin 8) allows the user to choose between using a single-ended or a

differential clock input and between offset binary or 2's complement output data format. The digital outputs are

CMOS compatible signals that are clocked by a synchronous data ready output signal (DRDY, pin 34) at the

same rate as the clock input. For the ADC11C125 the clock frequency can be between 5 MSPS and 125 MSPS

(typical) with fully specified performance at 125 MSPS. The analog input is acquired at the falling edge of the

clock and the digital data for a given sample is output on the falling edge of the DRDY signal and is delayed by

the pipeline for 7 clock cycles. The data should be captured on the rising edge of the DRDY signal.

Power-down is selectable using the PD/Sleep pin (pin 7). A logic high on the PD/Sleep pin disables everything

except the voltage reference circuitry and reduces the converter power consumption to 5 mW. When PD/Sleep is

biased to V_A/2 the the chip enters sleep mode. In sleep mode everything except the voltage reference circuitry

and its accompanying on chip buffer is disabled; power consumption is reduced to 50 mW. For normal operation,

the PD/Sleep pin should be connected to the analog ground (AGND). A duty cycle stabilizer maintains

performance over a wide range of clock duty cycles.

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC11C125:

3.0V ≤ V_A≤ 3.6V

V_D= V_A

V_DR= 1.8V

5 MHz ≤ f_CLK≤ 125 MHz

1.0V internal reference

0.9V ≤ V_REF≤ 1.1V (for an external reference)

V_CM= 1.5V (from V_RM

)

Single Ended Clock Mode

ANALOG INPUTS

Signal Inputs

Differential Analog Input Pins

The ADC11C125 has one pair of analog signal input pins, V_IN+ and V_IN−, which form a differential input pair. The

input signal, V_IN, is defined as

V_IN= (V_IN+) – (V_IN−)

(4)

Figure 21 shows the expected input signal range. Note that the common mode input voltage, V_CM, should be

1.5V. Using V_RM(pin 45) for V_CMwill ensure the proper input common mode level for the analog input signal. The

peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the differential pair

should have a peak-to-peak voltage equal to the reference voltage, V_REF, be 180° out of phase with each other

and be centered around V_CM.The peak-to-peak voltage swing at each analog input pin should not exceed the

value of the reference voltage or the output data will be clipped.

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Figure 21. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB can be described as approximately

E_FS= 2048 ( 1 - sin (90° + dev))

(5)

Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship

to each other (see Figure 22). For single frequency inputs, angular errors result in a reduction of the effective full

scale input. For complex waveforms, however, angular errors will result in distortion.

Figure 22. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause

Distortion

It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source

impedance for the differential inputs will improve even ordered harmonic performance (particularly second

harmonic).

Table 1 indicates the input to output relationship of the ADC11C125.

Table 1. Input to Output Relationship

−

V_IN

Binary Output

000 0000 0000

010 0000 0000

100 0000 0000

110 0000 0000

111 1111 1111

2’s Complement Output

100 0000 0000

_CM− V_REF/2

_CM− V_REF/4

V_CM

V_CM+ V_REF/2

V_CM+ V_REF/4

V_CM

Negative Full-Scale

Mid-Scale

110 0000 0000

000 0000 0000

V_CM+ V_REF/4

V_CM+ V_REF/2

_CM− V_REF/4

_CM− V_REF/2

010 0000 0000

011 1111 1111

Positive Full-Scale

Driving the Analog Inputs

The V_IN+ and the V_IN− inputs of the ADC11C125 have an internal sample-and-hold circuit which consists of an

analog switch followed by a switched-capacitor amplifier. The analog inputs are connected to the sampling

capacitors through NMOS switches, and each analog input has parasitic capacitances associated with it.

When the clock is high, the converter is in the sample phase. The analog inputs are connected to the sampling

capacitor through the NMOS switches, which causes the capacitance at the analog input pins to appear as the

pin capacitance plus the internal sample and hold circuit capacitance (approximately 9 pF). While the clock level

remains high, the sampling capacitor will track the changing analog input voltage. When the clock transitions

from high to low, the converter enters the hold phase, during which the analog inputs are disconnected from the

sampling capacitor. The last voltage that appeared at the analog input before the clock transition will be held on

the sampling capacitor and will be sent to the ADC core. The capacitance seen at the analog input during the

hold phase appears as the sum of the pin capacitance and the parasitic capacitances associated with the sample

and hold circuit of each analog input (approximately 6 pF). Once the clock signal transitions from low to high, the

analog inputs will be reconnected to the sampling capacitor to capture the next sample. Usually, there will be a

difference between the held voltage on the sampling capacitor and the new voltage at the analog input. This will

cause a charging glitch that is proportional to the voltage difference between the two samples to appear at the

analog input pin. The input circuitry must be fast enough to allow the sampling capacitor to settle before the clock

signal goes low again, as incomplete settling can degrade the SFDR performance.

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A single-ended to differential conversion circuit is shown in Figure 23. A transformer is preferred for high

frequency input signals. Terminating the transformer on the secondary side provides two advantages. First, it

presents a real broadband impedance to the ADC inputs and second, it provides a common path for the charging

glitches from each side of the differential sample-and-hold circuit.

One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF

transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs

for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the

analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed

to the ADC core.

The SFDR performance of the converter depends on the external signal conditioning circuity used, as this affects

how quickly the sample-and-hold charging glitch will settle. An external resistor and capacitor network as shown

in Figure 23 should be used to isolate the charging glitches at the ADC input from the external driving circuit and

to filter the wideband noise at the converter input. These components should be placed close to the ADC inputs

because the analog input of the ADC is the most sensitive part of the system, and this is the last opportunity to

filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input

capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling

applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear

delay response.

Input Common Mode Voltage

The input common mode voltage, V_CM, should be in the range of 1.4V to 1.6V and be a value such that the peak

excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is

recommended to use V_RM(pin 45) as the input common mode voltage.

Reference Pins

The ADC11C125 is designed to operate with an internal 1.0V reference, or an external 1.0V reference, but

performs well with external reference voltages in the range of 0.9V to 1.1V. The internal 1.0 Volt reference is the

default condition when no external reference input is applied to the V_REFpin. If a voltage in the range of 0.9V to

1.1V is applied to the V_REFpin, then that voltage is used for the reference. The V_REFpin should always be

bypassed to ground with a 0.1 µF capacitor close to the reference input pin. Lower reference voltages will

decrease the signal-to-noise ratio (SNR) of the ADC11C125. Increasing the reference voltage (and the input

signal swing) beyond 1.1V may degrade THD for a full-scale input, especially at higher input frequencies.

It is important that all grounds associated with the reference voltage and the analog input signal make connection

to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

The Reference Bypass Pins (V_RP, V_RM, and V_RN) are made available for bypass purposes. All these pins should

each be bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a 10 µF capacitor should be placed between

the V_RPand V_RNpins, as shown in Figure 23. This configuration is necessary to avoid reference oscillation,

which could result in reduced SFDR and/or SNR. V_RMmay be loaded to 1mA for use as a temperature stable

1.5V reference. The remaining pins should not be loaded.

Smaller capacitor values than those specified will allow faster recovery from the power down and sleep modes,

but may result in degraded noise performance. Loading any of these pins, other than V_RM, may result in

performance degradation.

The nominal voltages for the reference bypass pins are as follows:

V_RM= 1.5 V

V_RP= V_RM+ V_REF/ 2

V_RN= V_RM− V_REF/ 2

Control Inputs

Power-Down & Sleep (PD/Sleep)

The power-down and sleep modes can be enabled through this three-state input pin. Table 2 shows how to

utilize these options.

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Table 2. Power Down/Sleep Selection Table

PD Input Voltage

Power State

Power-down

Sleep

V_A

V_A/2

AGND

The power-down and sleep modes allows the user to conserve power when the converter is not being used. In

the power-down state all bias currents of the analog circuitry, excluding the reference are shut down which

reduces the power consumption to 5 mW with no clock running. In sleep mode some additional buffer circuitry is

left on to allow an even faster wake time; power consumption in the sleep mode is 50 mW with no clock running.

In both of these modes the output data pins are undefined and the data in the pipeline is corrupted.

The Exit Cycle time for both the sleep and power-down mode is determined by the value of the capacitors on the

V_RP, V_RMand V_RNreference bypass pins (pins 43, 44 and 45). These capacitors lose their charge when the ADC

is not operating and must be recharged by on-chip circuitry before conversions can be accurate. For power-down

mode the Exit Cycle time is about 3 ms with the recommended component values. The Exit Cycle time is faster

for sleep mode. Smaller capacitor values allow slightly faster recovery from the power down and sleep mode, but

can result in a reduction in SNR, SINAD and ENOB performance.

Clock Mode Select/Data Format (CLK_SEL/DF)

Single-ended versus differential clock mode and output data format are selectable using this quad-state function

pin. Table 3 shows how to select between the clock modes and the output data formats.

Table 3. Clock Mode and Data Format Selection Table

CLK_SEL/DF Input Voltage

Clock Mode

Differential

Output Data Format

2's Complement

Offset Binary

V_A

(2/3) * V_A

(1/3) * V_A

AGND

Differential

Single-Ended

2's Complement

Offset Binary

CLOCK INPUTS

The CLK+ and CLK− signals control the timing of the sampling process. The CLK_SEL/DF pin (pin 8) allows the

user to configure the ADC for either differential or single-ended clock mode. In differential clock mode, the two

clock signals should be exactly 180° out of phase from each other and of the same amplitude. In the single-

ended clock mode, the clock signal should be routed to the CLK+ input and the CLK− input should be tied to

AGND in combination with the correct setting from Table 3.

To achieve the optimum noise performance, the clock inputs should be driven with a stable, low jitter clock signal

in the range indicated in the Electrical Table. The clock input signal should also have a short transition region.

This can be achieved by passing a low-jitter sinusoidal clock source through a high speed buffer gate. This

configuration is shown in Figure 23. The trace carrying the clock signal should be as short as possible and

should not cross any other signal line, analog or digital, not even at 90°. Figure 23 shows the recommended

clock input circuit.

The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the

charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.

This is what limits the minimum sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905

(SNLA035) for information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is

used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that

the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

(6)

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where t_PDis the signal propagation rate down the clock line, "L" is the line length and Z_Ois the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical t_PDis about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of

"L" and t_PDshould be the same (inches or centimeters).

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC11C125 has a Duty Cycle Stabilizer. It is designed to maintain performance over a

clock duty cycle range of 30% to 70%.

DIGITAL OUTPUTS

Digital outputs consist of the 1.8V CMOS signals D0-D10, DRDY, OVR and OGND.

The ADC11C125 has 16 CMOS compatible data output pins: 11 data output bits corresponding to the converted

input value, a data ready (DRDY) signal that should be used to capture the output data, an over-range indicator

(OVR) which is set high when the sample amplitude exceeds the 11-Bit conversion range and three output

ground pins (OGND) which should be ignored except when used for compatibility with a 12 or 14 bit part. Valid

data is present at these outputs while the PD/Sleep pin is low.

Data should be captured and latched with the rising edge of the DRDY signal. Depending on the setup and hold

time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the DRDY signal

can be used to latch the data. Generally, rising-edge capture would maximize setup time with minimal hold time;

while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the

falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the

ASIC. Refer to the AC Electrical Characterisitics table.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through V_DRand DRGND. These large charging

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

reduce this problem. Additionally, bus capacitance beyond the specified 5 pF/pin will cause t_ODto increase,

reducing the setup and hold time of the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can

be done by using a programmable logic device (PLD) such as the LC4032V-25TN48C to level translate the ADC

output data from 1.8V to 3.3V for use by any other circuitry. Only one load should be connected to each output

pin. The outputs of the ADC14155 have 40Ω on-chip series resistors to limit the output currents at the digital

outputs. Additionally, inserting series resistors of about 22Ω at the digital outputs, close to the ADC pins, will

isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise

result in performance degradation. See Figure 23.

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+3.3V from

Regulator

+3.3V from

Regulator

+1.8V from

Regulator

+1.8V from

Regulator

+3.3V from

Regulator

0.01 mF

0.1 mF

0.01 mF

0.1 mF

REF

DRDY

10 mF

0.1 mF

OVR

(MSB) D10

10 mF

0.1 mF

49.9

10 mF

0.1 mF

ADC11C125

LC4032V-25TN48C

PLD

11-bit

0.1 mF

15 pF

33.2

Digital

Output

Word

0.1 mF

24.9

15 pF

(LSB) D0

OGND

PD/Sleep

CLK_SEL/DF

Flux XFMR: ADT1-1WT or ETC1-1T

Balun XFMR: ADT1-12 or ETC1-1-13

(See ADC11C125 User‘s Guide for

other Input Network Configurations)

15 pF

OGND

CLK+

CLK-

OGND

CLK

0.1 mF

24.9

NC7WV125K8X

High Speed Buffer

NOTE: If 14-bit compatibility is not required do not connect pins 17 - 19) Application Circuit using Transformer Drive Circuit

Figure 23. Application Circuit using Transformer Drive Circuit

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF capacitor and with a 0.01 µF ceramic chip capacitor

close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.

As is the case with all high-speed converters, the ADC11C125 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mV_P-P

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during power turn on and turn off.

The V_DRpin provides power for the output drivers and may be operated from a supply in the range of 1.6V to

2.0V. This enables lower power operation, reduces the noise coupling effects from the digital outputs to the

analog circuitry and simplifies interfacing to lower voltage devices and systems. Note, however, that t_OD

increases with reduced V_DR. A level translator may be required to interface the digital output signals of the

ADC11C125 to non-1.8V CMOS devices.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC11C125 between these areas, is required to achieve

specified performance.

The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the

ADC11C125's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

The effects of the noise generated from the ADC output switching can be minimized through the use of 22Ω

resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.

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SNAS387C –MAY 2007–REVISED APRIL 2013

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane area.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors and transformers. Mutual inductance can change the

characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by

side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog

input and the clock input at 90° to one another to avoid magnetic coupling.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of

the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The

ADC11C125 should be between these two areas. Furthermore, all components in the reference circuitry and the

input signal chain that are connected to ground should be connected together with short traces and enter the

ground plane at a single, quiet point. All ground connections should have a low inductance path to ground.

DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition

region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree

shown in Figure 24 . The gates used in the clock tree must be capable of operating at frequencies much higher

than those used if added jitter is to be prevented. Best performance will be obtained with a single-ended drive

input drive, compared with a differential clock.

As mentioned in Layout and Grounding, it is good practice to keep the ADC clock line as short as possible and to

keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to

reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings

have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 24. Isolating the ADC Clock from other Circuitry with a Clock Tree

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REVISION HISTORY

Changes from Revision B (April 2013) to Revision C

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 23

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC11C125CISQ/NOPB

ACTIVE

WQFN

RHS

250

RoHS & Green

Level-3-260C-168 HR

-45 to 85

ADC11C125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC11C125CISQ/NOPB WQFN

RHS

250

178.0

16.4

7.3

1.3

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WQFN RHS 48

SPQ

Length (mm) Width (mm) Height (mm)

208.0 191.0 35.0

ADC11C125CISQ/NOPB

250

Pack Materials-Page 2

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ADC11C125 [TI]

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