ADC12040CIVYX/NOPB [TI]

12 位 40MSPS 模数转换器 (ADC) | NEY | 32 | -40 to 85;


型号：	ADC12040CIVYX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	12 位 40MSPS 模数转换器 (ADC) \| NEY \| 32 \| -40 to 85 转换器模数转换器
文件：	总32页 (文件大小：1080K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12040

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ADC12040 12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold

Check for Samples: ADC12040

FEATURES

DESCRIPTION

The ADC12040 is a monolithic CMOS analog-to-

digital converter capable of converting analog input

signals into 12-bit digital words at 40 Megasamples

per second (MSPS), minimum. This converter uses a

differential, pipeline architecture with digital error

correction and an on-chip sample-and-hold circuit to

minimize die size and power consumption while

providing excellent dynamic performance. Operating

on a single 5V power supply, this device consumes

just 340 mW at 40 MSPS, including the reference

current. The Power Down feature reduces power

consumption to 40 mW.

•

Single +5V Supply Operation

Internal Sample-and-Hold

•

Outputs 2.35V to 5V Compatible

Pin Compatible with ADC12010, ADC12020,

ADC12L063, ADC12L066

•

Power Down Mode

On-Chip Reference Buffer

APPLICATIONS

•

Ultrasound and Imaging

Instrumentation

The differential inputs provide a full scale differential

input swing equal to 2V_REFwith the possibility of a

single-ended input, although full use of the differential

input is required for optimum performance. For ease

of use, the buffered, high impedance, single-ended

reference input is converted on-chip to a differential

reference for use by the processing circuitry. Output

data format is 12-bit offset binary.

Cellular Base Stations/Communications

Receivers

•

Sonar/Radar

xDSL

Wireless Local Loops/Cable Modems

HDTV/DTV

This device is available in the 32-lead LQFP package

and will operate over the industrial temperature range

of −40°C to +85°C.

DSP Front Ends

KEY SPECIFICATIONS

•

Supply Voltage: +5V ±5%

DNL: ±0.4 LSB (typ)

SNR (f_IN= 10MHz): 69 dB (typ)

ENOB (f_IN= 10MHz): 11.2 bits (typ)

Power Consumption, 40 MHz: 340 mW (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12040

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Connection Diagram

Block Diagram

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

Non-Inverting analog signal Input. With a 2.0V reference voltage, the

V_IN

ground-referenced input signal level is 2.0 V_P-Pcentered on V_CM

Inverting analog signal Input. With a 2.0V reference voltage the

ground-referenced input signal level is 2.0 V_P-Pcentered on V_CM

This pin may be connected to V_CMfor single-ended operation, but a

differential input signal is required for best performance.

−

V_IN

Reference input. This pin should be bypassed to ground with a 0.1

µF monolithic capacitor. V_REFis 2.0V nominal and should be

between 1.0V to 2.4V.

V_REF

AGND

V_RP

V_RM

These pins are high impedance reference bypass pins. Connect a

0.1 µF capacitor from each of these pins to AGND. DO NOT load

these pins.

V_RN

DIGITAL I/O

CLK

Digital clock input. The input is sampled on the rising edge of CLK.

OE is the output enable pin that, when low, enables the TRI-STATE

data output pins. When this pin is high, the outputs are in a high

impedance state.

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

DGND

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

Pin No.

Symbol

Equivalent Circuit

Description

Digital data output pins that make up the 12-bit conversion results.

D0 is the LSB, while D11 is the MSB of the offset binary output

word. Output levels are TTL/CMOS compatible.

14–19,

22–27

D0–D11

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet +5V voltage source and bypassed to ground with 0.1 µF

monolithic capacitors located within 1 cm of these power pins, and

with a 10 µF capacitor.

5, 6, 29

V_A

4, 7, 28

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same

quiet +5V source as is V_Aand bypassed to ground with a 0.1 µF

monolithic capacitor in parallel with a 10 µF capacitor, both located

within 1 cm of the power pin.

V_D

9, 12

DGND

The ground return for the digital supply.

Positive digital supply pin for the ADC12040's output drivers. This

pin should be connected to a voltage source of +2.35V to +5V and

be bypassed to DR GND with a 0.1 µF monolithic capacitor. If the

supply for this pin is different from the supply used for V_Aand V_D, it

should also be bypassed with a 10 µF tantalum capacitor. V_DR

should never exceed the voltage on V_D. All bypass capacitors should

be located within 1 cm of the supply pin.

V_DR

The ground return for the digital supply for the ADC12040's output

drivers. This pin should be connected to the system ground, but not

be connected in close proximity to the ADC12040's DGND or AGND

pins. See LAYOUT AND GROUNDING for more details.

DR GND

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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(1)(2)(3)

Absolute Maximum Ratings

V_A, V_D, V_DR

6.5V

≤ 100 mV

|V_A–V_D|

Voltage on Any Input or Output Pin

−0.3V to (V_Aor V_D+0.3V)

±25 mA

(4)

Input Current at Any Pin

(4)

Package Input Current

±50 mA

(5)

Package Dissipation at T_A= 25°C

ESD Susceptibility

See

(6)

Human Body Model

2500V

250V

(6)

Machine Model

(7)

Soldering Temperature, Infrared, 10 sec.

Storage Temperature

235°C

−65°C to +150°C

(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two. This note does not apply to any power or ground pin.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature, (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax - T_A)/θ_JA. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

(7) The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the

temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body

must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.

(1)(2)

Operating Ratings

Operating Temperature

Supply Voltage (V_A, V_D)

Output Driver Supply (V_DR

V_REFInput

−40°C ≤ T_A≤ +85°C

+4.75V to +5.25V

+2.35V to V_D

)

1.0V to 2.2V

V_CMInput

0.5V to 3.0V

CLK, PD, OE

−0.05V to (V_D+ 0.05V)

−0V to (V_A− 1.0V)

≤100mV

V_INInput

|AGND–DGND|

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Package Thermal Resistance

Package

θ_JA

32-Lead LQFP

79°C / W

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Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, V_REF= +2.0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits apply for T_A= T_J= T_MINto T_MAX

all other limits T_A= T_J= 25°C

(1)(2)(3)

Units

(Limits)

(4)

Symbol

Parameter

Conditions

Typical

Limits

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

±1.8

±1.0

±2.1

±0.9

Bits (min)

LSB (max)

%FS (max)

(5)

INL

DNL

Integral Non Linearity

Differential Non Linearity

Gain Error

±0.7

±0.4

±0.1

−0.1

Offset Error (V_IN+ = V_IN−)

Under Range Output Code

Over Range Output Code

4095

DYNAMIC CONVERTER CHARACTERISTICS

FPBW

Full Power Bandwidth

0 dBFS Input, Output at −3 dB

f_IN1 MHz, V_IN−0.5 dBFS

100

MHz

SNR

Signal-to-Noise Ratio

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0,5 dBFS

f_IN= 10 MHz, V_IN= −0,5 dBFS

f_IN= 1 MHz, V_IN= −0,5 dBFS

f_IN= 10 MHz, V_IN= −0,5 dBFS

f_IN= 1 MHz, V_IN= −0,5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

69.5

66.5

dB (min)

SINAD

ENOB

THD

Signal-to-Noise and Distortion

Effective Number of Bits

Total Harmonic Distortion

dB (min)

Bits

11.2

−82

−80

10.7

−67

Bits (min)

dB (max)

SFDR

IMD

Spurious Free Dynamic Range

Intermodulation Distortion

dB (min)

f_IN= 9.5 MHz and 10.5 MHz, each = −8

dBFS

−75

dBFS

REFERENCE AND ANALOG INPUT CHARACTERISTICS

V_CM

Common Mode Input Voltage

V_A/2

(CLK LOW)

(CLK HIGH)

C_IN

V_INInput Capacitance (each pin to GND) V_IN= 2.5 Vdc + 0.7 V_rms

1.0

2.2

V (min)

V (max)

MΩ (min)

(6)

V_REF

Reference Voltage

2.00

100

Reference Input Resistance

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per ⁽⁾. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100

mV. As an example, if V_Ais 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. See Figure 1

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +2.0V (4V_P-Pdifferential input), the 12-bit LSB is 977 µV.

(4) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

(5) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through

positive and negative full-scale.

(6) Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23

package) is recommended for this application.

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DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, V_REF= +2.0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits apply for T_A= T_J= T_MINto T_MAX

all other limits T_A= T_J= 25°C

(1)(2)(3)

Typical

Units

(Limits)

(5)

Symbol

Parameter

Conditions

Limits

(4)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

V_D= 5.25V

V_D= 4.75V

V_IN= 5.0V

V_IN= 0V

2.0

1.0

V (min)

V (max)

µA

−10

µA

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V_DR= 2.5V

V_DR= 3V

2.3

2.7

0.4

V (min)

V (max)

V_OUT(1)

V_OUT(0)

I_OZ

Logical “1” Output Voltage

Logical “0” Output Voltage

TRI-STATE Output Current

I_OUT= −0.5 mA

I_OUT= 1.6 mA, V_DR= 3V

V_OUT= 2.5V or 5V

V_OUT= 0V

100

−100

−20

+I_SC

Output Short Circuit Source Current

Output Short Circuit Sink Current

V_OUT= 0V

mA (min)

−I_SC

V_OUT= V_DR

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, V_REF= 2.0V

PD Pin = V_DR

mA (max)

I_A

Analog Supply Current

PD Pin = DGND

PD Pin = V_DR, f_CLK= 0

7.3

mA (max)

I_D

Digital Supply Current

(6)

PD Pin = DGND, C_L= 0 pF

PD Pin = V_DR, f_CLK= 0

mA (max)

I_DR

Digital Output Supply Current

Total Power Consumption

(7)

PD Pin = DGND, C_L= 0 pF

PD Pin = V_DR, f_CLK= 0

340

366

Rejection of Full-Scale Error with

V_A= 4.75V vs. 5.25V

PSRR1 Power Supply Rejection

PSRR2 Power Supply Rejection

SNR Degradation w/10 MHz,

200 mV_P-Priding on V_A

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per ⁽⁾. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100

mV. As an example, if V_Ais 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. See Figure 1

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +2.0V (4V_P-Pdifferential input), the 12-bit LSB is 977 µV.

(4) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

(5) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

(6) I_DRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR=V_DR(C₀x f₀+ C₁x f₁+....C₁₁

f₁₁) where V_DRis the output driver power supply voltage, C_nis total capacitance on the output pin, and f_nis the average frequency at

which that pin is toggling.

(7) Excludes I_DR. See previous note.

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AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, V_REF= +2.0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits apply for T_A= T_J= T_MINto T_MAX

all other limits T_A= T_J= 25°C

(1)(2)(3)(4)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(5)

f_CLK

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

MHz (min)

kHz

f_CLK

100

t_CH

11.25

ns (min)

Clock Cycles

ns (max)

t_CL

Clock Low Time

t_CONV

Conversion Latency

V_DR= 2.5V, −45°C < T_A< +85°C

V_DR= 2.5V, T_A= +25°C

16.3

15.9

15.7

14.9

t_OD

Data Output Delay after Rising CLK Edge

V_DR= 3.0V, −45°C < T_A< +85°C

V_DR= 3.0V, T_A= +25°C

1.2

t_AD

t_AJ

Aperture Delay

Aperture Jitter

ps rms

t_DIS

t_EN

t_PD

Data outputs into TRI-STATE Mode

Data Outputs Active after TRI-STATE

Power Down Mode Exit Cycle

t_CLK

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per ⁽⁾. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100

mV. As an example, if V_Ais 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. See Figure 1

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +2.0V (4V_P-Pdifferential input), the 12-bit LSB is 977 µV.

(4) Timing specifications are tested at TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge.

(5) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average

Outgoing Quality Level).

Figure 1.

Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V_CM) is the d.c. potential present at both signal inputs to the ADC.

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CONVERSION LATENCY See PIPELINE DELAY.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between the

Positive Full Scale Error and the Negative Full Scale Error:

Gain Error = Pos. Full Scale Error − Neg. Full Scale Error

(1)

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12040 is ensured

not to have any missing codes.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale (−V_REF).

OFFSET ERROR is the difference between the two input voltages [ (V_IN+) – (V_IN−) ] required to cause a

transition from code 2047 to 2048.

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline

Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data

lags the conversion by the pipeline delay.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below the reference voltage.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC12040, PSRR1 is the ratio of the change in Full-Scale Error that results from a

change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding

upon the power supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal

amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is

any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first nine

harmonic components to the rms value of the input signal. THD is calculated as

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where

•

F₁is the RMS power of the fundamental (output) frequency

f₂through f₁₀are the RMS power of the first 9 harmonic frequencies in the output spectrum

(2)

Timing Diagram

Output Timing

Transfer Characteristic

Figure 2. Transfer Characteristic

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Typical Performance Characteristics

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

DNL

vs.

V_A

DNL

Figure 3.

Figure 4.

DNL

vs.

Temperature

DNL

vs.

Clock Duty Cycle

Figure 5.

INL

Figure 6.

INL

vs.

V_A

Figure 7.

Figure 8.

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Typical Performance Characteristics (continued)

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

INL

vs.

Temperature

Clock Duty Cycle

Figure 9.

Figure 10.

SNR

vs.

Temperature

THD

vs.

Temperature

Figure 11.

Figure 12.

SINAD

vs.

Temperature

SNR

vs.

Clock Duty Cycle

Figure 13.

Figure 14.

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Typical Performance Characteristics (continued)

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

THD

SINAD and ENOB

vs.

Clock Duty Cycle

vs.

Clock Duty Cycle

Figure 15.

Figure 16.

Spectral Response

IMD @ F₁= 9.5MHz, F₂= 10.5MHz

Figure 17.

Figure 18.

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FUNCTIONAL DESCRIPTION

Operating on a single +5V supply, the ADC12040 uses a pipeline architecture and has error correction circuitry

to help ensure maximum performance. The differential analog input signal is digitized to 12 bits.

The reference input is buffered to ease the task of driving that pin and the output word rate is the same as the

clock frequency. The analog input voltage is acquired at the rising edge of the clock and the digital data for a

given sample is delayed by the pipeline for 6 clock cycles.

A logic high on the power down (PD) pin reduces the converter power consumption to 40 mW.

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12040:

4.75V ≤ V_A≤ 5.25V

V_D= V_A

2.35V ≤ V_DR≤ V_D

100 kHz ≤ f_CLK≤ 50 MHz

1.0V ≤ V_REF≤ 2.2V

0.5V ≤ V_CM≤ 3.0V

0V ≤ V_IN≤ (V_A− 1.0V)

V_REFand V_CMmust be such that the signal swing remains within the limits of 0V to V_A.

Analog Inputs

The ADC12040 has two signal input pins, V_IN+ and V_IN−, forming a differential input pair, and one reference input

pin, V_REF

Reference Pins

The ADC12040 is designed to operate with a 2.0V reference, but performs well with reference voltages in the

range of 1.0V to 2.2V. Lower reference voltages will decrease the signal-to-noise ratio (SNR). Increasing the

reference voltage (and the input signal swing) beyond 2.2V will degrade THD for a full-scale input

It is important that all grounds associated with the reference voltage and the input signal make connection to the

ground plane at a single point to minimize the effects of noise currents in the ground path.

The three Reference Bypass Pins (V_RP, V_RMand V_RN) are made available for bypass purposes only. These pins

should each be bypassed to ground with a 0.1 µF capacitor. Smaller capacitor values will allow faster recovery

from the power down mode, but may result in degraded noise performance. DO NOT LOAD these pins.

Signal Inputs

The signal inputs are V_IN+ and V_IN−. The input signal, V_IN, is defined as

V_IN= (V_IN+) – (V_IN−)

(3)

Figure 19 shows the expected input signal range.

Note that the common mode input voltage range is 1V to 3V with a nominal value of V_A/2. The input signals

should remain between ground and 4V.

The Peaks of the individual input signals (V_IN+ and V_IN−) should each never exceed the voltage described as

V_IN+, V_IN− = V_REF+ V_CM≤ 4V

(4)

to maintain THD and SINAD performance.

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Figure 19. Expected Input Signal Range

The ADC12040 performs best with a differential input with each input centered around a V_CM. The peak-to-peak

voltage swing at V_IN+ and V_IN− each should not exceed the value of the reference voltage or the output data will

be clipped. The two input signals should be exactly 180° out of phase from each other and of the same

amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For a

complex waveform, however, angular errors will result in distortion.

For angular deviations of up to 10 degrees from these two signals being 180 out of phase, the full scale error in

LSB can be described as approximately

E_FS= 4096 ( 1 - sin (90° + dev))

where

•

Where dev is the angular difference, in degrees, between the two signals having a 180° relative phase

relationship to each other (see Figure 20)

(5)

Drive the analog inputs with a source impedance less than 100Ω.

Figure 20. Angular Errors Between the Two Input Signals Will Reduce the Output Level

For differential operation, each analog input signal should have a peak-to-peak voltage equal to the input

reference voltage, V_REF, and be centered around a common mmode voltage, V_CM

Table 1. Input to Output Relationship – Differential Input

−

V_IN

Output

_CM− V_REF/2

_CM− V_REF/4

V_CM

V_CM+ V_REF/2

V_CM+ V_REF/4

V_CM

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

V_CM+ V_REF/2

V_CM− V_REF/4

V_CM− V_RE/2F

Table 2. Input to Output Relationship – Single-Ended Input

−

V_IN

Output

_CM− V_REF

V_CM

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

V_CM− V_REF/2

V_CM

V_CM+ V_REF/2

V_CM+V_REF

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Single-Ended Operation

Single-ended performance is lower than with differential input signals. For this reason, single-ended operation is

not recommended. However, if single-ended operation is required, and the resulting performance degradation is

acceptable, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input.

The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD

performance (Figure 19(b)). For example, set V_REFto 1.0V and bias V_IN− to 1.0V and drive V_IN+ with a signal

range of 0V to 2.0V.

Because very large input signal swings can degrade distortion performance, better performance with a single-

ended input can be obtained by reducing the reference voltage while maintaining a full-range output. and indicate

the input to output relationship of the ADC12040.

Driving the Analog Inputs

The V_IN+ and the V_IN− inputs of the ADC12040 consist of an analog switch followed by a switched-capacitor

amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when

the clock is low, and 7 pF when the clock is high. Although this difference is small, a dynamic capacitance is

more difficult to drive than is a fixed capacitance, so choose the driving amplifier carefully. The LMH6550, the

LMH6702 and the LMH6628 are a good amplifiers for driving the ADC12040.

The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving

source tries to compensate for this, it adds noise to the signal. To prevent this, use an RC at each of the inputs,

as shown in Figure 22 and Figure 23. These components should be placed close to the ADC because the input

pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The

capacitors are for Nyquist applications and should be eliminated for undersampling applications.

The LMH6550 and the LMH6552 are excellent devices for driving the ADC12040, especially when single-ended

to differential conversion with d.c. coupling is necessary. An example of the use of the LMH6550 to drive the

analog input of the ADC12040 is shown in Figure 22.

For high frequency, narrow band applications, a transformer is generally the recommended way to drive the

analog inputs, as shown in Figure 23.

Input Common Mode Voltage

The input common mode voltage, V_CM, should be in the range indicated in OPERATING CONDITIONS and be of

a value such that the peak excursions of the analog input signal do not go more negative than ground or more

positive than the V_Asupply voltage. The nominal V_CMshould generally be equal to V_REF/2, but V_RMcan be used

as a V_CMsource as long as V_RMneed not supply more than 10 µA of current. Figure 22 shows the use of the V_RM

output to drive the V_CMinput of the LMH6550. The common mode output voltage of the LMH6550 is equal to the

V_CMinput input voltage.

DIGITAL INPUTS

The digital TTL/CMOS compatible inputs consist of CLK, OE and PD.

The CLK Input

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 100 kHz to 50 MHz with rise and fall times of less than 3ns. The trace carrying the clock

signal should be as short as possible and should not cross any other signal line, analog or digital, not even at

90°.

If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point

where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 100 ksps.

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12040 is designed to maintain performance over a range of duty cycles. While it is

specified and performance is ensured with a 50% clock duty cycle, performance is typically maintained over a

clock duty cycle range of 45% to 55%.

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The clock line should be terminated at its source in the characteristic impedance of that line. It is highly desirable

that the the source driving the ADC CLK input only drive that pin. However, if that source is used to drive other

things, each driven pin should be a.c. terminated with a series RC to ground, as shown in Figure 21, such that

the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

where

•

t_PDis the signal propagation rate down the clock line

"L" is the line length

Z_Ois the characteristic impedance of the clock line

(6)

This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock

source. Typical t_PDis about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and t_PDshould be

the same (inches or centimeters).

Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application

Note AN-905 (SNLA035) or AN-1113 (SNLA011) for information on setting and determining characteristic

impedance

The OE Input

The OE input, when high, puts the output pins into a high impedance state. When this pin is low the outputs are

in the active state. The ADC12040 will continue to convert whether this input is high or low, but the output can

not be read while the OE pin is high.

The OE input should NOT be used to multiplex devices together to drive a common bus as this will result in

excessive capacitance on the data output pins, reducing SNR and SINAD performance of the converter. See

DATA OUTPUTS.

The PD Input

The PD input, when high, holds the ADC12040 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 70 mW with a 40MHz clock and 40mW if the clock is

stopped. The output data pins are undefined in this mode. The data in the pipeline is corrupted while in the

power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32.

These capacitors loose their charge in the Power Down mode and must be charged by on-chip circuitry before

conversions can be accurate.

DATA OUTPUTS

The ADC12040 has 12 TTL/CMOS compatible Data Output pins. Valid offset binary data is present at these

outputs while the OE and PD pins are low. While the t_ODtime provides information about output timing, a simple

way to capture a valid output is to latch the data on the edge of the conversion clock (pin 10). Which edge to use

will depend upon the clock frequency and duty cycle. If the rising edge is used, the t_ODtime can be used to

determine maximum hold time acceptable of the driven device data inputs. If the falling edge of the clock is used,

care must be taken to be sure that adequate setup and hold times are allowed for capturing the ADC output

data.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large charging

current spikes can cause on-chip noise that can couple into the analog circuitry, degrading dynamic

performance. Adequate power supply bypassing and careful attention to the ground plane will reduce this

problem. Additionally, bus capacitance beyond that specified will cause t_ODto increase, making it difficult to

properly latch the ADC output data. The result could be an apparent reduction in dynamic performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series 100Ω resistors at the digital outputs,

close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output

currents, which could otherwise result in performance degradation. See Figure 21.

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While the ADC12040 will operate with V_DRvoltages down to 1.8V, t_ODincreases with reduced V_DR. Be careful of

external timing when using reduced V_DR

CHOKE

+5V

10 mF

330

499

REF

0.1 mF

2.00k

DRV

Power Down

LM4040-2.5

1 mF

REF

12 x 100W

0.1 mF

D11 (MSB)

D10

Ground for the 2.00k resistor, the

0.1 mF bypass capacitor, the ground

pin for the LM4040-2.5, the bypass

capacitors on pins 30, 31 and 32 of

the ADC12040 and pin 28 of the

ADC12040 should be connected to

a common point in the analog

ground plane.

74ACQ541

12 BIT

ADC12040

DATA

OUTPUT

CLK

Differential

Drive^(A)

SIGNAL

INPUT

D0 (LSB)

CLOCK

INPUT

74ACQ541

CLK

1/4

See 74ACQ04

Text

AGND

DGND

DRGND

See

Text

CLK

INPUT

See

Figure 21. Simple Application Circuit with Single-Ended to Differential Buffer

511, 1%

To ADC

255, 1%

280, 1%

50W

SIGNAL

INPUT

75 pF

V_CM

Amplifier:

LMH6550

49.9,

75 pF

To ADC

511, 1%

From ADC

LMV321

511, 1%

Figure 22. Differential Drive Circuit of Figure 21

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Figure 23. Driving the Signal Inputs with a Transformer

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor

within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series

inductance.

As is the case with all high-speed converters, the ADC12040 is sensitive to power supply noise. Accordingly, the

noise on the analog supply pin should be kept below 150 mV_P-P

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during turn on and turn off of power.

The V_DRpin provides power for the output drivers and may be operated from a supply in the range of 2.35V to

V_D(nominal 5V). This can simplify interfacing to 3V devices and systems. DO NOT operate the V_DRpin at a

voltage higher than V_D.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12040 between these areas, is required to achieve

specified performance.

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The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the

ADC12040's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

Digital circuits create substantial supply and ground current transients. The logic noise thus generated could

have significant impact upon system noise performance. The best logic family to use in systems with A/D

converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the

74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest

supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. In high speed

circuits, however, it is often necessary to use these higher speed devices. Best performance requires careful

attention to PC board layout and to proper signal integrity techniques.

The effects of the noise generated from the ADC output switching can be minimized through the use of 47Ω to

100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as

possible.

Figure 24. Example of a Suitable Layout

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane volume.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies

beside each other.

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The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

Figure 24 gives an example of a suitable layout. A single ground plane is recommended with separate analog

and digital power planes. The analog and digital power planes should NOT overlap each other. All analog

circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All

digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, all components in the

reference circuitry and the input signal chain that are connected to ground should be connected together with

short traces and enter the ground plane at a single point. All ground connections should have a low inductance

path to ground.

DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate

the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 25.

As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible

and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can

lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°

crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 25. Isolating the ADC Clock from other Circuitry with a Clock Tree

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 300 mV beyond the supply rails (more than 300 mV below the ground pins or 300 mV above

the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not

uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot

that goes above the power supply or below ground when their output lines are not properly terminated. A resistor

of about 33Ω to 47Ω in series with any offending digital input, close to the signal source, should eliminate the

problem.

Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC12040 with a device that is powered from supplies outside the

range of the ADC12040 supply. Such practice may lead to conversion inaccuracies and even to device damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large

charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate

bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem.

Additionally, bus capacitance beyond that specified will cause t_ODto increase, making it difficult to properly latch

the ADC output data. The result could, again, be an apparent reduction in dynamic performance.

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The digital data outputs should be buffered (with 74AC541, for example). Dynamic performance can also be

improved by adding series resistors at each digital output, close to the ADC12040, which reduces the energy

coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors

is 100Ω.

Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen

at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is

more difficult to drive than is a fixed capacitance.

If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade

performance. A small series resistor and shunt capacitor at each amplifier output (as shown in Figure 22 and

Figure 23) will improve performance. The LMH6550, the LMH6702 and the LMH6628 have been successfully

used to drive the analog inputs of the ADC12040.

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will

affect the effective phase between these two signals. Remember that an operational amplifier operated in the

non-inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, V_REF

should be in the range of

1.0V ≤ V_REF≤ 2.2V

(7)

Operating outside of these limits could lead to performance degradation.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

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REVISION HISTORY

Changes from Revision F (March 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 22

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC12040CIVY/NOPB

ADC12040CIVYX/NOPB

ACTIVE

LQFP

NEY

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

ADC12040

CIVY

ACTIVE

NEY

1000 RoHS & Green

ADC12040

CIVY

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

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23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC12040CIVYX/NOPB

LQFP

NEY

1000

330.0

16.4

9.3

2.2

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

LQFP NEY 32

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

ADC12040CIVYX/NOPB

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADC12040CIVY/NOPB

NEY

LQFP

250

9 X 24

150

322.6 135.9 7620 12.2

11.1 11.25

Pack Materials-Page 3

PACKAGE OUTLINE

NEY0032A

LQFP - 1.6 mm max height

SCALE 1.800

PLASTIC QUAD FLATPACK

7.1

6.9

PIN 1 ID

7.1

6.9

9.4

TYP

8.6

0.27

0.17

OPTIONAL:

SHARP CORNERS EXCEPT

PIN 1 ID CORNER

28X 0.8

4X 5.6

32X

0.2

C A B

SEE DETAIL A

1.6 MAX

SEATING PLANE

0.09-0.20

TYP

0.25

GAGE PLANE

(1.4)

0.1

0.15

0.05

0.75

0.45

0 -7

DETAIL

DETAIL A

TYPICAL

4219901/A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration MS-026.

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EXAMPLE BOARD LAYOUT

NEY0032A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

32X (1.6)

32X (0.4)

SYMM

(8.5)

28X (0.8)

(R0.05) TYP

(8.5)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219901/A 10/2016

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

NEY0032A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

32X (1.6)

32X (0.4)

SYMM

(8.5)

28X (0.8)

(R0.05) TYP

(8.5)

SOLDER PASTE EXAMPLE

SCALE 8X

4219901/A 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

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