ADC122S021CIMMX [TI]

ADC122S021 2 Channel, 50 ksps to 200 ksps 12-Bit A/D Converter;


型号：	ADC122S021CIMMX
厂家：	TEXAS INSTRUMENTS
描述：	ADC122S021 2 Channel, 50 ksps to 200 ksps 12-Bit A/D Converter 光电二极管转换器
文件：	总25页 (文件大小：1337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC102S021

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SNAS281G –FEBRUARY 2005–REVISED MARCH 2013

ADC102S021 2 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

Check for Samples: ADC102S021

FEATURES

DESCRIPTION

The ADC102S021 is

a low-power, two-channel

•

Specified Over a Range of Sample Rates.

Two Input Channels

CMOS 10-bit analog-to-digital converter with a high-

speed serial interface. Unlike the conventional

practice of specifying performance at a single sample

rate only, the ADC102S021 is fully specified over a

sample rate range of 50 ksps to 200 ksps. The

converter is based on a successive-approximation

circuit. It can be configured to accept one or two input

signals at inputs IN1 and IN2.

Variable Power Management

Single Power Supply with 2.7V - 5.25V Range

APPLICATIONS

•

Portable Systems

Remote Data Acquisition

Instrumentation and Control Systems

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

serial interfaces.

KEY SPECIFICATIONS

•

DNL: ± 0.13 LSB (typ)

INL: ± 0.13 LSB (typ)

SNR: 61.8 dB (typ)

Power Consumption

The ADC102S021 operates with a single supply that

can range from +2.7V to +5.25V. Normal power

consumption using a +3V or +5V supply is 1.94 mW

and 6.9 mW, respectively. The power-down feature

reduces the power consumption to just 0.12 µW using

a +3V supply, or 0.47 µW using a +5V supply.

–

3V Supply: 1.94mW (typ)

5V Supply: 6.9 mW (typ)

The ADC102S021 is packaged in an 8-lead VSSOP

package. Operation is specified over the industrial

temperature range of −40°C to +85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. Pin-Compatible Alternatives by Resolution and Speed⁽¹⁾

Specified for Sample Rates of:

Resolution

50 to 200 ksps

ADC122S021

ADC102S021

ADC082S021

200 to 500 ksps

ADC122S051

ADC102S051

ADC082S051

500 ksps to 1Msps

ADC122S101

12-bit

10-bit

8-bit

ADC102S101

ADC082S101

(1) All devices are fully pin and function compatible.

Connection Diagram

SCLK

DOUT

DIN

ADC102S021

GND

IN2

IN1

Figure 1. VSSOP Package

See Package Number DGK0008A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC102S021

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Block Diagram

10-BIT

SUCCESSIVE

APPROXIMATION

ADC

IN1

IN2

MUX

T/H

GND

SCLK

CONTROL

LOGIC

DIN

DOUT

Figure 2.

Table 2. Pin Descriptions and Equivalent Circuits

Pin No.

Name

Description

ANALOG I/O

5,4

IN1 and IN2

Analog inputs. These signals can range from 0V to V_A.

DIGITAL I/O

SCLK

DOUT

Digital clock input. This clock directly controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.

Digital data input. The ADC102S021's Control Register is loaded through this pin on rising edges of

the SCLK pin.

DIN

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long

as CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to

GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.

V_A

GND

The ground return for the die.

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Absolute Maximum Ratings^(1)(2)(3)

Analog Supply Voltage V_A

−0.3V to 6.5V

−0.3V to V_A+0.3V

±10 mA

Voltage on Any Pin to GND

(4)

Input Current at Any Pin

(4)

Package Input Current

±20 mA

(5)

Power Consumption at T_A= 25°C

See

(6)

ESD Susceptibility

Human Body Model

Machine Model

2500V

250V

Junction Temperature

Storage Temperature

+150°C

−65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds the power supply (that is, V_IN< GND or V_IN> V_A), the current at that pin should be limited to

10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an

input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the V_Apin. The current into the V_Apin is

limited by the Analog Supply Voltage specification.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax − T_A)/θ_JA. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms

Operating Ratings⁽¹⁾⁽²⁾

Operating Temperature Range

−40°C ≤ T_A≤ +85°C

+2.7V to +5.25V

−0.3V to V_A

V_ASupply Voltage

Digital Input Pins Voltage Range

Clock Frequency

50 kHz to 16 MHz

0V to V_A

Analog Input Voltage

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

Package Thermal Resistance⁽¹⁾⁽²⁾

Package

θ_JA

8-lead VSSOP

250°C / W

(1) Soldering process must comply with Texas Instruments Reflow Temperature Profile specifications.

(2) Reflow temperature profiles are different for lead-free and non-lead-free packages.

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ADC102S021 Converter Electrical Characteristics⁽¹⁾

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 0.8 MHz to 3.2 MHz, f_SAMPLE= 50

ksps to 200 ksps, unless otherwise noted. Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C.

Parameter

Test Conditions

Typ

Limits⁽¹⁾

Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

Bits

+0.3

−0.4

±0.4

±0.5

±0.7

LSB (max)

LSB (min)

LSB (max)

INL

Integral Non-Linearity

±0.13

DNL

V_OFF

OEM

FSE

Differential Non-Linearity

Offset Error

±0.13

+0.1

Channel to Channel Offset Error Match

Full-Scale Error

±0.02

−0.11

Channel to Channel Full-Scale Error

Match

FSEM

+0.02

±0.5

LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

V_A= +2.7 to 5.25V

f_IN= 39.9 kHz, −0.02 dBFS

SINAD

SNR

Signal-to-Noise Plus Distortion Ratio

Signal-to-Noise Ratio

61.8

−86

61.3

−72

dB (min)

dB (max)

dB (min)

Bits (min)

V_A= +2.7 to 5.25V

f_IN= 39.9 kHz, −0.02 dBFS

V_A= +2.7 to 5.25V

f_IN= 39.9 kHz, −0.02 dBFS

THD

Total Harmonic Distortion

V_A= +2.7 to 5.25V

f_IN= 39.9 kHz, −0.02 dBFS

SFDR

ENOB

Spurious-Free Dynamic Range

Effective Number of Bits

V_A= +2.7 to 5.25V

f_IN= 39.9 kHz, −0.02 dBFS

9.9

9.8

V_A= +5.25V

f_IN= 39.9 kHz

Channel-to-Channel Crosstalk

−87

−82

−81

Intermodulation Distortion, Second

Order Terms

V_A= +5.25V

f_a= 40.161 kHz, f_b= 41.015 kHz

IMD

Intermodulation Distortion, Third Order

Terms

V_A= +5.25V

f_a= 40.161 kHz, f_b= 41.015 kHz

V_A= +5V

V_A= +3V

MHz

FPBW

-3 dB Full Power Bandwidth

ANALOG INPUT CHARACTERISTICS

V_IN

Input Range

0 to V_A

µA (max)

I_DCL

DC Leakage Current

±1

Track Mode

Hold Mode

C_INA

Input Capacitance

DIGITAL INPUT CHARACTERISTICS

V_A= +5.25V

V_A= +3.6V

2.4

2.1

0.8

±10

V (min)

V_IH

Input High Voltage

V_IL

Input Low Voltage

Input Current

V (max)

µA (max)

pF (max)

I_IN

V_IN= 0V or V_A

±0.1

C_IND

Digital Input Capacitance

(1) The min/max specification limits are specified by design, test, or statistical analysis.

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ADC102S021 Converter Electrical Characteristics⁽¹⁾(continued)

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 0.8 MHz to 3.2 MHz, f_SAMPLE= 50

ksps to 200 ksps, unless otherwise noted. Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C.

Parameter

Test Conditions

Typ

Limits⁽¹⁾

Units

DIGITAL OUTPUT CHARACTERISTICS

I_SOURCE= 200 µA

_A− 0.03

_A− 0.5

V (min)

V_OH

Output High Voltage

Output Low Voltage

I_SOURCE= 1 mA

I_SINK= 200 µA

I_SINK= 1 mA

_A− 0.1

0.03

0.1

0.4

V (max)

V_OL

I_OZH, I_OZLTRI-STATE Leakage Current

±0.01

±1

µA (max)

pF (max)

C_OUT

TRI-STATE Output Capacitance

Output Coding

Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (C_L= 10 pF)

2.7

V (min)

V_A

Supply Voltage

5.25

V (max)

V_A= +5.25V,

f_SAMPLE= 200 ksps, f_IN= 40 kHz

1.3

0.55

1.8

0.7

mA (max)

Supply Current, Normal Mode

(Operational, CS low)

V_A= +3.6V,

f_SAMPLE= 200 ksps, f_IN= 40 kHz

mA (max)

I_A

V_A= +5.25V,

f_SAMPLE= 0 ksps

Supply Current, Shutdown (CS high)

V_A= +3.6V,

f_SAMPLE= 0 ksps

V_A= +5.25V

V_A= +3.6V

V_A= +5.25V

V_A= +3.6V

6.9

9.5

2.5

mW (max)

µW

Power Consumption, Normal Mode

(Operational, CS low)

1.94

0.47

0.12

P_D

Power Consumption, Shutdown (CS

high)

µW

AC ELECTRICAL CHARACTERISTICS

0.8

3.2

200

MHz (min)

MHz (max)

ksps (min)

ksps (max)

SCLK cycles

% (min)

f_SCLK

Clock Frequency

See⁽²⁾

f_S

Sample Rate

t_CONV

Conversion Time

SCLK Duty Cycle

f_CLK= 3.2 MHz

% (max)

t_ACQ

Track/Hold Acquisition Time

Throughput Time

Full-Scale Step Input

SCLK cycles

Acquisition Time + Conversion Time

(2) This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is

specified under Operating Ratings.

ADC102S021 Timing Specifications

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 0.8 MHz to 3.2 MHz, f_SAMPLE= 50

ksps to 200 ksps, Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C.

Parameter

Test Conditions

V_A= +3.0V

Typ

−3.5

−0.5

+4.5

+1.5

Limits⁽¹⁾

Units

t_CSU

Setup Time SCLK High to CS Falling Edge

See⁽²⁾

ns (min)

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

t_CLH

Hold time SCLK Low to CS Falling Edge

ns (min)

(1) Tested limits are specified to Texas Instrument's AOQL (Average Outgoing Quality Level).

(2) Clock may be either high or low when CS is asserted as long as setup and hold times t_CSUand t_CLHare strictly observed.

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ADC102S021 Timing Specifications (continued)

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 0.8 MHz to 3.2 MHz, f_SAMPLE= 50

ksps to 200 ksps, Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C.

Parameter

Test Conditions

V_A= +3.0V

Typ

Limits⁽¹⁾

Units

t_EN

Delay from CS Until DOUT active

ns (max)

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

+16.5

+15

t_ACC

Data Access Time after SCLK Falling Edge

ns (max)

t_SU

t_H

t_CH

t_CL

Data Setup Time Prior to SCLK Rising Edge

Data Valid SCLK Hold Time

SCLK High Pulse Width

ns (min)

0.5 x t_SCLK0.3 x t_SCLKns (min)

SCLK Low Pulse Width

0.5 x t_SCLK0.3 x t_SCLKns (min)

V_A= +3.0V

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

1.7

1.2

Output Falling

Output Rising

t_DIS

CS Rising Edge to DOUT High-Impedance

ns (max)

1.0

Timing Diagrams

Power Down

Power Up

Hold

Track

Hold

Track

SCLK

Control register

b4 b3 b2

Control register

b4 b3

DIN

DOUT

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB9 DB8 DB7 DB6 DB5

Figure 3. ADC102S021 Operational Timing Diagram

Figure 4. Timing Test Circuit

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Figure 5. ADC102S021 Serial Timing Diagram

CSU

SCLK

CLH

SCLK

Figure 6. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold

capacitor to charge up to the input voltage.

APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the

input signal is acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy

from one analog input that appears at the measured analog input.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below

V_REFand is defined as:

V_FSE= V_max+ 1.5 LSB – V_REF

(1)

where V_maxis the voltage at which the transition to the maximum code occurs. FSE can be

expressed in Volts, LSB or percent of full scale range.

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (V_REF− 1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last

code transition). The deviation of any given code from this straight line is measured from the center of that

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code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components that are present at

the output and are not present at the input and result from two sinusoidal frequencies being applied to the

ADC input at the same time. It is defined as the ratio of the power in the second and third order

intermodulation products to the sum of the power in both of the original frequencies. IMD is usually

expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be

reached with any input value. The ADC102S021 is specified not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the

converter output to the rms value of the sum of all other spectral components below one-half the sampling

frequency, not including d.c. or harmonics included in the THD specification.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of

the input signal to the rms value of all of the other spectral components below half the clock frequency,

including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal where a spurious signal is any signal present in the output

spectrum that is not present at the input, excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five

harmonic components at the output to the rms level of the input signal frequency as seen at the output.

THD is calculated as

A_f2²+3+ A_f6

THD = 20 • log₁₀

A_f1

(2)

where Af₁is the RMS power of the input frequency at the output and Af₂through Af₆are the

RMS power in the first 5 harmonic frequencies. Accurate THD measurement requires a

spectrally pure sine wave (monotone) at the ADC input.

THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the

acquisition time plus the conversion and read out times. In the case of the ADC102S021, this is 16 SCLK

periods.

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Typical Performance Characteristics

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

DNL - V_A= 3.0V

INL - V_A= 3.0V

Figure 7.

Figure 8.

DNL - V_A= 5.0V

INL - V_A= 5.0V

Figure 9.

Figure 10.

DNL vs. Supply

INL vs. Supply

Figure 11.

Figure 12.

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Typical Performance Characteristics (continued)

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

DNL vs. Clock Frequency

INL vs. Clock Frequency

Figure 13.

Figure 14.

DNL vs. Clock Duty Cycle

INL vs. Clock Duty Cycle

Figure 15.

Figure 16.

DNL vs. Temperature

INL vs. Temperature

Figure 17.

Figure 18.

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Typical Performance Characteristics (continued)

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

SNR vs. Supply

THD vs. Supply

Figure 19.

Figure 20.

SNR vs. Clock Frequency

THD vs. Clock Frequency

Figure 21.

Figure 22.

SNR vs. Clock Duty Cycle

THD vs. Clock Duty Cycle

Figure 23.

Figure 24.

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Typical Performance Characteristics (continued)

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

SNR vs. Input Frequency

THD vs. Input Frequency

Figure 25.

Figure 26.

SNR vs. Temperature

THD vs. Temperature

Figure 27.

Figure 28.

SFDR vs. Supply

SINAD vs. Supply

Figure 29.

Figure 30.

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Typical Performance Characteristics (continued)

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

SFDR vs. Clock Frequency

SINAD vs. Clock Frequency

Figure 31.

Figure 32.

SFDR vs. Clock Duty Cycle

SINAD vs. Clock Duty Cycle

Figure 33.

Figure 34.

SFDR vs. Input Frequency

SINAD vs. Input Frequency

Figure 35.

Figure 36.

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Typical Performance Characteristics (continued)

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

SFDR vs. Temperature

SINAD vs. Temperature

Figure 37.

Figure 38.

ENOB vs. Supply

ENOB vs. Clock Frequency

Figure 39.

Figure 40.

ENOB vs. Clock Duty Cycle

ENOB vs. Input Frequency

Figure 41.

Figure 42.

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Typical Performance Characteristics (continued)

T_A= +25°C, f_SAMPLE= 50 ksps to 200 ksps, f_SCLK= 0.8 MHz to 3.2 MHz, f_IN= 39.9 kHz unless otherwise stated.

ENOB vs. Temperature

Spectral Response - 3V, 200 ksps

Figure 43.

Figure 44.

Spectral Response - 5V, 200 ksps

Power Consumption vs. Throughput

Figure 45.

Figure 46.

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APPLICATIONS INFORMATION

ADC102S021 OPERATION

The ADC102S021 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter. Simplified schematics of the ADC102S021 in both track and hold modes

are shown in Figure 47 and Figure 48, respectively. In Figure 47, the ADC102S021 is in track mode: switch SW1

connects the sampling capacitor to one of two analog input channels through the multiplexer, and SW2 balances

the comparator inputs. The ADC102S021 is in this state for the first three SCLK cycles after CS is brought low.

Figure 48 shows the ADC102S021 in hold mode: switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The ADC102S021 is in this state for the fourth through sixteenth SCLK cycles after CS

is brought low.

The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of

16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is

clocked into the DIN pin to indicate the multiplexer address for the next conversion.

CHARGE

REDISTRIBUTION

IN1

DAC

MUX

SAMPLING

IN2

CAPACITOR

SW1

CONTROL

LOGIC

SW2

GND

Figure 47. ADC102S021 in Track Mode

CHARGE

REDISTRIBUTION

DAC

IN1

IN2

MUX

SAMPLING

CAPACITOR

SW1

CONTROL

LOGIC

SW2

GND

Figure 48. ADC102S021 in Hold Mode

USING THE ADC102S021

An ADC102S021 timing diagram and a serial interface timing diagram for the ADC102S021 are shown in the

Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers.

SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data

output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the

ADC102S021's Control Register is placed at DIN, the serial data input pin. New data is written to DIN with each

conversion.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain

an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when

CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a

power down state when CS is high and also between continuous conversion cycles.

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During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13

SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting at the 5th clock. If

there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK

after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK,

where "N" is an integer.

When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the

subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track

mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC

enters the track mode on the first falling edge of SCLK after the falling edge of CS.

During each conversion, data is clocked into the ADC at DIN on the first 8 rising edges of SCLK after the fall of

CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the

conversion after the current one. See Table 3, Table 4, and Table 5.

If CS and SCLK go low within the times defined by t_CSUand t_CLH, the rising edge of SCLK that begins clocking

data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum

t_CSUand T_CLHtimes given in the Timing Specifications.

There are no power-up delays or dummy conversions required with the ADC102S021. The ADC is able to

sample and convert an input to full conversion immediately following power up. The first conversion result after

power-up will be that of IN1.

Table 3. Control Register Bits

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DONTC

ADD2

ADD1

ADD0

DONTC

Table 4. Control Register Bit Descriptions

Bit #:

Symbol:

Description

7 - 6, 2 - 0

DONTC

ADD0

ADD1

ADD2

Don't care. The value of these bits do not affect the device.

These bits determine which input channel will be sampled and converted in the next track/hold

cycle. The mapping between codes and channels is shown in Table 5.

Table 5. Input Channel Selection

ADD2

ADD1

ADD0

Input Channel

IN1 (Default)

IN2

Not allowed. The output signal at the D_OUTpin is indeterminate if ADD1 is high.

ADC102S021 TRANSFER FUNCTION

The output format of the ADC102S021 is straight binary. Code transitions occur midway between successive

integer LSB values. The LSB width for the ADC102S021 is V_A/1024. The ideal transfer characteristic is shown in

Figure 49. The transition from an output code of 00 0000 0000 to a code of 00 0000 0001 is at 1/2 LSB, or a

voltage of V_A/2048. Other code transitions occur at steps of one LSB.

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111...111

111...110

111...000

011...111

1LSB = V_A/1024

000...010

000...001

000...000

+V_A- 1.5LSB

0.5LSB

ANALOG INPUT

Figure 49. Ideal Transfer Characteristic

TYPICAL APPLICATION CIRCUIT

A typical application of the ADC102S021 is shown in Figure 50. Power is provided, in this example, by the Texas

Instruments LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages.

The power supply pin is bypassed with a capacitor network located close to the ADC102S021. Because the

reference for the ADC102S021 is the supply voltage, any noise on the supply will degrade device noise

performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient

decoupling from other circuitry to keep noise off the ADC102S021 supply pin. Because of the ADC102S021's low

power requirements, it is also possible to use a precision reference as a power supply to maximize performance.

The four-wire interface is shown connected to a microprocessor or DSP.

LP2950

1 mF

TANT

0.1 mF

1 mF

0.1 mF

SCLK

IN1

IN2

DIN

MICROPROCESSOR

DSP

ADC102S021

DOUT

GND

Figure 50. Typical Application Circuit

ANALOG INPUTS

An equivalent circuit for one of the ADC102S021's input channels is shown in Figure 51. Diodes D1 and D2

provide ESD protection for the analog inputs. At no time should any input go beyond (V_A+ 300 mV) or (GND −

300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, the

ESD diodes should not be used to clamp the input signal.

The capacitor C1 in Figure 51 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor

R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the

ADC102S021 sampling capacitor and is typically 30 pF. The ADC102S021 will deliver best performance when

driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.

This is especially important when using the ADC102S021 to sample AC signals. Also important when sampling

dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic

performance.

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30 pF

3 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

Figure 51. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC102S021's digital output DOUT is limited by, and cannot exceed, the supply voltage, V_A. The digital

input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted

before V_Awithout any latchup risk.

POWER SUPPLY CONSIDERATIONS

The ADC102S021 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with

one exception: the ADC102S021 automatically enters power-down mode between the 16th falling edge of a

conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams).

The ADC102S021 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles.

The ADC102S021 will perform conversions continuously as long as CS is held low.

The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.

The Power Consumption vs. Sample Rate curve in the Typical Performace Characteristics section shows the

typical power consumption of the ADC102S021 versus throughput. To calculate the power consumption, simply

multiply the fraction of time spent in the normal mode by the normal mode power consumption , and add the

fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation.

Power Management

When the ADC102S021 is operated continuously in normal mode, the maximum throughput is f_SCLK/16.

Throughput may be traded for power consumption by running f_SCLKat its maximum 3.2 MHz and performing

fewer conversions per unit time, putting the ADC102S021 into shutdown mode between conversions. A plot of

typical power consumption versus throughput is shown in the Typical Performance Characteristics section. To

calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by

the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the

shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part

back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is

because the power consumption in the shutdown mode is so small that it can be ignored for all practical

purposes.

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the power supply, V_A. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the supply. If these

variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the

substrate that will degrade noise performance if that current is large enough. The larger is the output

capacitance, the more current flows through the die substrate and the greater is the noise coupled into the

analog channel, degrading noise performance.

To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load

capacitance is greater than 50 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC

output pin as practical. This will limit the charge and discharge current of the output capacitance and improve

noise performance.

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REVISION HISTORY

Changes from Revision F (March 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 19

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PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ADC102S021CIMM/NOPB

ADC102S021CIMMX/NOPB

ACTIVE

VSSOP

DGK

1000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

X17C

ACTIVE

DGK

3500

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC102S021CIMM/NOPB VSSOP

DGK

1000

3500

178.0

330.0

12.4

5.3

3.4

1.4

8.0

12.0

ADC102S021CIMMX/NOP VSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC102S021CIMM/NOPB

VSSOP

DGK

1000

3500

210.0

367.0

185.0

367.0

35.0

ADC102S021CIMMX/NOP

Pack Materials-Page 2

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