ADC128S102CIMT [TI]
八通道、50kSPS 至 1MSPS、12 位模数转换器 (ADC) | PW | 16 | -40 to 105;
| 型号： | ADC128S102CIMT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 八通道、50kSPS 至 1MSPS、12 位模数转换器 (ADC) | PW | 16 | -40 to 105 光电二极管 转换器 模数转换器 |
| 文件： | 总32页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC128S102
SNAS298G –AUGUST 2005–REVISED JANUARY 2015
ADC128S102 8-Channel, 500-ksps to 1-Msps, 12-Bit A/D Converter
1 Features
3 Description
The ADC128S102 is a low-power, eight-channel
CMOS 12-bit analog-to-digital converter specified for
conversion throughput rates of 500 ksps to 1 MSPS.
The converter is based on
approximation register architecture with an internal
track-and-hold circuit. It can be configured to accept
up to eight input signals at inputs IN0 through IN7.
1
•
•
•
•
•
•
Eight Input Channels
Variable Power Management
Independent Analog and Digital Supplies
SPI/QSPI™/MICROWIRE™/DSP Compatible
Packaged in 16-Lead TSSOP
Key Specifications
a
successive-
The output serial data is straight binary and is
compatible with several standards, such as SPI,
QSPI, MICROWIRE, and many common DSP serial
interfaces.
–
–
–
Conversion Rate 500 ksps to 1 MSPS
DNL (VA = VD = 5.0 V) +1.5 / −0.9
LSB (maximum) INL (VA = VD = 5.0 V) ±1.2
LSB (maximum)
The ADC128S102 may be operated with independent
analog and digital supplies. The analog supply (VA)
can range from +2.7 V to +5.25 V, and the digital
supply (VD) can range from +2.7 V to VA. Normal
power consumption using a +3-V or +5-V supply is
2.3 mW and 10.7 mW, respectively. The power-down
feature reduces the power consumption to 0.06 µW
using a +3-V supply and 0.25 µW using a +5-V
supply.
–
Power Consumption
–
–
3V Supply 2.3 mW (typical)
5V Supply 10.7 mW (typical)
2 Applications
•
•
•
•
•
Automotive Navigation
Portable Systems
The ADC128S102 is packaged in a 16-lead TSSOP
package. Operation over the extended industrial
temperature range of −40°C to +105°C is ensured.
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC128S102
TSSOP (16)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VA is used as the Reference
VD can be set independently
of VA
for the ADC
“Analog” Supply Rail
“Digital” Supply Rail
VD
VA
VIN7
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
4-wire SPI
SAR
ADC
MCU
VIN3
VIN0
AGND
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC128S102
SNAS298G –AUGUST 2005–REVISED JANUARY 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 16
7.5 Programming........................................................... 16
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
Power Supply Recommendations...................... 20
9.1 Power Supply Sequence......................................... 20
9.2 Power Supply Noise Considerations....................... 20
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Specifications ............................................... 7
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1 Device Support...................................................... 22
11.2 Trademarks........................................................... 23
11.3 Electrostatic Discharge Caution............................ 23
11.4 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2013) to Revision G
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 20
2
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
CS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
DOUT
DIN
V
A
AGND
IN0
V
D
ADC128S102
IN1
DGND
IN7
IN2
IN3
IN6
IN4
IN5
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
3
AGND
Supply
IN
The ground return for the analog supply and signals.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long
as CS is held low.
1
CS
12
14
DGND
DIN
Supply
IN
The ground return for the digital supply and signals.
Digital data input. The ADC128S102's Control Register is loaded through this pin on rising edges of
the SCLK pin.
Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK
pin.
15
4 - 11
16
DOUT
OUT
IN
IN0 to IN7
SCLK
Analog inputs. These signals can range from 0 V to VREF.
Digital clock input. The ensured performance range of frequencies for this input is 8 MHz to 16 MHz.
This clock directly controls the conversion and readout processes.
IN
Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be
connected to a quiet +2.7-V to +5.25-V source and bypassed to GND with 1-µF and 0.1-µF
monolithic ceramic capacitors located within 1 cm of the power pin.
2
VA
VD
Supply
Supply
Positive digital supply pin. This pin should be connected to a +2.7 V to VA supply, and bypassed to
GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.
13
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6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
See
.
MIN
−0.3
−0.3
−0.3
–10
MAX
UNIT
V
Analog Supply Voltage VA
Digital Supply Voltage VD
Voltage on Any Pin to GND
6.5
VA + 0.3, max 6.5
V
VA +0.3
10
V
(3)
Input Current at Any Pin
mA
mA
Package Input Current(3)
–20
20
(4)
Power Dissipation at TA = 25°C
See
Junction Temperature
150
150
°C
°C
Storage temperature, Tstg
−65
For soldering specifications: see product folder at www.ti.com and SNOA549
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. In the 16-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum
operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12
mW. The values for maximum power dissipation listed above will be reached only when the ADC128S102 is operated in a severe fault
condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
6.2 ESD Ratings
VALUE
±2500
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model (MM)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
105
5.25
VA
UNIT
°C
V
Operating Temperature, TA
VA Supply Voltage
–40
2.7
2.7
0
VD Supply Voltage
Digital Input Voltage
Analog Input Voltage
Clock Frequency
V
VA
V
0
VA
V
8
16
MHz
(1) All voltages are measured with respect to GND = 0V, unless otherwise specified.
4
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6.4 Thermal Information
ADC128S102
THERMAL METRIC(1)
PW
16 PINS
110
42
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
56
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
5
ψJB
55
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1
(1)
MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(2)
UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing
Codes
12
Bits
VA = VD = +3.0V
–1
±0.4
±0.5
+0.4
−0.2
+0.7
−0.4
+0.8
+1.1
±0.1
±0.3
+0.8
+0.3
±0.1
±0.3
1
1.2
0.9
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Non-Linearity (End Point
Method)
INL
VA = VD = +5.0V
–1.2
VA = VD = +3.0V
−0.7
DNL
Differential Non-Linearity
1.5
VA = VD = +5.0V
−0.9
–2.3
–2.3
–1.5
–1.5
–2.0
–2.0
–1.5
–1.5
VA = VD = +3.0V
VA = VD = +5.0V
VA = VD = +3.0V
VA = VD = +5.0V
VA = VD = +3.0V
VA = VD = +5.0V
VA = VD = +3.0V
VA = VD = +5.0V
2.3
2.3
1.5
1.5
2.0
2.0
1.5
1.5
VOFF
OEM
FSE
Offset Error
Offset Error Match
Full Scale Error
Full Scale Error Match
FSEM
DYNAMIC CONVERTER CHARACTERISTICS
VA = VD = +3.0V
VA = VD = +5.0V
8
MHz
MHz
FPBW
Full Power Bandwidth (−3dB)
11
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
70
70
73
73
dB
dB
dB
dB
dB
dB
Signal-to-Noise Plus Distortion
Ratio
SINAD
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
70.8
70.8
73
SNR
THD
Signal-to-Noise Ratio
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
73
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
−88
−90
−74
−74
Total Harmonic Distortion
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
(2) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Electrical Characteristics (continued)
The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1
(1)
MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(2)
UNIT
VA = VD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
75
91
dB
SFDR
ENOB
ISO
Spurious-Free Dynamic Range
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
75
11.3
11.3
92
11.8
11.8
82
dB
Bits
Bits
dB
dB
dB
dB
dB
dB
VA = VD = +3.0V,
fIN = 40.2 kHz
Effective Number of Bits
VA = VD = +5.0V,
fIN = 40.2 kHz, −0.02 dBFS
VA = VD = +3.0V,
fIN = 20 kHz
Channel-to-Channel Isolation
VA = VD = +5.0V,
fIN = 20 kHz, −0.02 dBFS
84
VA = VD = +3.0V,
fa = 19.5 kHz, fb = 20.5 kHz
−89
−91
−88
−88
Intermodulation Distortion,
Second Order Terms
VA = VD = +5.0V,
fa = 19.5 kHz, fb = 20.5 kHz
IMD
VA = VD = +3.0V,
fa = 19.5 kHz, fb = 20.5 kHz
Intermodulation Distortion, Third
Order Terms
VA = VD = +5.0V,
fa = 19.5 kHz, fb = 20.5 kHz
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
0 to VA
V
IDCL
DC Leakage Current
–1
1
µA
pF
pF
Track Mode
Hold Mode
33
3
CINA
Input Capacitance
DIGITAL INPUT CHARACTERISTICS
VA = VD = +2.7V to +3.6V
VA = VD = +4.75V to +5.25V
VA = VD = +2.7V to +5.25V
VIN = 0V or VD
2.1
2.4
V
V
VIH
Input High Voltage
VIL
Input Low Voltage
Input Current
0.8
1
V
IIN
–1
D − 0.5
–1
±0.01
2
µA
pF
CIND
Digital Input Capacitance
4
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA,
VA = VD = +2.7V to +5.25V
VOH
Output High Voltage
Output Low Voltage
V
V
V
ISINK = 200 µA to 1.0 mA,
VA = VD = +2.7V to +5.25V
VOL
0.4
1
Hi-Impedance Output Leakage
Current
IOZH, IOZL
VA = VD = +2.7V to +5.25V
µA
pF
Hi-Impedance Output
COUT
2
4
(1)
Capacitance
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
Analog and Digital Supply
Voltages
VA, VD
VA ≥ VD
2.7
5.25
V
6
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Electrical Characteristics (continued)
The following specifications apply for TA = 25°C, AGND = DGND = 0 V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1
(1)
MSPS, CL = 50pF, unless otherwise noted. MIN and MAX limits apply for TA = TMIN to TMAX
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(2)
UNIT
VA = VD = +2.7V to +3.6V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
0.76
1.5
mA
Total Supply Current
Normal Mode ( CS low)
VA = VD = +4.75V to +5.25V,
fSAMPLE = 1 MSPS, fIN = 40 kHz
2.13
20
3.1
mA
nA
IA + ID
VA = VD = +2.7V to +3.6V,
fSCLK = 0 ksps
Total Supply Current
Shutdown Mode (CS high)
VA = VD = +4.75V to +5.25V,
fSCLK = 0 ksps
50
nA
VA = VD = +3.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
2.3
4.5
mW
mW
µW
µW
Power Consumption
Normal Mode ( CS low)
VA = VD = +5.0V
fSAMPLE = 1 MSPS, fIN = 40 kHz
10.7
0.06
0.25
15.5
PC
VA = VD = +3.0V
fSCLK = 0 ksps
Power Consumption
Shutdown Mode (CS high)
VA = VD = +5.0V
fSCLK = 0 ksps
AC ELECTRICAL CHARACTERISTICS
fSCLKMIN Minimum Clock Frequency
VA = VD = +2.7V to +5.25V
VA = VD = +2.7V to +5.25V
8
0.8
50
MHz
MHz
fSCLK
Maximum Clock Frequency
16
1
500
ksps
Sample Rate
Continuous Mode
fS
VA = VD = +2.7V to +5.25V
VA = VD = +2.7V to +5.25V
VA = VD = +2.7V to +5.25V
VA = VD = +2.7V to +5.25V
MSPS
tCONVERT Conversion (Hold) Time
13 SCLK cycles
40%
30
70
DC
SCLK Duty Cycle
60%
tACQ
Acquisition (Track) Time
Throughput Time
Aperture Delay
3 SCLK cycles
Acquisition Time + Conversion Time
VA = VD = +2.7V to +5.25V
16 SCLK cycles
ns
tAD
VA = VD = +2.7V to +5.25V
4
6.6 Timing Specifications
The following specifications apply for TA = 25°C, VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz,
fSAMPLE = 500 ksps to 1 MSPS, and CL = 50pF. MIN and MAX apply for TA = TMIN to TMAX
.
PARAMETER
TEST CONDITIONS
MIN
10
TYP
0
MAX(1)
UNIT
ns
tCSH
tCSS
tEN
CS Hold Time after SCLK Rising Edge
CS Setup Time prior to SCLK Rising Edge
CS Falling Edge to DOUT enabled
10
4.5
5
ns
30
27
ns
tDACC
tDHLD
tDS
DOUT Access Time after SCLK Falling Edge
DOUT Hold Time after SCLK Falling Edge
DIN Setup Time prior to SCLK Rising Edge
DIN Hold Time after SCLK Rising Edge
17
4
ns
ns
10
10
3
ns
tDH
3
ns
0.4 x
tSCLK
tCH
tCL
SCLK High Time
SCLK Low Time
ns
ns
0.4 x
tSCLK
DOUT falling
DOUT rising
2.4
0.9
20
20
ns
ns
tDIS
CS Rising Edge to DOUT High-Impedance
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Power
Down
Power Up
Power Up
Hold
Track
Track
Hold
10
CS
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
1
2
3
4
5
6
7
8
SCLK
Control register
ADD2 ADD1 ADD0
ADD2 ADD1 ADD0
DIN
DOUT
FOUR ZEROS
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FOUR ZEROS
DB11 DB10 DB9
Figure 1. ADC128S102 Operational Timing Diagram
CS
t
t
CONVERT
ACQ
2
t
CH
SCLK
1
3
t
4
5
6
7
8
16
t
t
DHLD
t
CL
DACC
t
DIS
EN
DOUT
DIN
FOUR ZEROS
DH
DB11 DB10
DB9
DB8
DB1 DB0
t
t
DS
DONTC
DONTC DONTC
ADD2
ADD1
ADD0
DONTC DONTC
Figure 2. ADC128S102 Serial Timing Diagram
SCLK
t
CSS
CS
CS
t
CSH
Figure 3. SCLK and CS Timing Parameters
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6.7 Typical Characteristics
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 4. DNL
Figure 5. DNL
Figure 6. INL
Figure 7. INL
Figure 8. DNL vs. Supply
Figure 9. INL vs. Supply
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 10. SNR vs. Supply
Figure 11. THD vs. Supply
Figure 12. ENOB vs. Supply
Figure 13. DNL vs. VD with VA = 5.0 V
Figure 14. INL vs. VD with VA = 5.0 V
Figure 15. DNL vs. SCLK Duty Cycle
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 16. INL vs. SCLK Duty Cycle
Figure 17. SNR vs. SCLK Duty Cycle
Figure 18. THD vs. SCLK Duty Cycle
Figure 19. ENOB vs. SCLK Duty Cycle
Figure 20. DNL vs. SCLK
Figure 21. INL vs. SCLK
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 22. SNR vs. SCLK
Figure 24. ENOB vs. SCLK
Figure 26. INL vs. Temperature
Figure 23. THD vs. SCLK
Figure 25. DNL vs. Temperature
Figure 27. SNR vs. Temperature
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Typical Characteristics (continued)
TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
Figure 28. THD vs. Temperature
Figure 29. ENOB vs. Temperature
Figure 30. SNR vs. Input Frequency
Figure 31. THD vs. Input Frequency
Figure 33. Power Consumption vs. SCLK
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Figure 32. ENOB vs. Input Frequency
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7 Detailed Description
7.1 Overview
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter.
7.2 Functional Block Diagram
IN0
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
A
.
.
.
MUX
T/H
AGND
AGND
IN7
V
D
SCLK
CS
ADC128S102
CONTROL
LOGIC
DIN
DOUT
DGND
7.3 Feature Description
7.3.1 ADC128S102 Operation
Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 34 and Figure 35
respectively. In Figure 34, the ADC128S102 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC128S102 is in this state for the first three SCLK cycles after CS is brought low.
Figure 35 shows the ADC128S102 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC128S102 is in this state for the last thirteen SCLK cycles
after CS is brought low.
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
CONTRO
SW1
+
-
IN7
L
LOGI
C
SW2
AGND
V
/2
A
Figure 34. ADC128S102 in Track Mode
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Feature Description (continued)
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
+
-
IN7
CONTROL
LOGIC
SW2
AGND
V
/2
A
Figure 35. ADC128S102 in Hold Mode
7.3.2 ADC128S102 Transfer Function
The output format of the ADC128S102 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC128S102 is VA / 4096. The ideal transfer characteristic is shown
in Figure 36. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of VA / 8192. Other code transitions occur at steps of one LSB.
111...111
111...110
111...000
|
1LSB = V /4096
A
011...111
000...010
000...001
000...000
+V - 1.5LSB
A
0.5LSB
0V
ANALOG INPUT
Figure 36. Ideal Transfer Characteristic
7.3.3 Analog Inputs
An equivalent circuit for one of the ADC128S102's input channels is shown in Figure 37. Diodes D1 and D2
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going
beyond this range will cause the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 37 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the
ADC128S102 sampling capacitor, and is typically 30 pF. The ADC128S102 will deliver best performance when
driven by a low-impedance source (less than 100 ohms). This is especially important when using the
ADC128S102 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-
pass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing
filters.
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Feature Description (continued)
V
A
C2
30 pF
D1
D2
R1
V
IN
C1
3 pF
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 37. Equivalent Input Circuit
7.3.4 Digital Inputs and Outputs
The ADC128S102's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone
to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT)
operating range is controlled by VD. The output high voltage is VD - 0.5V (min) while the output low voltage is
0.4V (max).
7.4 Device Functional Modes
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with
one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down
mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent
conversion (see Figure 1).
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS
is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical
specifications. The Power Consumption vs. SCLK curve in the Typical Characteristics section shows the typical
power consumption of the ADC128S102. To calculate the power consumption (PC), simply multiply the fraction of
time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction of time
spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Equation 1.
tN
tS
x
x
PS
PC =
PN +
tN + tS
tN + tS
(1)
7.5 Programming
7.5.1 Serial Interface
An operational timing diagram and a serial interface timing diagram for the ADC128S102 are shown in the
Timing Specifications section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC128S102's
Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
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Programming (continued)
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than
one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling
edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling
edge of SCLK. "N" is an integer value.
The ADC128S102 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters
track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 3 for
setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next input for conversion is clocked into a control register
through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1, Table 2, and Table 3.
There is no need to incorporate a power-up delay or dummy conversions as the ADC128S102 is able to acquire
the input signal to full resolution in the first conversion immediately following power-up. The first conversion result
after power-up will be that of IN0.
Table 1. Control Register Bits
Bit 7 (MSB)
DONTC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Table 2. Control Register Bit Descriptions
Bit No:
Symbol:
Description
7, 6, 2, 1, 0
DONTC
ADD2
ADD1
ADD0
Don't care. The values of these bits do not affect the device.
5
4
3
These three bits determine which input channel will be sampled and converted at the next
conversion cycle. The mapping between codes and channels is shown in Table 3.
Table 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN0 (Default)
IN1
IN2
IN3
IN4
IN5
IN6
IN7
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Since the ADC128S102 integrates an 8 to 1 MUX on the front end, the
device is typically used in applications where multiple voltages need to be monitored. In addition to having 8
input channels, the ADC128S102 can operate at sampling rates up to 1 MSPS. As a result, the ADC128S102 is
typically run in burst fashion where a voltage is sampled for several times and then the ADC128S102 can be
powered-down. This is a common technique for applications that are power limited. Due to the high bandwidth
and sampling rate, the ADC128S102 is suitable for monitoring AC waveforms as well as DC inputs. The following
example shows a common configuration for monitoring AC inputs.
8.2 Typical Application
The following sections outline the design principles of data acquisition system based on the ADC128S102.
A typical application is shown in Figure 38. The analog supply is bypassed with a capacitor network located close
to the ADC128S102. The ADC128S102 uses the analog supply (VA) as its reference voltage, so it is very
important that VA be kept as clean as possible. Due to the low power requirements of the ADC128S102, it is also
possible to use a precision reference as a power supply.
5V
3.3V
1uF
0.1uF
0.1uF
1uF
High
VA
VD
VDD
Impedance
Source
+
100
100
GPIOa
GPIOb
GPIOc
GPIOd
LMV612
IN7
SCLK
CS
100
100
100
33n
MCU
ADC128S102
IN3
IN0
DOUT
DIN
Schottky
Diode
(optional)
100
Low
GND
Impedance
Source
AGND
DGND
33n
Figure 38. Typical Application Circuit
8.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing signals ranging 0 to 5 V, BW = 10 kHz, and a
throughput of 125 kSPS.
The ADC128S102 has to interface to an MCU whose supply is set at 3.3 V.
8.2.2 Detailed Design Procedure
The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from
the fact that VA is also a reference potential for the ADC.
The requirement of interfacing to the MCU which is powered by 3.3-V supply, forces the choice of 3.3-V as a VD
supply.
Sampling is in fact a modulation process which may result in aliasing of the input signal, if the input signal is not
adequately band limited. The maximum sampling rate of the ADC128S102 when all channels are enabled is, Fs:
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Typical Application (continued)
FSCLK
Fs =
16´8
(2)
Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be
sampled at the maximum rate of:
F
SCLK
Fs _ sin gle =
16
(3)
In order to avoid the aliasing the Nyquist criterion has to be met:
F
s
BWsignal
£
2
(4)
Therefore it is necessary to place anti-aliasing filters at all inputs of the ADC. These filters may be single pole low
pass filters whose pole location has to satisfy, assuming all channels sampled in sequence:
1
F
SCLK
£
p´R´ C 16´8
(5)
(6)
128
R ´ C ³
p´FSCLK
With Fsclk = 16 MHz, a good choice for the single pole filter is:
•
•
R = 100
C = 33 nF
This reduces the input BWsignal = 48 kHz. The capacitor at the INx input of the device provides not only the
filtering of the input signal, but it also absorbs the charge kick-back from the ADC. The kick-back is the result of
the internal switches opening at the end of the acquisition period.
The VA and VD sources are already separated in this example, due to the design requirements. This also
benefits the overall performance of the ADC, as the potentially noisy VD supply does not contaminate the VA. In
the same vain, further consideration could be given to the SPI interface, especially when the master MCU is
capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal
path may help in reducing the ground bounce, and thus improve the overall noise performance of the system.
Care should be taken when the signal source is capable of producing voltages beyond VA. In such instances the
internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide
the desired clamping action use Schottky diodes as shown in Figure 38.
8.2.3 Application Curve
Figure 39. Typical Performance
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9 Power Supply Recommendations
There are three major power supply concerns with this product: power supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
9.1 Power Supply Sequence
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital
supply (VD) cannot exceed the analog supply (VA) by more than 300 mV. Therefore, VA must ramp up before or
concurrently with VD.
9.2 Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if
the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly
into the analog supply, causing greater performance degradation than would noise on the digital supply alone.
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will
dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise
in the substrate that will degrade noise performance if that current is large enough. The larger the output
capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog
channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance. Since the series resistor and the load
capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
10 Layout
10.1 Layout Guidelines
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have
significant impact upon system noise performance. To avoid performance degradation of the ADC128S102 due
to supply noise, do not use the same supply for the ADC128S102 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes
should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be
placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal
chain that are connected to ground should be connected together with short traces and enter the analog ground
plane at a single, quiet point.
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10.2 Layout Example
ANALOG
SUPPLY
RAIL
CS
VA
SCLK
DOUT
DIN
toMCU
AGND
IN0
VD
“DIGITAL” SUPPLY RAIL
IN1
DGND
IN7
IN2
IN3
IN6
to analog
IN4
IN5
signal sources
VIA to GROUND PLANE
GROUND PLANE
Figure 40. Layout Schematic
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another
channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-
Channel Isolation, except for the sign of the data.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below
+
VREF and is defined as:
VFSE = Vmax + 1.5 LSB – VREF
+
where
•
•
Vmax is the voltage at which the transition to the maximum code occurs.
FSE can be expressed in Volts, LSB or percent of full scale range.
(7)
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above
the last code transition). The deviation of any given code from this straight line is measured from
the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as
the ratio of the power in both the second or the third order intermodulation products to the power in
one of the original frequencies. Second order products are fa ± fb, where fa and fb are the two sine
wave input frequencies. Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is usually expressed
in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be
reached with any input value. The ADC128S102 is ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
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Device Support (continued)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not
including d.c. or the harmonics included in THD.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral
component is any signal present in the output spectrum that is not present at the input and may or
may not be a harmonic.
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion and read out times. In the case of the ADC128S102, this is 16
SCLK periods.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five
harmonic components at the output to the rms level of the input signal frequency as seen at the
output. THD is calculated as:
2
2
A
+ꢀ+ A
f2
f10
THD = 20 log
10
2
A
f1
where
•
•
Af1 is the RMS power of the input frequency at the output
Af2 through Af10 are the RMS power in the first 9 harmonic frequencies
(8)
11.2 Trademarks
MICROWIRE is a trademark of Texas Instruments.
QSPI is a trademark of Motorola, Inc..
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC128S102CIMT
ADC128S102CIMT/NOPB
ADC128S102CIMTX/NOPB
NRND
TSSOP
TSSOP
TSSOP
PW
16
16
16
92
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
-40 to 105
128S102
CIMT
ACTIVE
ACTIVE
PW
92
RoHS & Green
SN
SN
128S102
CIMT
PW
2500 RoHS & Green
128S102
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC128S102CIMTX/
NOPB
TSSOP
PW
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
ADC128S102CIMTX/
NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADC128S102CIMT
ADC128S102CIMT
PW
PW
PW
TSSOP
TSSOP
TSSOP
16
16
16
92
92
92
495
495
495
8
8
8
2514.6
2514.6
2514.6
4.06
4.06
4.06
ADC128S102CIMT/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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